Semiconductor device, semiconductor chip, and semiconductor circuit

Abstract

A semiconductor device (100) includes a semiconductor substrate (1) of a first conductivity type, a well region (2) of a second conductivity type, a source region (4) of the second conductivity type, a drain region (3) of the second conductivity type, a first gate region (5) of the first conductivity type, and a first diffusion layer (6) of the second conductivity type. The semiconductor substrate (1) has a first main surface (11) on which the well region (2), the source region (4), the drain region (3), and the first gate region (5) are formed. The drain region (3) is disposed separately from the source region (4). The first gate region (5) is disposed between the source region (4) and the drain region (3). The first diffusion layer (6) is formed separately from the first main surface (11). The concentration of impurities in the first diffusion layer (6) is greater than the concentration of impurities in the well region (2). The first gate region (5) and the first diffusion layer (6) are closer to the source region (4) than the drain region (3).

Description

Technical Field

[0001] This disclosure relates to semiconductor devices, semiconductor chips, and semiconductor circuits. Background Technology

[0002] As an alternative to the structure of a metal oxide semiconductor field-effect transistor (MOSFET) with high voltage resistance, semiconductor devices with a junction field-effect transistor (JFET) structure are known (for example, see Japanese Patent Application Publication No. 2009-43923).

[0003] However, semiconductor devices with a JFET configuration may have increased channel resistance, although there is no need to boost the gate potential. Summary of the Invention

[0004] This disclosure is made to solve the aforementioned problems, and the purpose of this disclosure is to provide a semiconductor device that suppresses channel resistance and a semiconductor chip having the semiconductor device.

[0005] According to the semiconductor device disclosed herein, it includes: a semiconductor substrate of a first conductivity type, a well region of a second conductivity type, a source region of a second conductivity type, a drain region of a second conductivity type, a first gate region of the first conductivity type, and a first diffusion layer of the second conductivity type. The semiconductor substrate has a first main surface. The well region is formed on the first main surface. The source region is formed on the first main surface. The drain region is formed on the first main surface. The drain region is disposed separately from the source region. The first gate region is formed on the first main surface. The first gate region is disposed between the source region and the drain region. The first diffusion layer is formed separately from the first main surface. The source region, drain region, and first gate region are respectively disposed inside the well region. The impurity concentration in the first diffusion layer is greater than the impurity concentration in the well region. The first gate region is closer to the source region than the drain region. The first diffusion layer is closer to the source region than the drain region.

[0006] The semiconductor chip according to this disclosure includes: a first semiconductor circuit region, a second semiconductor circuit region, and the aforementioned semiconductor device. The second semiconductor circuit region operates at a reference potential different from that of the first semiconductor circuit region. The semiconductor device is disposed on the outer periphery of the second semiconductor circuit region.

[0007] The semiconductor circuit according to this disclosure includes: the aforementioned semiconductor device and a bootstrap capacitor connected to the semiconductor device.

[0008] The above and other objects, features, aspects and advantages of the present invention will become clear from the following detailed description of the invention in conjunction with the accompanying drawings. Attached Figure Description

[0009] Figure 1 This is a schematic cross-sectional view of the semiconductor device according to Embodiment 1.

[0010] Figure 2 This is a schematic top view of the semiconductor substrate according to Embodiment 1.

[0011] Figure 3 This is a schematic top view of a modified example 1 of the semiconductor substrate in Embodiment 1.

[0012] Figure 4 This is a schematic top view of a modified example 2 of the semiconductor substrate in Embodiment 1.

[0013] Figure 5 This is a schematic top view of a modified example 3 of the semiconductor substrate in Embodiment 1.

[0014] Figure 6 This is a schematic top view of a modified example 4 of the semiconductor substrate in Embodiment 1.

[0015] Figure 7 This is a schematic top view of a modified example 5 of the semiconductor substrate in Embodiment 1.

[0016] Figure 8 This is a schematic cross-sectional view of the semiconductor device according to Embodiment 2.

[0017] Figure 9 This is a schematic cross-sectional view of the semiconductor device according to Embodiment 3.

[0018] Figure 10 This is a schematic cross-sectional view of a variation 6 of the semiconductor device according to Embodiment 3.

[0019] Figure 11 This is a schematic cross-sectional view of the semiconductor device according to Embodiment 4.

[0020] Figure 12 This is a schematic cross-sectional view of the semiconductor device according to Embodiment 5.

[0021] Figure 13 This is a schematic cross-sectional view of the semiconductor device according to Embodiment 6.

[0022] Figure 14 This is a schematic cross-sectional view of the semiconductor device according to Embodiment 7.

[0023] Figure 15 This is a schematic top view of the semiconductor substrate according to Embodiment 7.

[0024] Figure 16 This is a schematic top view of a modified example 7 of the semiconductor substrate in embodiment 7.

[0025] Figure 17 This is a schematic cross-sectional view of the semiconductor device according to Embodiment 8.

[0026] Figure 18 This is a schematic diagram of the semiconductor chip according to embodiment 9.

[0027] Figure 19 This is a schematic diagram of the semiconductor circuit of embodiment 10. Detailed Implementation

[0028] The embodiments of this disclosure will now be described. Furthermore, unless otherwise specifically mentioned, the same or corresponding parts will be labeled with the same reference numerals in the following drawings, and their descriptions will not be repeated.

[0029] Implementation method 1.

[0030] <Structure of Semiconductor Devices>

[0031] Figure 1 This is a schematic cross-sectional view of the semiconductor device 100 according to Embodiment 1. Figure 1 The semiconductor device 100 shown is a semiconductor device 100 having a junction field effect transistor (JFET) structure, and includes: a semiconductor substrate 1, a well region 2, a source region 4, a drain region 3, a first gate region 5, a first diffusion layer 6, an oxide film 7, and electrodes 8a, 8b, and 8c.

[0032] In the semiconductor device 100 of this embodiment 1, the semiconductor substrate 1 and the first gate region 5 each have a first conductivity type. In the semiconductor device 100 of this embodiment 1, the well region 2, the source region 4, the drain region 3, and the first diffusion layer 6 each have a second conductivity type. Furthermore, in the semiconductor device 100 of this embodiment 1, the first conductivity type is p-type, and the second conductivity type is n-type.

[0033] In the semiconductor device 100 of this embodiment 1, the impurities in the well region 2 are, for example, phosphorus (P). The impurities in the drain region 3 and the source region 4 are, for example, arsenic (As). The impurities in the first gate region 5 are, for example, boron (B) or difluoroborane anion (BF2). The impurities in the first diffusion layer 6 are, for example, arsenic (As) or antimony (Sb).

[0034] Alternatively, the first conductivity type can be n-type, and the second conductivity type can be p-type.

[0035] like Figure 1As shown, the semiconductor substrate 1 has a first main surface 11. Any material can be used as the material constituting the semiconductor substrate 1. The material constituting the semiconductor substrate 1 can be silicon (Si) or a silicon-containing compound. The semiconductor substrate 1 can be a wide-bandgap semiconductor such as silicon carbide (SiC) or gallium nitride (GaN), or it can be an SOI (Silicon on Insulator) substrate.

[0036] Well region 2, drain region 3, source region 4, and first gate region 5 are formed inside the semiconductor substrate 1. Specifically, well region 2, drain region 3, source region 4, and first gate region 5 are formed on the first main surface 11. Well region 2 is formed on a portion of the first main surface 11. Drain region 3, source region 4, and first gate region 5 are disposed inside well region 2.

[0037] like Figure 1 As shown, the drain region 3, source region 4, and first gate region 5 are respectively arranged separately from each other. Furthermore, as... Figure 1 As shown, the direction in which the source region 4 separates from the drain region is defined as the x-direction. The direction perpendicular to the first principal surface 11 is defined as the z-direction. The z-direction is perpendicular to the x-direction. The direction perpendicular to both the x-direction and the z-direction is defined as the y-direction. That is, the x-direction and the y-direction are in-plane directions of the first principal surface 11.

[0038] Drain region 3 has a drain region end 31. Drain region end 31 is closest to source region 4 in the x-direction within drain region 3. Source region 4 has a source region end 41. Source region end 41 is closest to drain region 3 in the x-direction within source region 4.

[0039] The first gate region 5 is disposed between the source region 4 and the drain region 3 in the x-direction. Specifically, the first gate region 5 has a first gate end 51 and a second gate end 52. The first gate end 51 is closest to the drain region 3 in the x-direction of the first gate region 5. The first gate end 51 is opposite to the drain region end 31. The second gate end 52 is closest to the source region 4 in the x-direction of the first gate region 5. The second gate end 52 is opposite to the source region end 41.

[0040] like Figure 1 As shown, the first gate region 5 is closer to the source region 4 in the x-direction than the drain region 3. From a different viewpoint, the first gate region 5 is disposed between the center A of the drain region end 31 and the source region end 41 in the x-direction.

[0041] An oxide film 7 is disposed on the first main surface 11. The oxide film 7 covers the upper surface of the well region 2, a portion of the upper surface of the drain region 3, a portion of the upper surface of the source region 4, and a portion of the upper surface of the first gate region 5. An electrode 8a is connected to the upper surface of the drain region 3 in the area exposed from the oxide film 7. An electrode 8b is connected to the upper surface of the source region 4 in the area exposed from the oxide film 7. An electrode 8c is connected to the upper surface of the first gate region 5 in the area exposed from the oxide film 7. The oxide film 7 is insulating.

[0042] A first diffusion layer 6 is formed inside the semiconductor substrate 1. The impurity concentration in the first diffusion layer 6 is greater than the impurity concentration in the well region 2. The first diffusion layer 6 is formed by separating from the first main surface 11 in the z-direction. Figure 1 As shown, the first diffusion layer 6 can be configured to contact both the well region 2 and the semiconductor substrate 1, and can be disposed inside the well region 2 or in contact with the first gate region 5.

[0043] Here, as Figure 1 As shown, the semiconductor device 100 of this embodiment is characterized by the formation of a first diffusion layer 6 near the first gate region 5. The first diffusion layer 6 is closer to the source region 4 in the x-direction than the drain region 3. In the semiconductor device 100 of this embodiment, the first diffusion layer 6 is disposed between the drain region 3 and the source region 4 in the x-direction. Thus, when a conduction current flows through the drain region 3 and the source region 4, the first diffusion layer 6 functions as a drift layer, that is, suppressing the channel resistance in the first gate region 5. As a result, the on-resistance in the semiconductor device 100 is suppressed.

[0044] As described above, the concentration of impurities in the first diffusion layer 6 is greater than the concentration of impurities in the well region 2. Therefore, when the first diffusion layer 6 is separated from the first main surface 11 in the z direction such that the first diffusion layer 6 is located below the first gate region 5, the parasitic operation of the vertical PNP structure formed by the first gate region 5, the well region 2 and the semiconductor substrate 1 is suppressed.

[0045] When the potential in the first gate region 5 is lower than the potential in the source region 4, for example when current flows from the source region 4 to the drain region 3, the depletion layer extends from the first gate region 5. As a result, the channel resistance increases.

[0046] Therefore, by applying a voltage close to that applied to the source region 4 to the first gate region 5, the propagation of the depletion layer can be suppressed. As a result, the on-resistance in the semiconductor device 100 can be reduced when the device is turned on. On the other hand, by switching the potential applied to the first gate region 5 when the device is turned off, leakage current during the off-state can be suppressed. In this way, multiple different potentials can also be applied to the first gate region 5.

[0047] The first diffusion layer 6 has a first diffusion layer end 61 and a second diffusion layer end 62. The first diffusion layer end 61 is closest to the drain region 3. The second diffusion layer end 62 is closest to the source region 4. In the x-direction, the second diffusion layer end 62 is located at the opposite position to the first diffusion layer end 61.

[0048] Next, the dimensions of the semiconductor device 100 will be described. The thickness of the semiconductor substrate 1 in the z-direction is 200 μm or more and 1000 μm or less. The depth of the well region 2 (the distance in the z-direction from the first main surface 11 to the lower end of the well region 2) is 3 μm or more and 10 μm or less. The depths of the drain region 3 and the source region 4 (the distances in the z-direction from the first main surface 11 to the lower ends of the drain region 3 and the source region 4) are 0.5 μm or more and 2.0 μm or less. The depth of the first gate region 5 (the distance in the z-direction from the first main surface 11 to the lower end of the first gate region 5) is 1.0 μm or more and 3.0 μm or less. The depth of the first diffusion layer 6 (the distance in the z-direction from the first main surface 11 to the lower end of the first diffusion layer 6) is 5.0 μm or more and 20.0 μm or less.

[0049] The width of the well region 2 in the x-direction is 50 μm or more and 300 μm or less. The width of the drain region 3 and the source region 4 in the x-direction is 1.0 μm or more and 10.0 μm or less. The width of the first gate region 5 in the x-direction (distance from the first gate end 51 to the second gate end 52) is 2 μm or more and 20 μm or less. The width of the first diffusion layer 6 in the x-direction (distance from the first diffusion layer end 61 to the second diffusion layer end 62) is 1 μm or more and 20 μm or less. In addition, the depth and width of the well region 2, drain region 3, source region 4, first gate region 5 and first diffusion layer 6 can be varied according to the characteristics of the semiconductor device 100, including its withstand voltage and current capacity.

[0050] The substrate resistance of the semiconductor device 100 in this embodiment 1 is 50 Ωcm or more and 250 Ωcm or less. The concentration of impurities in the well region 2 is 1.0 × 10⁻⁶. 15 cm －3 Above and 5.0×10 16 cm －3The impurity concentrations in both drain region 3 and source region 4 are 1.0 × 10⁻⁶. 17 cm －3 Above and 5.0×10 20 cm －3 The concentration of impurities in the first gate region 5 is 5.0 × 10⁻⁶. 16 cm －3 Above and 5.0×10 18 cm －3 The concentration of impurities in the first diffusion layer 6 is greater than the concentration of impurities in the well region 2, for example, 5.0 × 10⁻⁶. 16 cm －3 Above and 1.0×10 19 cm －3 The impurity concentrations of the well region 2, drain region 3, source region 4, first gate region 5, and first diffusion layer 6 described above can also be varied according to the characteristics of the semiconductor device 100, including its breakdown voltage and current capacity. To suppress the contact resistance between the upper surface of the first gate region 5 and the electrode 8c, the impurity concentration on the upper surface (silicon surface) of the first gate region 5 can also be 1.0 × 10⁻⁶. 17 cm －3 Above and 5.0×10 20 cm －3 the following.

[0051] When the RESURF (Reduced Surface Field) condition is met in well region 2 (the concentration of impurities in well region 2 is measured in cm³), the impurity concentration in well region 2 is [missing information]. －3 The product of the depth (in cm) of region 2 and the depth of region 2 is 6.9 × 10⁻⁶. 11 cm －2 In the following situation, when a high potential is applied to the drain region 3 to maintain the voltage withstand capability, the well region 2 is depleted. As a result, the voltage withstand capability of the semiconductor device 100 of this embodiment 1 is improved.

[0052] However, even when the well region 2 meets the RESURF condition, when the diffusion layer, including the well region 2 and the first diffusion layer 6, does not meet the RESURF condition, the first diffusion layer 6 hinders the depletion of the well region 2, and thus the breakdown voltage of the semiconductor device 100 decreases sharply.

[0053] The first diffusion layer 6 includes a first peak concentration region 6a. The first peak concentration region 6a is the region with the highest impurity concentration in the first diffusion layer 6. Furthermore, in Figure 1 The region representing the first peak concentration region 6a is shown by a dashed line.

[0054] like Figure 1As shown, when viewed from the first gate end 51, the first peak concentration region 6a of the first diffusion layer 6 can also be disposed on the right side. From a different viewpoint, when viewed from the first gate end 51, the first peak concentration region 6a is located in the opposite position to the drain region 3 in the x-direction. The first peak concentration region 6a can be disposed between the first gate end 51 and the source region 4, or it can overlap with the source region 4 when viewed from above on the first main surface 11. In this way, the first diffusion layer 6 does not hinder the depletion of the well region 2. That is, the breakdown voltage of the semiconductor device 100 of this embodiment 1 is improved.

[0055] In this way, a semiconductor device 100 with suppressed on-resistance and high voltage withstand capability can be obtained. In addition, if the first peak concentration region 6a in the x-direction is disposed between the first gate end 51 and the source region 4, the first diffusion layer end 61 in the x-direction can also be disposed between the first gate end 51 and the drain region 3.

[0056] The direction of the current flowing through the drain region 3 and the source region 4 can also be opposite.

[0057] <Methods for Manufacturing Semiconductor Devices>

[0058] The manufacturing method of the semiconductor device 100 of this embodiment 1 will be described.

[0059] First, the process of preparing the substrate is carried out. In this process, the substrate constituting the semiconductor substrate 1 is prepared first.

[0060] Next, the process of forming the first diffusion layer 6 is performed. In this process, the first diffusion layer 6 is formed on the substrate by using ion implantation.

[0061] Next, the process of forming an epitaxial layer is performed. In this process, an epitaxial layer is formed on a substrate by epitaxial growth to cover the first diffusion layer 6. In this way, a semiconductor substrate 1 formed by the substrate and the epitaxial layer and having the first diffusion layer 6 disposed therein is formed.

[0062] Next, the process of forming oxide film 7 is carried out. In this process, oxide film 7 is formed on the upper surface (first main surface 11) of the epitaxial layer by using thermal oxidation.

[0063] Next, the process of forming the well region 2, drain region 3, source region 4, and first gate region 5 is performed. In this process, firstly, an opening for exposing the first main surface 11 is formed at a predetermined location on the oxide film 7. Next, using ion implantation, the well region 2, drain region 3, source region 4, and first gate region 5 are formed on the upper surface (first main surface 11) of the epitaxial layer from the opening formed in the oxide film 7.

[0064] Next, the process of forming electrodes 8a, 8b, and 8c is performed. In this process, a metal layer is formed on the oxide film 7 and the first main surface 11 by vapor deposition of a metal such as aluminum (Al). By patterning this metal layer, electrodes 8a, 8b, and 8c are formed to fill the openings formed in the oxide film 7. In this way, it is possible to obtain... Figure 1 The semiconductor device 100 shown.

[0065] Alternatively, high-energy ion implantation can be performed on the semiconductor substrate 1. This allows the first diffusion layer 6 to be formed inside the semiconductor substrate 1 without using epitaxial growth. Alternatively, epitaxial growth can be used to form the well region 2.

[0066] Figure 2 This is a schematic top view of the semiconductor substrate 1 according to Embodiment 1. Additionally, in Figure 2 In the diagram, the outline of the first diffusion layer 6 is represented by dashed lines. For example... Figure 1 As shown, when viewed from above, the first diffusion layer 6 can also overlap with the first gate region 5. In this way, the parasitic operation of the vertical PNP structure formed by the first gate region 5, the well region 2, and the semiconductor substrate 1 is suppressed.

[0067] Furthermore, when viewed from above, the first peak concentration region 6a can also overlap with the first gate region 5. In this way, the parasitic operation of the vertical PNP structure formed by the first gate region 5, the well region 2, and the semiconductor substrate 1 is further suppressed.

[0068] like Figure 2 As shown, the first gate region 5 and the first diffusion layer 6 can also be formed intermittently. From a different viewpoint, the first gate region 5 may also include a plurality of first gate region portions arranged separately from each other along the y-direction. The first diffusion layer 6 may also include a plurality of first diffusion layer portions arranged separately from each other along the y-direction. When viewed from above on the first main surface 11, the plurality of first diffusion layer portions overlap with the respective plurality of first gate region portions.

[0069] Figures 3-7 These are schematic top views of variations 1 to 5 of the semiconductor substrate 1 according to Embodiment 1. Figures 3-7 respectively with Figure 2 correspond. Figures 3-7 The semiconductor substrate 1 shown in each example has substantially the same properties as... Figure 1 and Figure 2 The semiconductor substrate 1 shown has the same structure and can achieve the same effect, but the structures of the first gate region 5 and the first diffusion layer 6 are different.

[0070] like Figure 3As shown, in a variation 1 of the semiconductor substrate 1 according to Embodiment 1, the first gate region 5 and the first diffusion layer 6 are formed discontinuously. When viewed from above, the first main surface 11 is arranged separately from the first gate region 5 along the y-direction. That is, when viewed from above, the plurality of first diffusion layers do not overlap with each of the plurality of first gate regions. Thus, the first diffusion layer 6 is not disposed at the lower part of the first gate region 5, resulting in a low concentration of impurities at the lower part of the first gate region 5. Therefore, leakage current during disconnection can be suppressed.

[0071] like Figure 4 As shown, in a variation 2 of the semiconductor substrate 1 of Embodiment 1, the first gate region 5 is formed discontinuously. On the other hand, the first diffusion layer 6 extends along the y-direction. When viewed from above, the first main surface 11 shows that multiple first gate regions overlap with one first diffusion layer 6. This reduces the number of channel regions formed by the first gate regions 5. Consequently, the area of ​​the first diffusion layer 6 is large, thus further suppressing the on-resistance in the semiconductor device 100.

[0072] like Figure 5 As shown, in Variation 3 of the semiconductor substrate 1 of Embodiment 1, the first diffusion layer 6 is formed discontinuously. On the other hand, the first gate region 5 extends along the y-direction. When viewed from above, the first main surface 11 shows that multiple first diffusion layer portions overlap with one first gate region 5. Thus, the channel region formed by the first gate region 5 increases. As a result, the area of ​​the first diffusion layer 6 is small, thereby further suppressing leakage current when disconnected.

[0073] like Figure 6 As shown, in variation 4 of the semiconductor substrate 1 of embodiment 1, the first gate region 5 and the first diffusion layer 6 extend along the y-direction. Thus, compared to the case where the first gate region 5 and the first diffusion layer 6 are formed discontinuously, the impact on electrical characteristics is reduced when the first gate region 5 and the first diffusion layer 6 are offset.

[0074] like Figure 7 As shown, in Variation 5 of the semiconductor substrate 1 in Embodiment 1, when the first main surface 11 is viewed from above, the first diffusion layer 6 overlaps with the source region 4. From a different viewpoint, when the first main surface 11 is viewed from above, in the x-direction, the first gate region 5 and the source region 4 are respectively disposed between the end point 61 of the first diffusion layer and the end point 62 of the second diffusion layer. Thus, between the first gate region 5 and the source region 4, the concentration of impurities in the lower part of the first gate region 5 and the source region 4 is high, thereby further suppressing the on-resistance.

[0075] <Effects>

[0076] The semiconductor device 100 disclosed herein includes: a semiconductor substrate 1 of a first conductivity type, a well region 2 of a second conductivity type, a source region 4 of a second conductivity type, a drain region 3 of a second conductivity type, a first gate region 5 of the first conductivity type, and a first diffusion layer 6 of the second conductivity type. The semiconductor substrate 1 has a first main surface 11. The well region 2 is formed on the first main surface 11. The source region 4 is formed on the first main surface 11. The drain region 3 is formed on the first main surface 11. The drain region 3 is disposed separately from the source region 4. The first gate region 5 is formed on the first main surface 11. The first gate region 5 is disposed between the source region 4 and the drain region 3. The first diffusion layer 6 is formed separately from the first main surface 11. The source region 4, the drain region 3, and the first gate region 5 are respectively disposed inside the well region 2. The impurity concentration in the first diffusion layer 6 is greater than the impurity concentration in the well region 2. The first gate region 5 is closer to the source region 4 than the drain region 3. The first diffusion layer 6 is closer to the source region 4 than the drain region 3.

[0077] Thus, when a conduction current flows through the drain region 3 and the source region 4, the first diffusion layer 6 functions as a drift layer. That is, it suppresses the channel resistance in the first gate region 5. As a result, the on-resistance in the semiconductor device 100 is suppressed. In addition, parasitic operations of the vertical PNP structure formed by the first gate region 5, the well region 2, and the semiconductor substrate 1 are suppressed.

[0078] According to the semiconductor device 100 described above, when the first main surface 11 is viewed from above, the first diffusion layer 6 overlaps with the first gate region 5.

[0079] In this way, the parasitic operation of the vertical PNP structure formed by the first gate region 5, the well region 2 and the semiconductor substrate 1 is further suppressed.

[0080] According to the semiconductor device 100 described above, when the first main surface 11 is viewed from above, the first diffusion layer 6 overlaps with the source region 4.

[0081] In this way, the concentration of impurities in the lower part of the first gate region 5 and the source region 4 is high, thus the on-resistance is further suppressed.

[0082] According to the semiconductor device 100 described above, the first diffusion layer 6 includes a first peak concentration region 6a where the impurity concentration is highest. When viewed from above, the first peak concentration region 6a overlaps with the first gate region 5.

[0083] In this way, the parasitic operation of the vertical PNP structure formed by the first gate region 5, the well region 2 and the semiconductor substrate 1 is further suppressed.

[0084] According to the semiconductor device 100 described above, the first gate region 5 has a first gate end 51 closest to the drain region 3. The first diffusion layer 6 includes a first peak concentration region 6a with the highest impurity concentration. The first peak concentration region 6a is located opposite to the drain region 3 when viewed from the first gate end 51.

[0085] In this way, the first diffusion layer 6 does not hinder the depletion of the well region 2. That is, the voltage withstand capability of the semiconductor device 100 is improved.

[0086] According to the semiconductor device 100 described above, multiple different potentials are applied to the first gate region 5.

[0087] In this way, the on-resistance in the semiconductor device 100 can be reduced when the circuit is turned on. On the other hand, when the circuit is turned off, leakage current can be suppressed by switching the potential applied to the first gate region 5.

[0088] Implementation method 2.

[0089] <Structure of Semiconductor Devices>

[0090] Figure 8 This is a schematic cross-sectional view of the semiconductor device 100 according to Embodiment 2. Figure 8 and Figure 1 correspond. Figure 8 The semiconductor device 100 shown has substantially the same... Figure 1 and Figure 2 The semiconductor device 100 shown has the same structure and can achieve the same effect, but differs in that the concentration of impurities in the first diffusion layer 6 increases from the first diffusion layer end 61 toward the second diffusion layer end 62.

[0091] That is, in the first diffusion layer 6, the concentration of impurities in the first diffusion layer 6 is minimum near the end 61 of the first diffusion layer 6. Therefore, the first diffusion layer 6 is easily depleted during voltage withstand. As a result, the voltage withstand capability of the semiconductor device 100 of this embodiment 2 is improved. In addition, the concentration of impurities in the first diffusion layer 6 is maximum near the end 62 of the second diffusion layer. Therefore, compared with the case where the overall impurity concentration of the first diffusion layer 6 is low, the on-resistance of the semiconductor device 100 can be suppressed.

[0092] <Effects>

[0093] According to the semiconductor device 100 described above, the first diffusion layer 6 has a first diffusion layer end 61 and a second diffusion layer end 62. The first diffusion layer end 61 is closest to the drain region 3. The second diffusion layer end 62 is closest to the source region 4. The concentration of impurities in the first diffusion layer 6 increases from the first diffusion layer end 61 toward the second diffusion layer end 62.

[0094] Thus, the first diffusion layer 6 is easily depleted during voltage withstand. As a result, the voltage withstand capability of the semiconductor device 100 is improved. Compared to cases where the overall impurity concentration of the first diffusion layer 6 is low, the on-resistance of the semiconductor device 100 can be suppressed.

[0095] Implementation method 3.

[0096] <Structure of Semiconductor Devices>

[0097] Figure 9 This is a schematic cross-sectional view of the semiconductor device 100 according to Embodiment 3. Figure 9 and Figure 1 correspond. Figure 9 The semiconductor device 100 shown has substantially the same... Figure 1 and Figure 2 The semiconductor device 100 shown has the same structure and can achieve the same effect, but it differs in that the semiconductor device 100 has an insulating layer 10 and multiple conductive layers 91, 92.

[0098] An insulating layer 10 is disposed on the first main surface 11. The insulating layer 10 is disposed in the x-direction between the source region 4 and the drain region 3. In the semiconductor device 100 of this embodiment 3, the insulating layer 10 is disposed in the x-direction between the first gate region 5 and the drain region 3. The insulating layer 10 can be formed by thermal oxidation of silicon or by forming an oxide film.

[0099] Conductive layers 91 and 92 are disposed between the first gate region 5 and the drain region 3 in the x-direction. A plurality of conductive layers 91 are disposed on the insulating layer 10 and the first main surface 11. Specifically, the plurality of conductive layers 91 are disposed separately from each other in the x-direction.

[0100] Among the plurality of conductive layers 91, the conductive layer 91 disposed closest to the drain region 3 spans the insulating layer 10 and the first main surface 11. Specifically, the conductive layer 91 disposed closest to the drain region 3 extends from the insulating layer 10 to the drain region end 31 of the drain region 3 in the x-direction. That is, one end of the conductive layer 91 disposed closest to the drain region 3 is disposed at the same position as the drain region end 31 in the x-direction.

[0101] Among the plurality of conductive layers 91, the conductive layer 91 disposed closest to the first gate region 5 spans the insulating layer 10 and the first main surface 11. Specifically, the conductive layer 91 disposed closest to the first gate region 5 extends from the insulating layer 10 to the first gate end 51 of the first gate region 5 in the x-direction. That is, one end of the conductive layer 91 disposed closest to the first gate region 5 is disposed at the same position as the first gate end 51 in the x-direction.

[0102] A potential equal to that of the drain region 3 is applied to the conductive layer 91 located closest to the drain region 3, and a potential equal to that of the source region 4 is applied to the conductive layer 91 located closest to the source region 4, thereby capacitively coupling the multiple conductive layers 91 and 92. As a result, the potential of the upper surface of the semiconductor device 100 is close to the potential of the first main surface 11. Thus, the voltage withstand capability of the semiconductor device 100 in this embodiment 3 is improved.

[0103] An oxide film 7 covers an insulating layer 10 and multiple conductive layers 91. Multiple conductive layers 92 are disposed on the oxide film 7. The multiple conductive layers 92 are disposed separately from each other along the x-direction. Thus, the multiple conductive layers 91 and 92 are formed discontinuously.

[0104] The materials constituting the multiple conductive layers 91 and 92 can be polycrystalline silicon or metals such as aluminum. The multiple conductive layers 91 and 92 are formed through deposition, photolithography, and etching processes. Alternatively, the multiple conductive layers 91 and 92 can be formed from other materials or using other methods.

[0105] Multiple conductive layers 92 can also be used as wiring layers as electrodes for the drain region 3 and the source region 4.

[0106] Figure 10 This is a schematic cross-sectional view of a variation 6 of the semiconductor device according to Embodiment 3. Figure 10 and Figure 9 correspond. Figure 10 The semiconductor device 100 shown has substantially the same... Figure 9 The semiconductor device 100 shown has the same structure and can achieve the same effect, but it differs in that the semiconductor device 100 has an oxide film 12 and multiple conductive layers 93.

[0107] An oxide film 12 is disposed on the oxide film 7. The oxide film 12 covers multiple conductive layers 92 and the oxide film 7. Figure 10 As shown, no multiple conductive layers 91 are disposed on the insulating layer 10. The oxide film 12 can also be formed by thermal oxidation of silicon.

[0108] The wiring layer used as electrodes 8a and 8b can also be used as conductive layer 92. When viewed from above, one end of electrode 8a can also extend along the x-direction on the upper surface of oxide film 7, so that one end of electrode 8a overlaps with a portion of insulating layer 10. When viewed from above, one end of electrode 8c can also extend along the x-direction on the upper surface of oxide film 7, so that one end of electrode 8c overlaps with a portion of insulating layer 10.

[0109] Multiple conductive layers 93 are disposed between the first gate region 5 and the drain region 3 in the x-direction. The multiple conductive layers 93 are disposed separately from each other in the x-direction.

[0110] <Effects>

[0111] The semiconductor device 100 described above includes an insulating layer 10 and a plurality of conductive layers 91. The insulating layer 10 is disposed between the source region 4 and the drain region 3. The plurality of conductive layers 91 are disposed on the insulating layer 10. The plurality of conductive layers 91 are disposed separately from each other.

[0112] In this way, the multiple conductive layers 91 are capacitively coupled. As a result, the potential of the upper surface of the semiconductor device 100 is close to the potential of the first main surface 11. Thus, the withstand voltage of the semiconductor device 100 is improved.

[0113] Implementation method 4.

[0114] <Structure of Semiconductor Devices>

[0115] Figure 11 This is a schematic cross-sectional view of the semiconductor device 100 according to Embodiment 4. Figure 11 and Figure 10 correspond. Figure 11 The semiconductor device 100 shown has substantially the same... Figure 10 The semiconductor device 100 shown has the same structure and can achieve the same effect, but differs in that the conductive layer 94 has a vortex-like shape when viewed from above on the first main surface 11. Specifically, the conductive layer 94 is not a plurality of discontinuously formed conductive layers 91, but is formed integrally.

[0116] Within the vortex-shaped conductive layer 94, the end of the conductive layer 94 located closest to the drain region 3 is applied with the same potential as the drain region 3, and the end of the conductive layer 94 located closest to the source region 4 is applied with the same potential as the source region 4, thereby achieving the same effect as the semiconductor device 100 of Embodiment 3.

[0117] The material constituting the conductive layer 94 can be polycrystalline silicon or a conductor. Other conductive layers can also be disposed on the upper or lower part of the conductive layer 94.

[0118] <Effects>

[0119] The semiconductor device 100 described above includes an insulating layer 10 and a conductive layer 94. The insulating layer 10 is disposed between the source region 4 and the drain region 3. The conductive layer 94 is disposed on the insulating layer 10. When viewed from above on the first main surface 11, the conductive layer 94 has a vortex-like shape.

[0120] In this way, the potential of the conductive layer 94 changes continuously. As a result, the potential of the upper surface of the semiconductor device 100 is close to the potential of the first main surface 11. Thus, the withstand voltage of the semiconductor device 100 is improved.

[0121] Implementation method 5.

[0122] <Structure of Semiconductor Devices>

[0123] Figure 12 This is a schematic cross-sectional view of the semiconductor device 100 according to Embodiment 5. Figure 12 and Figure 1 correspond. Figure 12 The semiconductor device 100 shown has substantially the same... Figure 1 and Figure 2 The semiconductor device 100 shown has the same structure and achieves the same effect, but differs in that it has a second diffusion layer 13 with a second conductivity type. That is, the conductivity type of the second diffusion layer 13 is the same as that of the well region 2 and the same as that of the first diffusion layer 6. The concentration of impurities in the second diffusion layer 13 is greater than that of the well region 2.

[0124] The second diffusion layer 13 is formed inside the semiconductor substrate 1. The second diffusion layer 13 is formed by separating from the first main surface 11 along the z-direction.

[0125] In the process of forming the first diffusion layer 6, the second diffusion layer 13 can also be formed together with the first diffusion layer 6 using ion implantation. In this way, the second diffusion layer 13 can be formed in the same process as the process of forming the first diffusion layer 6, thereby shortening the manufacturing process of the semiconductor device 100 of this embodiment 5.

[0126] The second diffusion layer 13 is formed in the same process as the process of forming the first diffusion layer 6, so that the depth of the second diffusion layer 13 (the distance from the first main surface 11 to the lower end of the second diffusion layer 13 in the z direction) can also be the same as the depth of the first diffusion layer 6 (the distance from the first main surface 11 to the lower end of the first diffusion layer 6 in the z direction).

[0127] The second diffusion layer 13 includes a second peak concentration region 13a. The second peak concentration region 13a is the region with the highest concentration of impurities in the second diffusion layer 13. The distance from the first main surface 11 to the first peak concentration region 13a can be more than 0.9 times and less than 1.1 times the distance from the first main surface 11 to the second peak concentration region 13a, or it can be the same as the distance from the first main surface 11 to the second peak concentration region 13a.

[0128] The second diffusion layer 13 is closer to the drain region 3 than the first diffusion layer 6. That is, from a different viewpoint, the second diffusion layer 13 can also be positioned on the left side when viewed from the center A.

[0129] Thus, when the drain region 2 is depleted during the withstand voltage maintenance, the second diffusion layer 13 inhibits the extension of the depleted layer. Consequently, when the drain region 3... Figure 12 When the region on the left side of the circuit (the region opposite to the source region 4 when viewed from the drain region 3) forms the semiconductor circuit region, the effects generated by the depletion layer are suppressed.

[0130] <Effects>

[0131] The semiconductor device 100 described above includes a second diffusion layer 13 of a second conductivity type. The second diffusion layer 13 is formed by separating it from the first main surface 11. The concentration of impurities in the second diffusion layer 13 is greater than the concentration of impurities in the well region 2. The second diffusion layer 13 is closer to the drain region 3 than the first diffusion layer 6.

[0132] Thus, when the drain region 2 is depleted during the withstand voltage maintenance, the second diffusion layer 13 inhibits the extension of the depleted layer. Consequently, when the drain region 3... Figure 12 When the region on the left side of the circuit (the region opposite to the source region 4 when viewed from the drain region 3) forms the semiconductor circuit region, the effects generated by the depletion layer are suppressed.

[0133] According to the semiconductor device 100 described above, the first diffusion layer 6 includes a first peak concentration region 6a where the impurity concentration is highest. The second diffusion layer 13 includes a second peak concentration region 13a where the impurity concentration is highest. The distance from the first main surface 11 to the first peak concentration region 6a is more than 0.9 times and less than 1.1 times the distance from the first main surface 11 to the second peak concentration region 13a.

[0134] In this way, the second diffusion layer 13 can be formed in the same process as the process of forming the first diffusion layer 6, thus shortening the manufacturing process of the semiconductor device 100 of this embodiment 5.

[0135] Implementation method 6.

[0136] <Structure of Semiconductor Devices>

[0137] Figure 13 This is a schematic cross-sectional view of the semiconductor device 100 according to Embodiment 6. Figure 13 and Figure 1 correspond. Figure 13 The semiconductor device 100 shown has substantially the same... Figure 1 and Figure 2The semiconductor device 100 shown has the same structure and achieves the same effect, but differs in that it has a third diffusion layer 14 of the second conductivity type. That is, the conductivity type of the third diffusion layer 14 is the same as that of the well region 2 and the same as that of the first diffusion layer 6. The concentration of impurities in the third diffusion layer 14 is less than that of the impurities in the well region 2.

[0138] The third diffusion layer 14 is formed inside the well region 2. Specifically, the third diffusion layer 14 is formed on the first main surface 11. The third diffusion layer 14 is in contact with the first diffusion layer 6. The third diffusion layer 14 is disposed between the source region 4 and the first gate region 5. The third diffusion layer 14 can be in contact with or separate from the source region 4 or the first gate region 5.

[0139] By forming a third diffusion layer 14, the depletion layer near the third diffusion layer 14 can easily extend when disconnected. Therefore, leakage current is further suppressed when disconnected.

[0140] <Effects>

[0141] According to the semiconductor device 100 described above, a third diffusion layer 14 of a second conductivity type is provided. The third diffusion layer 14 is disposed between the source region 4 and the first gate region 5. The concentration of impurities in the third diffusion layer 14 is less than the concentration of impurities in the well region 2.

[0142] In this way, the depletion layer near the third diffusion layer 14 can easily extend when disconnected. Therefore, the leakage current is further suppressed when disconnected.

[0143] Implementation method 7.

[0144] <Structure of Semiconductor Devices>

[0145] Figure 14 This is a schematic cross-sectional view of the semiconductor device 100 according to Embodiment 7. Figure 14 and Figure 1 correspond. Figure 14 The semiconductor device 100 shown has substantially the same... Figure 1 and Figure 2 The semiconductor device 100 shown has the same structure and can achieve the same effect, but the difference is that the semiconductor device 100 has a second gate region 54 of the first conductivity type. That is, the conductivity type of the second gate region 54 is the same as that of the first gate region 5.

[0146] The second gate region 54 is formed inside the semiconductor substrate 1. Specifically, the second gate region 54 is formed on the first main surface 11. The second gate region 54 is disposed inside the well region 2. An electrode 8d is connected to the upper surface of the second gate region 54 in the region exposed from the oxide film 7.

[0147] The second gate region 54 is located opposite to the drain region 3 when viewed from the source region 4. That is, the second gate region 54 is located opposite to the first gate region 5 when viewed from the source region 4.

[0148] By forming a second gate region 54, the depletion layer near the second gate region 54 can easily extend when disconnected. Therefore, leakage current is further suppressed when disconnected.

[0149] Figure 15 This is a schematic top view of the semiconductor substrate 1 in Embodiment 7. Figure 15 and Figure 2 Corresponding. For example... Figure 15 As shown, the first gate region 5 and the second gate region 54 can also be arranged on the outer periphery of the source region 4. Specifically, when viewed from above on the first main surface 11, the shape of the first gate region 5 can also be C-shaped. The first gate region 5 includes a first portion extending along the y-direction and a pair of second portions extending along the x-direction. The first portion is separated from the source region 4 in the x-direction. Each of the pair of second portions is separated from the source region 4 in the y-direction. One end of each of the pair of second portions can also contact the second gate region 54.

[0150] Figure 16 This is a schematic top view of a variation of Example 7 in the semiconductor substrate 1 of Embodiment 7. (As shown) Figure 16 As shown, one end of each of the pair of second portions can also be separated from the second gate region 54 in the x direction. That is, the first gate region 5 and the second gate region 54 can also be separated from each other.

[0151] The voltages applied to the first gate region 5 and the second gate region 54 can be the same or different. When the voltages applied to the first gate region 5 and the second gate region 54 are different, leakage current can be suppressed without reducing the current value between the drain region 3 and the source region 4 when the circuit is turned on.

[0152] <Effects>

[0153] The semiconductor device 100 described above includes a second gate region 54 of a first conductivity type. The second gate region 54 is formed on the first main surface 11. When viewed from the source region 4, the second gate region 54 is located opposite to the drain region 3. The second gate region 54 is disposed inside the well region 2.

[0154] Thus, by forming a second gate region 54, the depletion layer near the second gate region 54 can easily extend when the gate is turned off. Therefore, leakage current during disconnection is further suppressed.

[0155] According to the semiconductor device 100 described above, the voltages applied to the first gate region 5 and the second gate region 54 are different from each other.

[0156] In this way, leakage current can be suppressed without reducing the resistance between the drain region 3 and the source region 4 when the circuit is turned on.

[0157] Implementation method 8.

[0158] <Structure of Semiconductor Devices>

[0159] Figure 17 This is a schematic cross-sectional view of the semiconductor device 100 according to Embodiment 8. Figure 17 and Figure 16 correspond. Figure 17 The semiconductor device 100 shown has substantially the same... Figure 15 and Figure 16 The semiconductor device 100 shown has the same structure and achieves the same effect, but differs in that it has a fourth diffusion layer 15 of the second conductivity type. That is, the conductivity type of the fourth diffusion layer 15 is the same as that of the well region 2 and the same as that of the first diffusion layer 6. The concentration of impurities in the fourth diffusion layer 15 is less than that of the impurities in the well region 2.

[0160] A fourth diffusion layer 15 is formed inside the well region 2. Specifically, the fourth diffusion layer 15 is formed on the first main surface 11. The fourth diffusion layer 15 is in contact with the first diffusion layer 6. The fourth diffusion layer 15 is disposed between the source region 4 and the second gate region 54. The fourth diffusion layer 15 can be in contact with or separate from the source region 4 or the second gate region 54.

[0161] By forming a fourth diffusion layer 15, the depletion layer near the fourth diffusion layer 15 tends to extend when disconnected. Therefore, leakage current is further suppressed when disconnected.

[0162] <Effects>

[0163] The semiconductor device 100 described above includes a fourth diffusion layer 15 of a second conductivity type. The fourth diffusion layer 15 is disposed between the source region 4 and the second gate region 54. The concentration of impurities in the fourth diffusion layer 15 is less than the concentration of impurities in the well region 2.

[0164] In this way, the depletion layer near the fourth diffusion layer 15 can easily extend when disconnected. Therefore, the leakage current is further suppressed when disconnected.

[0165] Implementation method 9.

[0166] <Structure of Semiconductor Devices>

[0167] Figure 18 This is a schematic diagram of the semiconductor chip 200 according to embodiment 9. Figure 18The semiconductor chip 200 shown includes: a wafer 19, a first semiconductor circuit region 16, a second semiconductor circuit region 17, and a semiconductor device 100 according to any one of embodiments 1 to 8. The first semiconductor circuit region 16, the second semiconductor circuit region 17, and the semiconductor device 100 are formed on the wafer 19. The second semiconductor circuit region 17 is disposed separately from the first semiconductor circuit region 16. The second semiconductor circuit region 17 operates at a reference potential different from the reference potential of the first semiconductor circuit region 16. The semiconductor device 100 is formed on the outer periphery of the second semiconductor circuit region 17.

[0168] In this way, the first semiconductor circuit region 16 and the second semiconductor circuit region 17 can be separated into the voltage withstand capability of the semiconductor device 100. As a result, the characteristics of the semiconductor chip 200 are improved.

[0169] The semiconductor chip 200 of this embodiment 9 can also be used, for example, as a semiconductor chip constituting a gate driver IC (Integrated Circuit) for operating power devices.

[0170] Furthermore, the semiconductor chip 200 according to Embodiment 9 can maintain voltage resistance and signal transmission in the outer peripheral region of the second semiconductor circuit region 17.

[0171] <Effects>

[0172] The semiconductor chip 200 disclosed herein includes: a first semiconductor circuit region 16, a second semiconductor circuit region 17, and the aforementioned semiconductor device 100. The second semiconductor circuit region 17 operates at a reference potential different from the reference potential of the first semiconductor circuit region 16. The semiconductor device 100 is disposed on the outer periphery of the second semiconductor circuit region 17.

[0173] Thus, the semiconductor chip 200 is used as a semiconductor chip constituting a gate driver IC (Integrated Circuit) for operating power devices. Furthermore, the semiconductor chip 200 can have voltage withstand and signal transmission functions in the outer peripheral region of the second semiconductor circuit region 17.

[0174] Implementation Method 10.

[0175] <Structure of Semiconductor Devices>

[0176] Figure 19 This is a schematic diagram of the semiconductor circuit of embodiment 10. Figure 19The semiconductor circuit shown includes: a power supply 20, a bootstrap capacitor 21, and a semiconductor device 100 according to any one of embodiments 1 to 8. The power supply 20 and the bootstrap capacitor 21 are connected to the semiconductor device 100.

[0177] Power supply 20 activates the drive circuit. Bootstrap capacitor 21 operates as an alternative to power supply 20. By assembling semiconductor device 100 into this semiconductor circuit, semiconductor device 100 includes both current regulation and anti-reverse current functions. That is, semiconductor device 100 operates as an alternative to bootstrap resistor and bootstrap diode. Thus, the semiconductor circuit including semiconductor device 100 can also function as a bootstrap circuit. As a result, the structure of the semiconductor circuit is simple.

[0178] <Effects>

[0179] The semiconductor circuit disclosed herein includes the aforementioned semiconductor device 100 and a bootstrap capacitor 21 connected to the semiconductor device 100.

[0180] In this way, the semiconductor device 100 can be used as a replacement for the bootstrap resistor and bootstrap diode. As a result, the semiconductor circuit including the semiconductor device 100 functions as a simple bootstrap circuit.

[0181] Embodiments of the invention have been described, but the embodiments disclosed herein should be considered illustrative rather than restrictive in all respects. The scope of the invention is set forth in the claims and is intended to include all equivalents thereof and all modifications thereof.

Claims

1. A semiconductor device, characterized in that, have: A semiconductor substrate of a first conductivity type has a first main surface; A second type of conductive well region is formed on the first main surface; The source region of the second conductivity type is formed on the first main surface; A drain region of a second conductivity type is formed on the first main surface and is disposed separately from the source region; A first gate region of a first conductivity type is formed on the first main surface and disposed between the source region and the drain region; as well as The first diffusion layer of the second conductivity type is formed by separating it from the first main surface. The source region, the drain region, and the first gate region are respectively disposed inside the well region. The concentration of impurities in the first diffusion layer is greater than the concentration of impurities in the well region. The first gate region is closer to the source region than the drain region. The first diffusion layer is closer to the source region than the drain region.

2. The semiconductor device according to claim 1, characterized in that, When viewed from above, the first diffusion layer overlaps with the first gate region.

3. The semiconductor device according to claim 2, characterized in that, When viewed from above, the first diffusion layer overlaps with the source region.

4. The semiconductor device according to any one of claims 1 to 3, characterized in that, The first diffusion layer includes a first peak concentration region where the impurity concentration is highest. When viewed from above, the first peak concentration region overlaps with the first gate region.

5. The semiconductor device according to any one of claims 1 to 4, characterized in that, The first gate region has a first gate end that is closest to the drain region. The first diffusion layer includes a first peak concentration region where the impurity concentration is highest. When viewed from the first gate end, the first peak concentration region is located opposite to the drain region.

6. The semiconductor device according to any one of claims 1 to 5, characterized in that, Multiple different potentials are applied to the first gate region.

7. The semiconductor device according to any one of claims 1 to 6, characterized in that, The first diffusion layer has: a first diffusion layer end closest to the drain region and a second diffusion layer end closest to the source region. The concentration of impurities in the first diffusion layer increases from the end of the first diffusion layer toward the end of the second diffusion layer.

8. The semiconductor device according to any one of claims 1 to 7, characterized in that, have: An insulating layer disposed between the source region and the drain region; and Multiple conductive layers are disposed on top of the insulating layer. The multiple conductive layers are arranged separately from each other.

9. The semiconductor device according to any one of claims 1 to 8, characterized in that, have: An insulating layer disposed between the source region and the drain region; and A conductive layer is disposed on top of the insulating layer. When viewed from above, the conductive layer has a vortex-like shape.

10. The semiconductor device according to any one of claims 1 to 9, characterized in that, A second diffusion layer having a second conductivity type is formed by separating it from the first main surface. The concentration of impurities in the second diffusion layer is greater than the concentration of impurities in the well region. The second diffusion layer is closer to the drain region than the first diffusion layer.

11. The semiconductor device according to claim 10, characterized in that, The first diffusion layer includes a first peak concentration region where the impurity concentration is highest. The second diffusion layer includes a region with the highest peak concentration of impurities. The distance from the first master surface to the first peak concentration region is more than 0.9 times and less than 1.1 times the distance from the first master surface to the second peak concentration region.

12. The semiconductor device according to any one of claims 1 to 11, characterized in that, A third diffusion layer having a second conductivity type is disposed between the source region and the first gate region. The concentration of impurities in the third diffusion layer is less than the concentration of impurities in the well region.

13. The semiconductor device according to any one of claims 1 to 12, characterized in that, A second gate region having a first conductivity type is formed on the first main surface and, when viewed from the source region, is located opposite to the drain region. The second gate region is disposed inside the well region.

14. The semiconductor device according to claim 13, characterized in that, The voltages applied to the first gate region and the second gate region are different from each other.

15. The semiconductor device according to claim 13 or 14, characterized in that, A fourth diffusion layer of a second conductivity type is disposed between the source region and the second gate region. The concentration of impurities in the fourth diffusion layer is less than the concentration of impurities in the well region.

16. A semiconductor chip, characterized in that, have: First semiconductor circuit region; A second semiconductor circuit region operates at a reference potential different from that of the first semiconductor circuit region; and The semiconductor device according to any one of claims 1 to 15, The semiconductor device is disposed on the outer periphery of the second semiconductor circuit region.

17. A semiconductor circuit, characterized in that, have: The semiconductor device according to any one of claims 1 to 15; and A bootstrap capacitor is connected to the semiconductor device.

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