Semiconductor device

Abstract

In one aspect, a semiconductor device is provided, comprising: first and second power rail structures extending in parallel, each comprising a bottom power rail and a top power rail disposed above the bottom power rail; a first row and a second row of complementary field effect transistor (CFET) devices extending in parallel with the first and second power rail structures; a row of local interconnects disposed between and extending in parallel with the first and second rows of CFET devices; a logic cell comprising at least one CFET device of the first row of CFET devices configured to implement a first logic gate and a first local interconnect of the row of local interconnects; and at least one CFET device of the second row of CFET devices configured to implement a second logic gate and a second local interconnect of the row of local interconnects.

Description

Technical Field

[0001] This invention generally relates to semiconductor devices, and more particularly to semiconductor devices comprising rows of complementary field-effect transistors. Background Technology

[0002] A complementary field-effect transistor (CFET) is a stacked transistor structure consisting of a bottom transistor and a top transistor stacked on top of the bottom transistor. The bottom and top transistors (or bottom and top devices) have complementary conductivity types (e.g., an NMOS device stacked on top of a PMOS device, or vice versa). CFETs therefore allow for a smaller coverage area compared to the traditional side-by-side arrangement of complementary transistor pairs. Thus, CFETs are a technique for achieving denser and more area-efficient circuits.

[0003] The standard cell approach enables circuit designers to efficiently design integrated circuits (ICs) by combining circuit cells, such as standard cells (SDCs) from a standard cell library. Each standard cell in the standard cell library can include a set of active devices (e.g., transistors such as CFETs) and associated metal interconnects, and is configured to provide a specific circuit function. Much of the IC's functionality is provided by logic cells, such as implementing various logic gates (e.g., NOT, AND, OR, NOR, etc.).

[0004] To improve the device density and performance of ICs, significant efforts have been made to advance design and process technologies to reduce the cell height and area of ​​standard logic cells, and to optimize the use of wiring resources in the interconnect layers above the cell area (such as the "M0" interconnect layer) to alleviate wiring congestion and reduce the standard cell track height. Summary of the Invention

[0005] However, as the inventors recognized, a challenge in further scaling the cell height and cell area of ​​CFET-based logic cells lies in the fact that conventional CFET-based logic cell designs typically include a pair of power rails on either side of each row of CFETs for powering the bottom and top transistor layers (VSS and VDD). Therefore, the space between adjacent CFET rows needs to accommodate interconnects (e.g., vertical connections, such as vias) for connecting the bottom and top transistors along that row of CFETs to their associated power rails, and for routing signals to and / or between the bottom and top transistor layers. This can lead to inter-row wiring congestion and limit the possibility of scaling the height of the circuit cell (measured in the row direction).

[0006] In view of the above, the object of the present invention is to provide a semiconductor device and logic unit having a design utilizing a CFET, but avoiding or mitigating the aforementioned problems. Further and alternative objectives will be understood from the following.

[0007] According to a first aspect of the present invention, a semiconductor device is provided, comprising:

[0008] The first and second power rail structures extend in parallel, each power rail structure including a bottom power rail and a top power rail disposed above the bottom power rail;

[0009] A row of local interconnects is arranged between and extends parallel to the first and second rows of CFET devices;

[0010] First and second rows of complementary field-effect transistor (CFET) devices extending parallel to first and second power rail structures, wherein the first row of CFET devices is arranged between the first power rail structure and the row of local interconnects, and the second row of CFET devices is arranged between the second power rail structure and the row of local interconnects.

[0011] Logic unit, including

[0012] At least one CFET device in the first row of CFET devices is configured to implement a first logic gate, and a first local interconnect in the row of local interconnects is configured to interconnect the top and bottom source / drain S / D of the first CFET device in the first row of CFET devices; and

[0013] The second row of CFET devices includes at least one CFET device configured to implement a second logic gate, and the second local interconnect in this row of local interconnects is configured to connect the top and bottom S / D interconnects of the second CFET device in at least one of the CFET devices in the second row of CFET devices.

[0014] The first logic gate is connected to the first input and output pins of the logic unit, and the second logic gate is connected to the second input and output pins of the logic unit.

[0015] The first power rail structure is configured to power the first logic gate, and the second power rail structure is configured to power the second logic gate.

[0016] In contrast to conventional CFET-based circuit implementations, this semiconductor device includes a pair of “stacked” power rail structures on either side of a pair of CFET device rows. Since each power rail structure includes a bottom power rail and a top power rail stacked above the bottom power rail, the bottom and top transistors of the CFET devices in the first and second rows of CFET devices (hereinafter interchangeably referred to as “first and second CFET rows”) can be powered from one side, rather than from both sides as in conventional implementations. Therefore, the space or “track” between the two CFET rows, which in conventional implementations would be used to provide power and signals between the bottom and top transistors of the first and second CFET rows, can thus be used here to accommodate a row of local interconnects for bottom and top S / D interconnects of the bottom and top transistors of the respective CFET rows. Consequently, contention between power wiring and signal routing within a given logic cell along each row of CFET devices can be avoided.

[0017] This configuration of a pair of consecutively stacked power rails surrounding a pair of first and second rows of CFET devices is referred to below as a “dual-row configuration” or “dual-row CFET”, and thus enables the reduction of wiring congestion between the first and second rows of CFETs, which in turn facilitates scaling of cell height and low rail height for implementing logic cells such as standard logic cells.

[0018] The semiconductor device in the first aspect further utilizes this dual-row configuration, wherein the logic cell uses one or more CFET devices in the first CFET row to implement the first logic gate, and uses one or more CFET devices in the second CFET row to implement the second logic gate. Therefore, two functionally independent logic gates can be implemented within the same logic cell, the cell height of which spans the width of the dual-row configuration (i.e., corresponding to the spacing between the first and second power rail structures).

[0019] In some embodiments, the bottom power rail is disposed in the bottom transistor layer of the bottom transistor including the first and second rows of CFET devices, or disposed in the back interconnect layer, and / or wherein the top power rail is disposed in the top transistor layer including the first and second rows of CFET devices.

[0020] Therefore, the bottom and top power rails do not need to significantly contribute to wiring congestion in the interconnect layer of the front interconnect structure above the top transistor layer. Instead, the bottom and top transistors of a CFET device along any given CFET row can be simply coupled to the adjacent bottom or top power rail by the lateral extension of their S / D contact portions (i.e., laterally to the row direction) to truncate the respective power rail structure. The first and second power rail structures can advantageously be aligned with the first and second cell boundaries of the logic cell. Thus, the S / D contact portions can extend to overlap with the first or second cell boundary.

[0021] In some embodiments, the logic unit further includes:

[0022] A first S / D contact structure includes a bottom S / D contact portion that contacts the bottom S / D of a first CFET device, a top S / D contact portion that contacts the top S / D of the first CFET device, and a first partial interconnect that interconnects the bottom and top S / D contact portions; and

[0023] The second S / D contact structure includes a bottom S / D contact portion that contacts the bottom S / D of the second CFET device, a top S / D contact portion that contacts the top S / D of the second CFET device, and a second partial interconnect that interconnects the bottom and top S / D contact portions.

[0024] Therefore, bottom-top S / D interconnects can be achieved by interconnecting the corresponding bottom and top S / D contact portions with corresponding local interconnects in the local interconnects arranged between the first and second CFET rows.

[0025] One advantage of using this row of local interconnects to achieve bottom-up S / D interconnects is that it eliminates the need for a vertically arranged "S / D contact merging layer" between the bottom and top S / D contact portions, which could introduce additional complexity during manufacturing, especially at drastically scaled cell heights. Therefore, the bottom and top S / D contact portions can be vertically spaced apart, with interconnect segments arranged laterally adjacent to and abutting the bottom and top S / D contact portions to interconnect them.

[0026] In some embodiments, a first S / D contact structure is connected to a first output pin of the logic cell, and a second S / D contact is connected to a second output pin of the logic cell. Therefore, the corresponding interconnect S / D features of the first CFET device and the second CFET device can be configured as corresponding output nodes of the first and second logic gates.

[0027] In some embodiments, each CFET device includes a gate shared by the bottom and top transistors of the respective CFET device and connected to a corresponding input pin of a logic cell. Therefore, the respective gates of the first and second CFET devices can be configured as the respective input nodes of the first and second logic gates.

[0028] In some embodiments, the first logic gate is implemented by N ≥ 1 CFET devices in the first row of CFET devices, and the second logic gate is implemented by N CFET devices in the second row of CFET devices. Therefore, the first and second logic gates can be implemented by the same number of CFET devices in their respective rows. For example, the first logic gate can be implemented by one CFET device in the first CFET row, and the second logic gate can be implemented by one CFET device in the second CFET row. As another example, the first logic gate can be implemented by two CFET devices in the first CFET row, and the second logic gate can be implemented by two CFET devices in the second CFET row. It should be noted that at least one CFET device in the corresponding row / logic gate of the logic cell is arranged directly opposite to each other.

[0029] In some embodiments, at least one CFET device of the first logic gate and at least one CFET device of the second logic gate are arranged in corresponding half-cells of the logic cell, wherein the cell width of each half-cell corresponds to (N+1) times the contact polysilicon pitch (CPP) of the CFET device. Therefore, the first and second logic cells can be implemented in corresponding half-cells of equal cell width. In this disclosure, "arranging CFET devices in corresponding "half-cells" of the logic cell" means that at least one CFET device of the first logic gate and at least one CFET device of the second logic gate are arranged in corresponding (non-overlapping) sub-cells having equal coverage areas corresponding to half-coverage areas of the logic cell.

[0030] In some embodiments, each half-cell includes a corresponding pair of dummy gates, wherein N CFET devices for each logic gate are arranged between the corresponding pair of dummy gates. Therefore, the first and second output pins of the logic cell (and thus the corresponding output nodes of the first and second logic gates) do not need to be shared with adjacent logic cells arranged along the CFET bar next to that logic cell.

[0031] In some embodiments, the number of CFETs per logic gate is N≥2, wherein the logic cell includes a corresponding back-side signal track aligned with each row of the first and second rows of CFET devices, and each back-side signal track includes a pair of metal lines interconnecting a pair of non-adjacent S / D interconnects of a pair of CFET devices in the corresponding CFET device row. Therefore, intra-cell signal transfer between S / D connections spaced apart by the gates of one or more CFET devices can be provided by the back-side signal tracks. Thus, intra-cell S / D connectivity can be provided without increasing routing congestion in the front-side interconnect structure.

[0032] In some embodiments, the first and second logic gates are the same logic gate. The first and second logic gates being the same logic gate here means that they perform the same logic / Boolean function.

[0033] In some embodiments, the circuit layout of the logic cell is point-symmetric. That is, the circuit layout (i.e., the layout of the CFET device, the gate of the CFET device, local interconnects, S / D contacts, etc.) is symmetric about the center point of the logic cell (i.e., rotationally symmetric about the center of the logic cell). This means that the logic cells can implement the first and second identical logic gates in corresponding half-cells having the same but rotated layout (e.g., rotated 180 degrees relative to each other).

[0034] In some embodiments, the first and second logic gates are inverter (NOT) gates, NAND gates, NOR gates, AND gates, or OR gates. Therefore, a logic cell can be implemented as a multi-bit NOT, NAND, NOR, AND, or OR gate by including two such gates within the coverage area of ​​the logic cell, each logic gate being connected to a corresponding input and output pin of the logic cell.

[0035] In some embodiments, the first logic gate is implemented by N = 1 CFET devices in the first row of CFET devices, and the second logic gate is implemented by N = 1 CFET devices in the second row of CFET devices, and the first and second logic gates are inverter gates. Therefore, a logic cell can implement two NOT gates using a single CFET device in each row of CFETs.

[0036] In some embodiments, the first logic gate is implemented by N = 2 CFET devices in the first row of CFET devices, and the second logic gate is implemented by N = 2 CFET devices in the second row of CFET devices. The first and second logic gates are AND, OR, NOR, or NAND gates, and N = 2. Therefore, a logic cell can implement two AND, OR, NOR, or NAND gates using two CFET devices in each row of CFETs. Attached Figure Description

[0037] The foregoing contents, additional objects, embodiments, features, and advantages of this disclosure can be better understood through the following illustrative and non-limiting detailed description with reference to the accompanying drawings. Unless otherwise stated, the same reference numerals will be used for the same elements in the drawings.

[0038] Figure 1 An example of two rows of CFETs in a dual-row configuration is illustrated schematically.

[0039] Figure 2 Another example of two rows of CFETs in a dual-row configuration is illustrated schematically.

[0040] Figure 3 A top view of a semiconductor device including a dual-row CFET is shown schematically according to an example.

[0041] Figure 4A logic cell comprising a dual-row CFET implementing a single inverter gate is schematically shown (as a comparative example).

[0042] Figure 5 A logic cell comprising a dual-row CFET that implements two inverter gates is schematically shown.

[0043] Figure 6a -b respectively shows Figure 5 Example circuit layout of the top and bottom transistor layers of the logic unit.

[0044] Figure 7 A logic cell comprising a dual-row CFET that implements two NAND gates is schematically shown.

[0045] Figure 8a -c indicates Figure 7 Example circuit layout of the top and bottom transistor layers of the logic unit.

[0046] Figure 9a -c schematically illustrates an additional example of a logic cell that includes a dual-row CFET and implements two identical logic gates. Detailed Implementation

[0047] The following detailed description of an example implementation of a logic cell (such as a standard logic cell) based on a so-called dual-row configuration / dual-row CFET is provided with reference to the accompanying drawings. The drawings are schematic only, and the relative dimensions of the elements (such as layers or other structures) shown may be exaggerated and are not drawn to scale. Instead, dimensions may be adjusted to make the illustration clear and easy to understand. When present in the drawings, the indicated axes X, Y, and Z point to a first horizontal direction, a second horizontal direction, and a vertical direction, respectively. It is evident from the drawings that the X direction corresponds to the width dimension of the logic cell (cell width) and the extension direction of the CFET row and local interconnect rows (i.e., the "row direction"). The X direction is also the extension direction of the power rail structure and the wiring rails shown. The Y direction corresponds to the height dimension of the logic cell (cell height) transverse to the first / row direction X. The term "horizontal" herein means a direction parallel to the main extension plane of the active device layer or the active device layer including semiconductor devices (e.g., CFET devices). In the case where the semiconductor device includes a substrate, the term "horizontal" can be equivalently understood as a direction parallel to the substrate, i.e., parallel to the main surface (e.g., the front side) of the substrate. The term "lateral" refers to a horizontal direction, typically laterally to the X-direction. The term "horizontal" is equivalently understood as a direction parallel to the coverage area / region of a logic cell. The term "vertical" in this document refers to a direction perpendicular or laterally to the horizontal XY plane, or equivalently, perpendicular or laterally to the active device layer or substrate. Therefore, terms indicating the relatively vertical arrangement of elements, such as "top," "upper," "bottom," "lower," etc., should be understood as relating to the vertical direction. It should be noted that when an element (e.g., an interconnect, contact, layer, or other structure) is referred to as "on another element," it can be directly on the other element or on one or more intermediate elements on the other element. Conversely, when an element is referred to as "directly on another element," there are no intermediate elements, and therefore the element is adjacent (i.e., in physical contact) to the other element. It should also be noted that, unless otherwise stated, terms related to elements (e.g., layers or other structures), such as "first" and "second," etc., may be used herein as labels to facilitate the distinction of different elements and do not necessarily imply that these elements are arranged or implemented in a particular order. Furthermore, the term "CFET" or "CFET device" herein refers to a device, more specifically, a stacked transistor device, comprising a bottom transistor of a first conductivity type and a top transistor of a second conductivity type opposite to the first conductivity type stacked on / above the bottom transistor, such as an NMOS top device stacked on a PMOS bottom device, and vice versa. More specifically, the top device is at least substantially disposed within the coverage area of ​​the bottom device. The bottom transistor is included in a bottom transistor layer of the semiconductor device / logic cell, and the top device is included in a top transistor layer of the semiconductor device / logic cell. Both the bottom and top transistor layers are included in an active device layer.

[0048] As mentioned above, the logic cells to be disclosed below are based on dual-row CFETs. Reference will now be made to... Figure 1-2 Discuss an example of a dual-row CFET.

[0049] Figure 1 Examples of two corresponding first and second CFET devices 110, 112 of semiconductor device 100 are schematically shown. CFET devices 110, 112 are dual-row CFETs and are thus included in corresponding CFET rows 101, 102 extending parallel in the X direction along the substrate (not shown separately) of semiconductor device 100. Each CFET device 110, 112 includes a bottom transistor 120 and a top transistor 130 stacked on top of the bottom transistor 120. The bottom transistor 120 is included in a bottom transistor layer 100B, and the top transistor 130 is included in a top transistor layer 100T.

[0050] Figure 1 The view is a partial cross-sectional projection to allow simultaneous viewing of the corresponding S / D (i.e., S / D region or feature) and channel regions of CFET devices 110 and 112. The following will primarily refer to CFET device 110, but may also include references to other devices. Figure 1 As shown, the discussion applies accordingly to other CFET devices 120.

[0051] As shown in the figure, the bottom transistor 120 includes a bottom S / D 124 (e.g., an epitaxial S / D body) and a bottom channel structure 122 (e.g., one or more stacked nanosheets, typically based on Si or SiGe). The bottom channel structure 122 is located between the bottom S / D 124 and the bottom channel structure 122. Figure 1 The bottom S / D region on the opposite side of the bottom channel structure 122 behind the plane shown extends along the X direction.

[0052] As shown, the top transistor 130 includes corresponding features, namely a top S / D 134 and a top channel structure 132 (e.g., one or more stacked nanosheets) extending in the X direction between the top S / D region 12a and the opposite top S / D.

[0053] CFET 110 also includes a gate 140 shared by bottom transistor 120 and top transistor 130. Gate 140 is arranged to surround bottom and top channel structures 122, 132 along the channel region, for example, in a gate-around-all (GAA) manner.

[0054] CFET device 110 also includes an S / D contact structure comprising a bottom S / D contact portion or contact portion 126 electrically connected (through adjacency) to a bottom S / D 124, and a top S / D contact portion or contact portion 136 electrically connected (through adjacency) to a top S / D 134. The top S / D contact portion 136 is perpendicularly separated from the bottom S / D contact portion 126. The bottom and top S / D contact portions 126, 136, and the bottom and top S / D 124, 134, may be perpendicularly separated in the Z direction, for example, through an intermediate insulating layer portion (e.g., an interlayer dielectric such as silicon oxide), as schematically shown. Figure 1 In the diagram, the bottom S / D contact portion 126 is shown as a layered feature adjacent to the bottom S / D 124 from below. However, this is only an example, and the bottom S / D contact portion 126 can also be formed to completely or partially surround the bottom S / D 124. This applies accordingly to the top S / D contact portion 136. The bottom S / D contact portion 126 can also be referred to as bottom metal diffusion (sometimes denoted as "BMD"), while the top S / D contact portion 136 can be referred to as top metal diffusion (sometimes denoted as "MD"). The bottom S / D contact portion 126 can advantageously be formed during back-side processing after front-side processing (e.g., including CFET device fabrication, formation of the L1 bus 180 (discussed below), patterning of the top transistor S / D contact portion, and fabrication of the front-side interconnect structure).

[0055] Two CFET rows 101, 102 are surrounded by a pair of first and second power rail structures 150, 160 extending along opposite sides of the CFET rows 101, 102. Thus, the CFET rows 101, 102 are arranged between and extend parallel to the first and second power rail structures 150, 160.

[0056] Each power rail structure 150, 160 includes bottom power rails 152, 162 and top power rails 154, 164 stacked above the respective bottom power rails 152, 162 at a vertical height above them. Thus, each top power rail 154, 164 is at least substantially arranged within the coverage area of ​​its associated bottom power rail 152, 162. Bottom power rails 152, 162 can be configured as pull-up voltage rails (VDD), and top power rails 154, 164 can be configured as pull-down voltage rails (VSS), and vice versa (depending on the channel type of the bottom and top transistors 120, 130), such that each power rail structure 150, 160 can provide pull-up and pull-down voltages to the CFETs in adjacent CFET rows 101, 102. Thus, each CFET device 110, 120 can be powered from one side (i.e., the respective outer side of row 101, 102).

[0057] According to the dual-row CFET design, the space between the first and second CFET rows 101, 102 accommodates a row of local interconnects (LI) 180, one such LI 180 in Figure 1 As can be seen, the LI bus 180 is arranged between and extends parallel to the first and second CFET buses 101, 102. More specifically, the first CFET bus 101 is arranged between the first power rail structure 150 and the LI bus 180. The second CFET bus 102 is arranged between the second power rail structure 150 and the LI bus 180. The LIs shown (and any number of other LIs in the LI bus 180) are arranged as shown between the bottom transistor layer 100B and the top transistor layer 100T, i.e., extending between them. The LI bus 180 is substantially centered between the CFET buses 101, 102 and the power rail structures 150, 160. The LIs 180 are distributed in the X direction. The LIs 180 can be substantially cylindrical or wall-shaped and vertically oriented metal interconnects. As shown, the LIs 180 have a vertical extension (in the Z direction) that matches the combined vertical extension of the bottom and top transistor layers 100B, 100T. In other words, each LI 180 extends vertically between the bottom (bottom portion) of the bottom transistor layer 100B or its vertically aligned portion and the top (top portion) of the top transistor layer 100T or its vertically aligned portion. This contrasts with conventionally used "high-pass vias," which are formed to extend continuously from the M0 interconnect layer to the bottom layer 100B, or from the top layer 100T to the back interconnect layer BMO. Therefore, high-pass vias have a greater height and aspect ratio than LI 180, thus introducing additional complexity in the manufacturing process. The LI row 180 can extend continuously between CFET rows 101 and 102, along their entire length or along a portion of them (segments). Any LI in the LI row 180 can be coupled to one or more bottom and / or top transistors of the first row of CFET 101 or the second row of CFET 102. Figure 1This is illustrated as an example for CFET device 101, where the bottom S / D contact portion 126 extends laterally to be electrically connected (through adjacency) to LI 180. Correspondingly, the top S / D contact portion 136 extends laterally to be electrically connected (through adjacency) to LI 180. As shown, the top S / D contact portion 136 can extend laterally to contact LI 180 from the side (i.e., adjaculate the sidewall of LI 180). As shown, the bottom S / D contact portion 126 can extend laterally into the coverage area of ​​the row of LI 180 (i.e., undercut the row of LI 180) so that LI 180 can contact or rest on the bottom S / D contact portion 126 from above. The lateral extension of the bottom S / D contact portion 126 can also be associated with the back or front center track BMO-3 or MO-4 (discussed below). That is, the bottom S / D contact portion 126 can extend laterally into the back or front center track BMO-3 or MO-4. However, the specific configuration can vary depending on the manufacturing process. For example, the connection between LI 180 and the bottom S / D contact portion 126 can be achieved by forming LI 180 as a vertical projection into the layer of the bottom S / D contact portion 126, so that the bottom S / D contact portion 126 can contact LI 180 from the side (i.e., adjacent to the sidewall of LI 180). Furthermore, although in Figure 1 The bottom S / D contact portion 126 is schematically shown as a single integral contact body that contacts the bottom S / D 124, but the bottom S / D contact portion 126 may include a first sub-portion adjacent to the bottom S / D 124 and a second sub-portion adjacent to the first sub-portion from below. Therefore, lateral connection with the LI 180 can be achieved by arranging the second sub-portion to extend between the first sub-portion and LI 180. In the case where the bottom S / D contact portion 126 is formed during back-side processing, the second sub-portion can typically be formed after the first sub-portion is formed.

[0058] Figure 1Further, a set of M0 tracks (M0-1 to M0-7) of the bottom interconnect layer (“M0”) of the front interconnect structure of semiconductor device 100 is represented by a dashed outline rectangle. The M0 tracks are arranged with a uniform spacing along the Y direction. The reference numeral BM0 correspondingly represents a set of BM0 tracks (BM0-1 to BM0-5) of the bottom BM0 layer of the back interconnect structure of semiconductor device 100. The BM0 tracks are arranged with a uniform spacing along the Y direction. Here, the designation “bottom” for M0 and BM0 layers means that M0 and BM0 layers are the interconnect layers (i.e., active device layers) of the front and back interconnect structures closest to the substrate and CFET devices, respectively. An M0 track can be a track associated with or belonging to a logic cell defined along CFET rows 101, 102, while a BM0 track can correspondingly be a track associated with or belonging to that logic cell. The term "front interconnect structure" herein refers to a vertically stacked interconnect structure (e.g., a line-back-end interconnect structure) including interconnect layers (e.g., M0, M1, M2, etc.) disposed on the front side of semiconductor device 100, i.e., above the top transistor layer 100T. The term "back interconnect structure" herein refers to an interconnect structure including one or more interconnect layers disposed on the back side of semiconductor device 100, i.e., below the bottom transistor layer 100B. The front and back sides of semiconductor device 100 may also be referred to as the front and back sides of active device layers, respectively. The front side of semiconductor device 100 / active device layer may correspond to the front and back sides of the substrate of semiconductor device 100. The term "interconnect layer" (front or back) herein refers to an interconnect layer (e.g., conductive traces, lines, and / or segments) of horizontal wiring (along the X and / or Y directions). Interconnect layers may also be referred to as metal line layers, metal wiring layers, or metallization layers. Continuous interconnect layers can be interconnected through intermediate via layers. Interconnect and via layers can be embedded in interlayer dielectrics.

[0059] Interconnects (e.g., lines, segments, contacts) of a given interconnect layer can be arranged in (or along) any of a set of wiring tracks within that given interconnect layer. In this disclosure, it is assumed that the wiring tracks for each layer mentioned are unidirectional, extending parallel in the X or Y direction, and arranged with a substantially uniform spacing or at least a regular spacing. As shown, the M0 track extends parallel in the X direction; this correspondingly applies to the BMO track. As those skilled in the art will appreciate, interconnects such as lines or segments arranged in any given wiring track do not need to extend along the full length of the track, but only need to be arranged to define an overlap relative to the structures to be interconnected (such as contacts or L1s of logic cells). Furthermore, depending on the wiring requirements of a particular logic cell implementation, some wiring tracks may not even be used.

[0060] Figure 1As an example, dashed lines illustrate the exemplary positions of a pair of opposing cell boundaries B1, B2 of a logic cell. Cell boundaries B1, B2 extend parallel to each other in the X direction. Here, cell boundaries B1, B2 are aligned with tracks BM0-1 and BM0-5, thus defining a pair of back-side "edge tracks" for the logic cell. It can also be seen that the centerline of the logic cell, and therefore LI row 180, is aligned with track BM0-3, thereby defining a back-side "center track" for the logic cell. The first and second CFET rows 101, 102 are aligned with tracks BM0-2 and BM0-4, thus defining a pair of back-side "eccentric tracks" for the logic cell. Correspondingly, in the front-side interconnect structure, cell boundaries B1, B2 are aligned with a pair of "outer tracks" M0-1, M0-7, while the centerline of the logic cell and LI row 180 are aligned with the "center track" M0-4. Additional orbitals M0-2, M0-3 and M0-5, M0-6 define corresponding "eccentric orbital" pairs between the edge orbitals M0-1, M0-4 and the center orbitals M0-4, M0-7, respectively.

[0061] exist Figure 1 In the example shown, bottom power rails 152 and 162 are arranged in the corresponding BM0 rails, BM0-1 and BM0-5. Top power rails 154 and 164 are arranged in the top transistor layer 100T (i.e., below the M0 layer). In another implementation, bottom power rails 152 and 162 can be similar to the top power rails arranged in the bottom transistor layer 100T. In this case, top power rails 154 and 164 can be formed with a smaller vertical dimension, for example, so as not to extend into the bottom transistor layer 100B. Although Figure 1 Not specifically shown, but top power rails 154, 164 may define local pull-down or pull-up rails for the top transistor layer 100T and connect to a corresponding global power rail 170 that may be located in the BMO-3 rails. This connection may be located in a region outside the logic cells of the semiconductor device 100, for example, in a region where a connection can be provided without competing for wiring resources with the connection between the bottom and top transistors of the CFET rows 101, 102.

[0062] Figure 2 Another example implementation of a dual-row CFET is shown. Figure 2 Similar to Figure 1 However, it further illustrates how the connection between the bottom S / D 124 and the bottom power rail 152 of the first CFET device 110 is achieved by arranging the bottom S / D contact portion 126 to extend laterally to overlap with the bottom edge rail BM0-1 and the cell boundary B1 and to contact / tap the bottom power rail 152 via the back contact portion or through hole 128.

[0063] Figure 2 It is also shown how the bottom S / D contact portion 126 of the second CFET 112 can be connected to the signal routing resources in the back eccentric track BM0-4 via the back contact portion or through-hole 129. Figure 2 It is also shown that the top S / D 134 can be connected / disconnected to the top power rail 154 by arranging the top S / D contact portion 136 to extend laterally toward the cell boundary B1 to contact / adjaculate with the top power rail 154. For example... Figure 2 As further shown, the top S / D contact portion 136 of the first CFET device 110 can alternatively be coupled to signal routing resources in the overlapping M0 track (M0-2 track exemplified here) via via 138. As further shown, the gate 140 of the CFET 10 can be coupled to signal routing resources in the overlapping M0 track (M0-6 track exemplified here) via gate via 142.

[0064] According to an example fabrication process for a dual-row CFET structure, CFET device processing can be monolithic, where both the top and bottom transistors are patterned together using a single active and dummy gate etching. The S / D region can be formed by cutting the active region between the dummy gates, blocking the top device, and epitaxially growing a highly doped S / D region for the bottom transistor. After depositing an isolation layer covering the bottom S / D region, the S / D region for the top transistor can be grown. The dummy gate can then be removed, releasing the nanosheet, and the gate filled with replacement metal to form the functional / active gate of the CFET device. In the next step, a top contact trench (MDT) and a “dangling” downward trench for the LI row can be formed. After completing the front-side back-end line (FS-BEOL) and thus forming the front interconnect structure, the wafer can be bonded to a carrier wafer, flipped, and removed, allowing access to the bottom transistor again. A bottom contact trench (MDB) for the bottom S / D contacts can be formed. This process can then be completed by forming a back-side interconnect structure.

[0065] In the following text, reference will be made to Figure 3 -9 Discusses example implementations of semiconductor devices and logic cells based on the dual-row CFET design shown above. Where appropriate, unless otherwise stated, the same reference numerals will be used to refer to the same elements. For example, reference numerals 101 and 102 refer to the first and second CFET rows. It should also be noted that each CFET device mentioned below may have the same... Figure 1-2 The corresponding configuration of either of the CFET devices 110 or 120.

[0066] Figure 3A schematic top view of a planar layout of semiconductor device 100 is shown, which includes multiple dual-row CFETs, each including a corresponding pair of first and second CFET rows 101, 102. Rectangular areas (such as the area labeled 103) typically indicate the location of logic cells (such as logic standard cells). The location of the back track BM0 is schematically indicated on the right side of the drawing area. As can be understood from the above, each track specified by "VDD / VSS" indicates the connection to... Figure 1-2 The power rail structures 150 and 160 correspond to the power rail structures of the stacked power rail structure. Therefore, each back rail designated "VDD / VSS" indicates the location of the bottom VDD power rail and also includes a top VSS power rail disposed above the bottom VDD power rail (and vice versa). The back rail designated "VSS" indicates the location of the global VSS (or VDD) power rail. As illustrated in cell 103, each cell includes a plurality of LI 182 in an associated LI row 180 extending through the cell, and a plurality of CFET devices 110 and 112 in associated first and second CFET rows 101 and 102, each CFET device including a shared gate 140.

[0067] Figure 4 The diagram schematically illustrates, as a comparative example, a logic cell C comprising a dual-row CFET implementing a single inverter gate INV. The dual-row CFET itself enables a low track height for the logic cell. However, implementing the logic gate using only one row of the dual rows in this way effectively results in half of the cell height dimension (in the Y direction) being unused. Figure 4 The implemented logic unit can be referred to as a single-bit logic unit in this paper because it provides only a single-bit output.

[0068] Figure 5 A semiconductor device 200 including a logic unit 202 is schematically shown. According to this disclosure, the logic unit 202 is instead implemented using a dual-row CFET to realize two inverter (NOT) gates INV-1 and INV-2. Therefore, Figure 4The unused cell area in the comparative example is used here to accommodate another inverter gate. Therefore, logic cell 202 implements a multi-bit (e.g., 2-bit input / output inverter) cell, effectively doubling the area used by logic cell 202. Inverters INV-1 and INV-2 are arranged in corresponding half-cells 210 and 220 of logic cell 202. The division of logic cell 202 into half-cells 210 and 220 is schematically indicated here by the dashed inner boundary corresponding to the center line of logic cell 202. The positions of the corresponding CFET devices of the first and second inverter gates are schematically indicated here only by the positions of their respective active gates. As shown, each active gate is surrounded by a pair of dummy gates arranged on the opposite cell boundaries of logic cell 202.

[0069] Now refer to Figure 6a -b provides a more detailed description of logic unit 202. Figure 6a -b shows example layouts of the top and bottom transistor layers 200T and 200B of logic cell 202, respectively.

[0070] Semiconductor device 200 includes first and second power rail structures 150, 160 extending parallel to each other in the X direction, and each power rail structure includes a bottom power rail 152, 162 (e.g., VDD) and a top power rail 154, 164 (e.g., VSS) arranged vertically above the bottom power rail 152, 162. Semiconductor device 200 also includes a row LI 180 arranged between and parallel to the first and second power rail structures 150, 160 in the X direction. As shown, the LI row 180 may be arranged on the centerline of logic cell 202 (i.e., substantially aligned with the centerline). Semiconductor device 200 also includes first and second rows of CFET devices 101, 102 extending parallel to the first and second power rail structures 150, 160 in the X direction. The first row of CFET devices 101 is arranged between the first power rail structure 150 and the LI row 180. The second row of CFET devices 102 is arranged between the second power rail structure 160 and the LI row 180. As shown in the figure, the first row of CFET devices 101 can be arranged on the center line between the first power rail structure 150 and the L1 row 180 (i.e., substantially aligned with the center line). Correspondingly, the second row of CFET devices 102 can be arranged on the center line between the second power rail structure 160 and the L1 row 180 (i.e., substantially aligned with the center line).

[0071] Logic cell 202 has first and second cell boundaries 202a and 202b extending parallel to each other in the X direction. The distance between the first and second cell boundaries 202a and 202b defines the cell height of logic cell 202. Logic cell 202 also has third and fourth cell boundaries 202c and 202d extending parallel to each other in the Y direction. The distance between the third and fourth cell boundaries 202c and 202d defines the cell width of logic cell 202. The first and second cell boundaries 202a-b are aligned with the first and second power rail structures 150 and 160, respectively. Therefore, the first power rail structure 150 and the second power rail structure 160 are arranged on the first and second cell boundaries 202a-b, respectively. The third and fourth cell boundaries 202c-d are aligned with the corresponding dummy gates 230 (see...). Figure 6a Therefore, the dummy gate 230 is arranged on the third and fourth cell boundaries 202c-d. Due to the presence of the dummy gate 230, the cell width of the logic cell 202 (in the X direction) corresponds to 2×CPP, where CPP is the contact polysilicon pitch of the CFET devices 212, 222 of the logic cell 200.

[0072] Logic unit 202 includes a first CFET device 212 in the first CFET row 101 and a second CFET device 222 in the second CFET row 102. Viewed in the Y direction, the first and second CFET devices 212 and 222 are arranged directly opposite each other. The first CFET device 212 is configured to implement a first logic gate, and the second CFET device 222 is configured to implement a second logic gate, where the first and second logic gates are corresponding inverters INV-1 and INV-2.

[0073] The first CFET device 212 includes a gate 214 shared by its bottom and top transistors. The second CFET device 222 includes a gate 224 shared by its bottom and top transistors. The gates 214 and 224 are aligned in the Y direction as shown, in other words, arranged in or aligned with a common "gate track" GT.

[0074] like Figure 6a As can be seen, the top transistor of the first CFET device 212 is connected to the top power rail 154 via the top S / D contact 218T. Correspondingly, the top transistor of the second CFET device 222 is connected to the top power rail 164 via the top S / D contact 228T. Figure 6bAs can be seen, the bottom transistor of the first CFET device 212 is connected to the bottom power rail 152 via the bottom S / D contact 218B. Correspondingly, the bottom transistor of the second CFET device 222 is connected to the bottom power rail 162 via the bottom S / D contact 228B. Therefore, the first CFET device 212 is connected between the first bottom and top power rails 152, 154. The second CFET device 222 is correspondingly connected between the second bottom and top power rails 162, 164. Thus, the first power rail structure 150 is configured to power a first logic gate, and the second power rail structure is configured to power a second logic gate.

[0075] Logic cell 202 also includes a first LI 182 and a second LI 184 in LI row 180. The first LI 182 is configured to interconnect the top and bottom S / D contact portions 216T, 216B of the first CFET device 212. The combination of the first LI 182 and the top and bottom S / D contact portions 216T, 216B forms a first S / D contact structure 216. The second LI 184 is configured to interconnect the top and bottom S / D contact portions 226T, 226B of the second CFET device 212. The combination of the second LI 184 and the top and bottom S / D contact portions 226T, 226B forms a second S / D contact structure 226. The first S / D contact structure 216 and the second S / D contact structure 226 are arranged on opposite sides of the common gate track of gates 214, 224.

[0076] The gates 214 and 224 of the first and second CFET devices are configured as input nodes of the corresponding logic gates INV-1 and INV-2, and are correspondingly connected to the corresponding input pins of the logic cell 202. The first and second S / D contact structures 216 and 226 are configured as output nodes of the corresponding logic gates INV-1 and INV-2, and are correspondingly connected to the corresponding output pins of the logic cell 202. Here, the term "pin" for input and output of the logic cell refers to a metal line or metal segment that is connected to the input / output node of the logic gate, respectively, to provide an input signal to the corresponding logic gate and to provide an output signal from the corresponding logic gate. The input and output pins can typically be arranged in the M0 track of the M0 front interconnect layer. For example, the input pin associated with the first logic gate INV-1 can be arranged in the M0-2 track, and the input pin associated with the second logic gate INV-2 can be arranged, for example, in the M0-6 track. The output pin associated with the first logic gate INV-1 can, for example, be arranged in track M0-3, and the input pin associated with the second logic gate INV-2 can, for example, be arranged in track M0-5. However, it is also possible to reverse the allocation of input and output pins relative to tracks M0-2, M0-3, M0-5, and M0-6. The input pins can be routed through corresponding vias (e.g., as shown in the image). Figure 2 The via 142 in the diagram is connected to gates 214 and 224. Output pins can be connected through corresponding vias (e.g., such as...). Figure 2 The through hole 138) is connected to the first and second S / D contact structures 216 and 226.

[0077] like Figure 6a Further illustrated, logic cell 202 can conceptually be divided or partitioned by inner boundary 202e into two sub-cells or half-cells 210, 220 with equal coverage areas. The first and second half-cells 210, 220 extend side-by-side with respect to each other in the cell width direction, i.e., in the X direction. The first half-cell 210 includes a first CFET device 212, and the second half-cell 220 includes a second CFET device 222. Here, inner boundary 202e is traced such that the corresponding LI 182, 184 of the corresponding logic gates INV-1, INV-2 are included in the corresponding half-cells 210, 220, rather than as... Figure 5 The inner boundary 202e is represented as a straight line. Therefore, this way of representing the inner boundary 202e is equivalent to associating the corresponding LI 182, 184 with their corresponding logic gates, rather than indicating LI 182, 184 as shared LI of logic unit 202 (which would be an equally valid depiction).

[0078] Therefore, in view of the above, the first logic gate INV-1 is implemented by a first half-cell 210 including a first CFET device 212 and a first LI 182. The second logic gate INV-2 is implemented by a second half-cell 220 including a second CFET device 222 and a second LI 184. Figure 6a As shown in -b, the layout of each half-cell 210, 220 is identical, but rotated 180 degrees relative to each other; in other words, they are flipped and mirrored relative to each other. In other words, the layout of logic cell 202 is point-symmetric, i.e., rotationally symmetric about the center of logic cell 202. Therefore, the (identical) first and second logic gates INV-1, INV-2 can be implemented by corresponding half-cells with the same layout and can be accommodated within the coverage area of ​​the same logic cell 202.

[0079] Figure 5 and 6a The logic gates of logic unit 202 of type -b are all implemented by one (N=1) CFET device in the corresponding CFET rows 101 and 102. The method of implementing logic units based on dual-row CFETs discussed above can be applied in a corresponding manner to implement other types of multi-bit logic gates using N≥2 CFET devices in each CFET row 101 and 102. This is in Figure 7 The illustration is shown in the middle. Figure 7As an example, a schematic layout of logic cell 302 of semiconductor device 300 is shown. Semiconductor device 300 includes a dual row of CFETs that implement two NAND gates NAND-1 and NAND-2 through two (N=2) CFET devices in each CFET row 101, 102. Each NAND gate is included in a corresponding half cell 310, 320.

[0080] Now refer to Figure 8a -b provides a more detailed description of logic unit 202. Figure 6a -b shows example layouts of the top and bottom transistor layers 300T and 300B of logic cell 302, respectively.

[0081] To implement the 2-bit input of the NAND gate, the first and second logic gates NAND-1 and NAND-2 are each implemented using two corresponding CFET devices 312-1, 312-2 and 322-1, 322-2. As shown in the figure, logic unit 302 can be divided into two corresponding half-units 310 and 320, just like logic unit 202. The first half-unit 310 implements the first logic gate NAND-1, and the second half-unit 320 implements the second logic gate NAND2. CFET device 312-1 can be referred to here as the first CFET device 312-1 of logic unit 302, and CFET device 322-1 can be referred to as the second CFET device 322-1 of logic unit 302.

[0082] Each CFET device 312-1, 312-2, 322-1, 322-2 includes respective gates A11, A21, A12, A22 shared by its bottom and top transistors. Gates A11 and A22 are aligned in the Y direction as shown, in other words, arranged in or aligned with a common first "gate track" GT1. Correspondingly, gates A21 and A12 are aligned in the Y direction, in other words, arranged in or aligned with a common second "gate track" GT2 parallel to the first gate track.

[0083] Logic unit 302 also includes a first LI 182 and a second LI 184 in LI row 180. The first LI 182 is configured to interconnect the top and bottom S / D contact portions 316T, 316B of the first CFET device 312. The combination of the first LI 182 and the top and bottom S / D contact portions 316T, 316B forms a first S / D contact structure 316. The second LI 184 is configured to interconnect the top and bottom S / D contact portions 326T, 326B of the second CFET device 322-1. The combination of the second LI 184 and the top and bottom S / D contact portions 326T, 326B forms a second S / D contact structure 326. Figure 6aThe discussion of the half-units 210 and 220 of logic unit 202 of -b is similar. The first LI 182 and the first S / D contact structure 316 are included in the first half-unit 310, and the second LI 184 and the second S / D contact structure 326 are included in the second half-unit 320.

[0084] Figure 8a In -b, you can easily see the further connections between the corresponding CFET devices 312-1, 312-2, 322-1, and 322-2 of the corresponding logic gates NAND-1, NAND-2 / half cells 310 and 320 and with the corresponding power rails.

[0085] The top and bottom S / D contacts 317T and 317B are shared by CFET devices 312-1 and 312-2. Correspondingly, the top and bottom S / D contacts 327T and 327B are shared by CFET devices 322-1 and 322-2. For example... Figure 8a As can be seen, the bottom transistors of CFET devices 312-1 and 312-2 are connected to the bottom power rail 152 via the bottom S / D contact 317B. Correspondingly, the bottom transistors of the second CFET devices 322-1 and 322-2 are connected to the bottom power rail 162 via the bottom S / D contact 327B. Figure 8b As can also be seen, the top transistor of CFET device 312-2 is connected to the top power rail 154 via the top S / D contact 318T. Correspondingly, the top transistor of CFET device 322-2 is connected to the top power rail 164 via the top S / D contact 328T. To complete the signal routing involved in the NAND gate, connections are also required on one hand between the bottom S / D contact 318B and the S / D contact structure 316, and on the other hand between the bottom S / D contact 328B and the S / D contact structure 326. Figure 8c This is a further view of the bottom layer 300B of logic cell 302, but some components are omitted to allow viewing of the back interconnect layer BM0. Therefore, as... Figure 8c As can be seen, to achieve these connections, each logic gate NAND-1, NAND-2 can utilize metal lines 344, 350 disposed in corresponding back-side signal tracks BM0-2, BM0-4 aligned with the corresponding CFET rows 101, 102. The metal lines 344 pass through a pair of back-side contacts 340, 342 (e.g., similar to...). Figure 2The back contact 129 is connected to the bottom S / D contacts 316B and 318B. Metal line 350 is correspondingly connected to the bottom S / D contacts 326B and 328B via a pair of back contacts 346 and 348. Thus, the corresponding metal lines connect a pair of non-adjacent S / D interconnects, namely 312-1 and 312-2, and 322-1 and 322-2, of a corresponding pair of CFET devices in the corresponding CFET rows 101 and 102.

[0086] The gates A11, A21, A12, and A22 of CFET devices 312-1, 312-2, 322-1, and 322-2 are configured as input nodes of the corresponding logic gates NAND-1 and NAND-2, and are correspondingly connected to the corresponding input pins of logic cell 302. The first and second S / D contact structures 316 and 326 are configured as output nodes of the corresponding logic gates NAND-1 and NAND-2, and are correspondingly connected to the corresponding output pins of logic cell 302. For example, the two input pins associated with the first logic gate NAND-1 can be arranged in track M0-2, and the two input pins associated with the second logic gate INV-2 can be arranged, for example, in track M0-6. The output pin associated with the first logic gate NAND-1 can be arranged, for example, in track M0-3, and the output pin associated with the second logic gate NAND-2 can be arranged, for example, in track M0-5. However, different allocations of input and output pins relative to tracks M0-2, M0-3, M0-5, and M0-6 are also possible. For reference Figure 6a As discussed in -b, the connection between the input / output pins and the gate and S / D contact of the logic unit 302 can be achieved through vias.

[0087] The corresponding CFET devices 312-1, 312-2 and 322-1, 322-2 are similar to Figure 6a The inverter implementation of -b is surrounded by corresponding pairs of dummy gates 330 aligned with the third and fourth cell boundaries 302c-d of logic cell 302. Therefore, logic cell 302 has a cell width (in the X direction) corresponding to (N+1)×CPP=3×CPP.

[0088] A similar approach can be applied to implement multi-bit AND gates. Figure 9a Logic unit 402 includes first and second AND gates AND-1 and AND-2, and a multi-bit OR gate ( Figure 9b Logic unit 502 includes first and second OR gates (OR-1, OR-2), and a multi-bit NOR gate ( Figure 9c The logic unit 602 includes first and second NOR gates NOR-1 and NOR-2.

[0089] Logic units 402, 502, and 602 can each be like... Figure 8a Like logic cell 302 of -b, it is implemented by three transistors in the corresponding CFET rows 101 and 102, and each can have a cell width of 3×CPP. Logic cells 402, 502, and 602 can each utilize the wiring resources in the back-side wiring layer BMO to interconnect a pair of non-adjacent S / D interconnects of the corresponding pair of CFET devices in the corresponding CFET rows 101 and 102, such as... Figure 8a The NAND gate logic unit 302 of -c is shown.

[0090] Including single-bit logic cells (utilizing only a single row in a CFET dual-row configuration, such as...) Figure 4 Example cell C) and multi-bit logic cells (utilizing two rows in a CFET dual-row configuration, such as...) Figure 5 , 6a The standard cell library (cells 202, 302, 402, 502, 604) of -b, 7, 8a-b, and 9a-C can provide flexibility in the circuit design flow. For example, closely spaced single-bit logic cells (e.g., each implementing a corresponding inverter gate) can be aggregated to form a multi-bit logic cell (e.g., implementing two inverter gates), thereby replacing the two single-bit logic cells and improving area utilization. Conversely, a multi-bit logic cell (e.g., implementing two AND gates) can be split into two single-bit logic cells (e.g., each implementing a corresponding AND gate), thereby replacing the multi-bit logic cell with two single-bit logic cells. While this may reduce the area utilization of a given multi-bit logic cell, it can still be beneficial in some cases if it enables more efficient signal routing between logic gates and surrounding logic cells. For example, these methods of aggregating and splitting logic cells can be implemented in the placement and routing process of electronic design automation (EDA) tools.

[0091] Those skilled in the art will recognize that the invention is by no means limited to the examples described above. Rather, many modifications and variations are possible within the scope of the appended claims. For example, it is conceivable that the method described above can also be applied to implement logic cells based on dual-row CFETs implementing first and second logic gates, but can be implemented using the same number of CFET devices in a row of CFETs, and thus by corresponding half-cells having the same cell width (e.g., (N+1) × CPP). Therefore, Figure 4 In the comparative example, the unused cell region can be implemented to accommodate another inverter gate.

Claims

1. A semiconductor device, comprising: A first power rail structure and a second power rail structure extending in parallel, each power rail structure including a bottom power rail and a top power rail arranged above the bottom power rail; A row of local interconnects is arranged between and extends parallel to the first row of CFET devices and the second row of CFET devices. A first row of complementary field-effect transistor (CFET) devices and a second row of CFET devices extending parallel to the first power rail structure and the second power rail structure, wherein the first row of CFET devices is arranged between the first power rail structure and the row of local interconnects, and the second row of CFET devices is arranged between the second power rail structure and the row of local interconnects. as well as Logic unit, including The first row of CFET devices is configured to implement a first logic gate, and the row of local interconnects is configured to interconnect the top and bottom source / drain S / D of the first CFET device in the first row of CFET devices; as well as The second row of CFET devices includes at least one CFET device configured to implement a second logic gate, and a second local interconnect configured to connect the top and bottom S / D interconnects of the second CFET device in the at least one CFET device in the second row of CFET devices. The first logic gate is connected to the first input pin and the first output pin of the logic unit, and the second logic gate is connected to the second input pin and the second output pin of the logic unit. The first power rail structure is configured to power the first logic gate, and the second power rail structure is configured to power the second logic gate.

2. The semiconductor device according to claim 1, characterized in that, The logic unit further includes: A first S / D contact structure, comprising a bottom S / D contact portion that contacts the bottom S / D of the first CFET device, a top S / D contact portion that contacts the top S / D of the first CFET device, and a first partial interconnect that interconnects the bottom S / D contact portion and the top S / D contact portion; and The second S / D contact structure includes a bottom S / D contact portion that contacts the bottom S / D of the second CFET device, a top S / D contact portion that contacts the top S / D of the second CFET device, and a second partial interconnection that interconnects the bottom S / D contact portion and the top S / D contact portion.

3. The semiconductor device according to claim 2, characterized in that, The first S / D contact structure is connected to the first output pin of the logic unit, and the second S / D contact portion is connected to the second output pin of the logic unit.

4. The semiconductor device according to claim 1, characterized in that, Each CFET device includes a gate shared by the bottom and top transistors of the respective CFET device and connected to the corresponding input pin of the logic cell.

5. The semiconductor device according to claim 1, characterized in that, The first logic gate is implemented by N≥1 CFET devices in the first row of CFET devices, and the second logic gate is implemented by N CFET devices in the second row of CFET devices.

6. The semiconductor device according to claim 5, characterized in that, At least one CFET device of the first logic gate and at least one CFET device of the second logic gate are arranged in corresponding half cells of the logic cell, and wherein the cell width of each half cell corresponds to several times the contact polysilicon pitch (CPP) of the CFET device.

7. The semiconductor device according to claim 5, characterized in that, Each half-cell includes a corresponding pair of dummy gates, wherein N CFET devices for each logic gate are arranged between the corresponding pair of dummy gates.

8. The semiconductor device according to claim 5, characterized in that, N ≥ 2, and wherein the logic unit includes a corresponding back-side signal track aligned with each of the first row of CFET devices and the second row of CFET devices, and each back-side signal track includes a metal line that interconnects a pair of non-adjacent S / D interconnects of a pair of CFET devices in the corresponding row of CFET devices.

9. The semiconductor device according to claim 1, characterized in that, The first logic gate and the second logic gate are the same logic gate.

10. The semiconductor device according to claim 9, characterized in that, The circuit layout of the logic unit is point-symmetric.

11. The semiconductor device according to claim 9, characterized in that, The first logic gate and the second logic gate are inverter gates, NAND gates, NOR gates, AND gates, or OR gates.

12. The semiconductor device according to claim 10, wherein, when dependent on claim 5, it is characterized in that: N=1 and the first logic gate and the second logic gate are inverter gates, or N=2 and the first logic gate and the second logic gate are AND, OR, NOR or NAND gates, and N=2.

13. The semiconductor device according to claim 1, characterized in that, The bottom power rail is arranged in a bottom transistor layer comprising the first row of CFET devices and the second row of CFET devices, or in a back interconnect layer, and / or the top power rail is arranged in a top transistor layer comprising the first row of CFET devices and the second row of CFET devices.

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