A bidirectional surge protector and a preparation method thereof

Abstract

This invention provides a bidirectional surge protector and its fabrication method, belonging to the field of semiconductor device technology. It includes: an epitaxial layer formed on a substrate; multiple deep trenches formed within the epitaxial layer; a first injection region formed within the epitaxial layer, electrically connected to the bottom and sidewalls of the deep trenches; and a second injection region formed within the epitaxial layer, electrically connected to the first injection region at the bottom of the deep trenches to form a trigger junction. Beneficial effects: By introducing the second injection region, which forms a trigger junction with the first injection region at the bottom of the deep trenches, this junction breaks down first during a negative surge, triggering the conduction of the longitudinal transistors; due to the depth of the deep trenches, current flows through the first injection region within the deep trenches to the bottom, further conducting the transistors along its path, making high-current conduction easier and more uniform; all parallel deep trenches within the chip can simultaneously respond to surges and share current, avoiding localized hot spots and improving the device's surge tolerance; it is compatible with standard process flows, reducing costs.

Description

Technical Field

[0001] This invention relates to the field of semiconductor device technology, and in particular to a bidirectional surge protector and its fabrication method. Background Technology

[0002] Transient voltage suppressors (TVS) are widely used clamping overvoltage protection devices on circuit boards. They are usually connected in parallel with the protected circuit to discharge instantaneous large currents caused by electrostatic discharge (ESD) or lightning strikes, clamping the voltage at a safe level and protecting downstream precision integrated circuits.

[0003] like Figure 1 As shown, traditional bidirectional transient voltage suppressors typically employ vertical NPN transistor structures or lateral interpolation NPN transistor structures. The transient current handling capability of these structures is directly proportional to the effective junction area; that is, the larger the effective junction area, the stronger the transient current handling capability. Therefore, performance improvement of transient voltage suppressors based on traditional structures encounters bottlenecks when chip area is limited.

[0004] In order to break through the limitations of traditional structures, such as Figure 2 As shown, the device, from bottom to top, includes a back drain metal layer 109, an N-type substrate 100, a P-type epitaxial layer 101, a deep trench 102, a polysilicon layer 103 within the trench, implantation regions 104 at the bottom and sidewalls of the trench, an oxide layer 105, an oxide layer 106, a first front metal layer 1071, a second front metal layer 1072, and a passivation layer 108. By utilizing deep trench etching (DTI) and polysilicon filling techniques, the two-dimensional planar structure is extended to three dimensions, significantly increasing current path and surge capability, providing a new approach to improving TVS performance.

[0005] However, due to the depth of the deep trench and the parasitic resistance of the doped polysilicon, current sharing issues exist in the bottom and middle regions of the deep trench, preventing this area from being effectively utilized and thus hindering the expected surge capability. Therefore, there is still room for optimization in the triggering mechanism and current distribution uniformity of the deep trench polysilicon NPN structure. Especially when facing extremely large surge currents, ensuring that all parallel units within the device can be triggered and turned on quickly and uniformly becomes the key to further improving its ultimate performance. Summary of the Invention

[0006] To address the above technical problems, this invention provides a bidirectional surge protector; furthermore, it also provides a method for manufacturing a bidirectional surge protector.

[0007] The technical problem solved by this invention can be achieved by the following technical solutions: A bidirectional surge protector includes: Substrate, the substrate having a first conductivity type; An epitaxial layer is formed on the substrate, the epitaxial layer having a first conductivity type; Multiple deep trenches are formed in the epitaxial layer, and the multiple deep trenches are distributed in an array, extending from the surface of the epitaxial layer toward the substrate; A first injection region is formed in the epitaxial layer, the first injection region is electrically connected to the bottom and sidewall of the deep trench, and the first injection region has a second conductivity type opposite to the first conductivity type; A second injection region is formed in the epitaxial layer. The second injection region has a first conductivity type and is electrically connected to the first injection region at the bottom of the deep trench to form a trigger junction.

[0008] Preferably, the first conductivity type is N-type and the second conductivity type is P-type; or the first conductivity type is P-type and the second conductivity type is N-type.

[0009] Preferably, it further includes: A deep trench isolation structure is formed in the epitaxial layer, the deep trench isolation structure extends from the surface of the epitaxial layer toward the substrate, and the deep trench isolation structure surrounds the plurality of deep trenches.

[0010] Preferably, the depth of the deep groove is 5μm to 53μm, the width of the deep groove is 0.5μm to 2.5μm, and the distance between two adjacent deep grooves is 1μm to 3μm.

[0011] Preferably, the implanted element in the second implantation region is boron or boron difluoride, the implantation energy in the second implantation region is 30~200 keV, and the implantation dose in the second implantation region is 1E14~2E16 cm⁻¹. -2 The injection angle of the second injection region is 0 degrees.

[0012] Preferably, it further includes: A first oxide layer is formed on the upper surface of the epitaxial layer; The second oxide layer is formed on the upper surface of the first oxide layer, and the deep trench is formed by photolithography and etching using the second oxide layer as a hard mask. A polycrystalline silicon layer is formed within the deep trench, the polycrystalline silicon layer having a second conductivity type; A front metal layer is formed on the upper surface of the epitaxial layer and the second oxide layer, and the front metal layer is electrically connected to the polysilicon layer. A passivation layer is formed on the upper surface of the second oxide layer and a portion of the front metal layer; A back metal layer is formed on the lower surface of the substrate.

[0013] Preferably, the thickness of the first oxide layer is 200 Å to 500 Å; and the thickness of the second oxide layer is 10000 Å to 20000 Å.

[0014] On the other hand, a method for manufacturing a bidirectional surge protector is also provided, for manufacturing a bidirectional surge protector as described above, comprising: Step S1: Provide a substrate having a first conductivity type, form an epitaxial layer having a first conductivity type on the substrate, form a first oxide layer on the epitaxial layer, and form a second oxide layer on the first oxide layer; Step S2: Using the second oxide layer as a hard mask, photolithography and etching are performed on the epitaxial layer to form multiple deep trenches. The multiple deep trenches are arranged in an array and extend from the surface of the epitaxial layer to the substrate. Step S3: Selective ion implantation is performed at the bottom of the deep trench to form a second implantation region; Step S4: Fill the deep trench with a polysilicon layer of the second conductivity type and perform thermal annealing to allow the polysilicon filled in the deep trench to diffuse into the epitaxial layer, forming a first implantation region. The first implantation region is electrically connected to the bottom and sidewall of the deep trench, and the first implantation region at the bottom of the deep trench is electrically connected to the second implantation region to form a trigger junction. Step S5: Remove excess polysilicon and form a front metal layer on the upper surface of the epitaxial layer and the second oxide layer. The front metal layer is electrically connected to the polysilicon layer. Step S6: A passivation layer is formed on the upper surface of the second oxide layer and part of the front metal layer, and an opening is made in the passivation layer to expose the front metal layer. Step S7: Thin the back side of the substrate to form a back metal layer on the lower surface of the substrate.

[0015] Preferably, in the hot annealing process of step S4, the annealing temperature is 950℃~1200℃ and the time is 60~180 minutes.

[0016] The advantages or beneficial effects of the technical solution of this invention are as follows: This invention introduces a second injection region, forming a trigger junction with the first injection region at the bottom of the deep trench. During a negative surge, this trigger junction first undergoes avalanche breakdown, injecting holes into the epitaxial layer, which can more effectively trigger the conduction of the vertical NPN transistors. Due to the depth of the deep trench, current flows through the first injection region within the trench to the bottom, causing the NPN transistors along its path to conduct further, making high-current conduction easier and more uniform. The introduction of the second injection region optimizes triggering and current spread, enabling all parallel deep trench units within the chip to respond to surges simultaneously and share the current, avoiding the formation of local hot spots, thereby greatly improving the surge tolerance of the device. The injection process of the second injection region is compatible with standard process flows, reducing costs. Attached Figure Description

[0017] Figure 1 This is a schematic diagram of the equivalent circuit of a conventional bidirectional transient voltage suppressor in the prior art; where Q1-Q4 are vertical NPN transistors; RP11-RP16 are parasitic resistors; Figure 2 This is a schematic diagram of a bidirectional transient voltage suppressor that utilizes deep trench etching and filling of polysilicon in the prior art. Figure 3 This is a schematic diagram of the structure of the bidirectional surge protector in a preferred embodiment 1 of the present invention; Figure 4 This is a schematic diagram of the equivalent circuit of the bidirectional surge protector in a preferred embodiment 1 of the present invention; Figures 5a-5h This is a schematic diagram of the structure of each step in the preparation method of the bidirectional surge protector in the preferred embodiment 1 of the present invention; Figure 6 This is a schematic diagram of the structure of the bidirectional surge protector in a preferred embodiment 2 of the present invention. Detailed Implementation

[0018] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0019] It should be noted that, unless otherwise specified, the embodiments and features described in the present invention can be combined with each other.

[0020] The present invention will be further described below with reference to the accompanying drawings and specific embodiments, but this is not intended to limit the scope of the invention.

[0021] Example 1 In a preferred embodiment of the present invention, based on the above-mentioned problems existing in the prior art, a bidirectional surge protector is provided, such as... Figure 3 As shown, it includes: Substrate 1, substrate 1 having a first conductivity type; Epitaxial layer 2 is formed on substrate 1, and epitaxial layer 2 has a first conductivity type; Multiple deep trenches 4 are formed in the epitaxial layer 2. The multiple deep trenches 4 are arranged in an array. The deep trenches 4 extend from the surface of the epitaxial layer 2 toward the substrate 1, and the bottom of the deep trenches 4 is spaced a certain distance from the surface of the substrate 1. The first injection region 7 is formed in the epitaxial layer 2. The first injection region 7 is electrically connected to the bottom and sidewall of the deep trench 4. The first injection region 7 has a second conductivity type opposite to the first conductivity type. The second injection region 5 is formed in the epitaxial layer 2. The second injection region 5 has a first conductivity type. The second injection region 5 is electrically connected to the first injection region 7 at the bottom of the deep trench 4 to form a trigger junction.

[0022] In this embodiment, the first implantation region 7 is a heavily doped implantation region, and the second implantation region 5 is also a heavily doped implantation region, and the two have different conductivity types to form a PN trigger junction.

[0023] Furthermore, if the first conductivity type is N-type, then the second conductivity type is P-type; or if the first conductivity type is P-type, then the second conductivity type is N-type. Hereinafter, N+, N-type, P+, and P-type refer to different doping concentrations. Specifically, the doping concentration of N-type is less than that of N+ type, and the doping concentration of P-type is less than that of P+ type. This embodiment uses N-type as the first conductivity type and P-type as the second conductivity type for illustration.

[0024] Specifically, in this embodiment, based on the traditional deep trench 4 filled with polysilicon structure, a P+ type second implantation region 5 is introduced at the bottom of the deep trench 4. This P+ type second implantation region 5 and the N+ type first implantation region 7 at the bottom of the deep trench 4 form an additional PN trigger junction, such as... Figure 4 The transistor Q4' is shown. Because a trigger junction of the NPN parasitic transistor is added at the bottom of the deep trench 4, all NPN transistors are turned on, and the surge current path is more uniform, thereby significantly improving the overall surge withstand capability of the device.

[0025] Furthermore, the depth of the deep groove 4 is 5μm~53μm, the width of the deep groove 4 is 0.5μm~2.5μm, and the distance between two adjacent deep grooves 4 is 1μm~3μm.

[0026] Furthermore, the implanted element in the second implantation region 5 is boron or boron difluoride, the implantation energy in the second implantation region 5 is 30~200 keV, and the implantation dose in the second implantation region 5 is 1E14~2E16 cm⁻¹. -2The injection angle of the second injection zone 5 is 0 degrees.

[0027] Furthermore, it also includes: The first oxide layer (not shown in the figure) is formed on the upper surface of the epitaxial layer 2; The second oxide layer 3 is formed on the upper surface of the first oxide layer, and the deep trench 4 is formed by photolithography and etching using the second oxide layer 3 as a hard mask. A polycrystalline silicon layer 6 is formed within the deep trench 4, and the polycrystalline silicon layer 6 has a second conductivity type. A front metal layer is formed on the upper surface of the epitaxial layer 2 and the second oxide layer 3. The front metal layer is electrically connected to the polysilicon layer 6. The front metal layer includes a first metal layer 81 and a second metal layer 82. The first metal layer 81 serves as the first port IO1 and the second metal layer 82 serves as the second port IO2. Passivation layer 9 is formed on the upper surface of the second oxide layer 3 and part of the front metal layer; A back metal layer 10 is formed on the lower surface of the substrate 1.

[0028] Furthermore, the thickness of the first oxide layer is 200 Å to 500 Å; the thickness of the second oxide layer 3 is 10000 Å to 20000 Å.

[0029] This invention provides a method for manufacturing a bidirectional surge protector, used to manufacture the bidirectional surge protector as described above, comprising: Step S1, as follows Figure 5a As shown, a substrate 1 having a first conductivity type is provided, an epitaxial layer 2 having a first conductivity type is formed on the substrate 1, a first oxide layer is formed on the epitaxial layer 2, and a second oxide layer 3 is formed on the first oxide layer.

[0030] Preferably, the resistivity of the P-type substrate 1 is 1 mΩ·cm to 7 mΩ·cm.

[0031] Preferably, the resistivity of the P-type epitaxial layer 2 is 10 mΩ·cm to 70 mΩ·cm, and the thickness of the epitaxial layer 2 is 8 μm to 60 μm.

[0032] Preferably, the first oxide layer is a thin oxide layer with a thickness of 200 Å to 500 Å; the second oxide layer 3 is a thick oxide layer, formed by chemical vapor deposition (CVD) and used as a hard mask (HM), with a thickness of 10,000 Å to 20,000 Å.

[0033] The second oxide layer 3 is photolithographically and etched to remove the second oxide layer 3 above the deep trench 4 region.

[0034] Step S2, as follows Figure 5bAs shown, the second oxide layer 3 is used as a hard mask to perform photolithography and etching on the epitaxial layer 2 to form multiple deep trenches 4. The multiple deep trenches 4 are distributed in an array and extend from the surface of the epitaxial layer 2 to the substrate 1.

[0035] Specifically, with the protection of a hard mask, a deep trench 4 with an extremely high aspect ratio is fabricated in the epitaxial layer 2 using dry etching technology. To ensure that the polysilicon has good filling characteristics, the width of the deep trench 4 is controlled; at the same time, to maintain sufficient current carrying capacity, multiple parallel deep trench 4 structures are adopted, and the spacing thickness between the deep trenches 4 meets specific design rules.

[0036] Preferably, the depth of the deep groove 4 is 5μm~53μm, the width of the deep groove 4 is 0.5μm~2.5μm, and the distance between two adjacent deep grooves 4 is 1μm~3μm.

[0037] Step S3, as follows Figure 5c As shown, selective ion implantation is performed at the bottom of the deep trench 4 to form the second implantation region 5.

[0038] Specifically, using the existing trench 4 structure as a mask, self-aligned local implantation is achieved. Through a precisely controlled ion implantation process, a high-concentration P+ type second implantation region 5 is selectively formed at the bottom of the trench 4. To ensure that the implanted ions are implanted only at the bottom of the trench 4, the implantation angle is controlled to 0 degrees.

[0039] Preferably, the implanted element in the second implantation region 5 is boron (B) or boron difluoride (BF2), the implantation energy in the second implantation region 5 is 30~200 keV, and the implantation dose in the second implantation region 5 is 1E14~2E16 cm⁻¹. -2 The injection angle of the second injection zone 5 is 0 degrees.

[0040] A rapid thermal annealing (RTA) step is performed after injection to partially activate impurities and repair injection damage.

[0041] Step S4, as follows Figure 5d As shown, a polycrystalline silicon layer 6 of a second conductivity type is filled into the deep trench 4, and then subjected to thermal annealing. Figure 5e As shown, the polysilicon filled in the deep trench 4 diffuses into the epitaxial layer 2 to form a first implantation region 7. The first implantation region 7 is electrically connected to the bottom and sidewalls of the deep trench 4. The first implantation region 7 at the bottom of the deep trench 4 is electrically connected to the second implantation region 5 to form a trigger junction.

[0042] Specifically, in order to obtain smooth and steep sidewalls of the deep trench 4, multiple sacrificial oxidation processes are used to repair lattice defects caused by etching; then, a high concentration of N+ type polycrystalline silicon layer 6 is deposited on the entire silicon wafer surface through chemical vapor deposition (LPCVD) to ensure that the deep trench 4 structure is completely filled.

[0043] Preferably, the resistivity of the N+ type polycrystalline silicon layer 6 is 3Ω·cm to 12Ω·cm, and the deposition thickness of the N+ type polycrystalline silicon layer 6 is 1μm to 2μm.

[0044] After the polysilicon layer 6 is deposited, high-temperature advance / annealing is performed to diffuse impurities in the N+ type polysilicon layer 6 into the silicon epitaxial layer 2, forming the N+ type first implantation region 7; at the same time, the implanted impurities in the P+ type second implantation region 5 at the bottom of the deep trench 4 are activated and advanced, and their doping distribution and junction depth are adjusted.

[0045] Preferably, the annealing temperature in the thermal annealing process is 950℃~1200℃, and the time is 60~180 minutes. After the thermal annealing process, an NPN structure is formed, consisting of an N+ type polysilicon layer 6, a diffused N+ type first injection region 7, a P-type epitaxial layer 2, an N+ type polysilicon layer 6, and a diffused N+ type first injection region 7. Simultaneously, the diffused N+ type first injection region 7 and the diffused P+ type second injection region 5 form a trigger junction, preferentially conducting. Furthermore, since the P+ type second injection region 5 is located at the bottom of the deep trench 4, current flows through the N+ type polysilicon layer 6 within the deep trench 4 to the bottom, further promoting the conduction of the NPN transistors (composed of the N+ type first injection region 7, the P-type epitaxial layer 2, and the N+ type first injection region 7) along its path, thus playing a role in current equalization.

[0046] Step S5, as follows Figure 5f As shown, remove excess polysilicon, such as Figure 5g As shown, a front metal layer is formed on the upper surface of the epitaxial layer 2 and the second oxide layer 3, and the front metal layer is electrically connected to the polysilicon layer 6.

[0047] Specifically, an anisotropic dry etch-back process is used to remove excess polysilicon from the surface of epitaxial layer 2, ensuring that the polysilicon material remains only inside the trench 4, forming a polysilicon-filled structure in trench 4. Alternatively, excess polysilicon can be removed by chemical mechanical polishing (CMP) or photolithography. In this embodiment, etch-back is preferred to save one photolithography layer.

[0048] Metal is deposited directly on the surface of the epitaxial layer 2 and the second oxide layer 3 to form a front metal layer. The front metal layer is then photolithographically etched and metal interconnects are formed to form a first metal layer 81 and a second metal layer 82. The first metal layer 81 serves as the first port IO1 and the second metal layer 82 serves as the second port IO2.

[0049] Preferably, the front metal layer adopts a three-layer composite structure of titanium (Ti), titanium nitride (TiN), and aluminum-silicon-copper alloy (AlSiCu); wherein the thickness of the titanium layer is 200Å~500Å, the thickness of the titanium nitride layer is 400Å~1000Å, and the thickness of the aluminum-silicon-copper alloy layer is 2μm~5μm.

[0050] Step S6, as follows Figure 5g As shown, a passivation layer 9 is formed on the upper surface of the second oxide layer 3 and part of the front metal layer, and an opening is made in the passivation layer 9 to expose the front metal layer.

[0051] Specifically, silicon nitride is deposited on the upper surface of the second oxide layer 3 and part of the front metal layer to form a passivation layer 9, and holes are made in the passivation layer 9 to expose the front metal layer. Compared with the through-hole process, in this embodiment, the surface is directly connected to the metal layer after polysilicon etch-back, saving the contact hole process.

[0052] This invention optimizes the process by reducing the number of photolithography layers for polycrystalline materials and contact holes, thereby improving performance while reducing costs.

[0053] Of course, contact holes can also be added to increase the contact area.

[0054] Step S7, as follows Figure 5h As shown, the substrate 1 is thinned on the back side to form a back metal layer 10 on the lower surface of the substrate 1.

[0055] Specifically, the back side of the silicon wafer is thinned to obtain the required silicon wafer thickness, and a metal layer is deposited on the back side through back metallization to form good ohmic contact and solderability.

[0056] Preferably, the thickness of the thinned substrate 1 is 80μm~150μm, and the back metal layer 10 adopts a three-layer composite structure of titanium (Ti), nickel (Ni), and silver (Ag).

[0057] The bidirectional surge protector and its fabrication method of this invention form a new PN trigger junction with the N+ type first injection region 7 diffused at the bottom of the deep trench 4 and the P+ type second injection region 5. When encountering a negative surge, i.e., when the first port IO1 is at a negative potential and the second port IO2 is at a positive potential, this trigger junction undergoes avalanche breakdown before other junctions, injecting holes into the P-type epitaxial layer 2, thereby more effectively triggering the conduction of the vertical NPN transistor (composed of the N+ type first injection region 7, the P+ type second injection region 5, the P-type epitaxial layer 2, and the N+ type first injection region 7). Due to the depth of the deep trench 4, current flows through the N+ type first injection region 7 within the deep trench 4 to the bottom, causing the NPN transistor (composed of the N+ type first injection region 7, the P-type epitaxial layer 2, and the N+ type first injection region 7) along its path to further conduct, solving the current sharing problem. The newly added trigger junction is equivalent to adding a triggering mechanism of parasitic structure, optimizing the conduction path, making large current conduction easier and more uniform, and improving the current sharing characteristics.

[0058] The introduction of the P+ type second injection region 5 optimizes the triggering process and current spread, enabling all parallel deep trench 4 units inside the chip to respond to surges almost simultaneously and share the current, thus avoiding the formation of local hot spots and greatly improving the surge tolerance of the device.

[0059] The implantation process of the P+ type second implantation region 5 can be easily integrated into the standard process flow after the deep trench 4 etching and before the polysilicon filling. It can be shared with the deep trench 4 etching mask without the need for additional photomasks. At the same time, it reduces the use of contact hole layer photomasks. Without the need for additional special processes, the manufacturing cost is greatly reduced and the process compatibility is strong.

[0060] Example 2 To enhance chip performance and reliability, such as Figure 6 As shown, this embodiment of the invention provides a bidirectional surge protector, which, based on embodiment 1, further includes: A deep trench isolation structure 11 is formed in the epitaxial layer 2. The deep trench isolation structure 11 extends from the surface of the epitaxial layer 2 toward the substrate 1 and surrounds a plurality of deep trenches 4.

[0061] Specifically, by introducing an additional trench isolation structure 11 in the peripheral area of ​​the chip, external noise and electrical interference can be effectively blocked, preventing them from affecting the working stability of the internal core components, improving the overall anti-interference capability and signal integrity of the chip, and further enhancing the reliability and service life of the product in complex application environments.

[0062] The above are merely preferred embodiments of the present invention and are not intended to limit the implementation methods and protection scope of the present invention. Those skilled in the art should recognize that any equivalent substitutions and obvious changes made using the content of this specification and illustrations should be included within the protection scope of the present invention.

Claims

1. A bidirectional surge protector, characterized in that, include: Substrate, the substrate having a first conductivity type; An epitaxial layer is formed on the substrate, the epitaxial layer having a first conductivity type; Multiple deep trenches are formed in the epitaxial layer, and the multiple deep trenches are distributed in an array, extending from the surface of the epitaxial layer toward the substrate; A first injection region is formed in the epitaxial layer, the first injection region is electrically connected to the bottom and sidewall of the deep trench, and the first injection region has a second conductivity type opposite to the first conductivity type; A second injection region is formed in the epitaxial layer. The second injection region has a first conductivity type and is electrically connected to the first injection region at the bottom of the deep trench to form a trigger junction.

2. The bidirectional surge protector according to claim 1, characterized in that, The first conductivity type is N-type, and the second conductivity type is P-type; or the first conductivity type is P-type, and the second conductivity type is N-type.

3. The bidirectional surge protector according to claim 1, characterized in that, Also includes: A deep trench isolation structure is formed in the epitaxial layer, the deep trench isolation structure extends from the surface of the epitaxial layer toward the substrate, and the deep trench isolation structure surrounds the plurality of deep trenches.

4. The bidirectional surge protector according to claim 1, characterized in that, The depth of the deep groove is 5μm to 53μm, the width of the deep groove is 0.5μm to 2.5μm, and the distance between two adjacent deep grooves is 1μm to 3μm.

5. The bidirectional surge protector according to claim 1, characterized in that, The implanted element in the second implantation region is boron or boron difluoride, the implantation energy in the second implantation region is 30~200 keV, the implantation dose in the second implantation region is 1E14~2E16 cm⁻², and the implantation angle in the second implantation region is 0 degrees.

6. The bidirectional surge protector according to claim 1 or 3, characterized in that, Also includes: A first oxide layer is formed on the upper surface of the epitaxial layer; The second oxide layer is formed on the upper surface of the first oxide layer, and the deep trench is formed by photolithography and etching using the second oxide layer as a hard mask. A polycrystalline silicon layer is formed within the deep trench, the polycrystalline silicon layer having a second conductivity type; A front metal layer is formed on the upper surface of the epitaxial layer and the second oxide layer, and the front metal layer is electrically connected to the polysilicon layer. A passivation layer is formed on the upper surface of the second oxide layer and a portion of the front metal layer; A back metal layer is formed on the lower surface of the substrate.

7. The bidirectional surge protector according to claim 6, characterized in that, The thickness of the first oxide layer is 200 Å to 500 Å; the thickness of the second oxide layer is 10000 Å to 20000 Å.

8. A method for preparing a bidirectional surge protector, used to prepare the bidirectional surge protector as described in any one of claims 1-7, characterized in that, include: Step S1: Provide a substrate having a first conductivity type, form an epitaxial layer having a first conductivity type on the substrate, form a first oxide layer on the epitaxial layer, and form a second oxide layer on the first oxide layer; Step S2: Using the second oxide layer as a hard mask, photolithography and etching are performed on the epitaxial layer to form multiple deep trenches. The multiple deep trenches are arranged in an array and extend from the surface of the epitaxial layer to the substrate. Step S3: Selective ion implantation is performed at the bottom of the deep trench to form a second implantation region; Step S4: Fill the deep trench with a polysilicon layer of the second conductivity type and perform thermal annealing to allow the polysilicon filled in the deep trench to diffuse into the epitaxial layer, forming a first implantation region. The first implantation region is electrically connected to the bottom and sidewall of the deep trench, and the first implantation region at the bottom of the deep trench is electrically connected to the second implantation region to form a trigger junction. Step S5: Remove excess polysilicon and form a front metal layer on the upper surface of the epitaxial layer and the second oxide layer. The front metal layer is electrically connected to the polysilicon layer. Step S6: A passivation layer is formed on the upper surface of the second oxide layer and part of the front metal layer, and an opening is made in the passivation layer to expose the front metal layer. Step S7: Thin the back side of the substrate to form a back metal layer on the lower surface of the substrate.

9. The method for preparing a bidirectional surge protector according to claim 8, characterized in that, In the heat annealing process of step S4, the annealing temperature is 950℃~1200℃ and the time is 60~180 minutes.

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