Wafer inspection method during or after dicing

Abstract

This disclosure relates to a method for image alignment of a grid array chip. The method may include: a step of acquiring an original image of the grid array chip; a step of global alignment of a first corrected image obtained by calculating the alignment offset between the actual position of each chip and a reference position from the original image and performing correction of the entire image based on the alignment offset, or by performing physical rotation error correction on the wafer and then acquiring the image again; and a step of fine-tuning correction of a first corrected image obtained by calculating a transformation matrix between a reference chip and a target chip on the first corrected image and applying the transformation matrix to each target chip.

Description

Technical Field

[0001] This disclosure relates to a wafer inspection method during or after dicing, specifically to a method for improving inter-chip comparison and inspection performance by aligning and correcting images of grid array chips taken for inspection of the wafer. Background Technology

[0002] Semiconductor manufacturing processes include a dicing process, which separates multiple dies integrated on a wafer into individual chip units. During the dicing process, the wafer is cut along scribe lines formed between the chips. The cut wafer is typically fixed to an adhesive film and then supported by a ring frame.

[0003] To ensure proper spacing between chips, the cut wafers require horizontal and vertical stretching of the thin film, thereby increasing the spacing between the chips. The target sample in this application may, for example, include a wafer with a diameter of 300 mm; if a ring frame is included, the total diameter can reach approximately 400 mm. However, this is merely exemplary, and the target sample is not limited to this.

[0004] like Figure 1 As shown, the individual chips 3 cut along scribe line 4 still exist within the 300mm wafer area, but the chip edges may curl under relatively weak adhesion, and scribe line 4 is not smooth and uniform due to inconsistent cutting quality of each chip. Furthermore, after film stretching, as... Figure 2 As shown, the spacing and rotation angle between chips may vary depending on the chip, and some chips may even fall off or be missing during the cutting process.

[0005] These physical conditions introduce various challenges to image-based detection and alignment algorithms. For example, irregular chip spacing, varying rotation angles, or inconsistent reference marker positions can make precise alignment and position correction of the entire chip array difficult. Furthermore, if some chips are missing or have curled edges, setting alignment references using reference points may be inaccurate. These problems significantly degrade the performance of common wafer inspection methods—chip-to-chip comparison inspection.

[0006] Therefore, a technology is needed that can overcome physical conditions such as uneven spacing between chips, rotation, deformation, and missing parts, and can accurately align and correct the entire grid array.

[0007] [Preliminary Technology Documents] [Patent Documents] Korean Patent Registration Publication No. 10-1561786 (registered on October 13, 2015) Summary of the Invention

[0008] According to one aspect of this disclosure, alignment can be achieved by taking into account various physical conditions such as chip spacing changes caused by thin film stretching, rotational errors, and chip defects.

[0009] In addition, accurate correction results can still be obtained despite uneven lines and deviations in marker positions.

[0010] In addition, by correcting local areas inside the chip, it is also possible to effectively correct chip deformation, local twisting, curling and other phenomena.

[0011] In addition, by generating a corrected image of the entire grid array alignment on the reference coordinate system, it can be used for subsequent automated optical inspection (AOI), defect analysis, etc.

[0012] In addition, even if some chips are missing, corrections can be made based on information from adjacent chips, thereby ensuring the stability of the system.

[0013] In addition, performing inter-chip comparison detection by aligning and correcting the images can improve detection performance and ensure the stability of the entire detection system.

[0014] The subject matter of this invention is not limited to the subject matter mentioned above, and those skilled in the art will clearly understand other subject matters not mentioned from the following description.

[0015] This invention provides a method for detecting grid array chips on a wafer, comprising: acquiring an original image of the grid array chips; calculating the alignment offset between the actual position of each chip and a reference position from the original image, and performing correction of the entire image based on the alignment offset, or acquiring the image again after performing physical rotation error correction on the wafer, thereby obtaining a first corrected image that is approximately aligned, a global alignment step; and calculating the transformation matrix between the reference chip and the target chip on the first corrected image, and applying the transformation matrix to each target chip, thereby converting the first corrected image into a second corrected image, a fine-tuning correction step.

[0016] In addition, the fine-tuning correction step is performed by a marker-based alignment method, which involves detecting at least one marker in the image of each target chip and calculating the transformation matrix based on the coordinate information of the marker.

[0017] In addition, the transformation matrix is ​​calculated separately for each target chip, and after applying the transformation matrix, a second correction image is generated in which each target chip is precisely aligned on the reference coordinate system.

[0018] In addition, the fine-tuning and correction steps include the following steps: extracting the reference marks of each target chip; setting a one-to-one correspondence between the reference marks of the reference chip and the reference chip; and calculating the transformation matrix based on the relative positions of the corresponding mark pairs of the target chip and the reference chip.

[0019] In addition, reference marks are physical identification patterns or structures configured at predefined locations inside the chip.

[0020] In addition, the transformation matrix includes offset information of the target chip in the X, Y, and θ axis directions to correct the misaligned target chip to an aligned state.

[0021] In addition, the transformation matrix includes correction vectors for each local region of the target chip to correct for deformation of the target chip.

[0022] In addition, the transformation matrix is ​​a 2D transformation matrix, which is composed of Euclidean transformation, affine transformation, or projective transformation matrices.

[0023] In addition, the fine-tuning and correction step involves taking the center of the ring frame as the origin, setting the horizontal and vertical directions of the ring frame as the X-axis and Y-axis respectively, constructing a reference coordinate system, and performing geometric correction on each chip to generate a second correction image in which the grid array of the chips is arranged in the correct orientation.

[0024] In addition, the global alignment step includes the following steps: calculating the approximate position of the alignment reference chip; and scanning the first group of chips arranged in at least one row or at least one column of the grid array chip to calculate the alignment offset.

[0025] In addition, the transformation matrix includes information on alignment offset.

[0026] In addition, the approximate position of the alignment reference chip is calculated from the specified template position within the alignment reference chip, and the alignment offset is calculated from the specified template position within the first group of chips.

[0027] In addition, the alignment offset is calculated based on the rotation angle of the specified template position of each chip in the first group relative to the baseline, and the first correction image is obtained with the entire chip rotated based on the rotation angle.

[0028] Additionally, it includes performing at least one preprocessing step, such as noise reduction, brightness correction, or contrast enhancement, before acquiring the original image.

[0029] According to one embodiment of this disclosure, alignment can be achieved by taking into account various physical conditions such as chip spacing changes caused by thin film stretching, rotational errors, and chip defects.

[0030] In addition, accurate correction results can still be obtained despite uneven lines and deviations in marker positions.

[0031] In addition, by correcting local areas inside the chip, it is also possible to effectively correct chip deformation, local twisting, curling and other phenomena.

[0032] In addition, by generating a corrected image of the entire grid array alignment on the reference coordinate system, it can be used for subsequent automated optical inspection (AOI), defect analysis, etc.

[0033] In addition, even if some chips are missing, corrections can be made based on information from adjacent chips, thereby ensuring the stability of the system.

[0034] In addition, performing inter-chip comparison detection by aligning and correcting the images can improve detection performance and ensure the stability of the entire detection system.

[0035] The effects of the present invention are not limited to those described above. Those skilled in the art to which this invention pertains can clearly understand any effects not mentioned from this specification and the accompanying drawings. Attached Figure Description

[0036] Figure 1 An example of a ring-shaped frame wafer is shown.

[0037] Figure 2 This illustrates the misalignment between adjacent chips on a ring-shaped frame wafer.

[0038] Figure 3 This is a flowchart of the method according to this disclosure.

[0039] Figure 4 This is a flowchart of a global alignment step according to an example of this disclosure.

[0040] Figure 5 The diagram shows the first corrected image obtained after a global alignment step from the original image of a wafer with a rotational error relative to the reference coordinate system.

[0041] Figure 6 An example is shown of the process of performing a global alignment.

[0042] Figure 7 This is a flowchart of fine-tuning correction step 130 according to an example of this disclosure.

[0043] Figure 8 Reference chips (DIEs) and target chips (DIEs) corresponding to each reference chip are shown.

[0044] Figure 9 An example is shown of correcting an image of a target chip using a transformation matrix.

[0045] Label Explanation

[0046] 1: Ring-shaped frame wafer 2: Ring frame 3: Chip 4: Drawing lines 100: Image Alignment Methods 110: Steps for acquiring the original image 120: Global Alignment Steps 121: Steps for setting information about the alignment reference chip and reference template 122: Template location detection steps on the original image 123: Alignment Offset Calculation Steps 124: First Correction Image Acquisition Step 130: Fine-tuning and correction steps 131: Label Detection Steps 132: Steps for setting up the correspondence between tags 133: Steps for calculating the transformation matrix 134: Second Correction Image Generation Step 140: Wafer Inspection Execution Steps D: Chip T: Template Detailed Implementation

[0047] The present disclosure will now be described in detail with reference to the accompanying drawings. However, this is merely exemplary, and the present disclosure is not limited to the specific embodiments described herein.

[0048] According to one example of the method disclosed herein, it can be executed by a hardware-implemented system or a control device that executes a software instruction set. More specifically, this disclosure relates to a wafer inspection method and system for inspecting the image alignment and correction process of grid array chips on a wafer, the system including an imaging device, a controller, and an output device or storage device, etc.

[0049] The imaging device may include at least one image sensor or image acquisition module as a component for capturing raw images of the chip, and may be combined with optical devices such as lenses, mirrors, and apertures, as well as illumination devices.

[0050] The controller, as a component controlling the image alignment and correction process, may include memory and a processor. The memory may be configured to store more than one instruction set, and the processor may execute the instruction set to perform operations such as chip alignment offset calculation, corrected image generation, transformation matrix calculation, and correction execution, as described later. The controller may include the function of aligning each chip according to a reference coordinate system and outputting a corrected image.

[0051] The output device or storage device can provide the corrected image data to the subsequent inspection system or analysis system so that subsequent wafer inspections such as automated optical inspection (AOI) and defect analysis can be performed.

[0052] Such a system can be implemented by more than one computing device or processor-based device, and can operate in a local or cloud-based environment. The system can consist of various forms of hardware, software, firmware, or combinations thereof, and can be configured to perform all or part of the aforementioned image alignment and correction process.

[0053] The image alignment and correction methods of this disclosure will be described in detail below.

[0054] like Figure 3 As shown, an image alignment method according to an example of this disclosure may include: a step 110 of acquiring an original image of the grid array chips; a global alignment step 120 of calculating the alignment offset between the actual position of each chip and the reference position from the original image, and performing correction of the entire image based on the alignment offset (e.g., rotation correction), or acquiring the image again after performing physical rotation error correction on the wafer, thereby obtaining a first corrected image that is approximately aligned; and a fine-tuning correction step 130 of calculating the transformation matrix between the reference chip and the target chip on the first corrected image, and applying the transformation matrix to each target chip, thereby converting the first corrected image into a second corrected image. The second corrected image acquired in the fine-tuning correction step 130 may be provided to a subsequent inspection system or analysis system for subsequent use in performing wafer inspections such as automated optical inspection (AOI) and defect analysis.

[0055] The following describes step 110 of acquiring the original image.

[0056] In this disclosure, "raw image" can refer to image data captured of all or part of a wafer fixed on a ring frame and the chips arranged thereon. The raw image can be acquired by an image acquisition device. The image acquisition device can be an optical imaging device using line scanning or area scanning methods, such as a TDI camera, a 3D structured light camera, a high-magnification optical microscope camera, a laser angle measurement sensor, etc. The image acquisition device can cover the entire ring frame or sequentially scan multiple areas to form the entire image.

[0057] The acquired raw images can typically include the position, rotation state and shape of individual chips, the spacing and alignment between chips, reference marks or structural patterns inside or outside the chips, the shape of the scribing boundary after cutting, and the absence or omission of some chips.

[0058] In addition, the original image may have various resolutions and contrasts, and may contain factors such as noise or shadows depending on the shooting environment (lighting, exposure conditions, etc.). These characteristics may become factors that need to be considered in subsequent alignment and correction processes.

[0059] The original image can be used as basic input data to determine the alignment status of the entire chip array and to perform transformation to the reference coordinate system and precise correction.

[0060] The following will refer to Figures 4 to 7 The following provides a detailed explanation of the global alignment step 120. Figure 4 This is a flowchart of a global alignment step according to an example of this disclosure. Figure 5 The image shows the first corrected image obtained after a global alignment step from the original image, which is tilted globally relative to the reference coordinate system. Figure 6 An example is shown of the process of performing a global alignment.

[0061] In this step, the alignment offset can be calculated, and a first corrected image can be obtained based on it. The global alignment step according to the invention is a preprocessing step for correcting the approximate alignment state of the entire chip array obtained from an original image fixed on a ring frame. In this step, the difference between the actual position of each chip and the reference position defined according to the design or system reference can be inferred, and uniform rotation and movement corrections are performed on the entire image, thereby bringing the grid array closer to the reference state.

[0062] More specifically, the global alignment step 120 may include the subroutines described below.

[0063] (a) Setting alignment reference chip and reference template information Among the multiple chips on the original image, one or more alignment reference chips (ARDs) can be selected. Alignment reference chips are used to define a reference coordinate system throughout the grid array; chips with guaranteed structural stability and recognizability can be selected. For example, based on the coordinate system reference on the ring wafer, the chip corresponding to the lowest left LLC (Lower left chip) can be selected, or a chip close to the center of the ring frame or with high template recognition quality can be selected.

[0064] The alignment reference chip can be assigned a predefined reference template position, which can correspond to a specific structure within the alignment reference chip (e.g., circuit pattern, edge shape, etc.). The reference template position can serve as a reference point on the reference coordinate system and as a reference for calculating the relative positional relationship with other chips.

[0065] (b) Detecting the template location on the original image The actual template T positions of multiple chips D are detected on the original image. These template positions can be defined based on specific patterns, structural features, or fixed positional references within each chip, and can be detected using image processing techniques such as template matching, edge detection, and feature point extraction. In addition to the alignment reference chip, the template positions of chip groups contained in more than one row or column can also be detected simultaneously. This process can be omitted if the alignment offset is calculated only using the reference chip; this will be further explained in the next section.

[0066] (c) Calculate alignment offset The alignment offset corresponding to the distance difference (ΔX, ΔY, Δθ) between the detected template position coordinates of each chip and the corresponding reference template position is calculated. Using multiple template position pairs as a reference, the rotation error (Δθ) of the entire array can be inferred based on the configuration error of each chip.

[0067] For example, such as Figure 6 As shown, a representative rotation angle θ can be inferred from chips D contained in more than one row or column, or the tilt of the entire grid can be calculated using multiple template positions T. Specifically, the overall tilt angle can be calculated by analyzing the degree to which the template positions of consecutive chip columns or rows deviate from the reference line (RL).

[0068] Alternatively, if the positional relationships between templates detected from a reference chip are known (e.g., vertical, horizontal, etc.), the rotational error (Δθ) of the entire array can be inferred using a single reference chip instead of multiple chips.

[0069] (d) Apply rotation and translation corrections The calculated alignment offsets (ΔX, ΔY, Δθ) can be uniformly applied to the entire image, thereby converting the original image into a first corrected image that is approximately aligned in the reference coordinate system. Alternatively, a first corrected image that is approximately aligned in the reference coordinate system can be obtained by performing physical rotation error correction on the wafer and then acquiring the image again.

[0070] The global alignment step according to this disclosure is a basic alignment step used before performing precision calibration on the entire chip, bringing the positions of each chip to a near-matched state in a reference coordinate system. In this step, the errors of individual chips are not precisely calibrated; only overall rotational, horizontal, and vertical positional corrections are applied.

[0071] This step corrects the physically slightly irregularly arranged chips to a near-reference arrangement, thus providing a stable base image—the first corrected image—for subsequent precise correction and registration of each chip. Fine-tuning of individual chips can be performed in subsequent fine-tuning steps.

[0072] The following will refer to Figures 7 to 9 The fine-tuning and correction step 130 is explained in detail. Figure 7 This is a flowchart of fine-tuning and correction step 130 according to an example of this disclosure. Figure 8 Reference chips (DIEs) and target chips (DIEs) corresponding to each reference chip are shown. Figure 9 An example is shown of correcting an image of a target chip using a transformation matrix.

[0073] After roughly aligning the entire chip array in the reference coordinate system through a global alignment step, a fine-tuning correction step can be performed to precisely correct and align each target chip. In this step, the relative positions, rotations, deformations, etc., between the reference die and each target chip can be accurately compared, and a transformation matrix expressed as a mathematical formula can be calculated, based on which a second corrected image is generated.

[0074] More specifically, this step may include the steps described below.

[0075] 1. Detection Marker One or more markers contained in the reference chip serving as the registration benchmark and each target chip are detected on the image. The markers are typically identifiable structures within the chip and may take the form of lines, corners, rectangles, crosses, circles, etc., and may consist of or include all or part of the template detected in the global alignment step 120. Preferably, at least four markers are defined and uniformly distributed within the chip area to calculate the transformation matrix.

[0076] 2. Set the mapping relationship between markers Establish a one-to-one correspondence between the markers on the reference chip and the markers on each target chip. The correspondence can be set automatically or manually based on factors such as position coordinates, pattern shape, and mutual distance.

[0077] 3. Calculate the transformation matrix Using the corresponding tag pairs as a reference, a transformation matrix containing transformation information that matches the target chip with the reference chip is calculated. This matrix can be a 2D transformation matrix, which can include translation, rotation θ, scaling, tilting, etc. in the X and Y directions, and can be composed of Euclidean transformation, affine transformation, or projective transformation.

[0078] The transformation matrix can include the X, Y, and θ axis offset information of each target chip. This information can be applied to each target chip to accurately correct misaligned or distorted target chips.

[0079] In some embodiments, the target chip can be divided into multiple local regions, and a nonlinear transformation containing correction vectors for each region can be applied. Although the chip is fixed on a ring frame, due to sawing, thermal deformation, residual stress, substrate bending, etc. during the manufacturing process, even if the entire chip is aligned, the chip edges may be bent or twisted. Therefore, the transformation matrix can perform local deformation correction based on pattern matching.

[0080] For example, if a specific reference circuit pattern within a chip is deformed due to its difference from the design data (CAD), the degree of deformation in each region can be inferred by matching it to the CAD, and nonlinear correction (warping) can be applied. For instance, if the pattern is compressed only in the X-axis direction, the bending or twisting can eventually be corrected by increasing the scaling factor of only that region.

[0081] In some embodiments, the transformation matrix may contain alignment offset information. By reusing the alignment offset calculated in the global alignment step during the fine-tuning correction step, the reference error during precision correction can be further reduced, and system processing time can be decreased.

[0082] 4. Generate the second corrected image The calculated transformation matrix is ​​applied to each target chip to adjust its position, rotation, scaling, or tilt. Correction is performed through coordinate transformation in the image coordinate system and can be mapped to individual pixels or sub-pixel units.

[0083] After calibration, each target chip will be positioned on the reference coordinate system, ultimately generating a second calibrated image in which the entire grid array is aligned in the correct orientation. If necessary, the alignment quality can be evaluated; if the calibration error exceeds the allowable range, the chip can be excluded or the calibration can be re-performed.

[0084] As described above, according to this disclosure, not only is the entire chip array roughly aligned, but individual chips are also precisely aligned, thereby ensuring high positional accuracy and reliability in subsequent inspection and analysis processes.

[0085] While embodiments of the present invention have been described above with reference to the accompanying drawings, it will be understood by those skilled in the art that the present invention can be implemented in other specific forms without altering its technical concept or essential features. Therefore, the above embodiments should be understood as exemplary and not restrictive in all respects.

Claims

1. A method for detecting grid array chips on a wafer, characterized in that, include: Steps for obtaining the raw image of a grid array chip; The global alignment step involves calculating the alignment offset between the actual position of each chip and the reference position from the original image, and performing image correction based on the alignment offset, or performing physical rotation error correction on the wafer and then acquiring the image again to obtain a roughly aligned first corrected image; and A fine-tuning correction step involves calculating the transformation matrix between the reference chip and the target chip on the first correction image and applying the transformation matrix to each target chip to convert the first correction image into a second correction image.

2. The method according to claim 1, characterized in that, The fine-tuning correction step is performed using a marker-based alignment method, which involves detecting at least one marker in the image of each target chip and calculating the transformation matrix based on the coordinate information of the marker.

3. The method according to claim 2, characterized in that, The transformation matrix is ​​calculated individually for each target chip, and after applying the transformation matrix, a second correction image is generated in which each target chip is precisely aligned on the reference coordinate system.

4. The method according to claim 3, characterized in that, The fine-tuning and correction process includes the following steps: Extract the reference markers for each target chip; Set the reference chip's reference mark and establish a one-to-one correspondence; The transformation matrix is ​​calculated based on the relative positions of the corresponding marker pairs of the target chip and the reference chip.

5. The method according to claim 4, characterized in that, A reference mark is a physical identification pattern or structure configured at a predefined location inside a chip.

6. The method according to claim 3, characterized in that, The transformation matrix includes offset information of the target chip in the X, Y, and θ axis directions to correct the misaligned target chip to an aligned state.

7. The method according to claim 6, characterized in that, The transformation matrix includes correction vectors for various local regions of the target chip to correct for deformation of the target chip.

8. The method according to claim 2, characterized in that, The transformation matrix is ​​a 2D (2-dimensional) transformation matrix. It consists of Euclidean, affine, or projective transformation matrices.

9. The method according to claim 1, characterized in that, The fine-tuning and calibration steps involve establishing a reference coordinate system with the center of the ring frame as the origin, setting the horizontal and vertical directions of the ring frame as the X and Y axes respectively, and then performing geometric calibration on each chip. This generates a second corrected image in which the chip's grid array is aligned in the positive direction.

10. The method according to claim 1, characterized in that, The global alignment process includes the following steps: Calculate the approximate location of the alignment reference chip; and The first group of chips arranged in at least one row or at least one column of the scan grid array chip is used to calculate the alignment offset.

11. The method according to claim 10, characterized in that, The transformation matrix includes information about the alignment offset.

12. The method according to claim 10, characterized in that, The approximate position of the alignment reference chip is calculated from a specified template position within the alignment reference chip. The alignment offset is calculated from the specified template position within the first group of chips.

13. The method according to claim 12, characterized in that, The alignment offset is calculated based on the rotation angle of the specified template position of each chip in the first group relative to the baseline. The first calibration image was obtained with the entire chip rotated based on the rotation angle.

14. The method according to claim 1, characterized in that, The global alignment step includes the step of inferring the rotational error (Δθ) of the entire array from a reference chip.

15. The method according to claim 1, characterized in that, It also includes performing at least one preprocessing step, such as noise reduction, brightness correction, or contrast enhancement, before acquiring the original image.

Images