Through-substrate via structures and processes

Abstract

A microelectronic structure is disclosed that includes a first element and a through-substrate via (TSV) structure. The first element includes a bulk portion having a front side and a back side opposite the front side. The TSV structure is disposed in an opening extending from the front side to the back side at least partially through the bulk portion. The TSV structure includes a conductive tip portion and a second conductive via portion. The second conductive via portion is disposed between the front side and the conductive tip portion. The conductive tip portion comprises a different conductive material than the second conductive via portion.

Description

Cross-references to related applications

[0001] This application claims priority to U.S. Nonprovisional Patent Application No. 18 / 515,964, filed November 21, 2023, which claims priority to U.S. Provisional Patent Application No. 63 / 587,010, filed September 29, 2023, the entire disclosure of which is incorporated herein by reference. Technical Field

[0002] This disclosure relates to structures having through-substrate vias and methods for forming the same. Background Technology

[0003] Semiconductor elements, such as integrated device dies or chips, can be mounted or stacked on other elements. For example, semiconductor elements can be mounted on a carrier, such as a packaging substrate, interposer, reconfigured wafer or element, or other semiconductor elements. As another example, semiconductor elements can be stacked on top of another semiconductor element; for instance, a first integrated device die can be stacked on top of a second integrated device die. In some arrangements, through-substrate vias (TSVs) can extend vertically through the thickness of the semiconductor element to transmit electrical signals through it, for example, from a first surface of the semiconductor element to a second opposing surface. There is a continuing need for improved methods of forming TSVs. Attached Figure Description

[0004] In this discussion, the devices and systems illustrated in the figures are shown as having multiple components. Various embodiments of the devices and / or systems described herein may include fewer components, but are still within the scope of this disclosure. Alternatively, other embodiments of the devices and / or systems may include additional components, or various combinations of said components, and are still within the scope of this disclosure.

[0005] These and other aspects will become apparent from the following description of preferred embodiments and the accompanying drawings, which are intended to illustrate and not limit the invention, wherein:

[0006] Figure 1A This is a schematic side cross-sectional view of the two elements prior to their hybrid bonding, according to an embodiment.

[0007] Figure 1B According to the embodiments, Figure 1A A schematic side cross-sectional view of the two elements after they are mixed and joined.

[0008] Figure 2A-2G The diagram shows a series of schematic side cross-sectional views of a method according to an embodiment, by which a first element of a microelectronic structure can be formed as a through-hole structure having a conductive tip made of a material different from the rest of the TSV before the back surface is exposed.

[0009] Figure 2H This is a schematic side cross-sectional view of the microelectronic structure according to an embodiment, wherein Figure 2G The first element shown is mixed and joined with a second element having a similar TSV structure.

[0010] Figures 3A-3D These are a series of schematic side cross-sectional views illustrating a method according to an embodiment, through which... Figure 2G The first component can be further processed to provide a bonding pad above the conductive tip.

[0011] Figure 4A This is a schematic side cross-sectional view of a microelectronic structure according to an embodiment, which is similar to... Figure 2G However, it has a redistribution layer formed above the side with the conductive tip.

[0012] Figure 4B This is a schematic side cross-sectional view of a microelectronic structure according to an embodiment, which is similar to... Figure 2G The microelectronic structure shown has a bonding pad formed on the back side of the conductive tip, wherein the bonding pad is wider than the conductive tip.

[0013] Figure 4C This is a schematic side cross-sectional view of a microelectronic structure, which is similar to... Figure 4B It is then combined with a second microelectronic component having a similar TSV structure.

[0014] Figures 5A-5D These are a series of schematic side cross-sectional views illustrating a method according to an embodiment, by which, before being exposed, similar to Figure 2G The microelectronic structure is provided with a sacrificial tip material, which is then replaced to form a conductive tip.

[0015] Figure 5E This is a schematic side cross-sectional view of the microelectronic structure according to an embodiment, wherein Figure 5D The first element shown is mixed and joined with a second element having a similar TSV structure.

[0016] Figure 6 This is a schematic side cross-sectional view of a microelectronic structure according to an embodiment, which is similar to... Figure 2G The microelectronic structure shown includes a conductive tip containing solder.

[0017] Figures 7A-7C A schematic side cross-sectional view of a microelectronic structure according to some embodiments is shown, which is similar to the microelectronic structure shown in the foregoing embodiments and is coupled to a second microelectronic element having various configurations in a conventional manner. Detailed Implementation

[0018] The embodiments described herein facilitate hybrid bonding on the back side of a substrate having through-substrate vias. Novel techniques for providing TSVs are taught, including segmented TSVs formed from multiple materials, which provides advantages for hybrid bonding preparation. In some embodiments, the deep vias formed from the front side of the substrate are only partially filled with a first material, for example, by using a bottom-up deposition technique or by filling and recessing. The remaining portion of the via is filled with a second material. When the substrate is thinned from the back side, the first material is first exposed. The back side can then be prepared for hybrid bonding. In some embodiments, the first material retains a portion of the TSV on the back side. In some embodiments, the first material is directly bonded to the conductor of another element in the hybrid bonding process. In other embodiments, pads are provided to intervene between the first material of the TSV and the conductor of the other element. In other embodiments, the first material is a sacrificial material, replaced by a suitable conductive material prior to hybrid bonding.

[0019] The various embodiments disclosed herein relate to direct bonding structures in which two or more elements can be directly bonded to each other without the intervention of an adhesive. Such processes and structures are referred to herein as “direct bonding” processes or “direct bonding” structures. Direct bonding can involve the bonding of one material on one element to one material on another element (also referred to herein as “uniform” direct bonding), where the materials on the different elements need not be identical, and no conventional adhesive material is used. Direct bonding can also involve the bonding of multiple materials on one element to multiple materials on another element (e.g., mixed bonding).

[0020] In some implementations (not illustrated), each bonding layer has one material. In these uniform direct bonding processes, only one material is directly bonded on each element. Example uniform direct bonding processes include ZIBOND® technology, commercially available from Adeia, Inc., San Jose, California. The materials of opposing bonding layers on different elements can be the same or different, and can contain elemental or compound materials. For example, in some embodiments, non-conductive bonding layers can be blanket-deposited over a portion of the base substrate without being patterned with conductive features (e.g., without pads). In other embodiments, bonding layers can be patterned on one or two elements and can be the same or different from each other, but one material from each element is directly bonded across the surface of the elements (or, if the elements are different sizes, across the surface of the smaller element) without adhesive. In another implementation of uniform direct bonding, one or both of the non-conductive bonding layers can contain one or more conductive features, but these conductive features do not participate in the bonding. For example, in some embodiments, opposing non-conductive bonding layers can be uniformly bonded directly to each other, and after bonding, a through-substrate via (TSV) can subsequently be formed through one element to provide electrical communication with the other element.

[0021] In various embodiments, bonding layers 108a and / or 108b may comprise non-conductive materials, such as dielectric materials or undoped semiconductor materials, such as undoped silicon, which may comprise natural oxides. Suitable dielectric bonding surfaces or materials for direct bonding include, but are not limited to, inorganic dielectrics, such as silicon oxide, silicon nitride, or silicon oxynitride, or may comprise carbon, such as silicon carbide, silicon oxycarbonitride, low-k dielectrics, SiCOH dielectrics, silicon carbonitride, or diamond-like carbon, or materials comprising a diamond surface. Despite containing carbon, such carbon-containing ceramic materials can still be considered inorganic materials. In some embodiments, the dielectric material at the bonding surface does not comprise polymeric materials, such as epoxy resins (e.g., epoxy adhesives, cured epoxy resins, or epoxy composites, such as FR-4 materials), resins, or molding materials.

[0022] In other embodiments, the bonding layer may include a conductive material, such as a deposited conductive oxide material, such as indium tin oxide (ITO), as disclosed in U.S. Provisional Patent Application No. 63 / 524,564, filed June 30, 2023, the entire contents of which are incorporated herein by reference to provide examples of conductive bonding layers without short-circuit contacts penetrating the interface.

[0023] In direct bonding, the first and second elements can be directly bonded to each other without an adhesive, unlike deposition processes, and the resulting interface structure differs structurally from that produced by deposition. In one application, the width of the first element in the bonded structure is similar to the width of the second element. In other embodiments, the width of the first element in the bonded structure differs from the width of the second element. The width or area of ​​the larger element in the bonded structure can be at least 10% larger than the width or area of ​​the smaller element. Furthermore, unlike the interface beneath the deposition layer, the interface between direct-bonded structures can include defect regions containing nanoscale voids (nanopores). Nanopores can be formed due to activation of one or both bonded surfaces (e.g., exposure to plasma, as described below).

[0024] The bonding interface between non-conductive bonding surfaces may include a higher concentration of material from activation and / or final chemical processing than the bulk of the bonding layer. For example, in embodiments where activation is performed using nitrogen plasma, a nitrogen concentration peak may form at the bonding interface. In some embodiments, the nitrogen concentration peak may be detected using secondary ion mass spectrometry (SIMS). In various embodiments, for example, nitrogen termination treatment (e.g., exposing the bonding surface to nitrogen-containing plasma) may replace the OH groups of the hydrolyzed (OH-terminated) surface with NH2 molecules, thereby producing a nitrogen-terminated surface. In embodiments where activation is performed using oxygen plasma, an oxygen concentration peak may form at the bonding interface between non-conductive bonding surfaces. In some embodiments, the bonding interface may comprise silicon oxynitride, silicon oxycarbonitride, or silicon carbonitride. Direct bonding may include covalent bonds with a strength higher than van der Waals bonds. The bonding layer may also comprise a polished surface planarized to a high degree of smoothness.

[0025] In direct bonding processes, such as uniform direct bonding and hybrid bonding, two components are joined together without the intervention of an adhesive. In indirect bonding processes using adhesives, an intervening material is typically applied to one or both components to achieve a physical bond between them. For example, in some adhesive-based processes, a flowable adhesive (e.g., an organic adhesive such as epoxy resin) that may include a conductive filler material can be applied to one or both components and cured to form a physical (rather than chemical or covalent) bond between the components. Typical organic adhesives lack strong chemical or covalent bonds with either component. In such processes, the bond between components is weak and / or easily reversed, for example, by reheating or removing the flux.

[0026] In contrast, direct bonding processes join two components by forming strong chemical bonds (e.g., covalent bonds) between opposing nonconductive materials. For example, in a direct bonding process between nonconductive materials, one or both nonconductive surfaces of the two components are planarized and chemically prepared (e.g., activated and / or capped) such that strong chemical bonds (e.g., covalent bonds) are formed when the components come into contact; these bonds are stronger than van der Waals or hydrogen bonds. In some embodiments (e.g., between opposing dielectric surfaces, such as opposing silicon oxide surfaces), the chemical bonds can form spontaneously upon contact at room temperature. In some embodiments, the chemical bonds between opposing nonconductive materials can be strengthened after annealing the components.

[0027] As described above, hybrid bonding is a type of direct bonding in which non-conductive features are directly bonded to non-conductive features, and conductive features are directly bonded to conductive features of the elements to be bonded. The non-conductive bonding materials and interfaces can be as described above, while conductive bonding can be formed, for example, as a direct metal-to-metal connection. In conventional metal bonding processes, a fusible metal alloy (e.g., solder) can be provided between the conductors of two elements, heated to melt the alloy, and then cooled to form a connection between the two elements. The resulting bond typically exhibits a clear interface with the conductors from both elements and can be reversed by reheating. In contrast, the direct metal bonding employed in hybrid bonding does not require melting or an intermediate fusible metal alloy and can produce strong mechanical and electrical connections, typically exhibiting mutual diffusion of the conductive features of the bond and grain growth at the bonding interface between the elements, even at much higher temperatures and pressures than thermocompression bonding.

[0028] Figure 1A and 1B Cross-sectional side views of a first element 102 and a second element 104, respectively, before and after the process of forming a direct-joint structure (more specifically, a hybrid-joint structure), according to some embodiments, are schematically illustrated. Figure 1B In the illustrated hybrid bonding structure 100, a first element 102 and a second element 104 are directly bonded to each other at a bonding interface 118 without the intervention of an adhesive. A conductive feature 106a of the first element 102 can be electrically connected to a corresponding conductive feature 106b of the second element 104. In the illustrated hybrid bonding structure 100, the conductive feature 106a is directly bonded to the corresponding conductive feature 106b without the intervention of solder or conductive adhesive.

[0029] The conductive features 106a and 106b of the illustrated embodiment are embedded in, and can be considered as part of, the first bonding layer 108a of the first element 102 and the second bonding layer 108b of the second element 104, respectively. The field regions of the bonding layers 108a and 108b extend between and partially or completely surround the conductive features 106a and 106b. The bonding layers 108a and 108b may include layers of non-conductive material suitable for direct bonding, as described above, and the field regions are directly bonded to each other without adhesive. The non-conductive bonding layers 108a and 108b may be disposed on the respective front surfaces 114a and 114b of the base substrate portions 110a and 110b.

[0030] First element 102 and second element 104 may include microelectronic elements, such as semiconductor elements, including, for example, integrated device dies, wafers, passive devices, discrete active devices (such as power switches), MEMS, etc. In some embodiments, the base substrate portion may include device portions, such as bulk semiconductor (e.g., silicon) portions of elements 102, 104, and a back-end interconnect (BEOL) layer located above such semiconductor portions. Bonding layers 108a, 108b may be provided during device fabrication as part of such BEOL layers, as part of redistribution layers (RDLs), or as specific bonding layers attached to existing devices (bonding pads extending from lower contacts). Active devices and / or circuit arrangements may be patterned and / or otherwise disposed in or on base substrate portions 110a, 110b, and may be in electrical communication with at least some of the conductive features 106a, 106b. Active devices and / or circuit arrangements may be disposed on or near the front surfaces 114a, 114b of the base substrate portions 110a, 110b, and / or on or near the opposite back surfaces 116a, 116b of the base substrate portions 110a, 110b. In other embodiments, the base substrate portions 110a, 110b may not include active circuit arrangements, but may include dummy substrates, passive interposers, passive optical elements (e.g., glass substrates, gratings, lenses), etc. Bonding layers 108a, 108b are shown as being provided on the front surface of the components, but similar bonding layers may be additionally or alternatively provided on the back surface of the components.

[0031] In some embodiments, the base substrate portions 110a and 110b may have significantly different coefficients of thermal expansion (CTE), and the bonding elements comprising such different base substrate portions may form a heterojunction structure. The CTE difference between base substrate portions 110a and 110b, and particularly between the bulk semiconductor (typically single-crystal) portions of base substrate portions 110a and 110b, may be greater than 5 ppm / °C or greater than 10 ppm / °C. For example, the CTE difference between base substrate portions 110a and 110b may be in the range of 5 ppm / °C to 100 ppm / °C, 5 ppm / °C to 40 ppm / °C, 10 ppm / °C to 100 ppm / °C, or 10 ppm / °C to 40 ppm / °C.

[0032] In some embodiments, one of the base substrate portions 110a and 110b may include a photoelectric single-crystal material (including perovskite materials) for optical piezoelectric or thermoelectric applications, while the other of the base substrate portions 110a and 110b may include a more conventional substrate material. For example, one of the base substrate portions 110a and 110b may include lithium tantalate (LiTaO3) or lithium niobate (LiNbO3), while the other of the base substrate portions 110a and 110b may include silicon (Si), quartz, fused silica glass, sapphire, or glass. In other embodiments, one of the base substrate portions 110a and 110b may include a group III-V single semiconductor material, such as gallium arsenide (GaAs) or gallium nitride (GaN), while the other of the base substrate portions 110a and 110b may include a non-group III-V semiconductor material, such as silicon (Si), or may include other materials with similar CTE, such as quartz, fused silica glass, sapphire, or glass. In other embodiments, one of the base substrate portions 110a and 110b includes a semiconductor material, while the other of the base substrate portions 110a and 110b includes an encapsulation material, such as a glass, organic, or ceramic substrate.

[0033] In some arrangements, the first element 102 may include a singulated element, such as a singulated integrated device die. In other arrangements, the first element 102 may include a carrier or substrate (e.g., a semiconductor wafer) comprising multiple (e.g., tens, hundreds, or more) device regions that, when singulated, form multiple integrated device dies, although in other embodiments, such a carrier may be a packaging substrate or a passive or active interposer. Similarly, the second element 104 may include a singulated element, such as a singulated integrated device die. In other arrangements, the second element 104 may include a carrier or substrate (e.g., a semiconductor wafer). Therefore, the embodiments disclosed herein can be applied to wafer-to-wafer (W2W), die-to-die (D2D), or die-to-wafer (D2W) bonding processes. In a W2W process, two or more wafers may be directly bonded to each other (e.g., direct hybrid bonding) and singulated using a suitable singulation process. After cutting, the side edges of the cut structure (e.g., the side edges of two joining elements) may be substantially flush (xy dimensions substantially aligned) and / or the edges of the joining interfaces of the joined and cut elements may extend together, and may include markings indicating the common cutting process of the joining structure (e.g., sawing markings if a sawing cutting process is used).

[0034] Although only two elements 102 and 104 are shown, any suitable number of elements can be stacked in the bonding structure 100. For example, a third element (not shown) can be stacked on top of the second element 104, a fourth element (not shown) can be stacked on top of the third element, and so on. In such embodiments, through-substrate vias (TSVs) can be formed to provide vertical electrical communication between and / or among the vertically stacked elements. Additionally or alternatively, one or more additional elements (not shown) can be stacked laterally adjacent to each other along the first element 102. In some embodiments, the laterally stacked additional elements may be smaller than the second element. In some embodiments, the bonding structure can be sealed with an insulating material, such as an inorganic dielectric (e.g., silicon oxide, silicon nitride, silicon oxynitride, etc.). One or more insulating layers can be provided over the bonding structure. For example, in some embodiments, a first insulating layer can be conformally deposited over the bonding structure, while a second insulating layer (which may include the same or different material as the first insulating layer) can be provided over the first insulating layer.

[0035] To achieve direct bonding between bonding layers 108a and 108b, bonding layers 108a and 108b can be fabricated for direct bonding. Non-conductive bonding surfaces 112a and 112b at the upper or outer surfaces of bonding layers 108a and 108b can be fabricated for direct bonding by polishing (e.g., chemical mechanical polishing (CMP)). The roughness of the polished bonding surfaces 112a and 112b can be less than 30 Å rms. For example, the roughness of bonding surfaces 112a and 112b can be in the range of about 0.1 Å rms to 15 Å rms, 0.5 Å rms to 10 Å rms, or 1 Å rms to 5 Å rms. Polishing can also be adjusted to cause the conductive features 106a and 106b to be recessed relative to the field regions of bonding layers 108a and 108b.

[0036] Preparation for direct bonding may further include cleaning and exposing one or both of the bonding surfaces 112a, 112b to plasma and / or an etchant to activate at least one of the surfaces 112a, 112b. In some embodiments, one or both of the surfaces 112a, 112b may be end-capped with a substance after activation or during activation (e.g., during plasma and / or etching processes). Without being limited to theory, in some embodiments, the activation process may be performed to break chemical bonds at the bonding surfaces 112a, 112b, and the end-capping process may provide additional chemicals at the bonding surfaces 112a, 112b that alter chemical bonds and / or increase the bonding energy during direct bonding. In some embodiments, activation and end-capping are provided in the same step, for example, plasma to activate and end-cap the surfaces 112a, 112b. In other embodiments, one or both of the bonding surfaces 112a, 112b may be end-capped in separate processes to provide additional substances for direct bonding. In various embodiments, the end-capping substance may include nitrogen. For example, in some embodiments, the bonding surfaces 112a, 112b may be exposed to nitrogen-containing plasma. Other end-capping materials may be suitable for increasing the bonding energy, depending on the material of the bonding surfaces 112a, 112b. Furthermore, in some embodiments, the bonding surfaces 112a, 112b may be exposed to fluorine. For example, one or more fluorine concentration peaks may be present at or near the bonding interface 118 between the first element 102 and the second element 104. Typically, fluorine concentration peaks appear at the interface between material layers. Further examples of activation and / or end-capping treatments can be found in U.S. Patent No. 9,391,143, column 5, lines 55 through 7, line 3; column 8, lines 52 through 9, lines 45; column 10, lines 24–36; column 11, lines 24–32, 42–47, 52–55, and 60–64; column 12, lines 3–14, 31–33, and 55–67; column 14, lines 38–40 and 44–50; and in U.S. Patent No. 10,434,749, column 4, lines 41–50; column 5, lines 7–22, 39, and 55–61; column 8, lines 25–31, 35–40, and 49–56; and column 12, lines 46–61, the teachings of which are incorporated herein by reference.

[0037] Therefore, in the direct bonding structure 100, the bonding interface 118 between the two non-conductive materials (e.g., bonding layers 108a, 108b) may include a very smooth interface with a high nitrogen (or other end-capping material) content and / or a fluorine concentration peak at the bonding interface 118. In some embodiments, various types of inspection techniques (e.g., SIMS techniques) may be used to detect the nitrogen and / or fluorine concentration peaks. After the activation process, the polished bonding surfaces 112a and 112b may become slightly rougher (e.g., approximately 1 Å to 30 Å, 3 Å to 20 Å, or possibly rougher). In some embodiments, activation and / or end-capping treatments may result in slightly smoother surfaces prior to bonding, for example, plasma treatment preferentially eroding high points on the bonding surface.

[0038] Non-conductive bonding layers 108a and 108b can be directly bonded to each other without an adhesive. In some embodiments, elements 102 and 104 are bonded together at room temperature without applying a voltage or external pressure or force exceeding that required to initiate contact between the two elements 102 and 104. Direct bonding (e.g., covalent dielectric bonding) between the non-conductive surfaces of bonding layers 108a and 108b can be achieved simply by contact. Subsequent annealing of the bonding structure 100 can then directly bond conductive features 106a and 106b.

[0039] In some embodiments, prior to direct bonding, conductive features 106a and 106b are recessed relative to the surrounding field area, such that after dielectric bonding and before annealing, the total gap between the relative contacts is less than 15 nm or less than 10 nm. Due to process variations, the recess depth of conductive features 106a and 106b can also vary across each element, so the aforementioned gap can represent the maximum or average gap (before annealing) between the corresponding conductive features 106a and 106b of the two bonding elements. During annealing, conductive features 106a and 106b can expand and contact each other to form a metal-to-metal direct bond.

[0040] During annealing, the conductive features 106a, 106b (e.g., metallic materials) expand, while the direct bonding between the surrounding non-conductive materials of the bonding layers 108a, 108b resists element separation, increasing the internal contact pressure between the opposing conductive features due to thermal expansion. Annealing also causes metal grain growth across the bonding interface, resulting in at least partial migration of grains from one element to the other across the bonding interface, and vice versa. Therefore, in some hybrid bonding embodiments, opposing conductive materials are joined at a heating temperature not exceeding the melting point of the conductive materials, thus allowing the bond to be formed at a lower annealing temperature compared to welding or thermocompression bonding.

[0041] In various embodiments, conductive features 106a, 106b may include discrete pads, contacts, electrodes, or traces at least partially embedded in the non-conductive field regions of bonding layers 108a, 108b. In some embodiments, conductive features 106a, 106b may include exposed contact surfaces of TSVs (e.g., through-silicon vias).

[0042] As described above, in some embodiments, prior to direct engagement Figure 1A In elements 102 and 104, portions of the corresponding conductive features 106a and 106b may be recessed beneath the non-conductive bonding surfaces 112a and 112b, for example, with recesses less than 30 nm, less than 20 nm, less than 15 nm, or less than 10 nm, e.g., in the range of 2 nm to 20 nm, or in the range of 4 nm to 10 nm. Due to process variations, the dielectric thickness and conductor recess depth can vary across elements. Therefore, the aforementioned recess depth ranges can be applied to individual conductive features 106a and 106b, or to the average depth of the recess relative to a local non-conductive field region. Even for individual conductive features 106a and 106b, their vertical recesses can vary across the feature, and thus can be measured at or near the lateral midpoint or center of the cavity in which a given conductive feature 106a or 106b is formed, or at the surface of the cavity.

[0043] Advantageously, high-density connections (e.g., small or fine spacing for a regular array) between conductive features 106a, 106b across the direct-attach interface 118 can be achieved using hybrid bonding technologies (e.g., direct-attach interconnects or DBI® technology, which are commercially available from Adeia, Inc. of San Jose, California).

[0044] In some embodiments, the spacing p of conductive features 106a, 106b (e.g., conductive traces embedded in the bonding surface of one bonding element of a bonding element) may be less than 40 µm, less than 20 µm, less than 10 µm, less than 5 µm, less than 2 µm, or even less than 1 µm. For some applications, the ratio of the spacing of conductive features 106a and 106b to one of the lateral dimensions (e.g., diameter) of the bonding pad is less than 20, or less than 10, or less than 5, or less than 3, and sometimes ideally less than 2. In various embodiments, conductive features 106a and 106b and / or traces may comprise copper or a copper alloy, although other metals may also be applicable, such as nickel, aluminum, or alloys thereof. The conductive features disclosed herein, such as conductive features 106a and 106b, may comprise fine-grained metals (e.g., fine-grained copper). In addition, the major lateral dimensions (e.g., pad diameter) can also be very small, for example, ranging from about 0.25 µm to 30 µm, from about 0.25 µm to 5 µm, or from about 0.5 µm to 5 µm.

[0045] For the hybrid bonding elements 102 and 104 shown, the orientations of one or more conductive features 106a and 106b from the opposing elements may be opposite to each other. As is known in the art, conductive features can typically be formed with nearly vertical sidewalls, particularly where the conductor sidewalls are defined by directional reactive ion etching (RIE) directly by etching the conductive material or indirectly by etching either of the surrounding insulator in a back-end process. However, the conductor sidewalls may exhibit some slight taper, where the conductor becomes narrower as it moves away from the surface initially exposed to the etch. This taper may be more pronounced when isotropic wet or dry etching is used to define the conductive sidewalls directly or indirectly. In the illustrated embodiment, at least one conductive feature 106b (and / or at least one internal conductive feature, such as a BEOL feature) in the bonding layer 108b of the upper element 104 may taper or narrow upwards away from the bonding surface 112b. In contrast, at least one conductive feature 106a (and / or at least one internal conductive feature, such as a BEOL feature) in the bonding layer 108a of the lower element 102 may taper or narrow downwards away from the bonding surface 112a. Similarly, any bonding layer (not shown) on the back surfaces 116a, 116b of elements 102, 104 may taper or narrow away from the back surface, having an opposite taper orientation to the front conductive features 106a, 106b of the same element.

[0046] As described above, during the annealing stage of the hybrid bonding process, conductive features 106a and 106b can expand and contact each other to form a metal-to-metal direct bond. In some embodiments, the materials of conductive features 106a and 106b of opposite elements 102 and 104 can diffuse into each other during the annealing process. In some embodiments, metal grains grow into each other across the bonding interface 118. In some embodiments, the metal is copper or includes copper, and its grains may have an orientation along the 111 crystal plane to improve copper diffusion across the bonding interface 118. In some embodiments, conductive features 106a and 106b may include a nanotwinned copper grain structure, which facilitates the incorporation of conductive features during annealing. There is substantially no gap between the non-conductive bonding layers 108a and 108b at or near the bonded conductive features 106a and 106b. In some embodiments, a barrier layer may be provided under and / or laterally around the conductive features 106a and 106b (e.g., possibly including copper). However, in other embodiments, no barrier layer may be provided under the conductive features 106a and 106b.

[0047] The embodiments taught herein relate to TSVs for back-side hybrid bonding. TSVs can be formed using many different methods, including via-first, via-mid, or via-back processes. In via-first or via-mid processes, relatively deep (e.g., several micrometers deep) blind vias are opened from the front side of a substrate, for example by reactive ion etching (RIE) or laser drilling. The substrate can be a bulk semiconductor material (e.g., silicon, III-V materials) with active devices, but in other embodiments, the substrate can be glass or ceramic, particularly for passive components (e.g., interposers or carrier substrates). For active component embodiments, the front side of the substrate typically includes devices (e.g., transistors) and metallization layers called back-end processing (BEOL) layers, which can be formed before or more generally after defining the TSV structure. For example, in a via-mid process, transistors are formed via a high-temperature front-end process, followed by the formation of the blind via TSV, and then multiple metallization or BEOL layers. The blind vias are filled with a conductive material, typically copper, due to its high conductivity. During this period, these vias can be considered buried TSVs, blind TSVs, or embedded TSVs. They do not actually extend all the way to the back side of the substrate because the substrate has not yet been thinned to its final thickness. Subsequently, the substrate (e.g., bulk semiconductor material) is thinned from the back side to expose the back side of the conductive material, effectively forming a TSV that extends from the front side of the substrate to the back side of the thinned substrate.

[0048] One problem with conventional via-first TSVs or via-mid TSVs is that, due to the large depths the openings are etched into the bulk substrate material, these openings often have varying depths, and the TSV depth before exposure can differ significantly across the substrate. For example, a TSV formed near the wafer center may have a different depth than one near the wafer edge. When exposing TSVs from the back side (e.g., using wafer back-side thinning followed by dry or wet etching to expose the bottom tip of the TSV), the resulting height variation means that as the substrate is thinned from the back side, deeper TSVs will be exposed first, and continuing to thin to expose shallower TSVs can lead to problems such as conductive material tailing across the substrate, substrate contamination due to prolonged exposure to conductive material that may diffuse into the substrate, breakage of some of the deeper TSVs, and wear of some of the barrier material protecting the conductive TSVs. Any copper tails from the TSVs during thinning, polishing, or CMP can contaminate adjacent silicon substrates and should be avoided. The embodiments taught herein can mitigate some of the problems introduced by variable-depth embedded TSVs during back-side exposure and subsequent processing.

[0049] In some embodiments, a TSV comprises at least two portions: a tip located at the back end of the TSV, and a second conductive portion located near the middle or front end of the TSV. In some embodiments, the material of the conductive tip is different from the material of the second conductive portion of the TSV. In some embodiments, the metal of the conductive tip is different from the metal of the second conductive portion of the TSV. A TSV can be formed using bottom-up deposition techniques. Some of these techniques are gas-based, but others are wet processes (electroplated or electroless).

[0050] The tip of the TSV structure may include a material that contaminates silicon less than copper, does not diffuse into silicon at room temperature (or has less diffusion in silicon than in copper), or is less prone to cross-substrate tailing than copper during chemical mechanical planarization (CMP).

[0051] Figure 2A-2G The schematic diagram illustrates the formation Figure 2G The method for constructing the microelectronic structure 200 is shown. The method presented is a bottom-up deposition process. Figure 2AA plurality of blind vias 202 formed from the front side 204 of a bulk substrate 206 are shown for forming a first element. The substrate 206 may comprise a wafer of a semiconductor material (e.g., silicon, a III-V material, or a more specialized compound material for optical devices), or may comprise a material such as glass, ceramic, or other suitable material. The substrate 206 may comprise active transistors, passive devices, or may serve as a carrier, bridge, or interposer. The blind vias 202 extend from the front side 204 or front surface of the substrate 206 toward the back side 208 or rear surface of the substrate 206. In some embodiments, the substrate 206 includes active devices (e.g., transistors) at the front side 204, which may be fabricated before or after the formation of the TSV. The depth 210 of the blind vias 202 is typically several micrometers and is deeper than the intended final (thinned) thickness 212 of the fabricated element (e.g., ...). Figure 2G (As shown). For example, the average depth 210 of blind via 202 can be between 0.5-5 μm, or between 5-50 μm, or between 10-150 μm, or deeper. In some embodiments, blind via 202 can have relatively high inhomogeneity, for example, depth differences can be as high as several micrometers. Significant differences may exist in the depth 210 of blind via 202 due to process variations or equipment limitations. TSV structures with different diameters or widths across the substrate may also cause variations in the depth 210 of blind via 202. Blind via 202 can be completely or partially lined with at least one layer, for example, a dielectric and / or conductive barrier layer 203, and may also be lined with a seed layer (not shown) for subsequent filling. Blind via 202 can be formed by, for example, RIE or laser drilling. In some embodiments, the lateral dimensions of blind vias or vias may differ. Within the design or layout of blind vias, the lateral dimensions of some vias, such as the diameter of the via, may be 10% to 40% smaller than adjacent vias. For example, the diameter of vias in a first array may be smaller than the diameter of vias in a second array. In practice, after the via formation process (e.g., via the RIE method), the depth of a smaller via may be less than that of a larger via. In some embodiments, the depth of the via can vary from 3 µm to more than 10 µm. In some embodiments, the larger via is suitable for providing power or ground or both, and in some embodiments, the smaller via is suitable for signal transmission.

[0052] Figure 2BA tip portion 214 is shown, disposed at the bottom of each of the blind vias 202, partially filling the blind via 202. In the illustrated embodiment, the tip portion 214 includes a conductive material to form a conductive tip portion 214. In other embodiments, the tip portion may include a sacrificial material to form a sacrificial tip portion, which may be conductive or dielectric. The conductive tip portion may form part of the final structure, while the sacrificial tip portion is configured to be removed and replaced during manufacturing. Additional details regarding the conductive and sacrificial tip portions will be discussed further below. Figure 2B The tip portion 214 shown in the figure is a conductive tip portion 214, a portion of which will remain in the final product. In some embodiments, at least one of a barrier layer 203 or a seed layer (not shown) may be arranged above the tip portion 214. Figure 2B The illustrated structure shows a barrier layer 203 lining within a blind hole 202. Although Figure 2C-2H The barrier layer 203 is not shown, but those skilled in the art will understand that, Figure 2B and 2C The barrier layer 203 does not need to be removed between corresponding periods. Instead, in some embodiments (by...) Figure 2A and 2B (representation), may include a barrier layer, while in other embodiments (by...) Figure 2C-2H (This indicates that the barrier layer may be omitted.) In some embodiments, the tip portion may include a conformal conductive coating. Some embodiments may also include gaps within the conductive coating of the tip portion. In other embodiments, the tip portion may include a conductive material with gaps.

[0053] The tip portion (e.g., conductive tip portion 214) may include a material that is less prone to tailing across the substrate (e.g., substrate 206) compared to copper during chemical mechanical planarization (CMP). In some embodiments, the tip portion may also be harder than copper. In some embodiments, the conductive tip portion (e.g., conductive tip portion 214) may be directly bonded to copper without the intervention of an adhesive, such as copper pads exposed at a bonding surface of another substrate. In some embodiments, the conductive tip portion may include nickel or a nickel alloy. In some embodiments, the conductive tip portion may be predominantly nickel, for example, with a nickel atomic percentage greater than 50%, greater than 60%, or greater than 90%. In some embodiments, the conductive tip portion may include cobalt, tungsten, indium, or a suitable alloy. In some other embodiments, the conductive tip portion may include a conductive adhesive. In other embodiments, as previously described, the conductive tip portion may include solder. In still other embodiments, the conductive tip portion may also include copper, but with a different impurity concentration or grain structure compared to the conductive second via portion.

[0054] Those skilled in the art will understand that any of a variety of techniques can be used to partially fill blind via 202 with only the tip portion (e.g., conductive tip portion 214). For example, vapor phase or wet processes (e.g., electroplating or non-electroplating) are known to be used for bottom-up filling of various materials. In some embodiments, the blind via may be partially or completely filled with the desired material, and then etched back (e.g., by wet or vapor phase etching) to leave only the tip portion in the bottom portion of the blind via.

[0055] Figure 2C Blind hole 202 is shown (e.g.) Figure 2B The remaining portion (shown) is located above the conductive tip portion 214 and filled with a conductive second via portion 216, which is disposed above the tip portion 214. The conductive tip portion 214 and the conductive second via portion 216 together form an embedded TSV structure 222. In some embodiments, a thin layer of another conductive material, such as a conductive barrier material (e.g., Ti, Ta, metal nitride, etc.), may be deposited on the tip portion before depositing the conductive second via portion. One or more metallization layers 224, such as BEOL layers and / or redistribution layers (RDLs), are disposed on the front side 204 of the bulk substrate 206. The conductive material deposited in the second via portion 216 is different from the material deposited in the conductive tip portion 214. In some embodiments, the conductive second via portion comprises copper. In some embodiments, the conductive second via portion is primarily copper, for example, with a copper atomic percentage greater than 50%, greater than 60%, or greater than 90%. In some embodiments, the material comprised in the second via portion is different from the material of the tip portion. In some embodiments, the metal or alloy comprised in the second via portion is different from the metal or alloy of the conductive tip portion. In some embodiments, prior to depositing the second conductive portion, another sublayer and / or conductive barrier layer and / or adhesive layer may be formed on the conductive tip portion.

[0056] Figure 2D The conductive tip portion 214 exposed or revealed from the back side of multiple TSV structures 222 is shown. The back side 208 of the bulk substrate 206 can be thinned using, for example, grinding, milling, etching, CMP, or a combination thereof. Those skilled in the art will understand that the TSV structures in the products used herein extend at least to the back side of the bulk portion of the substrate after thinning, and may also extend to the front side of the bulk portion of the substrate. Typically, the final stage of the thinning process for exposing the embedded TSV structures includes a planarization stage, such as CMP. As the back side 208 is thinned, the deepest TSV structure 222a (e.g., Figure 2C As shown, the shallowest TSV structure 222b is exposed first, while the shallowest TSV structure 222b is exposed last. To expose the shallowest TSV structure 222b (as shown...), Figure 2CAs shown), the tip portion 214a of the deeper TSV structure (e.g., TSV structure 222a) must also be thinned. At least partly for this reason, the thickness 228 of the conductive tip portion 214 (as shown) Figure 2D The thicknesses (as shown) vary. In some embodiments, the tip portion (e.g., conductive tip portion 214) has an original thickness 226 within the TSV structure 222 (as shown). Figure 2C As shown), the thickness is greater than (at least 1 time, for example, 1-5 times or 1.1-2.5 times) the depth 210a of the deepest blind hole 202a and the depth 210b of the shallowest blind hole 202b (as shown). Figure 2A The difference is shown in the figure. In other words, even if the tip portion 214a of the deepest TSV structure 222a is thinned to expose the tip portion 214b of the shallowest TSV structure 222b, in some embodiments, no tip portion is completely thinned away. In other words, in some embodiments, no second via portion (e.g., second conductive via portion 216) of any TSV structure (e.g., TSV structure 222) is exposed on the back side (e.g., the back side 208 of the thinned substrate 206). Advantageously, the tip portion (whether conductive or sacrificial) may comprise a material that is less prone to tailing than copper during planarization to expose the tip portion. In other embodiments, mechanical grinding, polishing, or polishing processes are performed only to bring it very close to the deepest TSV structure (e.g., TSV structure 222a), but without exposing any of its tip portions (e.g., tip portion 214a) by grinding, polishing, or polishing. Instead, the tips (e.g., tip portion 214) are exposed by selectively etching a bulk substrate (e.g., substrate 206) to avoid material contamination of the substrate at the tips during this mechanical grinding or polishing. Sufficient substrate material is then removed by etching to expose or reveal the tips of all TSVs.

[0057] Figure 2E The illustration shows a bulk substrate 206 being selectively etched such that a TSV structure 222 protrudes from the back surface 208 of the substrate 206. In some embodiments, the selective etching is dry etching and can be isotropic, but more typically directional. In some embodiments, for example, where the bulk substrate comprises silicon, a RIE using SF6 can selectively etch silicon while selectively etching the selected conductive tip material (e.g., nickel) and any liner barrier material of the TSV (e.g., ...). Figure 2A The barrier layer 203 shown causes minimal damage. The material used for the tip portion (whether conductive or sacrificial) can be more resistant to selective etchants than the bulk substrate 206. The amount of protrusion 230 can also define the desired thickness of the dielectric layer 232 to be formed (e.g., dielectric bonding layer) (see [reference]). Figure 2F-2G(and description). In some embodiments, the protrusion 230 of the TSV structure 222 on the back side 208 of the substrate 206 may be less than 100 nm, less than 10 μm, or between 50 nm and 100 nm, or between 500 nm and 15 μm.

[0058] Figure 2F One or more dielectric layers 232 are shown deposited over the back face 208 of substrate 206 and over the back face of TSV structure 222. Dielectric layer 232 may include any of the dielectric bonding materials described above and may also be used to aid in planarization for subsequent bonding. For example, dielectric layer 232 may include an initial thin silicon nitride layer (as a barrier and / or etch stop) and a thicker silicon oxide layer above it. In some embodiments, the silicon oxide layer is deposited directly over the tip portion (e.g., conductive tip portion 214) and the back face of the bulk semiconductor material. In other embodiments, a thin layer of silicon oxynitride or silicon carbonitride may also be deposited on top of the oxide layer or embedded within the dielectric layer 232. In some embodiments, dielectric layer 232 may include layers of inorganic and polymeric materials. The polymeric material may include, for example, a high-temperature epoxy coating. The strong adhesion and lateral mechanical support of the hard polymer layer to the TSV structure helps prevent breakage of the TSV structure during CMP.

[0059] Figure 2G It shows Figure 2F The structure after planarization to expose the conductive tip portion 214 of the TSV structure 222. Figure 2G The back side of the microelectronic structure 200 can be fabricated for hybrid bonding, for example by adequate planarization and any desired activation and / or end-capping, as described above. Those skilled in the art will understand that the surface of the conductive tip portion 214 can be slightly recessed relative to the surface 233 of the surrounding dielectric layer 232 to facilitate metal bonding during the annealing / expansion phase of the hybrid bonding, as described above. Figure 2GThe second conductive via portion 216 and the conductive tip portion 214 of the TSV structure 222 may include and are primarily formed of different metals, as described above. Furthermore, the relative heights or thicknesses 228a, 228b, and / or diameters of the conductive tip portions 214a, 214b may vary due to design variations (signal and ground or power) or variations in the etching depth described above. In some embodiments, the height or thickness (e.g., thickness 228b) of the conductive tip portion (e.g., conductive tip portion 214) may vary by more than 1% between different TSV structures, for example, 0.5-25%, 1-10%, more than 15%, or more than 20% (relative to the thinner of the two conductive tip portions 214a being compared). Similarly, the diameter of the conductive tip portion 214 may vary by more than 1% between different TSV structures, for example, 0.5-25%, 1-10%, more than 15%, or more than 20%. These height / thickness differences, for example... Figure 2G The difference between the thickness 228b of the thicker conductive tip portion 214b and the thickness 228a of the thinner conductive tip portion 214a can be applied to the TSV conductive tip portion in various embodiments taught herein, including sacrificial embodiments.

[0060] Figure 2H The joining structure 250 is shown, in particular the back side of the first element 260. Figure 2G The first microelectronic structure 200 is coupled along a bonding interface 265 to a bonding layer 272 (e.g., a BEOL or RDL layer) on the front side 276 of the second element 270. In some embodiments, conductive tip portions (e.g., conductive tip portions 214) of a TSV (e.g., TSV structure 222) are directly bonded at the back side of the first element (e.g., first element 260) to contact pads (e.g., contact pads 274) on the front side or front side (e.g., front side 276) of the second element (e.g., second element 270). In some embodiments, the metal-to-metal bonding between the contacts of the first and second microelectronic structures is a direct nickel-to-copper bonding. In the illustrated embodiment, the second element 270 includes a second microelectronic structure (e.g., an integrated circuit) and also includes a TSV structure 222' similar to the TSV structure of the first element 260. In other embodiments, the second element does not need to include a TSV, or may include a TSV formed by other techniques.

[0061] Figures 3A-3D A method for forming a microelectronic structure 300 according to another embodiment is schematically illustrated. The microelectronic structure 300 formed by this method (e.g.) Figure 3D (As shown) Similar to Figure 2GThe microelectronic structure 200 shown differs in that the microelectronic structure 300 also has a bonding pad 318 or conductive bonding layer, disposed above the back side of the conductive tip portion 214 and embedded in the dielectric layer 232. Figure 3A Similar to Figure 2G .

[0062] Figure 3B It shows Figure 3A A recess 308 is formed in the conductive tip portion 214. This results in the partial removal of the tip portion 214. For example, the conductive tip portion 214 may be selectively etched relative to the surrounding dielectric layer 232. In other embodiments, the recess 308 of the conductive tip portion 214 may be formed during planarization or CMP.

[0063] Figure 3C The back surface 208 of substrate 206 and the back surface of TSV structure 222 are shown (e.g.) Figure 3B A conductive layer 317 is deposited above the surface (as shown). The conductive layer 317 may include copper or another conductive material suitable for hybrid bonding. The conductive layer 317 can be deposited using physical vapor deposition methods (sputtering, evaporation), CVD or ALD methods, or by using plating techniques, such as electroplating or electroless plating, or combinations thereof. In other embodiments, multiple such conductive layers comprising various conductive materials or alloys may be deposited.

[0064] Figure 3D This shows the effect after planarization to expose the bonding dielectric layer 232. Figure 3C The structure leaves bonding pads 318 on the back side of the conductive tip portion 214 of the TSV structure 322. Figure 3D The back side of the microelectronic structure 300 can be fabricated for hybrid bonding, as described above. This microelectronic structure 300 is similar to... Figure 2G The microelectronic structure 200 shown differs in that it also has a bonding pad 318 disposed above the back side of the conductive tip portion 214 and embedded in the dielectric layer 232. In some embodiments, the bonding pad (e.g., bonding pad 318) may be the bottommost feature of a TSV (e.g., TSV structure 322) and may function effectively in a DBI bonding structure of TSV to pad. The dimensions of the bonding pad 318 are determined by... Figure 3BA partial recess 308 defines the conductive tip portion 214, and therefore may not require a separate photomask. The bonding pad 318 may comprise a material different from the conductive tip portion 214 (e.g., primarily nickel) (e.g., primarily copper). In some embodiments, the bonding pad may have a specific grain orientation (e.g., 111 grain orientation), a nanostructure, or a specific impurity concentration suitable for low-temperature bonding. Those skilled in the art will understand that the surface of the bonding pad 318 may be slightly recessed relative to the surface of the surrounding dielectric layer 232 to facilitate metal bonding during the annealing / expansion phase of hybrid bonding, as described above. In some embodiments, a bonding structure (not shown) can be formed by directly bonding two elements, similar to... Figure 3D The structure shown. During direct bonding, the conductive tip of the bonding pad 318 of the TSV structure 322 on the back side of the first element (e.g., the first microelectronic structure 300) can be directly bonded to the contact pad or DBI pad formed on the front or front surface of the second element (e.g., the second microelectronic structure 300), and the back side of the first element can be directly bonded to the front side of the second element without any adhesive.

[0065] Figures 4A-4C Various configurations of microelectronic structures 400a and 400b and bonding structure 450 are shown. Figure 4A The microelectronic structure 400a is shown, similar to Figure 2G The illustrated microelectronic structure 200 has one or more RDLs 424 formed over the back surface 208 of the microelectronic structure 200 for electrical communication between the conductive tip portion 214 of the TSV structure 222 and bonding pads 414 in the bonding layer of the one or more RDLs 424. Figure 2G or Figure 3D The microelectronic structures 200 and 300 shown (which are capable of realizing TSV-to-pad hybrid bonding structures (e.g., Figure 2H The joint structure shown (250) is different. Figure 4A The microelectronic structure 400a in the middle will be able to achieve pad-to-pad hybrid bonding. Figure 4B The microelectronic structure 400b is shown, having bonding pads 418, similar to... Figure 3D The microelectronic structure shown. Figure 4B The microelectronic structure 400b and Figure 3D The difference in microelectronic structure is that Figure 4B The bonding pads 418 of the microelectronic structure 400b are wider than those of the TSV structure 222 and can be photolithographically defined by masking and etching the dielectric layer 232, depositing pad material (e.g., copper), and CMP. The bonding pads (e.g., Figure 4A 414 or Figure 4B-4CThe conductive material of the bonding pad 418 may be the same as or different from the material of the conductive tip portion 214. For example, if the conductive tip portion comprises nickel, the bonding pad may comprise copper. Those skilled in the art will understand that the surface 419 of the bonding pad 418 may be slightly recessed relative to the surface 233 of the surrounding dielectric layer 232 to facilitate metal bonding during the annealing / expansion phase of the hybrid bonding, as described above.

[0066] Figure 4C A hybrid bonding structure 450 according to some embodiments is shown. Figure 4C The hybrid bonding structure 450 illustrates two microelectronic structures 400c, 400d, which are hybrid-bonded in a back-to-back configuration, i.e., the back surface 408a (having a TSV structure 422a) of one microelectronic structure 400c is hybrid-bonded with the back surface 408b of the second microelectronic structure 400d (having a TSV structure 422b). The electrical connection between the TSV structure 422a of the first microelectronic structure 400c and the TSV structure 422b of the second microelectronic structure 400d is shown as an intermediate bonding pad 418 passing through the TSV conductive tip portion 214 of each microelectronic structure 400c, 400d.

[0067] Figures 5A-5D A method for forming a microelectronic structure 500 according to another embodiment is schematically illustrated. The microelectronic structure 500 formed by this method (in...) Figure 5D (as shown in the image) similar to Figure 2G The microelectronic structure 200 is shown. However, the illustrated method employs a sacrificial tip portion 515, which is exposed on the back side after being subjected to conductive material (e.g., Figure 5C The conductive layer 513 shown is replaced so that the resulting conductive tip portion 514 can have a different composition than that of the aforementioned embodiment. Figure 5A Similar to Figure 2G The difference is Figure 2G The tip portion 214 shown is part of the final microelectronic structure 200, while Figure 5A The tip portion 515 shown is sacrificial (i.e., not part of the final microelectronic structure 500). It can be... Figure 5A A seed layer, a barrier layer, and / or an adhesive layer material (not shown) are provided between the sacrificial tip portion 515 and the second conductive via portion 216, similar to the description of the seed layer, barrier layer, and / or adhesive layer material. Figure 6 The barrier material 603 shown and discussed.

[0068] Figure 5B The sacrificial material with the sacrificial tip portion 515 removed is shown (in Figure 5A (As shown in the image). Sacrificial tip portion 515 (in...) Figure 5A(As shown in the diagram) was essentially removed from the microelectronic structure, in the TSV structure 522 (in Figure 5C A cavity 508 is formed at the tip of the rear end of the part shown in the diagram. Figure 2E Similar to the tip portion 214 shown, the sacrificial tip portion 515 may include a material with relative etch resistance to the etchant capable of etching the bulk substrate 206. In embodiments where the bulk substrate 206 is silicon and the selective etchant is SF6, the sacrificial tip portion 515 should include a material corresponding to... Figure 2E The substrate is etched back using a material that is relatively resistant to SF6 etching. The sacrificial tip portion 515 may include a material that can also be selectively removed from the back side 208 of the structure without damaging the dielectric layer 232 (such as...). Figure 5B (As shown). The material of the sacrificial tip portion 515 can also be selected to allow selective removal relative to the second conductive via portion 216 above the sacrificial tip portion 515, although this limitation can be omitted, particularly when a barrier material (not shown) is provided between the sacrificial tip portion 515 and the second conductive via portion 216. For example, the sacrificial tip portion 515 may include an organic material; for example, polyimide (PI), polybenzoxazole (PBO), benzocyclobutene (BCB)-based polymers, etc. Exemplary selective etching includes selective plasma etching or wet etching of organic materials, which can selectively remove sacrificial materials including organic materials such as PI, PBO, BCB, etc., with minimal damage to the surrounding materials exposed to the etching (e.g., silicon, silicon oxide, metal nitrides, and copper). In some embodiments, the sacrificial tip portion may include a polymeric material and may vaporize when heated in a vacuum at temperatures below 400°C or below 300°C. Using a barrier layer (not shown) between the sacrificial tip portion 515 and the second conductive via portion 216 generally expands the range of selective etching chemicals available for removing the sacrificial material. In some embodiments, inorganic materials may also be used as sacrificial materials at the bottom of the TSV tip; for example, silicon oxide. In some embodiments, back-side thinning (including grinding, milling, and polishing) from the back side of the structure can continue until the bottom tips of all TSV structures are exposed. The sacrificial materials can be selected such that exposing the bulk substrate 206 to these sacrificial materials during thinning does not contaminate (e.g., via diffusion) the bulk substrate 206.

[0069] In some embodiments, removing the sacrificial material exposes a barrier layer (not shown) previously disposed between the sacrificial tip portion 515 and the second conductive via portion 216. In some embodiments, removing the sacrificial material exposes the second conductive via portion 216 at the back surface 208 of the substrate 206.

[0070] Figure 5CA conductive layer 513 is shown deposited over the back side 208 of the substrate and over the back side of the TSV structure 522. The conductive layer 513 backfills the cavity 508 formed by removing the sacrificial tip portion 515 of the TSV structure 522, thereby replacing the sacrificial material. In some embodiments, prior to the deposition of the conductive layer over the back side of the substrate, another conductive barrier layer and / or seed layer (not shown) may be deposited on the exposed back side of the second conductive via portion of the TSV structure. In some embodiments, the conductive layer 513 comprises copper, a copper alloy, nickel, a nickel alloy, tungsten, and / or indium, or another metal capable of direct bonding with copper. In some embodiments, as described with respect to the second conductive portion, the conductive layer 513 is primarily copper. The conductive layer 513 may be deposited using plating techniques, such as electroplating or electroless plating.

[0071] Figure 5D It shows Figure 5C The structure is in the state after planarization to expose dielectric layer 232. Figure 5D The back surface 208 of the microelectronic structure 500 can be fabricated for hybrid bonding, as described above. Those skilled in the art will understand that the surface of the (alternative) conductive tip portion 514 can be slightly recessed relative to the surface 233 of the surrounding dielectric layer 232 to facilitate metal bonding during the annealing / expansion phase of the hybrid bonding, as described above.

[0072] Figure 5D The microelectronic structure 500 is similar to Figure 2G The microelectronic structures shown are 200, but one difference between them is that... Figure 5D The conductive tip portion 514 can be composed of the same as... Figure 5D The second conductive via portion 216 is more similar. Although the two portions of the TSV structure 522 may have similar compositions, such as being predominantly copper, they are deposited at different times and may have used different processes. For example, the second conductive via portion 216 is located in the corresponding... Figure 2C The sediment was deposited in a very deep and high aspect ratio opening during that period, while the conductive tip portion 514 was... Figure 5CThe material is deposited into a much shallower depression (e.g., between 0.5 μm and 10 μm) at the same time point. Those skilled in the art will understand that, therefore, even if the two portions 514, 216 have similar copper contents, they can have different impurity levels and / or they can have different crystal structures (e.g., different average grain size or orientation) due to different additives used during deposition, such that in some embodiments, the two portions 514, 216 can be distinguished from each other in the final structure. In some embodiments, the conductive tip portion may have a specific grain orientation (e.g., 111 grain orientation), a nanostructure, or a specific impurity concentration suitable for low-temperature bonding to another element without any intervening binder (e.g., direct bonding, as described above). Additionally, in some embodiments, a barrier layer and / or a seed layer (not shown) may be intervened between the conductive tip portion 514 and the second conductive via portion 216.

[0073] Figure 5E A joining structure 550 is shown, wherein the first element 560 (e.g., Figure 5D The back side of the first microelectronic structure 500 is hybridly bonded to the second element 570 (e.g., another such element) along the bonding interface 565. Figure 5D The BEOL or RDL 572 is on the front side 576 of the microelectronic structure 500 shown. In some embodiments, the conductive tip portion 514 of the TSV structure 522 at the back side of the first element 560 is directly bonded to the contact pad 574 on the front side or front surface 576 of the second element 570. In some embodiments, the TSV structure 522 of the first element 560 is electrically connected to the TSV structure 522' of the second element 570. In some embodiments, the metal-to-metal bond between the first element 560 and the second element 570 is a direct copper-to-copper bond.

[0074] Figure 6 Additional aspects of the microelectronic structure 600 are shown. Figure 6 Similar to Figure 2G The difference is Figure 6 The conductive tip portion 614 of the microelectronic structure 600 shown (which can be Figure 2B (Or formed at 5C) includes conductive binders, such as solder. Although Figure 2G The microelectronic structure 200 shown is configured to bond to the second element via hybrid bonding without the need for an adhesive, but Figure 6 The microelectronic structure 600 shown is configured to be bonded to the second element using a more conventional technique. Figure 6 The microelectronic structure 600 shown can be used with Figure 2A-2G The method shown is the same as the method formed, or through Figures 5A-5DThe sacrificial process is formed, the difference being that the conductive tip portion 614 includes a conductive adhesive. Additionally, in Figure 6 In the illustrated embodiment, the TSV structure 622 of the microelectronic structure 600 has an optional lateral offset 652 relative to the bonding pad 675, which is electrically connected to the TSV structure 622 via a conductive trace 676.

[0075] Figure 6 An optional barrier material 603 is also shown, which is inserted between the conductive tip portion 614 and the second conductive via portion 216. The barrier material 603 can be a conductive barrier layer, such as tungsten or various transition metal nitrides, and can be positioned corresponding to... Figure 2B and Figure 2C Deposition between periods shown. Figure 6 Optional barrier layer 605 and seed layer 607 are also shown, which are inserted between TSV structure 622 and bulk substrate 206.

[0076] Figures 7A-7C Various schematic diagrams of bonding structures 750a-c, including microelectronic structures 700a-f (with TSV structure 722), are shown. These microelectronic structures 700a-f are similar to... Figure 2G , 3D The difference between those in 4B and 5D is that, for example... Figure 6 As shown, the microelectronic structure 700a-f does not need to be fabricated for hybrid bonding. Figures 7A-7C The two microelectronic structures 700 shown in each example are bonded together by a more conventional metal-to-metal configuration, rather than by direct bonding. In some embodiments, Figures 7A-7C The first microelectronic structure and the second microelectronic structure 700 shown are joined together by thermocompression bonding or welding.

[0077] exist Figure 7A In the middle, there are two microelectronic structures, 700a and 700b—each of which is related to... Figure 6 The structures shown are similar—bonded back-to-back to form a bonding structure 750a. A conductive tip portion 714a on the back side of a TSV structure 722a of a microelectronic structure 700a is metal-to-metal bonded to a conductive tip portion 714b on the back side of a TSV structure 722b of a second microelectronic structure 700b. The conductive tip portions 714a, 714b may include solder, as per [reference to...]. Figure 6 As described above. In other embodiments, the contacts at the engagement interface 765 may be included after the conductive tip portion 714 is exposed (e.g., Figure 2D ) or in use the conductive tip portion 514 (e.g., as Figures 5A-5D (As shown) The copper bump or copper post provided during or after the replacement of the sacrificial tip portion 515.

[0078] Figure 7B A microelectronic structure 700c is shown, which has a TSV structure 722c. The TSV structure 722c includes a conductive tip portion 714c and a second conductive via portion 216, which are configured differently. As described in the previous embodiments, the microelectronic structure 700c is bonded to a second microelectronic structure 700d in a back-to-back configuration to form a bonding structure 750b. The conductive tip portion 714c on the back side of the TSV structure 722c of one microelectronic structure 700c is bonded directly or via intervening bumps or pillars to a metallization layer 224 (e.g., a BEOL layer or an RDL layer) of the second microelectronic structure 700d. The second microelectronic structure 700d includes the TSV structure 722d, which itself includes the conductive tip portion 714d. Figure 7B In the illustrated embodiment, the TSV structure 722c of the first microelectronic structure 700c is laterally offset 752 relative to the TSV structure 722d of the second microelectronic structure 700d. A conductive tip portion 714c on the back side of the TSV structure 722c of the microelectronic structure 700c is bonded to an intervention contact pad 774 of the second microelectronic structure 700d, which is electrically connected to the TSV structure 722d of the second microelectronic structure 700d via a conductive trace 776.

[0079] Figure 7C A microelectronic structure 700e is shown, which has a TSV structure 722e. The TSV structure 722e includes a conductive tip portion 714e and a second conductive via portion 216 that are configured differently. As described in the previous embodiment, the microelectronic structure 700e is bonded to a second microelectronic structure 700f in a back-to-back configuration to form a bonding structure 750c. The conductive tip portion 714e on the back side of the TSV structure 722e of one microelectronic structure 700e is bonded to an intervention contact pad 775 of the second microelectronic structure 700f, which is electrically connected to the TSV structure 722f of the second microelectronic structure 700f.

[0080] In one aspect, the microelectronic structure includes a first element and a through-substrate via (TSV) structure. The first element includes a bulk portion having a front side and a back side opposite to the front side. The TSV structure is disposed in an opening extending from the front side to the back side and at least partially penetrating the bulk portion. The TSV structure includes a conductive tip portion and a second conductive via portion. The second conductive via portion is disposed between the front side and the conductive tip portion. The conductive tip portion contains a conductive material different from the second conductive via portion.

[0081] In some embodiments, the back side of the first element is fabricated for hybrid bonding. In some embodiments, the conductive tip portion comprises a material less prone to tailing than copper during chemical mechanical polishing (CMP). In some embodiments, the second conductive via portion is primarily copper. In some embodiments, the conductive tip portion comprises nickel. In some embodiments, the conductive tip portion is primarily nickel. In some embodiments, the conductive tip portion comprises indium. Some embodiments also include a dielectric layer disposed on the back side of the bulk portion. In some embodiments, the TSV structure further includes a bonding pad disposed above the back side of the conductive tip portion, and the bonding pad is embedded in the dielectric layer. In some embodiments, the bonding pad is primarily copper. In some embodiments, the bonding pad is recessed relative to the dielectric layer. In some embodiments, the conductive tip portion is recessed relative to the dielectric layer. In some embodiments, the first element comprises a plurality of TSV structures, wherein the thickness of the conductive tip portion of one of the plurality of TSV structures differs from the thickness of the conductive tip portion of another of the plurality of TSV structures by more than 1%. Some embodiments also include a barrier layer and / or a seed layer disposed along at least a portion of the interface between the TSV structure and the bulk portion. Some embodiments also include a second element hybridly bonded to the back side of the first element.

[0082] In another aspect, a method of forming a microelectronic structure includes providing a plurality of via structures in a bulk substrate material. Each via structure is disposed in a blind via extending through the bulk substrate from a front side to a back side portion of the bulk substrate material. Each via structure includes a pointed portion in the blind via and a second via portion disposed in the blind via, conducting between the front side and the pointed portion. The second via portion comprises a different material than the pointed portion. The method also includes exposing the pointed portions of the plurality of via structures from the back side.

[0083] In some embodiments, the method further includes fabricating a back side for hybrid bonding. In some embodiments, fabricating a back side for hybrid bonding includes etching back the bulk substrate from the back side, causing a conductive tip portion to protrude from the bulk substrate. In such embodiments, fabricating a back side for hybrid bonding further includes depositing a dielectric bonding layer over and around the tip portion after etching back, and polishing the dielectric bonding layer to expose the tip portion. In some embodiments, providing a plurality of via structures includes filling the bottom portion of a blind via with a bottom-up deposition process to form a tip portion in the bottom portion, and extending the blind via from the tip portion to a void on the front side of the bulk substrate material. In such embodiments, providing a plurality of via structures further includes depositing a second via portion into the void. Some embodiments also include etching the back side of the bulk substrate material such that the tip portion of the via structure protrudes from the bulk substrate material. In some embodiments, the height by which the tip portion of the via structure protrudes from the bulk substrate material is less than 100 nanometers. Some embodiments also include depositing a dielectric layer over the back side of the bulk substrate and over the protruding via structure. Some embodiments also include planarizing the dielectric layer to expose the tip portion of the via structure from the back side. Some embodiments also include a bonding pad disposed above the back side of the tip portion. In such embodiments, the bonding pad is embedded in a dielectric layer, and the tip portion is conductive. In some embodiments, the second via portion is primarily copper. In some embodiments, the tip portion is conductive. In some embodiments, the tip portion is primarily nickel. In some embodiments, the tip portion includes a sacrificial material. Such embodiments also include selectively removing the sacrificial material and replacing it with a conductive tip portion after exposing the tip portion. Some embodiments also include co-bonding the microelectronic structure to the second element.

[0084] Unless the context explicitly requires it, throughout the specification and claims, the terms “comprise,” “comprising,” “include,” “including,” and similar terms should be interpreted in an inclusive sense, rather than an exclusive or exhaustive sense; that is, meaning “including but not limited to.” The term “coupled,” as commonly used herein, refers to two or more elements that can be directly connected or connected through one or more intermediate elements. Similarly, the term “connected,” as commonly used herein, refers to either two or more elements that can be directly connected or connected through one or more intermediate elements. Additionally, the terms “this,” “above,” “below,” and similar terms, when used in this application, should refer to the application as a whole, not a specific part of it. Furthermore, as used herein, when describing a first element “on” or “above” a second element, the first element may be directly on or above the second element such that the first and second elements are in direct contact, or the first element may be indirectly on or above the second element such that one or more elements intervene between the first and second elements. Where the context permits, the use of singular or plural terms in the above specific embodiments may also include the plural or singular, respectively. When the word "or" refers to a list of two or more items, it encompasses all of the following interpretations of the word: any one of the items in the list, all of the items in the list, and any combination of the items in the list.

[0085] Furthermore, the conditional language used herein, such as “can,” “could,” “might,” “may,” “e.g.,” “for example,” “such as,” etc., unless expressly stated otherwise or understood differently in the context of use, is generally intended to convey that certain embodiments include certain features, elements, and / or states that are not included in other embodiments. Therefore, such conditional language is not generally intended to imply that features, elements, and / or states are necessary in any way for one or more embodiments.

[0086] While certain embodiments have been described, these embodiments are presented by way of example only and are not intended to limit the scope of this disclosure. In fact, the novel apparatuses, methods, and systems described herein can be embodied in a variety of other forms; furthermore, various omissions, substitutions, and modifications can be made to the form of the methods and systems described herein without departing from the spirit of this disclosure. For example, although various modules are presented in a given arrangement, alternative embodiments may perform similar functions using different components and / or circuit topologies, and some modules may be deleted, moved, added, subdivided, combined, and / or modified. Each of these modules can be implemented in a variety of different ways. Elements and behaviors of the various embodiments described above can be combined in any suitable way to provide further embodiments. The appended claims and their equivalents are intended to cover such forms or modifications falling within the scope and spirit of this disclosure.

Claims

1. A microelectronic structure, comprising: The first element includes a block-shaped portion having a front side and a back side opposite to the front side; as well as A through-substrate via (TSV) structure is disposed in an opening extending from the front side to the back side and at least partially penetrating the bulk portion, the TSV structure comprising: The conductive tip portion and the second conductive through-hole portion are disposed between the front surface and the conductive tip portion, and the conductive tip portion comprises a conductive material different from the second conductive through-hole portion.

2. The microelectronic structure according to claim 1, wherein, The back side of the first element is prepared for hybrid bonding.

3. The microelectronic structure according to claim 1, wherein, The conductive tip portion comprises a material that is less prone to tailing than copper during chemical mechanical polishing (CMP).

4. The microelectronic structure according to claim 3, wherein, The second conductive via is mainly made of copper.

5. The microelectronic structure according to claim 4, wherein, The conductive tip portion includes nickel.

6. The microelectronic structure according to claim 5, wherein, The conductive tip portion is primarily nickel.

7. The microelectronic structure according to claim 4, wherein, The conductive tip portion includes indium.

8. The microelectronic structure according to claim 1, further comprising: A dielectric layer is disposed on the back side of the block portion.

9. The microelectronic structure according to claim 8, wherein, The TSV structure further includes a bonding pad disposed above the back side of the conductive tip portion, wherein the bonding pad is embedded in the dielectric layer.

10. The microelectronic structure according to claim 9, wherein, The bonding pads are primarily made of copper.

11. The microelectronic structure according to claim 10, wherein, The bonding pads are recessed relative to the dielectric layer.

12. The microelectronic structure according to claim 8, wherein, The conductive tip portion is recessed relative to the dielectric layer.

13. The microelectronic structure according to claim 1, wherein, The first element includes a plurality of TSV structures, wherein the thickness of the conductive tip portion of one of the plurality of TSV structures differs from the thickness of the conductive tip portion of another of the plurality of TSV structures by more than 1%.

14. The microelectronic structure according to claim 1, further comprising: A barrier layer and / or a seed layer are disposed along at least a portion of the interface between the TSV structure and the block portion.

15. The microelectronic structure according to any one of the preceding claims further comprises: The second element is mixed and bonded to the back side of the first element.

16. A method for forming a microelectronic structure, the method comprising: A plurality of via structures are provided in a bulk substrate material, each via structure being disposed in a blind via extending partially through the bulk substrate from the front side of the bulk substrate material toward the back side of the bulk substrate material, each via structure comprising: The pointed portion, in the blind hole, and A second through-hole portion is disposed within the blind hole, between the front surface and the tip portion, wherein the second through-hole portion comprises a different material from the tip portion; and The tip portion of the plurality of through-hole structures is exposed from the back side.

17. The method of claim 16, further comprising: The back side is prepared for hybrid bonding.

18. The method according to claim 17, wherein, Preparing the back side for hybrid bonding includes: The bulk substrate is etched back from the back side, causing the conductive tip portion to protrude from the bulk substrate; Following the etchback, a dielectric bonding layer is deposited above and around the tip portion; and Polish the dielectric bonding layer to expose the tip portion.

19. The method of claim 16, wherein, The plurality of through-hole structures include: The bottom portion of the blind via is filled using a bottom-up deposition process to form the tip portion in the bottom portion, and to form a void extending the blind via from the tip portion to the front side of the bulk substrate material; and The second through-hole portion is deposited into the void.

20. The method of claim 19, further comprising: The back side of the bulk substrate material is etched such that the tip portion of the through-hole structure protrudes from the bulk substrate material.

21. The method according to claim 20, wherein, The tip portion of the through-hole structure protrudes less than 100 nanometers from the bulk substrate material.

22. The method of claim 20, further comprising: A dielectric layer is deposited over the back side of the bulk substrate and over the protruding via structure.

23. The method of claim 22, further comprising: The dielectric layer is planarized to expose the tip portion of the via structure from the back side.

24. The method of claim 22, further comprising: A bonding pad is provided above the back side of the tip portion, wherein the bonding pad is embedded in the dielectric layer, and wherein the tip portion is conductive.

25. The method according to claim 19, wherein, The second through-hole portion is mainly made of copper.

26. The method according to claim 19, wherein, The tip portion is conductive.

27. The method according to claim 25 or 26, wherein, The tip portion is primarily nickel.

28. The method according to claim 19, wherein, The tip portion includes a sacrificial material, and the method further includes: after exposing the tip portion, selectively removing the sacrificial material and replacing the sacrificial material with a conductive tip portion.

29. The method according to any one of claims 16 to 28, further comprising: The microelectronic structure is hybridized and bonded to the second element.

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