FPGA configuration system based on double-channel control switch and remote upgrading method
The FPGA configuration system, which uses a dual-channel control switch, enables flexible channel switching between the FPGA and CPU with the Flash memory. This solves the problems of cumbersome FPGA upgrade operations and low reliability in existing technologies, and provides flexibility and reliability for remote upgrades.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- MILKY WAY ELECTRONICS EQUIP FACTORY SHANXI PROVINCE
- Filing Date
- 2026-01-23
- Publication Date
- 2026-06-12
AI Technical Summary
Existing FPGA software upgrade methods rely on JTAG tools or FPGA built-in Flash control programs, resulting in cumbersome operation, poor flexibility, and low reliability, making remote upgrades impossible.
An FPGA configuration system based on a dual-channel control switch is adopted, which realizes dynamic switching between the FPGA-Flash and CPU-Flash channels by controlling the switch state through the CPU's GPIO, simplifying FPGA design and improving upgrade flexibility and reliability.
It eliminates the need for built-in Flash control programs in the FPGA, supports remote or field upgrades, reduces FPGA development complexity, improves system reliability and flexibility, and requires minimal hardware modifications at a low cost.
Smart Images
Figure CN122195463A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of field-programmable gate array (FPGA) technology, specifically to an FPGA configuration system and remote upgrade method based on a dual-channel control switch. This system enables the FPGA program to be read, written, and upgraded directly via an external CPU through an external CPU without requiring intervention from the FPGA's internal logic. Background Technology
[0002] An FPGA is a programmable logic device widely used in communications, industrial control, and other fields. Its functionality is determined by a configuration file loaded into it. This configuration file is typically stored in external non-volatile memory, most commonly SPI-interface Flash memory. When the FPGA powers on, it automatically reads the configuration from this Flash memory and loads it. With the continuous iteration of device functional requirements and the need for fault repair, FPGA software upgrades have become a crucial step in ensuring the normal operation and functional updates of the equipment.
[0003] Currently, there are two main methods for upgrading FPGA software: Upgrading via JTAG interface: This method requires dedicated JTAG debugging tools and physical contact with the device's JTAG interface to complete the upgrade operation. In industrial sites, enclosed cabinets, and other scenarios, the equipment is often in an environment where it is inconvenient to disassemble or access. Upgrading via JTAG interface is not only cumbersome to operate, but also cannot achieve remote upgrades, resulting in extremely poor flexibility.
[0004] CPU indirect control upgrade: This method requires the FPGA to be pre-programmed with Flash control software, and the CPU to perform functions such as erasing, writing, and verifying the Flash. The CPU sends instructions and data to the FPGA via the bus, and the FPGA controls the Flash, thereby completing the FPGA upgrade program. However, this upgrade method has obvious drawbacks: First, the FPGA needs to take on the additional Flash control function, increasing the design complexity of the FPGA program and consuming FPGA logic resources; second, if the FPGA control program malfunctions, it will directly lead to the failure of the upgrade function, resulting in low system reliability.
[0005] Existing FPGA software upgrade technologies cannot simultaneously meet the requirements of "FPGA self-booting", "upgrade convenience" and "low development complexity". Therefore, there is an urgent need for a remote FPGA software upgrade solution that does not require the FPGA's built-in Flash control program and can flexibly switch communication channels. Summary of the Invention
[0006] This invention addresses the problem of traditional FPGA upgrade methods relying on JTAG tools and FPGA built-in control programs by providing an FPGA configuration system and remote upgrade method based on a dual-channel control switch. The core of this method is to achieve dynamic switching of the Flash communication channel through a hardware switch, which simplifies FPGA development and improves upgrade flexibility and reliability.
[0007] This invention is implemented using the following technical solution: an FPGA configuration system based on a dual-channel control switch, comprising an FPGA, a CPU, a Flash memory chip, and a dual-channel control switch, wherein the dual-channel control switch comprises: one output channel connected to the SPI interface of the Flash memory chip; two input channels: a first input channel connected to the SPI interface of the FPGA, and a second input channel connected to the SPI interface of the CPU; and a control terminal connected to the GPIO interface of the CPU for receiving channel selection signals. When the GPIO output is low, the first input channel is connected, i.e., the FPGA-Flash channel is turned on; when the GPIO output is high, the second input channel is connected, i.e., the CPU-Flash channel is turned on.
[0008] The aforementioned FPGA configuration system based on a dual-channel control switch uses an M300 CPU, an SMQ7VX690TFFG1761IP FPGA, an SM25QH256MX FLASH, and two ADG787 chips, designated U1 and U2, as the dual-channel control switch. When pins IN1 and IN2 of the ADG787 chip are 0, channels S1B and S2B output, while channels S1A and S2A are closed; when pins IN1 and IN2 are 1, channels S1A and S2A output, while channels S1B and S2B are closed. The SPI interface pins SPI_CS, SPI_CLK, SPI_MISO, and SPI_MOSI of the FPGA chip are connected to the S1B and S2B pins of the dual-channel control switches U1 and U2, respectively, to realize SPI signal transmission of the FPGA-Flash channel. The SPI interface pins SPI_CS, SPI_CLK, SPI_MISO, and SPI_MOSI of the CPU chip are connected to the S1A and S2A pins of the dual-channel control switches U1 and U2, respectively, to realize SPI signal transmission of the CPU-Flash channel. The SPI_CS, SPI_CLK, SPI_MOSI, and SPI_MISO of the FLASH chip are connected to the D1 and D2 pins of U1 and U2, respectively, to receive SPI signals from the FPGA chip or CPU chip. The GPIO_CTRL of the CPU chip is connected to the IN1 pin of the dual-channel control switch U1, outputting a level signal to control the working state of the dual-channel control switch. The IN2 pin of U1 and the IN1 and IN2 pins of U2 are both connected to the IN1 pin of U1.
[0009] A remote upgrade method for FPGA based on a dual-channel control switch includes the following steps: (1) Self-starting state Step 1: After the system is powered on, the CPU chip first completes its own initialization and sets the GPIO interface controlling the dual-channel control switch to a low-level output state by default. Step 2: When the dual-channel control switch receives a low-level signal, the first input channel is connected, that is, the FPGA-Flash channel is turned on; Step 3: After the FPGA powers on, it reads the configuration file from the Flash memory and completes the self-startup process; (2) Upgrade status Step 1: Upgrade Trigger: The host computer sends an upgrade command to the CPU via serial port. The CPU parses the command and triggers the upgrade. Step 2: Channel Switching: After receiving the upgrade trigger signal, the CPU switches the GPIO interface of the control switch from low level to high level; when the dual-channel control switch receives the high-level signal, it disconnects the FPGA-Flash channel and connects the second input channel, that is, the CPU-Flash channel is turned on; Step 3: Program Writing and Verification: The CPU starts SPI master mode and performs the following operations: Program backup: Reads the current version of the program data from Flash into memory for software version rollback in case of upgrade failure; Erase upgrade program area: Send sector erase command to Flash to erase the sector corresponding to the upgrade program area, ensuring that the storage space is writable; Read the upgrade program: The CPU reads the FPGA upgrade program configuration file from local storage; Write and Verification: Send a write command to the Flash storage chip to write the upgrade program to the upgrade program area sector by sector; after the write is completed, read the data in the Flash to perform integrity verification. If the verification passes, the program is successfully written. If the verification fails, rewrite once. If the rewrite verification fails, the software version is rolled back. Step 4: Channel Reset and FPGA Reboot: After the upgrade program is fully written and verified, the CPU restores the GPIO interface of the control switch to low level, the dual-channel control switch switches back to the FPGA-Flash channel, and the FPGA is reset. Step 5: Loading the new program: After the FPGA restarts, it reads the Flash again through the SPI interface. At this time, the upgrade program area has stored the new program. The FPGA loads the new program and runs it to complete the software upgrade.
[0010] In the above-mentioned FPGA remote upgrade method based on a dual-channel control switch, in step 4 of the upgrade process, the CPU sends a reset signal to the FPGA through a dedicated GPIO pin to trigger the FPGA to restart. If there is no dedicated reset pin, the FPGA can be restarted by manually pressing the FPGA reset button or by powering off.
[0011] In the aforementioned FPGA remote upgrade method based on a dual-channel control switch, the sector corresponding to the upgrade program area is the sector corresponding to the storage bitstream file.
[0012] The aforementioned FPGA remote upgrade method based on a dual-channel control switch reads the local storage during the upgrade process as the external Flash storage of the CPU, and the external Flash of the CPU stores the bitstream file to be upgraded in advance.
[0013] The present invention has the following beneficial effects: 1. Simplified FPGA design: FPGAs do not require writing Flash control programs, only retaining the basic SPI communication interface, which reduces the complexity of FPGA program development and power consumption.
[0014] 2. Enhanced upgrade flexibility: No need to rely on JTAG tools; upgrades can be performed remotely or on-site via the CPU, making it especially suitable for scenarios where it is inconvenient to disassemble equipment, such as industrial sites.
[0015] 3. Enhanced maintainability and reliability: Channel switching is achieved through a hardware switch, avoiding upgrade failures caused by errors in the FPGA control program, and only one channel is active at a time to prevent signal conflicts.
[0016] 4. Simple hardware structure: The core only adds a low-cost dual-channel control switch, with minimal hardware modifications, simple implementation, low cost, and easy integration and promotion in existing systems.
[0017] 5. Compatible with traditional self-booting: Maintains the original self-booting logic of the FPGA in non-upgrade state, without changing the normal operation process of the device. It has strong compatibility and can directly replace traditional FPGA upgrade solutions. Attached Figure Description
[0018] Figure 1 This is a schematic diagram of the hardware connections for an FPGA software upgrade device.
[0019] Figure 2 This is a flowchart illustrating the steps involved in an FPGA software upgrade process. Detailed Implementation
[0020] The core of this invention is to introduce a dedicated dual-channel control switch between the CPU and the configuration Flash. The switch state is controlled by the CPU's GPIO, realizing the switching between two single channels: "FPGA-Flash" (self-boot) and "CPU-Flash" (upgrade). The specific hardware structure and upgrade process are as follows: 1. Hardware structure and connection relationships This device consists of four core modules: an FPGA chip, a CPU chip, a Flash memory chip, and a dual-channel control switch. The interface definitions and functions of each module are as follows: 1) FPGA chip: The core functional chip. An FPGA chip that supports SPI master mode is selected. It needs to be started and run by reading the program of the Flash memory chip. Only the SPI interface for communication with Flash is retained. No additional Flash control program needs to be designed.
[0021] 2) CPU chip: Upgraded control core with two key interfaces: one is a GPIO port for controlling the switch, which outputs a high-low level switching channel; the other is an SPI interface for transmitting the upgrade program, which can communicate directly with Flash.
[0022] 3) Flash memory chip: program storage carrier, with only a single SPI channel interface, requiring a dual-channel control switch to select the communication target.
[0023] 4) Dual-channel control switch: The dual-channel switching switch is the core of this invention, and it includes: An output channel is connected to the SPI interface of the Flash memory chip (including signals such as SCK, CS#, MOSI, and MISO).
[0024] Two input channels: The first input channel is connected to the SPI interface of the FPGA. The second input channel is connected to the SPI master controller interface of the CPU.
[0025] A control terminal is connected to the GPIO interface of the CPU to receive the channel selection signal. When the GPIO output is low, the first input channel is connected, that is, the "FPGA-Flash" channel is turned on. When the GPIO output is high, the second input channel is connected, that is, the "CPU-Flash" channel is turned on.
[0026] The dual-channel control switch is a hardware circuit, preferably implemented as a multiplexer (MUX) to ensure good support for high-speed SPI signals.
[0027] 2. Working principle and upgrade method / steps The core logic of this invention is "hardware channel switching + phased control", which is divided into two core phases: self-starting state (normal operation) and upgrade state. The specific process is as follows: (1) Self-starting state Step 1: After the device is powered on, the CPU chip first completes its own initialization and sets the GPIO interface controlling the dual-channel control switch to a low-level output state by default. Step 2: When the dual-channel control switch receives a low-level signal, the first input channel is connected, that is, the "FPGA-Flash" channel is turned on; Step 3: After the FPGA powers on, it reads the configuration file from the Flash memory and completes the self-startup process; (2) Upgrade status (temporary working mode) Step 1: Upgrade Trigger. Trigger the CPU to enter upgrade mode using the following method: Remote triggering: The host computer sends an "upgrade command" to the CPU via serial port, Ethernet or other communication methods. The CPU then parses the command and triggers the upgrade. Step 2: Channel Switching. After receiving the upgrade trigger signal, the CPU immediately switches the GPIO port of the control switch from low to high level; when the dual-channel control switch receives the high-level signal, it disconnects the "FPGA-Flash" channel, and the second input channel is connected, that is, the "CPU-Flash" channel is turned on.
[0028] Step 3: Program writing and verification. The CPU starts SPI master mode and performs the following operations: Program backup: Reads the current version of the program data from Flash into memory for software version rollback in case of upgrade failure; Erase upgrade program area: Send a "sector erase command" to Flash to erase the sector corresponding to the upgrade program area, ensuring that the storage space is writable; Read the upgrade program: The CPU reads the FPGA upgrade program configuration file from local storage; Write and Verification: Send a write command to the Flash storage chip to write the upgrade program to the upgrade program area sector by sector; after the write is completed, read the data in the Flash to perform integrity verification. If the verification passes, the program is successfully written. If the verification fails, rewrite once. If the rewrite verification fails, the software version is rolled back.
[0029] Step 4: Channel Reset and FPGA Reboot. After the upgrade program is fully written and verified, the CPU restores the GPIO port of the control switch to a low level, and the dual-channel control switch switches back to the "FPGA-Flash" channel; the CPU sends a "reset signal" (low-level reset) to the FPGA through a dedicated GPIO pin, triggering the FPGA reboot; if there is no dedicated reset pin, the "FPGA reset button" can be pressed manually or the power can be turned off to achieve a reboot.
[0030] Step 5: Loading the new program. After the FPGA restarts, it reads the Flash again via the SPI interface. At this time, the upgrade program area has stored the new program. The FPGA loads the new program and runs it, completing the software upgrade. Example
[0031] 1. Hardware Selection CPU: M300 chip, which has rich GPIO interfaces and high-performance SPI interface, and can efficiently complete channel control and upgrade program transmission tasks. FPGA: SMQ7VX690TFFG1761IP chip. This chip has stable performance, supports SPI master mode, and can meet the needs of most industrial and embedded scenarios. FLASH: SM25QH256MX chip, with a storage capacity of 256MB, supports SPI communication, and has sector erase and page write functions to meet the storage and upgrade requirements of FPGA programs.
[0032] Dual-channel control switches: The ADG787 chip integrates two independently selectable single-pole double-throw (SPDT) switches to ensure stable SPI signal transmission and avoid communication errors caused by signal attenuation or delay. This device requires two chips, designated U1 and U2. When pins IN1 and IN2 are 0, channels S1B and S2B output, while channels S1A and S2A are disabled; when pins IN1 and IN2 are 1, channels S1A and S2A output, while channels S1B and S2B are disabled.
[0033] To clarify the hardware connections between the chips and ensure correct assembly and stable operation of the device, the core pin connections of each chip are as follows: The SPI interface pins AL36 (SPI_CS), N10 (SPI_CLK), AN36 (SPI_MISO), and AM36 (SPI_MOSI) of the FPGA chip are connected to the S1B and S2B pins of the dual-channel control switch U1 and the S1B and S2B pins of U2, respectively, to realize the SPI signal transmission of the "FPGA-Flash" channel. The SPI interface pins U10 (SPI_CS), T10 (SPI_CLK), U11 (SPI_MISO), and T11 (SPI_MOSI) of the CPU chip are connected to the S1A and S2A pins of the dual-channel control switch U1 and the S1A and S2A pins of U2, respectively, to realize the SPI signal transmission of the "CPU-Flash" channel. The 1st pin (SPI_CS), 6th pin (SPI_CLK), 2nd pin (SPI_MOSI), and 5th pin (SPI_MISO) of the FLASH chip are connected to the D1 and D2 pins of U1 and the D1 and D2 pins of U2, respectively, to receive SPI signals from the FPGA chip or the CPU chip. The L2 pin (GPIO_CTRL) of the CPU chip is connected to the IN1 pin of the dual-channel control switch U1, and the output level signal controls the working state of the dual-channel control switch. Furthermore, the IN2 pin of U1 and the IN1 and IN2 pins of U2 are all connected to the IN1 pin of U1, ensuring that the four independent channels of the dual-channel control switch can switch synchronously and guarantee the consistency of the SPI signal.
[0034] Based on the above FPGA software upgrade device, the specific processes for the FPGA self-starting state (normal operation) and upgrade state are as follows: (1) Self-starting state Step 1: After the device is powered on, the CPU chip first completes its own initialization and sets the GPIO interface controlling the dual-channel control switch to a low-level output state by default. Step 2: When the dual-channel control switch receives a low-level signal, the first input channel is connected, that is, the "FPGA-Flash" channel is turned on; Step 3: After the FPGA powers on, it reads the configuration file from the Flash memory and completes the self-startup process; (2) Upgrade status (temporary working mode) Step 1: Upgrade Trigger: The host computer sends an "upgrade command" to the CPU via serial port. The CPU parses the command and triggers the upgrade. Step 2: Channel Switching: After receiving the upgrade trigger signal, the CPU immediately switches the GPIO port of the control switch from low level to high level; when the dual-channel control switch receives the high-level signal, it disconnects the "FPGA-Flash" channel and connects the second input channel, that is, the "CPU-Flash" channel is turned on; Step 3: Program Writing and Verification: The CPU starts SPI master mode and performs the following operations: Program backup: Reads the current version of the program data from Flash into memory for software version rollback in case of upgrade failure; Erase upgrade program area: Send a "sector erase command" to Flash to erase the sector corresponding to the upgrade program area, ensuring that the storage space is writable; Read the upgrade program: The CPU reads the configuration file of the Flash upgrade program from local storage; Write and Verification: Send a write command to the Flash storage chip to write the upgrade program to the upgrade program area sector by sector; after the write is completed, read the data in the Flash to perform integrity verification. If the verification passes, the program is successfully written. If the verification fails, rewrite once. If the rewrite verification fails, the software version is rolled back. Step 4: Channel Reset and FPGA Reboot: After the upgrade program is fully written and verified, the CPU will restore the GPIO port of the control switch to a low level, and the dual-channel control switch will switch back to the "FPGA-Flash" channel. Step 5: Loading the new program: After power failure and restart, the FPGA reads the Flash again through the SPI interface. At this time, the upgrade program area has stored the new program. The FPGA loads the new program and runs it to complete the software upgrade.
Claims
1. An FPGA configuration system based on a dual-channel control switch, characterized in that: The system includes an FPGA, a CPU, a Flash memory chip, and a dual-channel control switch. The dual-channel control switch comprises: one output channel connected to the SPI interface of the Flash memory chip; two input channels: a first input channel connected to the SPI interface of the FPGA and a second input channel connected to the SPI interface of the CPU; and a control terminal connected to the GPIO interface of the CPU to receive channel selection signals. When the GPIO output is low, the first input channel is connected, i.e., the FPGA-Flash channel is turned on; when the GPIO output is high, the second input channel is connected, i.e., the CPU-Flash channel is turned on.
2. The FPGA configuration system based on a dual-channel control switch according to claim 1, characterized in that: The CPU uses the M300 chip, the FPGA uses the SMQ7VX690TFFG1761IP chip, the FLASH uses the SM25QH256MX chip, and the dual-channel control switch uses two ADG787 chips, defined as U1 and U2. When the IN1 and IN2 pins of the ADG787 chip are 0, the S1B and S2B channels output, and the S1A and S2A channels are closed; when the IN1 and IN2 pins are 1, the S1A and S2A channels output, and the S1B and S2B channels are closed. The SPI interface pins SPI_CS, SPI_CLK, SPI_MISO, and SPI_MOSI of the FPGA chip are connected to the S1B and S2B pins of the dual-channel control switches U1 and U2, respectively, to realize SPI signal transmission of the FPGA-Flash channel. The SPI interface pins SPI_CS, SPI_CLK, SPI_MISO, and SPI_MOSI of the CPU chip are connected to the S1A and S2A pins of the dual-channel control switches U1 and U2, respectively, to realize SPI signal transmission of the CPU-Flash channel. The SPI_CS, SPI_CLK, SPI_MOSI, and SPI_MISO of the FLASH chip are connected to the D1 and D2 pins of U1 and U2, respectively, to receive SPI signals from the FPGA chip or CPU chip. The GPIO_CTRL of the CPU chip is connected to the IN1 pin of the dual-channel control switch U1, outputting a level signal to control the working state of the dual-channel control switch. The IN2 pin of U1 and the IN1 and IN2 pins of U2 are both connected to the IN1 pin of U1.
3. A remote upgrade method for FPGA based on a dual-channel control switch, characterized in that: Includes the following steps: (1) Self-starting state Step 1: After the system is powered on, the CPU chip first completes its own initialization and sets the GPIO interface controlling the dual-channel control switch to a low-level output state by default. Step 2: When the dual-channel control switch receives a low-level signal, the first input channel is connected, that is, the FPGA-Flash channel is turned on; Step 3: After the FPGA powers on, it reads the configuration file from the Flash memory and completes the self-startup process; (2) Upgrade status Step 1: Upgrade Trigger: The host computer sends an upgrade command to the CPU via serial port. The CPU parses the command and triggers the upgrade. Step 2: Channel Switching: After receiving the upgrade trigger signal, the CPU switches the GPIO interface of the control switch from low level to high level; when the dual-channel control switch receives the high-level signal, it disconnects the FPGA-Flash channel and connects the second input channel, that is, the CPU-Flash channel is turned on; Step 3: Program Writing and Verification: The CPU starts SPI master mode and performs the following operations: Program backup: Reads the current version of the program data from Flash into memory for software version rollback in case of upgrade failure; Erase upgrade program area: Send sector erase command to Flash to erase the sector corresponding to the upgrade program area, ensuring that the storage space is writable; Read the upgrade program: The CPU reads the FPGA upgrade program configuration file from local storage; Write and Verification: Send write commands to the Flash storage chip to write the upgrade program to the upgrade program area sector by sector; After the writing is complete, the data in the Flash is read for integrity verification. If the verification passes, the program is successfully written. If the verification fails, the data is rewritten. If the rewrite verification fails, the software version is rolled back. Step 4: Channel Reset and FPGA Reboot: After the upgrade program is fully written and verified, the CPU restores the GPIO interface of the control switch to low level, the dual-channel control switch switches back to the FPGA-Flash channel, and the FPGA is reset. Step 5: Loading the new program: After the FPGA restarts, it reads the Flash again through the SPI interface. At this time, the upgrade program area has stored the new program. The FPGA loads the new program and runs it to complete the software upgrade.
4. The FPGA remote upgrade method based on a dual-channel control switch according to claim 3, characterized in that: In step 4 of the upgrade process, the CPU sends a reset signal to the FPGA through a dedicated GPIO pin, triggering the FPGA to restart. If there is no dedicated reset pin, the FPGA can be restarted manually by pressing the reset button or by powering off.
5. A remote FPGA upgrade method based on a dual-channel control switch according to claim 3 or 4, characterized in that: The upgrade program area in the Flash memory chip is a sector that stores the FPGA bitstream file.
6. The FPGA remote upgrade method based on a dual-channel control switch according to claim 5, characterized in that: The local storage during the upgrade process is the external Flash storage of the CPU, which stores the bitstream file to be upgraded in advance.