Memory management system, method, control unit, medium and program product
By introducing an address translation management unit, unified invalidation operations and status confirmations for multiple system memory management units are achieved, solving the problem of cumbersome operations in the control unit and improving operational efficiency and system performance.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- SHANGHAI BIREN TECH CO LTD
- Filing Date
- 2026-04-30
- Publication Date
- 2026-06-12
AI Technical Summary
In a system-on-a-chip (SoC), the control unit needs to control multiple system memory management units to perform invalid operations, resulting in low operating efficiency and affecting system performance.
An address translation management unit is introduced, which enables unified invalidation operations and status confirmation for multiple system memory management units by configuring request registers and reading response registers, thus simplifying the control process.
It improves the efficiency of ineffective operations in multiple system memory management unit scenarios, simplifies the software control process, reduces the CPU processing burden, and enhances system performance.
Smart Images
Figure CN122195880A_ABST
Abstract
Description
Technical Field
[0001] This disclosure relates to the field of chip technology, and more specifically, to a memory management system, method, control unit, medium, and program product. Background Technology
[0002] A System Memory Management Unit (SMMU) can be used in a large System-on-Chip (SoC) chip to implement the translation of virtual addresses (VA) to physical addresses (PA). To improve address translation performance, multiple SMMUs can be integrated within the SoC. Each SMMU can deploy a memory address translation cache, which stores translation entries between virtual and physical addresses for the purpose of translating between them. For example, this memory address translation cache can be a Translation Lookaside Buffer (TLB). When the translation rules between virtual and physical addresses change, the memory address translation cache can be invalidated, for example, by invalidating all translation entries in the cache, so that new translation entries can be generated according to the changed translation rules.
[0003] In related technologies, the process of controlling each system memory management unit to perform invalid operations is cumbersome, resulting in low operational efficiency and affecting system performance. Summary of the Invention
[0004] One object of this disclosure is to provide a new technical solution regarding memory management.
[0005] According to a first aspect of the present disclosure, a memory management system is provided, the memory management system including a control unit, an address translation management unit, and a plurality of system memory management units, the address translation management unit being connected to the control unit and the plurality of system memory management units respectively, the address translation management unit including a request register and a response register, and the system memory management units including a memory address translation cache for performing virtual address and physical address translation; wherein: The control unit is configured to set the request register in the address translation management unit to a first preset value when it is necessary to perform an invalid operation on the memory address translation cache in the multiple system memory management units; The address translation management unit is configured to control multiple system memory management units to perform invalidation operations on the memory address translation cache when the request register is configured to a first preset value; and to configure the response register to a second preset value when it is determined that the invalidation operation was successfully executed. The control unit is also configured to read the response register and determine whether the invalid operation was successfully executed based on the value of the response register.
[0006] Optionally, the address translation management unit is specifically used to output an invalid request signal to a plurality of system memory management units when the request register is configured to a first preset value; The system memory management unit is used to invalidate the memory address translation cache in response to the invalid request signal.
[0007] Optionally, the address translation management unit outputs an invalid request signal to the system memory management unit through multiple trigger signal lines, with each trigger signal line corresponding to one system memory management unit.
[0008] Optionally, the request register includes a request bit, which is used to control the signals output by the plurality of trigger signal lines; or, The request register includes a plurality of request bits, each of which is used to control a signal output by one of the trigger signal lines.
[0009] Optionally, the system memory management unit is configured to output an invalid response signal to the address translation management unit if the invalid operation is successfully executed. The address translation management unit is specifically configured to set the response register to the second preset value when it receives invalid response signals output by multiple system memory management units.
[0010] Optionally, the address translation management unit further includes a logic operation circuit, which performs a logical AND operation on invalid response signals received from multiple system memory management units, and configures the value of the response register based on the operation result.
[0011] Optionally, each of the system memory management units corresponds to a response signal line, and the system memory management unit outputs the invalid response signal to the address translation management unit through the response signal line.
[0012] According to a second aspect of the present disclosure, a memory management method is provided, applied to a control unit in a memory management system. The memory management system includes the control unit, an address translation management unit, and a plurality of system memory management units. The address translation management unit is connected to the control unit and the plurality of system memory management units, and the address translation management unit includes a request register and a response register. The method includes: When it is necessary to invalidate the memory address translation cache in multiple system memory management units, the request register in the address translation management unit is configured to a first preset value, so that the address translation management unit controls multiple system memory management units to invalidate the memory address translation cache; and when it is determined that the invalidation operation is successfully executed, the response register is configured to a second preset value. Read the response register in the address translation management unit, and determine whether the invalid operation was executed successfully based on the value of the response register.
[0013] According to a third aspect of the present disclosure, a control unit is provided, including a memory and a processor, the memory being used to store computer instructions, and the processor being used to invoke the computer instructions from the memory to perform the method described in the second aspect.
[0014] According to a fourth aspect of the present disclosure, a computer-readable storage medium is provided having a computer program stored thereon, the computer program implementing the method described in the second aspect when executed by a processor.
[0015] According to a fifth aspect of the present disclosure, a computer program product is provided, the computer program product including a computer program that, when executed by a processor, implements the method described in the second aspect.
[0016] Based on the memory management method provided in this disclosure, an address translation management unit is introduced into the memory management system. The control unit only needs to perform a request register operation on the address translation management unit once to trigger invalid operations of multiple system memory management units. Furthermore, the invalid operation status can be confirmed by reading the response register. Compared with configuring and querying each system memory management unit one by one, this disclosure simplifies the operation of the control unit, simplifies the software control flow, and improves the efficiency of invalid operations in scenarios with multiple system memory management units.
[0017] Other features and advantages of this disclosure will become clear from the following detailed description of exemplary embodiments with reference to the accompanying drawings. Attached Figure Description
[0018] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments of the present disclosure and, together with the description, serve to explain the principles of the disclosure.
[0019] Figure 1 This is a schematic diagram of the structure of a memory management system provided in an embodiment of this disclosure.
[0020] Figure 2 This is a schematic diagram of another memory management system provided in an embodiment of this disclosure.
[0021] Figure 3 This is a schematic diagram of another memory management system provided in an embodiment of this disclosure.
[0022] Figure 4 This is a flowchart illustrating a memory management method provided in an embodiment of this disclosure.
[0023] Figure 5 This is a schematic diagram of the structure of a control unit provided in an embodiment of this disclosure. Detailed Implementation
[0024] Various exemplary embodiments of this disclosure will now be described in detail with reference to the accompanying drawings.
[0025] The following description of at least one exemplary embodiment is merely illustrative and is not intended to limit this disclosure or its application or use. Techniques, methods, and apparatus known to those skilled in the art may not be discussed in detail, but where appropriate, such techniques, methods, and apparatus may be considered part of the specification.
[0026] It should be noted that similar labels and letters in the following figures indicate similar items, so once an item is defined in one figure, it need not be discussed further in subsequent figures.
[0027] In related technologies, in order to improve the address translation performance between virtual addresses and physical addresses, a system-on-chip (SoC) can integrate multiple system memory management units to realize the translation of virtual addresses to physical addresses. Different system memory management units can be allocated to different intellectual property cores (IP cores). For example, each system memory management unit can be allocated to a corresponding intellectual property core for individual use, or it can be allocated to multiple intellectual property cores for shared use.
[0028] When the translation rules between virtual and physical addresses change, the control unit (e.g., the CPU) can control the system memory management unit to invalidate the memory address translation cache, invalidating all translation entries in the cache. For example, the invalidation operation can be performed by the control unit's software. When performing this operation, the software on the control unit can configure each system memory management unit sequentially, then read the internal state of each system memory management unit sequentially, completing the invalidation operation for all system memory management units. In this approach, the software needs to perform configuration and read operations separately for each system memory management unit, resulting in cumbersome software operations, low execution efficiency, and increased CPU processing burden. Therefore, simplifying the operation process and improving the efficiency of invalidation operations for multiple system memory management units has become an urgent problem to be solved.
[0029] To address the problems in related technologies, embodiments of this disclosure provide a method such as... Figure 1 The memory management system shown. Figure 1 As shown, the memory management system 10 may include a control unit 11, an address translation management unit 12, and multiple memory management units 13. The multiple memory management units 13 may include, for example: Figure 1 The memory management unit 0, memory management unit 1, memory management unit 2, and memory management unit 3 are shown. This control unit can be a central processing unit (CPU) or a host CPU.
[0030] The address translation management unit 12 can be connected to the control unit 11 and multiple system memory management units 13, respectively. Exemplarily, the address translation management unit 12 can be directly connected to the control unit 11, or it can be connected to the control unit 11 via a bus. Exemplarily, the address translation management unit 12 and the memory management units 13 can be at least some components of the system-on-a-chip 19.
[0031] The system memory management unit 13 may include a memory address translation cache for performing virtual address and physical address translation. For example, this memory address translation cache may be a translation back buffer (TLB) for caching translation entries from virtual addresses to physical addresses.
[0032] The address translation management unit 12 may include a target register, which can be written to and / or read by the control unit. For example, the target register may include a request register 121 and / or a response register 122. The request register 121 can be configured by the control unit to trigger invalidation operations in the memory address translation caches of multiple system memory management units according to the control unit's configuration. The response register 122 can be read by the control unit to determine whether the invalidation operations of the multiple system memory management units were successfully executed. Exemplarily, the invalidation operation of the system memory management unit may include marking all translation entries in the memory address translation cache as invalid or directly clearing the contents of the memory address translation cache.
[0033] The control unit can be used to configure the request register in the address translation management unit to a first preset value when invalidation operations are required on the memory address translation caches in multiple system memory management units. For example, the first preset value can be any pre-set value. The request register can include one or more bits. If the request register is a single bit, the first preset value can be 1, meaning the request register can be configured to 1; if the request register includes multiple bits (e.g., four bits), a specific bitmask value (e.g., binary values 0001, 0101, or 1111) can be written. The control unit 11 can write the first preset value to the request register 121 through a target interface (e.g., PCIe bus, AXI bus, etc.). This write operation can employ a standard register access protocol to improve configuration accuracy and real-time performance.
[0034] In some examples, the address translation management unit 12 can be used to control multiple system memory management units 13 to invalidate the memory address translation cache when the request register 121 is configured to a first preset value.
[0035] Furthermore, the address translation management unit 12 can also be used to configure the response register 122 to a second preset value when it is determined that an invalid operation was successfully executed. For example, the second preset value can be any pre-set value. The response register can include one or more bits. If the response register is a single bit, the first preset value can be 1, that is, the response register can be configured to 1; if the response register includes multiple bits (such as four bits), a specific bitmask value (such as binary values 0001, 0101, or 1111) can be written to it.
[0036] The control unit 11 can also be used to read the response register 122 and determine whether the invalidation operation was successfully executed based on the value of the response register 122. For example, the control unit 11 can read the current value of the response register 122 through the target interface. If the current value of the response register 122 is a second preset value (e.g., a bit value of 1), it can be determined that the invalidation operation was successfully executed, meaning that all invalidation operations of the system memory management units have been successfully completed. Further, the control unit 11 can continue to execute subsequent operations, such as updating page tables, resuming task execution, or starting a new virtual address mapping. Conversely, if the current value of the response register 122 is not the second preset value, it indicates that the invalidation operation has not yet been completed, and the control unit 11 can continue to wait or execute other tasks, reading the response register 122 again after a certain interval to confirm. In some examples, the control unit 11 can use a polling method to periodically read the response register 122. The polling period can be configured according to system performance requirements, for example, set to 10 microseconds, 50 microseconds, or 100 microseconds. In other examples, the address translation management unit 12 can send an interrupt signal to the control unit 11 when the response register 122 is configured to a second preset value, so that the control unit 11 can respond in a timely manner to the completion of invalid operations, thereby further improving the real-time performance of the system.
[0037] By adopting the above technical solution, an address translation management unit is introduced into the memory management system. The control unit only needs to perform a request register operation on the address translation management unit once to trigger invalid operations of multiple system memory management units. Furthermore, the status confirmation of invalid operations can be completed by reading the response register. Compared with configuring and querying each system memory management unit one by one, the embodiments of this disclosure can simplify the operation of the control unit, simplify the control flow of the software, and improve the efficiency of invalid operations in scenarios with multiple system memory management units.
[0038] In some embodiments of this disclosure, the address translation management unit 12 may control multiple system memory management units 13 to perform invalidation operations on the memory address translation cache when the request register 121 is configured to a first preset value.
[0039] For example, when the request register is configured to a first preset value, the address translation management unit can send an invalid request instruction to multiple system memory management units, and control the multiple system memory management units 13 to perform invalid operations on the memory address translation cache through the invalid request instruction.
[0040] For example, when the request register is configured to a first preset value, the address translation management unit can output an invalid request signal to multiple system memory management units; the system memory management unit can respond to the invalid request signal and perform an invalid operation on the memory address translation cache.
[0041] For example, when the control unit 11 writes a specific value (such as configuring a bit to 1) to the request register 121 through the target interface, the address translation management unit 12 can detect the configuration change and automatically generate an invalid request signal. This invalid request signal can be a level signal or a pulse signal, used to notify all or some system memory management units to begin invalidating the memory address translation cache. Upon receiving the invalid request signal, the system memory management unit can mark all or some translation entries in its memory address translation cache as invalid, or directly clear the contents of the memory address translation cache, so that the virtual address to physical address mapping can be re-established based on the updated page table.
[0042] In this way, the control unit can trigger multiple system memory management units to perform invalid operations in parallel by configuring a single request register, which significantly simplifies the software control process.
[0043] In some examples, the address translation management unit can output invalid request signals to the system memory management unit through multiple trigger signal lines, with each trigger signal line corresponding to a system memory management unit.
[0044] For example, the address translation management unit 12 may include the same number of trigger signal line output ports as the system memory management units. For instance, when there are four system memory management units (system memory management units 0 to 3) in the system, the address translation management unit 12 may include four independent trigger signal lines, each connected to the invalid request input port of one of the four system memory management units. Figure 1 As shown, the trigger signal line tlb_inv0 corresponds to system memory management unit 0, the trigger signal line tlb_inv1 corresponds to system memory management unit 1, the trigger signal line tlb_inv2 corresponds to system memory management unit 2, and the trigger signal line tlb_inv3 corresponds to system memory management unit 3.
[0045] When the request register 121 is configured to a first preset value, the address translation management unit 12 can send invalid request signals to each system memory management unit 13 simultaneously or in a predetermined order via these trigger signal lines. For example, after detecting a change in a specific bit of the request register 121, the address translation management unit 12 can pull all trigger signal lines from low to high, or send a pulse signal, thereby notifying all system memory management units 13 to initiate an invalidation operation. This one-to-one signal line connection method ensures that each system memory management unit 13 can independently and accurately receive the invalid request signal, avoiding interference or delay during signal transmission.
[0046] It should be noted that the address translation management unit 12 may also have only one trigger signal line output port, and multiple trigger signal lines may be connected based on the same trigger signal line output port.
[0047] In some examples, the request register may include a request bit, which can be used to control the signals output by multiple trigger signal lines.
[0048] For example, the request register 121 can be a single-bit register. When this bit is set to 1, the address translation management unit 12 can simultaneously pull up the level of all trigger signal lines, thereby broadcasting an invalid request signal to all system memory management units 13. This implementation has a simple hardware structure and is suitable for scenarios that require unified invalidation operations on all system memory management units. Using this method, centralized control of multiple system memory management units can be achieved with minimal hardware resources, and the overall operation time can be significantly shortened.
[0049] In other examples, the request register may include multiple request bits, each of which can be used to control a signal output from a trigger signal line.
[0050] For example, when there are four system memory management units (MMUs) in the system, request register 121 can be a 4-bit register, where bit 0 controls the trigger signal line connected to system memory management unit 0, bit 1 controls the trigger signal line connected to system memory management unit 1, and so on. Software can selectively trigger invalidation operations on some system memory management units by writing different bitmask values to request register 121. For instance, if the software only needs to perform invalidation operations on system memory management units 0 and 2, request register 121 can be configured with the binary value 0101, thereby pulling only the corresponding two trigger signal lines high. In this way, more flexible and finer-grained invalidation operation control can be achieved to meet the needs of different application scenarios.
[0051] In some embodiments of this disclosure, the address translation management unit 12 may configure the response register 122 to a second preset value when it is determined that an invalid operation was successfully executed.
[0052] For example, if an invalid operation is successfully executed, the system memory management unit can send an invalid response message to the address translation management unit, which will then configure the response register 122 to a second preset value based on the invalid response message.
[0053] For example, the system memory management unit can output an invalid response signal to the address translation management unit if an invalid operation is successfully executed. The address translation management unit can configure its response register to a second preset value when it receives invalid response signals from multiple system memory management units. This invalid response signal can be a level signal or a pulse signal, used to notify the address translation management unit that a particular system memory management unit has successfully executed an invalid operation on the memory address translation cache.
[0054] For example, when a system memory management unit completes the invalidation operation of its memory address translation cache, it can pull the level of its output invalidation response signal line from low to high, or send a pulse signal, to notify the address translation management unit that the invalidation operation of the system memory management unit has been completed. The address translation management unit 12 can continuously monitor the status of the invalidation response signals of each system memory management unit. When it detects that all system memory management units involved in the invalidation operation have pulled their invalidation response signals high, the address translation management unit 12 can configure the response register to a second preset value (e.g., configure a specific bit to 1), indicating that the global invalidation operation has been completed. For example, the address translation management unit 12 can use logic operation circuits (such as logic AND gates) to summarize multiple invalidation response signals. When all signals are high, it automatically configures the response register 122 to the second preset value. As another example, the address translation management unit 12 can use a bit mapping method to map the invalidation response signals of each system memory management unit to different bits of the response register 122, so that the control unit (such as software running on the control unit) can accurately query the completion status of each system memory management unit.
[0055] In this way, the control unit 11 can quickly determine whether all invalid operations of all system memory management units have been completed by reading the value of the response register 122, without having to query the internal state of each system memory management unit individually. This significantly reduces the polling overhead of the software in the control unit and improves the system's response efficiency.
[0056] In some examples, each system memory management unit 13 may correspond to a response signal line, through which the system memory management unit 13 can output an invalid response signal to the address translation management unit 12. For example, system memory management unit 0 can be connected to a specific input port of address translation management unit 12 via a dedicated response signal line tlb_inv_sta0, system memory management unit 1 can be connected to another input port of address translation management unit 12 via another independent response signal line tlb_inv_sta1, system memory management unit 2 can be connected to another input port of address translation management unit 12 via another independent response signal line tlb_inv_sta2, system memory management unit 3 can be connected to another input port of address translation management unit 12 via another independent response signal line tlb_inv_sta3, and so on.
[0057] Each response signal line can independently transmit the invalidation operation completion status of the corresponding system memory management unit without interference. For example, the response signal line can use a single-bit level signal, initially low, and pulled high when the corresponding system memory management unit completes the invalidation operation. The address translation management unit 12 can monitor the level status of these response signal lines to keep track of the invalidation operation progress of each system memory management unit in real time. This one-to-one response signal line connection method ensures the accuracy and real-time nature of status feedback, avoiding status confusion or delays caused by signal sharing.
[0058] Figure 2 This is a schematic diagram of another memory management system provided in an embodiment of this disclosure. Figure 2 As shown, the memory management system may also include software 15 and operating system 16, which may run on control unit 11. For example, software 15 may be an application or driver, and operating system 16 may be used to manage system resources and schedule tasks.
[0059] In some examples, the control unit 11 and the system-on-a-chip 19 can be connected via a target interface, which can be a Peripheral Component Interconnect Express (PCIe) interface or other types of interfaces. The system-on-a-chip may also include an on-chip bus, which can be used to enable communication between different units of the on-chip system. The various units of the on-chip system can be connected to the control unit via the on-chip bus and the interface.
[0060] In some examples, the system-on-a-chip 19 may include multiple intellectual property cores (e.g., graphics processors, neural network accelerators, etc.), which may include, for example... Figure 2 The diagram shows intellectual property cores 0, 1, 2, and 3. Each intellectual property core can correspond to a system memory management unit (SMU), which is used to translate virtual addresses to physical addresses. It should be noted that multiple intellectual property cores can also correspond to the same SMU for the same virtual address to physical address translation.
[0061] Each intellectual property core 14 and system memory management unit 13 can be interconnected via the on-chip bus to jointly access system memory. When the software 15 or operating system 16 needs to modify the page table or switch processes, it can initiate an invalid operation request to the address translation management unit 12 through the control unit 11. The address translation management unit 12 can send invalid request signals to each system memory management unit 13 through multiple trigger signal lines (such as tlb_inv0 to tlb_inv3). Each system memory management unit 13 can execute the invalid operation in parallel and report the completion status to the address translation management unit 12 through the corresponding response signal lines (such as tlb_inv_sta0 to tlb_inv_sta3). The address translation management unit 12 can write the summarized status information into the response register 122 for the control unit 11 to read. In this way, efficient and unified management of multiple system memory management units can be achieved in a complex on-chip system, meeting the needs of high-performance computing and multi-task parallel processing.
[0062] Figure 3 This is a schematic diagram of another memory management system provided in an embodiment of this disclosure. For example... Figure 3 As shown, the address translation management unit 12 in the memory management system may also include a logic operation circuit 123, which can perform a logical AND operation on invalid response signals received from multiple system memory management units 13, and configure the value of the response register 122 based on the operation result.
[0063] For example, the logic operation circuit 123 can be a multi-input AND gate circuit, whose input is connected to the invalid response signal line of all system memory management units, and whose output is connected to a specific bit of the response register 122.
[0064] When all invalid response signals of the system memory management units are high (indicating that their invalidation operations have been completed), the output of the AND gate can be high, thus configuring the corresponding bit of the response register 122 to 1. If the invalid response signal of any system memory management unit is still low (indicating that the invalidation operation of that unit has not yet been completed), the output of the AND gate can remain low, and the corresponding bit of the response register 122 can remain 0. For example, assuming there are 4 system memory management units in the system, the logic operation circuit 123 can use these 4 invalid response signal lines as inputs. Only when all 4 signal lines are high will the output be high. At this time, the response register 122 can be configured to a second preset value (such as a certain bit being 1), indicating that the global invalidation operation has been completed.
[0065] This logic circuit automatically aggregates and judges the status signals of multiple system memory management units at the hardware level, eliminating the need for software to read and compare the status of each memory management unit individually. This further simplifies the software logic and reduces the CPU's processing burden. This enables a more efficient and real-time status feedback mechanism, improving the overall system performance.
[0066] Figure 4 This is a flowchart illustrating a memory management method provided in an embodiment of this disclosure. This memory management method can be... Figures 1 to 3 The control unit in the memory management system shown executes the operation. This memory management system may include a control unit, an address translation management unit, and multiple system memory management units. The address translation management unit may be connected to the control unit and the multiple system memory management units, and may include a request register and a response register. For example... Figure 4 As shown, the memory management method of this embodiment may include the following steps S410 to S420.
[0067] Step S410: When it is necessary to perform invalidation operations on the memory address translation caches in multiple system memory management units, configure the request register in the address translation management unit to a first preset value.
[0068] For example, when the control unit detects a page table update event, a process switch event, or other scenario requiring a refresh of the memory address translation cache, it can write a first preset value to the request register of the address translation management unit via the target interface. This first preset value can be a specific combination of bits used to instruct the address translation management unit to initiate an invalidation process. For instance, if the request register is a single-bit register, the control unit can configure it to 1; if the request register is a multi-bit register, the control unit can write the corresponding bitmask value according to the range of system memory management units that need to be invalidated.
[0069] By configuring the request register in the address translation management unit to a first preset value, the address translation management unit can control multiple system memory management units to perform invalidation operations on the memory address translation cache, and, if it is determined that the invalidation operation was successfully executed, configure the response register to a second preset value.
[0070] For example, when the request register is configured to a first preset value, the address translation management unit (ATM) can automatically control multiple system memory management units (MMUs) to perform invalidation operations on the memory address translation cache. The ATM can send invalidation request signals to each MMU via a trigger signal line. Each MMU can respond to the signal and execute the invalidation operation of its respective memory address translation cache in parallel. After all participating MMUs have completed their invalidation operations, the ATM can configure the response register to a second preset value if the invalidation operation was successful. For instance, the ATM can perform a logical AND operation on the invalidation response signals of each MMU using logic operation circuitry. When the result is true, it configures a specific bit in the response register to 1.
[0071] Step S420: Read the response register in the address translation management unit and determine whether the invalid operation was successfully executed based on the value of the response register.
[0072] For example, the control unit can determine whether all or a specified system memory management unit has completed an invalid operation by reading the value in the response register.
[0073] Using the above method, the control unit does not need to interact with each system memory management unit separately, reducing software operation steps and improving the efficiency of executing invalid operations.
[0074] This disclosure also provides a control unit, such as... Figure 5As shown, the control unit 11 may include a memory 1110 and a processor 1120. The memory can be used to store computer instructions, and the processor can be used to retrieve computer instructions from the memory to execute all or part of the steps of any of the methods in the foregoing embodiments of this disclosure. The processor may be one or more, and these processors may execute instructions individually or jointly. Similarly, the memory may be one or more, and these memories may store the aforementioned computer instructions individually or jointly. The control unit may be a CPU, or a chip in the form of an Application Specific Integrated Circuit (ASIC), System on Chip (SOC), Field Programmable Gate Array (FPGA), Programmable Logic Array (PLA), etc., which is not limited in this embodiment.
[0075] This disclosure also provides a computer-readable storage medium storing a computer program thereon, which, when executed by a processor, implements all or part of the steps of any of the methods in the foregoing embodiments of this disclosure. Optionally, the computer-readable storage medium may be a non-transitory storage medium, but is not limited thereto, and may also be a temporary storage medium.
[0076] This disclosure also provides a computer program product that may include a computer program that, when executed by a processor, can implement all or part of the steps of any of the methods in the foregoing embodiments of this disclosure.
[0077] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. The same or similar parts between the various embodiments can be referred to each other.
[0078] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and apparatuses according to various embodiments of the present disclosure. In this regard, each block in a flowchart or block diagram may represent a module, unit, or part of a circuit. In some alternative implementations, the functions marked in the blocks may occur in a different order than those marked in the drawings. For example, two consecutive blocks may actually be executed substantially in parallel, or they may sometimes be executed in reverse order, depending on the functions involved. It should be noted that embodiments of the present disclosure may include some or all of the functions marked in the multiple blocks in the drawings, and may also include other functions not shown in the blocks in the drawings. It should also be noted that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, may be implemented in hardware that performs the specified function or action, or in a combination of dedicated hardware and computer instructions. Unless otherwise specified, implementation in hardware, implementation in software, and implementation in a combination of software and hardware may be equivalent.
[0079] The various embodiments of this disclosure have been described above. These descriptions are exemplary and not exhaustive, and are not limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used herein is chosen to best explain the principles, practical application, or improvement of the technology in the market, or to enable others skilled in the art to understand the embodiments disclosed herein. The scope of this disclosure is defined by the appended claims.
Claims
1. A memory management system, characterized in that, The memory management system includes a control unit, an address translation management unit, and multiple system memory management units. The address translation management unit is connected to the control unit and the multiple system memory management units, and includes a request register and a response register. Each system memory management unit includes a memory address translation cache for performing virtual address and physical address translation. The control unit is configured to set the request register in the address translation management unit to a first preset value when it is necessary to perform an invalid operation on the memory address translation cache in the multiple system memory management units; The address translation management unit is configured to control multiple system memory management units to perform invalidation operations on the memory address translation cache when the request register is configured to a first preset value; and to configure the response register to a second preset value when it is determined that the invalidation operation was successfully executed. The control unit is also configured to read the response register and determine whether the invalid operation was successfully executed based on the value of the response register.
2. The memory management system according to claim 1, characterized in that, The address translation management unit is specifically used to output an invalid request signal to a plurality of system memory management units when the request register is configured to a first preset value. The system memory management unit is used to invalidate the memory address translation cache in response to the invalid request signal.
3. The memory management system according to claim 2, characterized in that, The address translation management unit outputs an invalid request signal to the system memory management unit through multiple trigger signal lines, with each trigger signal line corresponding to one system memory management unit.
4. The memory management system according to claim 3, characterized in that, The request register includes a request bit, which is used to control the signals output by the plurality of trigger signal lines; or... The request register includes a plurality of request bits, each of which is used to control a signal output by one of the trigger signal lines.
5. The memory management system according to any one of claims 1 to 4, characterized in that, The system memory management unit is configured to output an invalid response signal to the address translation management unit if the invalid operation is successfully executed. The address translation management unit is specifically configured to set the response register to the second preset value when it receives invalid response signals output by multiple system memory management units.
6. The memory management system according to claim 5, characterized in that, The address translation management unit further includes a logic operation circuit, which performs a logical AND operation on invalid response signals received from multiple system memory management units, and configures the value of the response register based on the operation result.
7. The memory management system according to claim 5, characterized in that, Each of the system memory management units corresponds to a response signal line, and the system memory management unit outputs the invalid response signal to the address translation management unit through the response signal line.
8. A memory management method, characterized in that, A control unit applied in a memory management system, the memory management system including the control unit, an address translation management unit, and multiple system memory management units, the address translation management unit being connected to the control unit and the multiple system memory management units respectively, the address translation management unit including a request register and a response register; the method includes: When it is necessary to invalidate the memory address translation cache in multiple system memory management units, the request register in the address translation management unit is configured to a first preset value, so that the address translation management unit controls multiple system memory management units to invalidate the memory address translation cache; and when it is determined that the invalidation operation is successfully executed, the response register is configured to a second preset value. Read the response register in the address translation management unit, and determine whether the invalid operation was executed successfully based on the value of the response register.
9. A control unit, characterized in that, The method includes a memory and a processor, the memory being used to store computer instructions, and the processor being used to retrieve the computer instructions from the memory to execute the method of claim 8.
10. A computer-readable storage medium, characterized in that, It stores a computer program that, when executed by a processor, implements the method of claim 8.
11. A computer program product, characterized in that, It includes a computer program that, when executed by a processor, implements the method of claim 8.