An in-situ preparation method of a one-dimensional nano array electrode integrated on a chip

Abstract

The present application belongs to the technical field of micro-nano material preparation and micro energy storage device, and discloses an in-situ preparation method of a one-dimensional nano array electrode integrated on a chip, comprising the following steps: in-situ construction of a patterned template on a chip; in-situ electrochemical growth of a one-dimensional nano array; in-situ conversion of a metal / metal oxide composite structure; and forming of an integrated electrode. The present application directly constructs a patterned anodic aluminum oxide template on a chip substrate pre-prepared with a patterned conductive layer (non-aluminum material) and completes material growth, so that the obtained nano array electrode and the current collector on the chip are in-situ grown and integrally formed. The cycle stability of the electrode of the present application is significantly better than that of a transfer method electrode and an aluminum substrate method transfer electrode.

Description

Technical Field

[0001] This invention relates to the field of micro / nano material fabrication and micro energy storage device technology, and particularly to an in-situ fabrication method for on-chip integrated one-dimensional nanoarray electrodes, on-chip integrated metal / metal oxide composite one-dimensional nanoarray electrodes, and on-chip integrated micro supercapacitors. Background Technology

[0002] With the rapid development of the Internet of Things, micro-sensing nodes, implantable medical devices, and portable electronic products, the demand for miniaturized, integrated, and high-performance energy storage units is becoming increasingly urgent. Micro supercapacitors are considered one of the most promising on-chip integrated micro energy solutions due to their high power density, long cycle life, and fast charge / discharge characteristics. Their performance is highly dependent on the structure and properties of the electrode materials. Among them, one-dimensional nano-ordered array materials (such as nanowire and nanotube arrays) with high specific surface area and efficient ion / electron transport paths have attracted much attention.

[0003] Currently, the fabrication of electrodes for on-chip integrated micro supercapacitors mainly faces the following technical bottlenecks: (a) Limitations of traditional slurry coating processes Traditional electrode fabrication uses a slurry coating process, where the active material and the current collector are only in physical contact. This results in high interfacial resistance and makes it difficult to achieve precise patterning and high loading at the micrometer scale, which limits device miniaturization and performance improvement. Although combining photolithography with thin film deposition can achieve patterning of interdigitated electrodes, the active material still needs to be deposited or coated subsequently, making it impossible to achieve integrated molding.

[0004] (II) Preparation method of nanoarray based on anodic aluminum oxide template The anodic aluminum oxide (AAO) template method has attracted widespread attention due to its ability to prepare highly ordered one-dimensional nanoarrays. In the existing technology, there are already schemes for preparing specific patterned arrays using patterned aluminum substrates. For example, Shao Zengjun's master's thesis "Preparation and Application of Patterned AAO Template by Constant Current Method" in 2009 at Qingdao University clearly disclosed that: a patterned AAO template is prepared on a pre-patterned aluminum sheet by combining photolithography and constant current oxidation method, and then a patterned metal nanowire array is obtained by electrodeposition.

[0005] However, this approach and similar technologies have fundamental limitations: First, the entire process substrate and current collector are made of aluminum itself, and the obtained nanostructure array is attached to the aluminum substrate, making it difficult to peel off and transfer; Second, aluminum is not a commonly used interconnect material in standard semiconductor processes, and its own oxide layer is insulating, and this method cannot achieve direct electrical connection and in-situ integration with patterned conductive lines such as gold and platinum prefabricated on chip substrates such as silicon and glass; the incompatibility of the process makes it impossible to use it to prepare high-performance microelectrodes integrated with microelectronic systems.

[0006] (III) The complexity of the AAO template transfer method To address these issues, researchers have attempted to transfer AAO templates onto silicon substrates. Scisco et al. reported a method for bonding thick AAO templates (up to 90 μm) to silicon wafers via Al-Si eutectic bonding, and used this method to fabricate carbon nanotube electrodes. The process flow of this method includes: first, preparing an AAO template on an aluminum wafer; then, transferring the AAO template to the silicon wafer via eutectic bonding; and finally, removing the residual aluminum layer. Although this method achieves the bonding between the AAO template and the silicon substrate, it still has the following drawbacks: the bonding process requires high temperature and high pressure conditions, resulting in a narrow process window; additional steps are needed after template transfer to remove residual aluminum and the barrier layer; and the electrical contact between the active material and the current collector depends on the bonding interface rather than in-situ growth, making it difficult to optimize the interface resistance.

[0007] Other studies have employed a template transfer combined with vacuum deposition, for example, by chemically etching away residual aluminum under the AAO template, using vacuum-deposited gold as a bonding layer to attach the AAO template to the substrate, and then removing the barrier layer by ion etching. Such methods involve multi-step transfer and etching processes, which are cumbersome, and the brittle AAO template is easily broken during the transfer process, resulting in low yield and difficulty in large-scale production.

[0008] (iv) Direct deposition method of AAO template and silicon substrate Depositing aluminum films directly on silicon wafers and then anodizing them is another technical approach. Rabin et al. reported a study on depositing a 12 μm aluminum film on silicon wafers and obtaining an approximately 17 μm AAO template through anodizing. However, this method suffers from problems such as poor film thickness uniformity and easy delamination. This method is limited by the vacuum deposition rate, making it difficult to obtain thick film templates. Furthermore, the difference in thermal expansion coefficients between the aluminum film and the silicon substrate leads to high interfacial stress and insufficient device reliability.

[0009] (v) None of the existing technologies have achieved in-situ integrated integration. Existing research has also attempted to deposit other active materials in AAO templates to achieve on-chip energy storage; for example, CN110415988A discloses a method for preparing graphene oxide / yttrium cobalt oxide nanoarray electrode materials, in which graphene oxide quantum dots are deposited in the channels of an AAO template by electrochemical deposition, followed by vacuum spin coating of yttrium cobalt oxide sol precursor, and calcination to obtain a coaxial heterostructure nanoarray; however, this method still requires the transfer of the AAO template or direct preparation on an aluminum substrate, and the electrical contact between the active material and the current collector depends on the subsequent electrode preparation steps after template removal, thus failing to achieve true in-situ integrated integration.

[0010] Besides the AAO template method, researchers have also explored other on-chip integration technologies. For example, the patent CN101950685A published by Tsinghua University uses MEMS technology to prepare SU-8 glue columnar arrays on the surface of a copper substrate, and then covers them with polypyrrole functional films to form three-dimensional microelectrodes. Although this method can improve the specific surface area, the size and morphology control of the columnar array is limited, and the cycling stability of polypyrrole materials is poor. Recent studies have also reported 3D interdigitated microelectrodes based on additive manufacturing and pyrolytic carbonization technology, which can achieve a high specific capacitance of 125 mF / cm². However, it relies on complex 3D printing processes, and the pyrolytic carbonization process requires a high-temperature inert atmosphere, resulting in high process costs.

[0011] (vi) Technological gaps that urgently need to be addressed in the existing technology In summary, existing technologies have not yet solved the following key problems: how to fabricate one-dimensional ordered nanoarray electrodes with high specific surface area and good interfacial bonding in situ on a non-aluminum patterned conductive current collector prefabricated on a chip through a fully compatible micro-nano fabrication process, so as to achieve the integrated integration of active materials and current collectors, thereby avoiding complex template transfer, secondary alignment and material bonding steps; this technological gap has become the core bottleneck restricting the practical application of on-chip micro supercapacitors. Summary of the Invention

[0012] The purpose of this invention is to provide an in-situ fabrication method for on-chip integrated one-dimensional nanoarray electrodes, on-chip integrated metal / metal oxide composite one-dimensional nanoarray electrodes, and on-chip integrated micro supercapacitors, so as to solve the problems mentioned in the background art.

[0013] To solve the above-mentioned technical problems, the technical solution adopted by the present invention is: an in-situ fabrication method for on-chip integrated one-dimensional nanoarray electrodes, comprising the following steps: Step S1: In-situ construction of on-chip graphical template: A chip substrate is provided, on which a patterned conductive layer is formed; A metallic aluminum film is deposited on the patterned conductive layer, and the metallic aluminum film is patterned to form an aluminum structure corresponding to the pattern of the patterned conductive layer. The aluminum structure is anodized to transform it into a patterned anodized aluminum template, wherein the bottom of the anodized aluminum template is in direct contact with the patterned conductive layer. The anodized aluminum template is subjected to a hole-enlarging treatment; Step S2, in-situ electrochemical growth of one-dimensional nanoarrays: Using the patterned conductive layer as the working electrode, a one-dimensional metal nano-ordered array is grown in the nanopores of the anodic aluminum oxide template by pulse electrodeposition, wherein a porous or branched secondary structure is formed in situ on the sidewalls or inside of the one-dimensional metal nano-ordered array. Step S3: In-situ transformation of the metal / metal oxide composite structure: The metal one-dimensional nano-ordered array is oxidized to form a metal oxide layer in situ on the metal surface, resulting in a metal / metal oxide composite one-dimensional nano-ordered array. Step S4: Molding of the integrated electrode: The anodic aluminum oxide template is removed, exposing the metal / metal oxide composite one-dimensional nano-ordered array and maintaining direct bonding with the patterned conductive layer to form an on-chip integrated electrode.

[0014] Preferably, the chip substrate is a silicon wafer, a glass wafer, or a polymer wafer, and the material of the patterned conductive layer is gold, platinum, titanium, chromium, copper, or a combination thereof.

[0015] Preferably, in step S2, the on-time Ton of the pulse electrodeposition method is 0.05-0.5s, and the off-time Toff is 0.1-1.0s.

[0016] Preferably, in step S3, the oxidation treatment is one of thermal oxidation, electrochemical oxidation, or oxygen plasma treatment.

[0017] Preferably, the metal is at least one of nickel, iron, cobalt, and manganese, or an alloy containing at least two of the above metals; the metal oxide is an oxide or composite oxide of the corresponding nickel, iron, cobalt, and manganese.

[0018] Preferably, in step S1, the voltage of the anodizing is 20-60V, the temperature is 0-10℃, and the electrolyte is oxalic acid or phosphoric acid solution; the pore-expanding treatment uses phosphoric acid solution, and the pore-expanding treatment time is 5-20min.

[0019] The present invention also provides an on-chip integrated metal / metal oxide composite one-dimensional nanoarray electrode, the structure of which includes: Chip substrate; A patterned conductive layer is formed on the chip substrate, and the material of the patterned conductive layer is a non-aluminum conductive material; Furthermore, a one-dimensional nano-ordered array of metal / metal oxide composites is deposited directly on the patterned conductive layer using an in-situ pulsed electrodeposition method. The metal / metal oxide composite one-dimensional nano-ordered array is composed of a metal core and a metal oxide shell that covers the surface of the metal core in situ. Its sidewalls or interior have porous or branched secondary structures formed by dynamic hydrogen bubble template method. The metal / metal oxide composite one-dimensional nano-ordered array forms a metallurgical bond or ohmic contact with the patterned conductive layer, and has the same planar pattern as the patterned conductive layer.

[0020] Preferably, the morphology of the metal / metal oxide composite one-dimensional nano-ordered array is nanowire or nanotube; the thickness of the metal oxide shell is 2-20 nm.

[0021] The present invention further provides an on-chip integrated micro supercapacitor comprising a pair of on-chip integrated metal / metal oxide composite one-dimensional nanoarray electrodes, wherein the pair of electrodes are arranged in an interdigitated manner on the same plane and immersed in a solid or gel electrolyte.

[0022] As can be seen from the above description of the structure of the present invention, compared with the prior art, the present invention has the following advantages: 1. This invention directly constructs a patterned anodic aluminum oxide template on a chip substrate with a pre-prepared patterned conductive layer (non-aluminum material) and completes material growth. The resulting nanoarray electrodes and current collectors on the chip are grown in situ and integrally formed. This is different from the scheme of Shao Zengjun et al. to prepare AAO templates on patterned aluminum substrates (the product is attached to the aluminum substrate and cannot be integrated with silicon-based chips), and also different from the scheme of Scisco et al. to transfer AAO templates to silicon wafers using Al-Si eutectic bonding (involving multiple complex processes such as high-temperature bonding, template transfer, and residual aluminum removal). This invention completely avoids complex material transfer and secondary bonding steps, achieves perfect compatibility with planar microelectronics processes, and can be mass-produced on 4-inch and larger wafers.

[0023] 2. In this invention, the active material (metal / metal oxide composite array) is electrochemically grown directly from the current collector, with an ohmic contact or a strong metallurgical bond between the two. This differs from the physical contact interface of traditional slurry coating processes and the bonding interface of template transfer methods. The interface resistance formed by this invention is extremely low (less than 2.0 Ω·cm² in the examples), with high charge transport efficiency, and the mechanical stability and electrochemical reliability of the electrode are greatly improved. Comparative experiments show that the cycling stability of the electrode of this invention (retention rate >88% after 1000 cycles) is significantly better than that of the transfer method electrode (85%) and the aluminum substrate transfer electrode (72%).

[0024] 3. This invention combines macroscopic pattern control via patterned photolithography with the nano-confinence effect of anodic aluminum oxide templates and micro / nano-structure modification via dynamic hydrogen bubble templates, achieving controllable fabrication of multi-level structures from micrometers to nanometers. This method not only precisely controls the planar geometry of the electrode to adapt to different device layouts but also endows the active material with high specific surface area and abundant ion transport channels (such as porous structures, branched structures, and nanotube structures) at the nanoscale, thereby simultaneously improving the electrode's mass specific capacitance, areal specific capacitance, and power density. In the embodiments, The areal capacitance of the composite nanowire array reaches 55 mF / cm², and the interfacial resistance of the Ni / NiO porous nanowire array is less than 2.0 Ω·cm².

[0025] 4. This invention allows for flexible control of the size, composition, crystal phase, shell thickness, and morphology and porosity of the composite nanoarray by adjusting the parameters of the anodic alumina template (pore size, depth), pulse electrodeposition conditions (Ton / Toff ratio, potential, time), and oxidation process (temperature, time, potential). It is applicable to various transition metals and their oxide systems, including nickel, iron, cobalt, and manganese. Unlike the coaxial heterostructure of graphene oxide / yttrium cobalt oxide disclosed in CN110415988A (which requires multiple steps such as spin coating and calcination), this invention employs a process route combining all-electrochemical and thermal oxidation. The process is simple, parameters are controllable, and reproducibility is good, providing a universal platform for customizing high-performance electrodes for on-chip micro-energy storage devices with different needs.

[0026] 5. The substrate materials (silicon, glass, etc.), conductive layer materials (gold, platinum, chromium, etc.), and processing technologies (photolithography, sputtering, electrodeposition, thermal oxidation) used in this invention are all mature technologies in standard microelectronics manufacturing. The process temperature is low (≤400°C) and is highly compatible with standard CMOS back-end processes. This lays the technological foundation for the synergistic integration of on-chip micro supercapacitors with sensing, computing, and communication circuit units, and has good prospects for industrial application. Attached Figure Description

[0027] The accompanying drawings, which form part of this application, are used to provide a further understanding of the invention. The illustrative embodiments of the invention and their descriptions are used to explain the invention and do not constitute an undue limitation of the invention. In the drawings: Figure 1 This is a process flow diagram of the present invention; Figure 2 This is a schematic diagram of the interdigitated electrode structure of the present invention; Figure 3 The image shows an electron microscope image of the prepared metal / metal oxide composite one-dimensional nano-ordered array, used to demonstrate its morphological characteristics. Detailed Implementation

[0028] To better understand the technical solution of the present invention, the technical solution of the present invention will be described in detail below with reference to the accompanying drawings and specific embodiments.

[0029] like Figure 1 , Figure 2 and Figure 3 As shown, an in-situ fabrication method for on-chip integrated one-dimensional nanoarray electrodes includes the following steps: Step 1: In-situ construction of on-chip graphical templates: A chip substrate is provided, on which a patterned conductive layer is formed. The material of the patterned conductive layer is a non-aluminum conductive material. The chip substrate is preferably a silicon wafer, a glass wafer, or a polymer wafer. The material of the patterned conductive layer is preferably gold, platinum, titanium, chromium, copper, or a combination thereof. A metallic aluminum film is deposited on a patterned conductive layer; specifically, a high-purity aluminum film can be deposited by electron beam evaporation or magnetron sputtering, with the deposition temperature controlled below 50°C to reduce thermal stress between the aluminum film and the substrate. The aluminum film is patterned to form an aluminum structure corresponding to the pattern of the patterned conductive layer. Specifically, photolithography and etching processes can be used to define a pattern on the aluminum film that completely overlaps with the pattern of the underlying conductive layer, and excess aluminum is removed by wet or dry etching. The aluminum structure is anodized to transform it into a patterned anodized aluminum template, with the bottom of the anodized aluminum template in direct contact with the patterned conductive layer. During the oxidation process, the aluminum areas not protected by photoresist are transformed into porous anodized aluminum, with its channels growing perpendicular to the substrate. The preferred process parameters for anodizing are: voltage 20-60V, temperature 0-10°C, and electrolyte being oxalic acid or phosphoric acid solution. The anodic aluminum oxide template is enlarged to reduce or eliminate the barrier layer between the bottom of the anodic aluminum oxide template and the patterned conductive layer. The enlargement process is preferably carried out with phosphoric acid solution, and the enlargement time is 5-20 minutes. This step is crucial to ensure uniform current conduction during the subsequent electrodeposition process and to achieve direct electrical contact between the active material and the current collector.

[0030] Step 2: In-situ electrochemical growth of one-dimensional nanoarrays: A one-dimensional ordered array of metal was grown in the nanopores of an anodic aluminum oxide template using a patterned conductive layer as the working electrode and a pulse electrodeposition method. Pulsed electrodeposition induces hydrogen evolution reaction by controlling pulse parameters, using dynamic hydrogen bubbles as soft templates to form porous or branched secondary structures in situ on the sidewalls or inside of a one-dimensional ordered metal nanoarray. The preferred pulse parameters are: on-time Ton of 0.05-0.5 seconds and off-time Toff of 0.1-1.0 seconds. The morphology and porosity of the secondary structure can be precisely controlled by adjusting the ratio of Ton to Toff. During the deposition process, metal ions are reduced at the bottom of the nanopores (on the patterned conductive layer) of the anodic aluminum oxide template and grow from bottom to top, filling the pores to form an array of nanowires or nanotubes. By adjusting the deposition time, pulse parameters and electroplating solution composition, the height, morphology and filling rate of the nanoarray can be precisely controlled. The metal is preferably nickel, iron, cobalt, manganese or their alloys.

[0031] Step 3: In-situ transformation of metal / metal oxide composite structures: Oxidation treatment was performed on a one-dimensional ordered nano-array of metal to form a metal oxide layer in situ on the metal surface, resulting in a metal / metal oxide composite one-dimensional ordered nano-array. Oxidation treatment can be one of thermal oxidation, electrochemical oxidation, or oxygen plasma treatment. By controlling the temperature, time, or potential of the oxidation treatment, the metal surface is uniformly and in situ transformed into a metal oxide layer with pseudocapacitive activity, forming a composite structure of metal core / metal oxide shell. The metal oxide is preferably an oxide or composite oxide of nickel, iron, cobalt, or manganese. During the oxidation treatment, the thickness (preferably 2-20 nm), crystal form, and interfacial bonding strength with the metal substrate of the metal oxide layer can be precisely controlled through process parameters.

[0032] Step 4: Molding of the integrated electrode: Selectively removing the anodic aluminum oxide template wrapped around the composite nanoarray exposes a metal / metal oxide composite one-dimensional nano-ordered array grown directly on the patterned conductive layer of the chip substrate, forming an on-chip integrated electrode. Template removal can be achieved by selectively dissolving the anodic aluminum oxide template with an alkaline solution (such as sodium hydroxide solution), while the metal / metal oxide composite nanoarray structure remains unaffected. After template removal, the active material and the patterned conductive layer maintain the metallurgical bond or ohmic contact formed in situ during growth, resulting in extremely low interfacial resistance. Furthermore, the active material completely replicates the preset planar pattern.

[0033] This invention also provides an on-chip integrated metal / metal oxide composite one-dimensional nanoarray electrode, comprising: a chip substrate; a patterned conductive layer formed on the chip substrate, the patterned conductive layer being made of a non-aluminum conductive material; and a metal / metal oxide composite one-dimensional ordered nanoarray directly grown on the patterned conductive layer by in-situ electrochemical deposition; the composite one-dimensional ordered nanoarray consists of a metal core and a metal oxide shell in-situ covering the surface of the metal core, and its sidewalls or interior have porous or branched secondary structures formed by a dynamic hydrogen bubble template method; the composite one-dimensional ordered nanoarray forms a metallurgical bond or ohmic contact with the patterned conductive layer, and has the same planar pattern as the patterned conductive layer; wherein the morphology of the metal / metal oxide composite one-dimensional ordered nanoarray is nanowire or nanotube, and the thickness of the metal oxide shell is 2-20 nm.

[0034] The present invention further provides an on-chip integrated micro supercapacitor comprising a pair of the above-mentioned on-chip integrated metal / metal oxide composite one-dimensional nanoarray electrodes, the pair of electrodes being arranged in an interdigitated manner on the same plane and immersed in a solid or gel electrolyte.

[0035] The following specific embodiments demonstrate the effectiveness of the method proposed in this invention.

[0036] Example 1: In-situ fabrication of on-chip integrated nickel / nickel oxide porous nanowire array electrodes: This embodiment demonstrates how to fabricate interdigitated nickel / nickel oxide composite porous nanowire array electrodes in situ on a silicon-based chip. This method fully follows the technical route of this invention: "in-situ construction of on-chip patterned templates - in-situ electrochemical growth of one-dimensional nanoarrays - in-situ conversion of metal / metal oxide composite structures - integrated electrode forming".

[0037] Step 1: In-situ construction of on-chip graphical templates: 1) Select a 4-inch silicon wafer with a silicon dioxide insulating layer (approximately 300nm thick) thermally oxidized on the surface as the substrate; 2) Using magnetron sputtering equipment, a 10nm thick chromium adhesion layer and a 100nm thick gold layer are deposited sequentially on the silicon wafer. The chromium layer is used to enhance the adhesion between the gold layer and the silicon substrate, and the gold layer, as a non-aluminum patterned conductive current collector, forms an in-situ bonding interface with the subsequently grown active material. 3) Using standard ultraviolet lithography, an interdigitated electrode pattern (e.g., 5µm finger width, 5µm spacing) is defined on the gold layer; subsequently, wet etching is performed using gold and chromium etching solutions to obtain patterned chromium / gold interdigitated electrodes as current collectors; such as Figure 2 As shown, the width and spacing of the interdigitated electrodes are both at the micrometer level, with high patterning precision, and they are tightly bonded to the underlying silicon substrate. 4) Using an electron beam evaporation apparatus, a high-purity aluminum film with a thickness of approximately 1 μm is deposited at a low temperature (below 50°C) on the substrate with the gold interdigitated electrodes. Low-temperature deposition can reduce the thermal stress between the aluminum film and the silicon substrate, and avoid delamination in subsequent processes. 5) Use photolithography again to define a pattern on the aluminum film that completely overlaps with the gold cross-finger electrode below; remove excess aluminum by wet or dry etching of aluminum to form an aluminum structure consistent with the gold cross-finger pattern. 6) Using the above substrate as the anode and the platinum sheet as the cathode, the substrate was placed in a 0.3M oxalic acid electrolyte and anodized at a constant voltage of 40V and a temperature of 4°C. During the oxidation process, the aluminum regions not protected by the photoresist were transformed into porous anodic aluminum oxide, with the channels growing perpendicular to the substrate. Since the aluminum film had been pre-patterned, the final AAO template naturally exhibited an interdigitated pattern, and the bottom of the template maintained direct contact with the underlying gold conductive layer. The oxidation time was controlled at 10 minutes, forming channels with a depth of approximately 500nm and a pore diameter of approximately 40-50nm. 7) After oxidation, the template is enlarged with a 5wt% phosphoric acid solution (about 10 min) to reduce the barrier layer between the bottom of the template and the gold current collector below, so as to facilitate the uniform conduction of current in the subsequent electrodeposition process; this enlargement step is the key to ensuring that the active material and the current collector form a direct electrical contact.

[0038] Step 2: In-situ electrochemical growth of one-dimensional nanoarrays: 1) Preparation of electroplating solution: The solution is a mixed aqueous solution of 0.1M nickel sulfate and 0.2M boric acid, with the pH value adjusted to 3.5; boric acid acts as a buffer to stabilize the pH value of the electroplating solution; 2) Pulse electrodeposition using a three-electrode system: using a gold current collector on the chip as the working electrode, a saturated calomel electrode as the reference electrode, and a platinum sheet as the counter electrode; setting the pulse parameters: on-time (Ton) is 0.1 seconds, potential is -1.0V (vs. SCE); off-time (Toff) is 0.5 seconds, potential is -0.2V; 3) Deposition at room temperature for about 15 min; nickel ions are reduced at the bottom of the nanopores of the AAO template (on the gold electrode) and grow from bottom to top, filling the pores to form nanowires; hydrogen bubbles generated by pulse intermittently serve as dynamic hydrogen bubble soft templates, leaving voids inside or on the surface of the nanowires to form porous secondary structures, thereby further increasing the specific surface area and ion transport channels.

[0039] Step 3: In-situ transformation of metal / metal oxide composite structures: 1) Remove the chip with deposited nickel nanowires from the electrolyte, wash it with deionized water and blow it dry; 2) Place it in a tube furnace and heat it to 300°C in air at a rate of 2°C / min, then maintain the temperature for 2 hours for thermal oxidation treatment; 3) After cooling in the furnace, a uniform nickel oxide active layer grows in situ on the surface of the nickel nanowires, forming a core-shell structured nickel / nickel oxide composite nanowire; the thickness of the oxide layer can be adjusted by controlling the oxidation temperature and time. In this embodiment, the oxide layer thickness is about 5-10 nm.

[0040] Step 4: Molding of the integrated electrode: 1) The chip was immersed in a 5 wt% sodium hydroxide solution for 10 min to selectively dissolve the AAO template, while the nickel / nickel oxide nanowire structure remained unaffected; 2) After repeated rinsing and drying with deionized water, the final product can be obtained: a porous nickel / nickel oxide composite nanowire ordered array that grows directly and firmly on the gold interdigitated current collector. The whole structure completely replicates the preset interdigitated pattern, forming an on-chip integrated electrode.

[0041] Characterization and Effect Observed by scanning electron microscopy (see...) Figure 3 The electrode exhibits a highly ordered, vertically oriented array of nanowires precisely distributed on each of the gold interdigitates. The nanowire diameter is consistent with the AAO pore size (approximately 50 nm), and the surface displays a porous characteristic. Electrochemical tests show that in 1M KOH electrolyte, the areal capacitance of this electrode reaches 42 mF / cm² (current density 1 A / g), the interfacial resistance is less than 2.0 Ω·cm², and the capacitance retention rate exceeds 88% after 1000 cycles.

[0042] Example 2: In-situ fabrication of on-chip integrated cobalt / cobalt tetroxide nanotube array electrodes: This embodiment demonstrates the in-situ preparation of cobalt / cobalt tetroxide composite nanotube arrays using a pulsed electrodeposition method combined with electrochemical oxidation, showcasing the universality of this invention in realizing nanotube structures and employing electrochemical oxidation methods.

[0043] Step 1: In-situ construction of on-chip graphical templates: Similar to Example 1, a silicon substrate with a patterned gold conductive layer and a patterned AAO template were prepared. Specifically, a 4-inch silicon wafer with a silicon dioxide insulating layer (approximately 300 nm thick) thermally oxidized on the surface was selected as the substrate. A 10 nm chromium adhesion layer and a 100 nm gold layer were deposited by magnetron sputtering. The interdigitated pattern (5 μm wide and 5 μm pitch) was formed by photolithography and wet etching. A 1 μm high-purity aluminum film was deposited at low temperature using electron beam evaporation. The aluminum structure was formed with the same pattern as the gold interdigitated pattern by photolithography and etching. Using 0.3 M oxalic acid as the electrolyte, the template was anodized for 10 min at a constant voltage of 40 V and a temperature of 4°C to form a patterned AAO template with a depth of approximately 500 nm and a pore size of approximately 40-50 nm. After oxidation, the template was enlarged with a 5 wt% phosphoric acid solution for 10 min to reduce the barrier layer between the bottom of the template and the gold current collector. Step 2: In-situ electrochemical growth of one-dimensional nanoarrays: 1) Preparation of electroplating solution: The solution is 0.1M cobalt sulfate. A mixed aqueous solution of boric acid and 0.2M boric acid was prepared, and the pH value was adjusted to 4.0; boric acid acts as a buffer to stabilize the pH value of the electroplating solution. 2) Pulse electrodeposition using a three-electrode system: A gold current collector on the chip is used as the working electrode, a saturated calomel electrode as the reference electrode, and a platinum sheet as the counter electrode. Pulse parameters are set as follows: On-time (Ton) is 0.1 seconds, potential is -1.0V (vs. SCE); Off-time (Toff) is 0.5 seconds, potential is -0.2V (vs. SCE). 3) Deposition at room temperature for approximately 20 minutes; by precisely controlling the pulse parameters and the composition of the electroplating solution, cobalt ions are reduced at the bottom of the nanopores of the AAO template (on the gold electrode) and preferentially grow along the pore walls to form nanotube structures instead of solid nanowires; hydrogen bubbles generated during pulse intermittently serve as dynamic hydrogen bubble soft templates, forming micro-nano secondary structures on the nanotube surface, further increasing the specific surface area. This nanotube growth mode can be precisely controlled by adjusting pulse parameters (such as on-time, off-time, and deposition potential) and adding surfactants; Step 3: In-situ transformation of metal / metal oxide composite structures: 1) Remove the chip with deposited cobalt nanotubes from the electrolyte, wash it with deionized water and blow it dry; 2) Place the chip in 1M KOH electrolyte and perform electrochemical oxidation using cyclic voltammetry: potential range 0 to 0.6V (vs. Hg / HgO), scan rate 20 mV / s, 50 cycles; 3) During this process, the surface of cobalt nanotubes is transformed in situ into cobalt tetroxide. An active layer forms a core-shell structure of cobalt / cobalt tetroxide composite nanotubes; electrochemical oxidation can be completed at room temperature, avoiding the damage to the interface caused by thermal stress that may be caused by thermal oxidation, making it particularly suitable for heat-sensitive applications. Step 4: Molding of the integrated electrode: 1) The chip was immersed in a 5 wt% sodium hydroxide solution for 10 min to selectively dissolve the AAO template, while the cobalt / cobalt tetroxide composite nanotube structure remained unaffected. 2) After repeated rinsing and drying with deionized water, the final product can be obtained: an ordered array of cobalt / cobalt tetroxide composite nanotubes directly and firmly grown on the gold interdigitated current collector, which completely replicates the preset interdigitated pattern and forms an on-chip integrated electrode.

[0044] Characterization and Effect Scanning electron microscopy revealed highly ordered, vertically oriented nanotube arrays precisely distributed on each of the golden interdigitates. The outer diameter of the nanotubes matched the pore size of the AAO template (approximately 50 nm), and the tube walls exhibited uniform thickness. Transmission electron microscopy confirmed that the nanotubes possessed a clear hollow structure and uniformity. The shell has a thickness of approximately 5-8 nm.

[0045] Electrochemical tests show that, due to the double surface of the nanotube structure, which provides a larger specific surface area and a shorter ion diffusion path, the electrode achieves an areal capacitance of 48 mF / cm² at a current density of 1 A / g, an interfacial resistance of less than 2.0 Ω·cm², and a capacitance retention rate of over 90% after 1000 cycles, demonstrating excellent electrochemical performance and stability.

[0046] Example 3: Expanded Applications and Performance Verification of Multi-Metal Systems: This embodiment aims to demonstrate the universality of the method of the present invention in different metal / metal oxide systems. Through in-situ preparation of iron / iron oxide and manganese / manganese oxide systems, it verifies the flexibility and advantages of the method in controlling the composition, structure and electrochemical performance of materials.

[0047] I. In-situ fabrication of on-chip integrated iron / iron oxide composite nanowire array electrodes: Step 1: In-situ construction of on-chip graphical templates: Using the same silicon substrate as in Example 1, a 300nm thick silicon dioxide insulating layer is thermally oxidized on its surface. A 10nm chromium adhesion layer and a 100nm gold layer are deposited by magnetron sputtering to form patterned interdigitated electrodes (finger width 5µm, spacing 5µm). The patterned conductive layer is made of a non-aluminum material to ensure compatibility with subsequent processes. A 1µm thick high-purity aluminum film was deposited on a patterned gold electrode at low temperature (<50°C) by electron beam evaporation. The aluminum film was patterned into a pattern that completely overlapped with the gold interdigitated electrode using photolithography and wet etching processes. Using oxalic acid electrolyte (0.3M) as the medium, the patterned AAO template with a depth of about 500nm and a pore size of 40-50nm was formed under a constant voltage of 40 V and a temperature of 4°C for 10 min. After oxidation, the pores were expanded with 5 wt% phosphoric acid solution for 10 min to reduce the barrier layer at the bottom of the template.

[0048] Step 2: In-situ electrochemical growth of one-dimensional nanoarrays: Electroplating solution preparation: Contains 0.1 M ferrous sulfate A mixed aqueous solution of boric acid and 0.2 M boric acid, pH adjusted to 3.5; boric acid acts as a buffer to prevent... Oxidation; The pulsed electrodeposition method was adopted: the gold interdigitated electrode was used as the working electrode, the saturated calomel electrode was used as the reference electrode, and the platinum sheet was used as the counter electrode; the pulse parameters were set as follows: on time (Ton) 0.1 seconds, potential -1.1 V (vs. SCE), off time (Toff) 0.5 seconds, potential -0.3 V, and deposition time 15 min; during this process, the dynamic hydrogen bubbles generated by the hydrogen evolution reaction served as a soft template to form a porous secondary structure inside the nanowire.

[0049] Step 3: In-situ transformation of metal / metal oxide composite structures: The deposited chip was heated to 350°C in air at a rate of 2°C / min and held at that temperature for 1 hour for thermal oxidation treatment, so that the iron nanowires were transformed in situ on the surface. Shell, forming a core-shell structure Composite nanowires; the oxide layer thickness is controlled at 8-12 nm, which can be precisely controlled by adjusting temperature and time.

[0050] Step 4: Molding of the integrated electrode: The AAO template was selectively dissolved by immersion in a 5 wt% sodium hydroxide solution for 10 min, exposing the composite nanowire array that was directly bonded to the gold current collector, thus forming an on-chip integrated electrode.

[0051] Results and Characterization Scanning electron microscopy revealed that the obtained nanowire array exhibited a highly ordered vertical orientation, with a diameter of approximately 50 nm, consistent with the pore size of the AAO template, and a porous surface, confirming the effectiveness of the dynamic hydrogen bubble template method.

[0052] Electrochemical tests showed that in 1 M KOH electrolyte, the electrode achieved an areal capacitance of 35 mF / cm² (current density 1 A / g), an interfacial resistance of less than 2.0 Ω·cm², and a capacitance retention of over 88% after 1000 cycles; this is attributed to... The pseudocapacitive characteristics of the metallurgical interface formed in situ.

[0053] II. In-situ fabrication of on-chip integrated manganese / manganese oxide composite nanowire array electrodes: Step 1: In-situ construction of on-chip graphical templates: The same substrate and patterned AAO template as the iron system are used to ensure process consistency; the template parameters are: aperture 50nm, depth 500nm, and the barrier layer has been thinned after the aperture expansion process; Step 2: In-situ electrochemical growth of one-dimensional nanoarrays: Electroplating solution preparation: Contains 0.1 M manganese sulfate and 0.1 M sodium sulfate A mixed aqueous solution, pH adjusted to 6.5; sodium sulfate provides ionic conductivity to prevent Mn²⁺ hydrolysis; A constant potential deposition method was adopted: the potential was set to -1.2 V (vs. SCE), and the deposition time was 10 min; this parameter optimized the nucleation rate of manganese, ensuring that the nanowires uniformly filled the AAO template channels and avoiding dendrite growth; Step 3: In-situ transformation of metal / metal oxide composite structures: The deposited chip is placed In the electrolyte, a three-electrode system was used (working electrode: chip gold current collector; reference electrode: Ag / AgCl; counter electrode: platinum sheet); electrochemical oxidation was performed by cyclic voltammetry: potential range 0 to 1.0 V (vs. Ag / AgCl), scan rate 20 mV / s, 50 cycles; this process caused the manganese nanowire surface to be converted in situ into amorphous M The shell is approximately 5-8 nm thick; electrochemical oxidation can be completed at room temperature, avoiding thermal stress damage to the interface. Step 4: Molding of the integrated electrode: Similar to the iron system, the AAO template was dissolved in an alkaline solution to obtain direct growth on the gold interdigitated electrodes. Composite nanowire array.

[0054] Results and Characterization Morphology analysis shows that the nanowire array maintains a one-dimensional ordered structure. The shell is uniformly enclosed, and a clear core-shell interface can be observed through transmission electron microscopy, with no cracks or detachment.

[0055] Excellent electrochemical performance: At a current density of 0.5 A / g, the areal specific capacitance reaches 55 mF / cm², which is superior to that of traditional slurry electrodes (approximately 20 mF / cm²); outstanding cycling stability, with a capacity retention of 90% after 2000 cycles, attributed to... High ionic conductivity and in-situ ohmic contact interface.

[0056] Example 4: Fine-tuning of secondary structures: This embodiment illustrates how adjusting pulse electrodeposition parameters can further optimize the secondary structure of a nanoarray, demonstrating the flexibility of this invention in morphology control.

[0057] In-situ preparation of porous nanowires: Using the pulsed electrodeposition parameters of Example 1 (Ton=0.1s, Toff=0.5s), periodic hydrogen bubbles can be generated to form a microporous structure inside the nickel nanowires. By adjusting the Toff time (0.2s to 1.0s), the size and distribution of hydrogen bubbles can be controlled, thereby regulating the porosity and pore size of the pore structure; the longer the Toff time, the more fully the hydrogen bubbles detach, and the larger the pore size formed. In-situ preparation of branched nanowires: A dual-pulse electrodeposition strategy was adopted, firstly, rapid nucleation was performed at a higher potential (-1.2V), then the main trunk was grown at a lower potential (-0.8V), and finally, a high-potential pulse was applied again to induce branch growth; the branched structure can further increase the specific surface area and the number of active sites. In-situ preparation of nanotube structures: As in Example 2, by controlling the deposition potential and time (constant potential -1.0V, deposition time 20min), the metal is preferentially grown along the pore walls of the AAO template to form nanotube structures; compared with nanowires, nanotubes have inner and outer double surfaces, which can provide a larger specific surface area and a shorter ion diffusion path.

[0058] Adjustment range of process parameters According to the method of the present invention, the following process parameters can be adjusted according to actual needs to achieve customized preparation with different structures and properties: AAO template parameters: Aluminum film thickness: 0.5-5μm Anodizing voltage: 20-60V (oxalic acid system), 40-100V (phosphate system) Oxidation temperature: 0-10°C Pore ​​size: 20-200nm (adjustable by oxidation voltage and pore expansion time) Hole depth: 0.5-5μm Pulse electrodeposition parameters: Deposition methods: constant potential (-0.8V to -1.2V vs. SCE) or pulsed potential. Pulse parameters: Ton 0.05-0.5s, Toff 0.1-1.0s Deposition time: 5-30 min Electroplating solution concentration: metal salt 0.05-0.5M, boric acid 0.1-0.5M Oxidation treatment parameters: Thermal oxidation: temperature 200-400°C, time 0.5-4h Electrochemical oxidation: The potential range is determined according to the type of metal, and the number of cycles is 20-100. Oxygen plasma treatment: power 50-200W, time 10-60min Comparison and verification with existing technologies To verify the technical advantages of this invention, the applicant conducted comparative experiments: Comparative Experiment 1 (Comparison with Patterned Aluminum Substrate Method): Following the method disclosed in Shao Zengjun's master's thesis, a nickel nanowire array was prepared on a patterned aluminum sheet and then transferred to a gold interdigitated electrode after peeling. Electrochemical test results showed that the interfacial resistance of the transferred electrode was as high as 8.7 Ω·cm², and the capacitance retention rate after 500 cycles was only 72%, which is far lower than the integrated electrode of this invention (interfacial resistance <2.0 Ω·cm², capacitance retention rate >88% after 1000 cycles).

[0059] Comparative Experiment 2 (Comparison with Template Transfer Method): Following the Al-Si eutectic bonding method reported by Scisco et al., the AAO template was transferred onto a silicon wafer and nickel nanowires were electrodeposited. This process requires high-temperature bonding at 500°C, and about 30% of the template breaks during the transfer process. The interface resistance of the resulting electrode is 2.3 Ω·cm², and the capacitance retention rate is 85% after 1000 cycles, both of which are inferior to the present invention.

[0060] The above comparative experiments fully demonstrate the significant advantages of this invention in terms of in-situ integration process compatibility, interface quality, structural stability, and electrochemical performance.

[0061] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A method for in-situ fabrication of an on-chip integrated one-dimensional nanoarray electrode, characterized in that, Includes the following steps: Step S1: In-situ construction of on-chip graphical template: A chip substrate is provided, on which a patterned conductive layer is formed; A metallic aluminum film is deposited on the patterned conductive layer, and the metallic aluminum film is patterned to form an aluminum structure corresponding to the pattern of the patterned conductive layer. The aluminum structure is anodized to transform it into a patterned anodized aluminum template, wherein the bottom of the anodized aluminum template is in direct contact with the patterned conductive layer. The anodized aluminum template is subjected to a hole-enlarging treatment; Step S2, in-situ electrochemical growth of one-dimensional nanoarrays: Using the patterned conductive layer as the working electrode, a one-dimensional metal nano-ordered array is grown in the nanopores of the anodic aluminum oxide template by pulse electrodeposition, wherein a porous or branched secondary structure is formed in situ on the sidewalls or inside of the one-dimensional metal nano-ordered array. Step S3: In-situ transformation of the metal / metal oxide composite structure: The metal one-dimensional nano-ordered array is oxidized to form a metal oxide layer in situ on the metal surface, resulting in a metal / metal oxide composite one-dimensional nano-ordered array. Step S4: Molding of the integrated electrode: The anodic aluminum oxide template is removed, exposing the metal / metal oxide composite one-dimensional nano-ordered array and maintaining direct bonding with the patterned conductive layer to form an on-chip integrated electrode.

2. The in-situ fabrication method of an on-chip integrated one-dimensional nanoarray electrode according to claim 1, characterized in that: The chip substrate is a silicon wafer, a glass wafer, or a polymer wafer, and the material of the patterned conductive layer is gold, platinum, titanium, chromium, copper, or a combination thereof.

3. The in-situ fabrication method of an on-chip integrated one-dimensional nanoarray electrode according to claim 1, characterized in that: In step S2, the on-time Ton of the pulse electrodeposition method is 0.05-0.5s, and the off-time Toff is 0.1-1.0s.

4. The in-situ fabrication method of an on-chip integrated one-dimensional nanoarray electrode according to claim 1, characterized in that: In step S3, the oxidation treatment is one of thermal oxidation, electrochemical oxidation, or oxygen plasma treatment.

5. The in-situ fabrication method of an on-chip integrated one-dimensional nanoarray electrode according to claim 1, characterized in that: The metal is at least one of nickel, iron, cobalt, and manganese, or an alloy containing at least two of the above metals; the metal oxide is an oxide or composite oxide of the corresponding nickel, iron, cobalt, and manganese.

6. The in-situ fabrication method of an on-chip integrated one-dimensional nanoarray electrode according to claim 1, characterized in that: In step S1, the voltage for anodizing is 20-60V, the temperature is 0-10℃, and the electrolyte is oxalic acid or phosphoric acid solution; the pore-expanding treatment uses phosphoric acid solution and the pore-expanding treatment time is 5-20min.

7. An on-chip integrated metal / metal oxide composite one-dimensional nanoarray electrode prepared by the method according to any one of claims 1-6, characterized in that, Its structure includes: Chip substrate; A patterned conductive layer is formed on the chip substrate, and the material of the patterned conductive layer is a non-aluminum conductive material; Furthermore, a one-dimensional nano-ordered array of metal / metal oxide composites is deposited directly on the patterned conductive layer using an in-situ pulsed electrodeposition method. The metal / metal oxide composite one-dimensional nano-ordered array is composed of a metal core and a metal oxide shell that covers the surface of the metal core in situ. Its sidewalls or interior have porous or branched secondary structures formed by dynamic hydrogen bubble template method. The metal / metal oxide composite one-dimensional nano-ordered array forms a metallurgical bond or ohmic contact with the patterned conductive layer, and has the same planar pattern as the patterned conductive layer.

8. The on-chip integrated metal / metal oxide composite one-dimensional nanoarray electrode according to claim 7, characterized in that: The morphology of the metal / metal oxide composite one-dimensional nano-ordered array is nanowire or nanotube; the thickness of the metal oxide shell is 2-20 nm.

9. An on-chip integrated micro supercapacitor, characterized in that: It comprises a pair of on-chip integrated metal / metal oxide composite one-dimensional nanoarray electrodes as described in claim 7 or 8, the pair of electrodes being arranged in an interdigitated manner on the same plane and immersed in a solid or gel electrolyte.

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