A timing control strategy for flexible interconnection energy transfer device multi-module

Abstract

The application relates to the technical field of power electronic device control, and discloses a timing control strategy for a multi-module flexible interconnected energy transfer device, which comprises the following steps: collecting AC side output instantaneous current, DC bus voltage and substrate transient temperature of a power module to construct basic state parameters; superimposing a time offset sequence to form a disturbance time increment, extracting a same-frequency temperature and a loss fluctuation to calculate a real-time transient thermal impedance; calculating a state deviation and mapping the state deviation into an opening compensation amount and a closing compensation amount; calculating a DC bus voltage change rate, and when the absolute value is greater than a set threshold, combining a parasitic inductance deviation amount to generate a feedforward timing compensation vector; comprehensively superimposing the basic opening and closing time, the disturbance time increment, the opening and closing compensation amounts and the feedforward timing compensation vector to generate an absolute opening edge and an absolute closing edge time, and writing the absolute opening edge and the absolute closing edge time into a hardware register. The application solves the problem of thermal-electric stress imbalance caused by inconsistent thermal impedances of multi-modules due to aging.

Description

Technical Field

[0001] This invention relates to the field of power electronic equipment control technology, specifically a timing control strategy for multiple modules of a flexible interconnected energy transfer device. Background Technology

[0002] Flexible interconnected energy transfer devices typically consist of multiple power modules physically connected in parallel or cascaded to meet the hardware requirements for large-capacity power conversion and transmission. Under normal operating conditions, existing control systems usually perform outer-loop steady-state voltage or current sharing control based on collected electrical state variables, and their underlying drive pulses are mostly generated according to fixed carrier phase shift rules and symmetrical pulse width modulation logic.

[0003] As the operating cycle extends, the insulating substrates and thermal interface materials within each power module undergo varying degrees of aging, leading to inconsistencies in transient thermal impedance between modules at the physical level. Traditional steady-state current sharing control only constrains each module to output equal current. When the transient thermal impedance of some modules increases due to physical aging, equal current distribution causes these aging modules to accumulate higher heat dissipation power, thereby triggering substrate temperature exceedances and accelerating the thermodynamic failure of internal power electronic devices. Existing control architectures struggle to identify microscopic changes in the actual heat dissipation performance of each module online without shutting down the device or adding additional hardware detection circuitry. Furthermore, they cannot achieve dynamic redistribution of thermoelectric stress between modules through intervention at the underlying nanosecond-level drive timing without altering the global baseband control command.

[0004] When facing transient conditions, the hardware architecture of multiple parallel modules inherently suffers from manufacturing tolerances due to the differences in the physical spatial arrangement of the busbars connecting each branch. When external load shedding or other conditions cause transient disturbances in the DC bus voltage, the inconsistent parasitic inductance of each branch leads to deviations in the transient current change rate. The pulse width modulation generation mechanism fixed in the existing control strategy cannot provide active feedforward compensation for the edge moments of the underlying drive pulse based on these differences in hardware parasitic parameters. As a result, during DC bus voltage transients, high-frequency transient circulating currents are easily generated on the parallel side of the multiple modules, thereby increasing the accumulation of electrical stress in the power modules during dynamic processes. Summary of the Invention

[0005] To address the shortcomings of existing technologies, this invention provides a timing control strategy for multiple modules in a flexible interconnected energy transfer device. This strategy solves the problems of thermoelectric stress imbalance caused by inconsistent thermal impedance due to physical aging of multiple power modules in the flexible interconnected energy transfer device, as well as transient circulating currents generated during DC bus voltage transients due to differences in parasitic inductance of parallel branches.

[0006] To achieve the above objectives, the present invention provides the following technical solution:

[0007] This invention provides a timing control strategy for multiple modules of a flexible interconnected energy transfer device, comprising the following steps:

[0008] The instantaneous AC output current, DC bus voltage, and transient temperature of the substrate of the power module in the energy transfer device are collected, and the reference duty cycle and reference carrier phase shift angle are extracted to construct the basic state parameters.

[0009] The generated time offset sequence is superimposed on the preset base conduction time to form the disturbance time increment. The same frequency temperature and loss fluctuation are extracted to calculate the real-time transient thermal impedance. The current weight and temperature weight are updated to correct the thermoelectric parameters.

[0010] The state deviation between the instantaneous output current of the AC side and the transient temperature of the substrate is calculated by weighting the current weight and the temperature weight, and mapped to the turn-on compensation amount and the turn-off compensation amount, which are used to generate the edge compensation timing.

[0011] The DC bus voltage change rate is calculated. When the absolute value of the DC bus voltage change rate is greater than a set threshold, a feedforward timing compensation vector is generated in combination with the pre-stored parasitic inductance deviation to provide transient feedforward compensation.

[0012] The basic turn-on time and basic turn-off time are generated based on the reference duty cycle and the reference carrier phase shift angle, and are superimposed with the disturbance time increment, the turn-on compensation amount, the turn-off compensation amount and the feedforward timing compensation vector to generate the absolute turn-on edge time and absolute turn-off edge time, which are written into the register to trigger the drive level to form a control closed loop.

[0013] Preferably, the basic state parameters for construction specifically include:

[0014] The instantaneous output current of the AC side of the power module in the energy transfer device and the DC bus voltage are synchronously obtained through the analog-to-digital conversion circuit.

[0015] Temperature and voltage signals are collected by a thermistor network mounted on the surface of the insulating substrate of the power module, and the temperature and voltage signals are calculated into the transient temperature of the substrate.

[0016] The reference duty cycle is read from the controller's preset storage space, and the reference carrier phase shift angle is calculated based on the mathematical ratio between the physical index number of the power module and the total number of modules.

[0017] Preferably, the step of superimposing the time offset sequence onto a preset base conduction time to form a disturbance time increment, and extracting the same-frequency temperature and loss fluctuations to calculate the real-time transient thermal impedance specifically includes:

[0018] A pseudo-random orthogonal time offset sequence with a preset low frequency and a preset low amplitude is generated as the time offset sequence;

[0019] The disturbance time increment is calculated by multiplying the time offset sequence with the set injection gain constant, and the disturbance time increment is superimposed on the basic conduction time of the power module. The perturbation generated by the high-frequency switching loss of the power module is extracted as the loss fluctuation.

[0020] The transient temperature of the substrate is extracted by orthogonal demodulation using discrete Fourier transform, and the amplitude of the temperature fluctuation at the same frequency as the time offset sequence is obtained as the same frequency temperature.

[0021] Calculate the ratio of the same-frequency temperature to the loss fluctuation, and use the ratio result as the real-time transient thermal impedance.

[0022] Preferably, the updated current weight and temperature weight specifically include:

[0023] Obtain the factory-calibrated rated transient thermal resistance, the set base temperature weighting constant, and the set thermal resistance sensitivity ratio gain;

[0024] The impedance deviation is obtained by subtracting the rated transient thermal impedance from the real-time transient thermal impedance. The dynamic compensation term is obtained by multiplying the impedance deviation by the thermal impedance sensitivity proportional gain.

[0025] The temperature weight is calculated by adding the dynamic compensation term to the basic temperature weight constant.

[0026] The current weight is calculated by subtracting the temperature weight from the value one, such that the sum of the current weight and the temperature weight equals one.

[0027] Preferably, the weighted calculation of the state deviation between the instantaneous output current of the AC side and the transient temperature of the substrate based on the current weight and the temperature weight specifically includes:

[0028] The current normalization factor is obtained by calculating the ratio of the absolute value of the instantaneous output current on the AC side to the rated current capacity.

[0029] The temperature normalization factor is obtained by calculating the ratio of the transient temperature of the substrate to the safe operating temperature threshold.

[0030] The thermoelectric coupling state variables of the power module are calculated by adding the product of the current weight and the current normalization factor to the product of the temperature weight and the temperature normalization factor.

[0031] The arithmetic mean of the thermoelectric coupling state variables of all power modules in the energy transfer device is calculated to obtain the system average state variables;

[0032] The state deviation is calculated by subtracting the system average state variable from the thermoelectric coupling state variable of the power module.

[0033] Preferably, the mapping is an on-compensation amount and an off-compensation amount, used to generate the edge compensation timing sequence, including:

[0034] Obtain the preset on-proportion mapping coefficient and the preset off-proportion mapping coefficient in the digital controller;

[0035] The opening ratio mapping coefficient is multiplied by the state deviation to obtain the opening compensation amount;

[0036] The shutdown compensation amount is obtained by multiplying the negative shutdown ratio mapping coefficient with the state deviation.

[0037] Preferably, calculating the DC bus voltage change rate, and when the absolute value of the DC bus voltage change rate is greater than a set threshold, generating a feedforward timing compensation vector in conjunction with the pre-stored parasitic inductance deviation specifically includes:

[0038] The rate of change of the DC bus voltage is calculated by taking the time derivative of the DC bus voltage.

[0039] When the absolute value of the DC bus voltage change rate is less than or equal to the set threshold, the feedforward timing compensation vector is set to zero.

[0040] When the absolute value of the DC bus voltage change rate is greater than the threshold, the parasitic inductance deviation amount pre-stored in the memory is read, and the set feedforward compensation coefficient, the parasitic inductance deviation amount and the sign function of the DC bus voltage change rate are multiplied together to obtain the feedforward timing compensation vector.

[0041] Preferably, generating the basic turn-on time and basic turn-off time based on the reference duty cycle and the reference carrier phase shift angle includes:

[0042] Read the preset switching cycle parameters, and generate the basic turn-on time in a disturbance-free state based on the switching cycle parameters, the reference duty cycle and the reference carrier phase shift angle through digital time comparison logic;

[0043] Based on the switching cycle parameters, the reference duty cycle, and the reference carrier phase shift angle, the basic off time in a disturbance-free state is generated through digital time comparison logic.

[0044] Preferably, the superposition of the disturbance time increment, the turn-on compensation amount, the turn-off compensation amount, and the feedforward timing compensation vector to generate the absolute turn-on edge time and the absolute turn-off edge time specifically includes:

[0045] The absolute turn-on edge time is generated by adding the base turn-on time, the turn-on compensation amount, the feedforward timing compensation vector, and the disturbance time increment.

[0046] The absolute turn-off edge time is generated by adding the base turn-off time, the turn-off compensation amount, and the feedforward timing compensation vector.

[0047] Preferably, the step of generating the absolute turn-on and absolute turn-off edges and writing them into the register to trigger the drive level to form a control closed loop specifically includes:

[0048] The generated absolute turn-on edge time and absolute turn-off edge time are converted into corresponding digital count values ​​that can be recognized by the underlying hardware;

[0049] The corresponding digital count value is written into the phase boundary and dead zone boundary register group of the high-resolution pulse width modulation module in the field programmable gate array processor, and the phase boundary and dead zone boundary register group is the register.

[0050] The hardware comparison circuit within the field-programmable gate array processor determines the matching status between the real-time count value and the value in the register. When the values ​​match, the drive level of the gate of the power electronic device in the power module is triggered to flip.

[0051] This invention provides a timing control strategy for multiple modules in a flexible interconnected energy transfer device. It offers the following advantages:

[0052] 1. This invention calculates real-time transient thermal impedance by superimposing a low-frequency pseudo-random orthogonal time offset sequence onto the basic conduction time to form a disturbance time increment, and extracting the amplitude of temperature fluctuations and power loss fluctuations at the same frequency. This processing method reuses the underlying pulse width modulation execution logic as a means of physical parameter detection, enabling the device to acquire changes in heat dissipation performance of the power module due to physical factors such as aging of thermal interface materials online without shutting down the device or adding additional hardware test circuits, providing an objective data basis for subsequent control parameter correction.

[0053] 2. This invention, based on current and temperature weights incorporating real-time transient thermal impedance feedback, calculates the state deviation by weighting the instantaneous output current on the AC side and the transient temperature of the substrate. This state deviation is then mapped to asymmetric on-state and off-state compensation values. This allows for independent, nanosecond-level fine-tuning of the effective conduction boundaries of each power module without altering the global baseband outer loop control command. Dynamic redistribution of thermoelectric stress is achieved based on the module's current physical aging and operating pressure, reducing the probability of power module damage due to continuous overheating.

[0054] 3. This invention calculates the DC bus voltage change rate in real time and generates a feedforward timing compensation vector by combining it with pre-stored parasitic inductance deviation when the absolute value exceeds a set threshold. When a sudden load change causes transient disturbances to the DC bus, the control system can actively output a feedforward time offset based on the inherent manufacturing tolerances of the hardware parasitic parameters. This offset directly cancels the timing misalignment caused by inconsistent line inductance at the bottom-level drive level reconstruction stage, thereby suppressing high-frequency circulating currents generated on the parallel side of multiple modules during transient processes. Attached Figure Description

[0055] Figure 1 This is a schematic diagram of the timing control strategy flow of the present invention;

[0056] Figure 2 This is a comparison curve of temperature distribution and transient circulation of the substrate of the multi-power module of the present invention. Detailed Implementation

[0057] The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0058] Reference Figure 1 , Figure 1 This is a flowchart illustrating a timing control strategy for multiple modules of a flexible interconnected energy transfer device according to an embodiment of the present invention. The present invention provides a timing control strategy for multiple modules of a flexible interconnected energy transfer device, comprising:

[0059] The instantaneous AC output current, DC bus voltage, and transient substrate temperature of the power module in the energy transfer device are collected, and the reference duty cycle and reference carrier phase shift angle are extracted to construct the basic state parameters.

[0060] The generated time offset sequence is superimposed on the preset base conduction time to form a disturbance time increment. The temperature and loss fluctuations at the same frequency are extracted to calculate the real-time transient thermal impedance. The current weight and temperature weight are updated to correct the thermoelectric parameters.

[0061] The state deviation is calculated by weighting the instantaneous output current of the AC side and the transient temperature of the substrate based on current weight and temperature weight, and mapped to the turn-on compensation amount and turn-off compensation amount, which are used to generate the edge compensation timing.

[0062] The DC bus voltage change rate is calculated. When the absolute value of the DC bus voltage change rate is greater than the set threshold, a feedforward timing compensation vector is generated by combining the pre-stored parasitic inductance deviation to provide transient feedforward compensation.

[0063] The basic turn-on time and basic turn-off time are generated based on the reference duty cycle and the reference carrier phase shift angle. These are then superimposed with the disturbance time increment, turn-on compensation amount, turn-off compensation amount, and feedforward timing compensation vector to generate the absolute turn-on edge time and absolute turn-off edge time, which are written into the register to trigger the drive level to form a control closed loop.

[0064] The aforementioned timing control strategy operates in a collaborative control hardware environment consisting of a digital signal processor and a field-programmable gate array processor.

[0065] The collaborative control hardware environment is connected to the flexible interconnected power transfer device via a communication bus. The flexible interconnected power transfer device contains multiple power modules that are physically connected in parallel or cascaded.

[0066] The digital signal processor integrates pre-set storage space and arithmetic logic units, and is connected to the analog-to-digital converter (ADC). The sampling channels of the ADC are connected to the electrical measurement nodes of each power module.

[0067] Each power module has a thermistor network mounted on its internal insulating substrate. The output of the thermistor network is connected to the channel of the analog-to-digital converter circuit to continuously output a temperature and voltage signal.

[0068] The digital signal processor (DSP) interacts with the field-programmable gate array (FPGA) processor via an internal data bus. The DSP performs synchronous acquisition of electrical and thermal state parameters, parameter identification calculations, and calculations of digital timing compensation quantities for various dimensions.

[0069] The field-programmable gate array (FPGA) processor incorporates a high-resolution pulse width modulation (PWM) module. This module includes phase boundary and dead-zone boundary register sets, as well as hardware comparator circuitry.

[0070] The field-programmable gate array processor receives the underlying time variable from the digital signal processor, writes the converted digital count value into a register group, and performs logical judgment through hardware comparison circuitry.

[0071] The gate drive circuits of the power electronic devices inside each power module are connected to the output pins of the field programmable gate array processor, and perform corresponding physical turn-on and turn-off actions according to the changes in the trigger level.

[0072] Reference Figure 1 At a fixed sampling trigger time in each switching cycle, the digital signal processor sends a synchronous sampling command to the analog-to-digital converter circuit through its internal trigger circuit.

[0073] To avoid electromagnetic interference caused by the transient operation of the high-frequency switching of the power modules, the sampling trigger time of the analog-to-digital converter (ADC) is set to the valley or peak value of the carrier counter of the high-resolution pulse width modulation module. After receiving the sampling command, the ADC synchronously acquires the analog voltage and current signals of each power module in the energy transfer device and converts them into digital quantities to obtain the instantaneous AC output current and DC bus voltage of the power modules.

[0074] The instantaneous output current of the AC side is set to be denoted as... The DC bus voltage is denoted as ,in Indicates the physical index number of the power module. This represents the current discrete sampling time.

[0075] The thermistor network mounted on the surface of the power module's insulating substrate includes NTC thermistors and precision voltage divider resistors. An analog-to-digital converter (ADC) acquires the analog voltage at the voltage divider nodes of this thermistor network to obtain a temperature voltage signal. After receiving this temperature voltage signal, the digital signal processor (DSP) calculates the real-time resistance value of the NTC thermistors based on the voltage division ratio of the hardware circuit and substitutes it into a nonlinear mathematical equation to solve for the transient temperature of the substrate. The specific formula for calculating the transient temperature of the substrate is expressed as follows:

[0076] ;

[0077] In the formula, To obtain the first Transient temperature of the substrate of each power module, in Kelvin; The set reference room temperature; The material constants of the NTC thermistor in the thermistor network; Represents the natural logarithm operation; For this NTC thermistor at reference room temperature The nominal resistance value below; This is the current resistance value of the NTC thermistor calculated based on the temperature and voltage signals.

[0078] The digital signal processor (DSP) reads the reference duty cycle generated by the closed-loop control logic operations of the outer loop voltage and current from its preset memory space. The DSP records the reference duty cycle as... .

[0079] The digital signal processor calculates the time reference, or reference carrier phase shift angle, for each power module in carrier interleaving control based on the physical index number of the current power module and the total number of modules in the power supply device. The formula for calculating the reference carrier phase shift angle is:

[0080] ;

[0081] In the formula, Indicates the first The reference carrier phase shift angle of each power module; This represents the physical index number of the power module, and its value is a positive integer. to ; This indicates the total number of modules operating in the flexible interconnected energy transfer device; This represents the phase angle of a complete switching carrier cycle. After the above calculations are completed, the instantaneous AC output current, DC bus voltage, substrate transient temperature, reference duty cycle, and reference carrier phase shift angle are stored in the data buffer, thus completing the construction of the basic state parameters.

[0082] Reference Figure 1 The digital signal processor uses an internal generator to generate a pseudo-random orthogonal time offset sequence with a preset low frequency and a preset low amplitude, and uses this as the time offset sequence. The frequency of this time offset sequence is set to be less than one-tenth of the switching frequency of the power module to form a slow, periodic control perturbation.

[0083] The digital signal processor obtains the set injection gain constant, multiplies the time offset sequence by the injection gain constant, and calculates the perturbation time increment. Its mathematical expression is:

[0084] ;

[0085] In the formula, Indicates at discrete sampling time Regarding the first The disturbance time increment generated by each power module; This represents the set nanosecond-level injection gain constant; This represents the instantaneous value of the time offset sequence generated at this moment.

[0086] The digital signal processor (DSP) superimposes the calculated perturbation time increment onto the fundamental on-time of the power module. This asymmetric superposition of time scales alters the voltage-current overlap area at the instants of turn-on and turn-off of the power electronic devices within the power module. Based on the switching characteristic parameters of the devices and this perturbation time increment, the DSP calculates the perturbation caused by the high-frequency switching losses of the power module and treats this perturbation as a loss fluctuation. The loss fluctuation is denoted as... This reflects the periodic changes in heat dissipation power caused by the time-shifted sequence.

[0087] A thermistor network on the surface of the insulating substrate continuously senses the thermal response generated by the periodic change in heat dissipation power. A digital signal processor receives the transient temperature signal of the substrate, which includes this thermal response, and extracts it using a discrete Fourier transform algorithm for orthogonal demodulation. By accumulating the sine and cosine components of the transient temperature signal within an integration time window corresponding to the period of the time offset sequence, the amplitude of the temperature fluctuation at the same frequency as the time offset sequence is obtained and taken as the same-frequency temperature. The same-frequency temperature is denoted as... .

[0088] After extracting the temperature and loss fluctuations at the same frequency, the digital signal processor performs a division operation to calculate the ratio of the temperature at the same frequency to the loss fluctuation, and uses the ratio as the real-time transient thermal impedance. The real-time calculation formula is:

[0089] ;

[0090] In the formula, Indicates the first The current real-time transient thermal impedance of each power module characterizes the dynamic hysteresis characteristics of the module to high-frequency switching thermal excitation under the current physical aging state. This represents the amplitude of the extracted temperature fluctuation at the same frequency as the time-offset sequence, i.e., the same-frequency temperature. Indicates the first Each power module at the current discrete sampling time Loss fluctuations (perturbations caused by high-frequency switching losses).

[0091] After acquiring the real-time transient thermal impedance, the digital signal processor (DSP) reads the factory-calibrated rated transient thermal impedance, the set base temperature weighting constant, and the set thermal impedance sensitivity proportional gain from the preset storage space. The DSP subtracts the rated transient thermal impedance from the real-time transient thermal impedance to obtain the impedance deviation, and then multiplies this impedance deviation by the thermal impedance sensitivity proportional gain to calculate the dynamic compensation term.

[0092] Subsequently, the digital signal processor (DSP) adds a dynamic compensation term to the base temperature weight constant to calculate the temperature weight. To satisfy the normalization constraints for multi-dimensional state variable evaluation, the DSP subtracts the calculated temperature weight from the numerical value to calculate the current weight. Its closed-loop adaptive correction equations are as follows:

[0093] ;

[0094] ;

[0095] In the formula, Indicates the updated number Temperature weighting of each power module; This represents the set base temperature weighting constant; Indicates the proportional gain of thermal impedance sensitivity; Indicates the first The current real-time transient thermal impedance of each power module characterizes the dynamic hysteresis characteristics of the module to high-frequency switching thermal excitation under the current physical aging state. This indicates the pre-stored factory-calibrated rated transient thermal resistance; Indicates the updated number The current weights of each power module are determined. Through the aforementioned mathematical closed-loop logic, the current weights and temperature weights are updated for subsequent thermoelectric parameter correction calculations.

[0096] Reference Figure 1 The digital signal processor receives the instantaneous AC output current and the transient temperature of the substrate from the basic state parameters. The digital signal processor reads the rated current capacity parameter from the preset storage space, calculates the absolute value of the sampled value of the instantaneous AC output current, and divides the absolute value by the rated current capacity to calculate the dimensionless current normalization factor.

[0097] The digital signal processor reads the safe operating temperature threshold parameter set in the preset storage space, divides the calculated transient temperature of the substrate by the safe operating temperature threshold, and calculates the dimensionless temperature normalization factor.

[0098] The digital signal processor (DSP) retrieves the updated current and temperature weights from the parameter identification stage. The DSP then adds the product of the current weight and the current normalization factor to the product of the temperature weight and the temperature normalization factor, performing a numerical summation to obtain the thermoelectric coupling state variables of the power module. The specific calculation formula for the thermoelectric coupling state variables is as follows:

[0099] ;

[0100] In the formula, Indicates the first Each power module at the current discrete sampling time Thermoelectric coupling state variables; Indicates the updated number Current weighting of each power module; Indicates the first The instantaneous current output on the AC side of each power module; This indicates the pre-stored rated current capacity of the module; Indicates the updated number Temperature weighting of each power module; Indicates the first The transient temperature of the substrate calculated by each power module; This indicates the set safe operating temperature threshold for the module.

[0101] The digital signal processor performs an arithmetic accumulation operation on the thermoelectric coupling state variables of all power modules operating in the energy transfer device, and divides the sum by the total number of modules to calculate the system average state variable of the entire energy transfer device. The mathematical expression for the system average state variable of the energy transfer device is:

[0102] ;

[0103] In the formula, Indicates inclusion The system average state variables of the energy transfer device of each power module; Indicates the total number of modules; Indicates the first Thermoelectric coupling state variables of each power module; This represents the summation index number of the power module, and its value is a positive integer. to .

[0104] After acquiring the system's average state variables, the digital signal processor will... The state deviation of a power module relative to the system average level is calculated by subtracting the thermoelectric coupling state variables of each power module from the system average state variables. The formula for calculating the state deviation is:

[0105] ;

[0106] In the formula, Indicates the first The state deviation of each power module; Indicates inclusion The system average state variables of the energy transfer device of each power module; Indicates the first Thermoelectric coupling state variables of each power module.

[0107] The digital signal processor (DSP) retrieves the preset on-state and off-state mapping coefficients from the digital controller's preset storage space. The DSP multiplies the on-state mapping coefficients by the state deviation to obtain the on-state compensation. Similarly, the DSP takes the negative value of the off-state mapping coefficients and multiplies them by the state deviation to obtain the off-state compensation. The mapping formulas for the on-state and off-state compensations are as follows:

[0108] ;

[0109] ;

[0110] In the formula, Indicates the first The nanosecond-level activation compensation amount calculated by each power module; This indicates the set activation ratio mapping coefficient; Indicates the first The nanosecond-level shutdown compensation amount calculated by each power module; This represents the set shutdown ratio mapping coefficient; Indicates the first The state deviation of each power module is determined by executing the multiplication mapping logic described above, thereby generating the edge compensation timing parameters.

[0111] Reference Figure 1 The digital signal processor (DSP) receives synchronously sampled DC bus voltages from the fundamental state parameters. In the discrete digital control system, the DSP uses historical voltage data from the previous sampling period and a backward differential numerical algorithm to calculate the time derivative of the current DC bus voltage, obtaining the rate of change of the DC bus voltage.

[0112] ;

[0113] In the formula, Represents discrete sampling time The rate of change of DC bus voltage; This represents the DC bus voltage at the current discrete sampling moment; This represents the DC bus voltage recorded in the memory for the previous discrete sampling period; This indicates the set fixed sampling period time of the digital control system.

[0114] The digital signal processor calculates the absolute value of the rate of change of the DC bus voltage and compares it with a transient disturbance voltage threshold set in a preset storage space. This transient disturbance voltage threshold is used to distinguish between steady-state ripple and transient disturbances caused by sudden changes in external load.

[0115] When the absolute value of the DC bus voltage change rate is less than or equal to a set threshold, the digital signal processor (DSP) determines that the current system is within the steady-state operating boundary. At this time, the DSP forces the value of the feedforward timing compensation vector to zero and does not perform any additional transient timing intervention.

[0116] When the absolute value of the DC bus voltage change rate exceeds a set threshold, the digital signal processor determines that the system has entered a transient process. Under this condition, due to the differences in the physical spatial arrangement of the power modules inside the flexible interconnected energy transfer device, the parasitic inductance of the busbars connecting each parallel branch has inherent manufacturing tolerances, which will cause inconsistent current change rates between branches during voltage transients.

[0117] To compensate for this physical difference, the digital signal processor (DSP) reads the parasitic inductance deviation recorded in the preset storage space. The DSP retrieves the set feedforward compensation coefficients and extracts the mathematical sign function of the DC bus voltage change rate. It then performs a multiplication operation on the feedforward compensation coefficients, the parasitic inductance deviation, and the sign function of the DC bus voltage change rate to calculate the feedforward timing compensation vector. The specific formula for calculating the feedforward timing compensation vector is as follows:

[0118] ;

[0119] In the formula, Indicates that for the first Feedforward timing compensation vectors generated by each power module; This represents the set feedforward compensation coefficient, whose dimensions convert the inductance quantization deviation into a time compensation metric. Indicates the pre-stored number Parasitic inductance deviation corresponding to each power module branch; Represents discrete sampling time The rate of change of DC bus voltage; The sign function outputs a positive one when the variable is greater than zero and a negative one when the variable is less than zero. Through this sign function, the direction of the feedforward timing compensation vector strictly follows the transient drop or rise direction of the DC bus voltage, providing physical characteristic-based transient feedforward compensation data for subsequent underlying drive timing.

[0120] Reference Figure 1 The digital signal processor (DSP) reads the switching cycle parameters from the preset storage space. The DSP executes digital time comparison logic to calculate and determine the [number]th [phase] based on the switching cycle parameters and the reference carrier phase shift angle. The local carrier time coordinate system of each power module within the current switching cycle. The digital signal processor multiplies the switching cycle parameter by the reference duty cycle to obtain the basic conduction duration, and according to the symmetrical carrier modulation rule, with the central axis of the time coordinate system as the reference, it proportionally distributes the basic conduction duration to both sides, generating the basic turn-on time and basic turn-off time under undisturbed conditions.

[0121] After obtaining the base time reference, the digital signal processor (DSP) performs algebraic synthesis calculations on multidimensional time variables. For the turn-on action, the DSP adds the base turn-on time, the calculated turn-on compensation amount, the feedforward timing compensation vector, and the disturbance time increment to generate the absolute turn-on edge time. The synthesis superposition formula is:

[0122] ;

[0123] In the formula, Indicates the first The absolute turn-on edge time generated by each power module and used for final execution; This indicates the uninterrupted base turn-on time generated by the dual closed-loop controller instructions; This indicates the amount of compensation enabled for thermoelectric balance mapping; This represents the feedforward timing compensation vector used to offset transient fluctuations in the DC bus. This represents the time increment of the disturbance used for extracting thermal impedance identification parameters.

[0124] For the turn-off action, the digital signal processor adds the basic turn-off time, the turn-off compensation amount, and the feedforward timing compensation vector to generate the absolute turn-off edge time. The formula for calculating the absolute turn-off edge time is:

[0125] ;

[0126] In the formula, Indicates the first The absolute turn-off edge time generated by each power module and used for final execution; This indicates the unperturbed basic turn-off time generated by the dual closed-loop controller instructions; This represents the amount of shut-off compensation used for thermoelectric balance mapping; This represents the feedforward timing compensation vector used to offset transient fluctuations in the DC bus. Since the disturbance time increment has already been injected during the turn-on phase to form a one-sided duty cycle perturbation, this term is not included in the calculation of the turn-off edge superposition.

[0127] After synthesizing the variables with physical time dimensions, the digital signal processor converts the generated absolute turn-on and absolute turn-off times into corresponding digital count values ​​recognizable by the underlying hardware. Specifically, this conversion is achieved by dividing the absolute time value by the period of the internal system clock of the field-programmable gate array processor and performing a floor operation, thereby obtaining a discrete integer count value that matches the bit width of the high-resolution pulse width modulation module's hardware timer.

[0128] The digital signal processor (DSP) transmits the generated digital count value to the field-programmable gate array (FPGA) processor via a communication interface and data bus. The FPGA processor receives this data and writes it into the phase boundary and dead-zone boundary registers of its internal high-resolution pulse-width modulation (PWM) module. At this point, the algorithmic results of the multi-dimensional timing control strategy have been solidified into the physical storage state of the underlying registers.

[0129] The hardware counter inside the Field-Programmable Gate Array (FPGA) processor increments or decrements under the drive of the system clock. The hardware comparator circuit within the FPGA continuously reads the real-time count value of this hardware counter and compares it with the values ​​in the phase boundary and dead-time boundary registers. When the hardware comparator circuit determines that the real-time count value perfectly matches the value in the registers, it generates a logic level transition signal. This signal is directly transmitted to the output port, triggering a toggle of the drive level of the gate of the corresponding power electronic device in the power module. This achieves closed-loop execution at the physical level of asymmetric timing control that integrates thermal impedance identification, thermoelectric state balance, and transient feedforward compensation.

[0130] Specific application examples:

[0131] A test platform was set up, including a flexible interconnected energy transfer device. This device consists of three physically parallel power modules (Module 1, Module 2, and Module 3). Under rated operating conditions, the rated instantaneous current carrying capacity of the AC side output of each power module was set to 50A, the rated DC bus voltage to 800V, the safe operating temperature threshold of the modules to 360K (87℃), and the fixed sampling period of the system to 100μs.

[0132] Hardware aging was simulated through physical intervention: uneven thermal grease was applied to the bottom layer of the insulating substrate of module one, increasing its initial transient thermal resistance by 25% compared to the factory calibration value; modules two and three maintained their normal physical state at the factory. At the same time, by adjusting the physical length of the parallel connection busbar, the parasitic inductance of the branch of module three was set to be 15% greater than the average parasitic inductance of modules one and two.

[0133] The device starts up and is loaded. The digital signal processor continuously superimposes a pseudo-random orthogonal time offset sequence with a frequency of 10Hz onto the basic conduction time.

[0134] After running for 20 seconds, the digital signal processor calculated the real-time transient thermal impedance of module one to be 0.45 K / W through discrete Fourier transform orthogonal demodulation extraction, while the transient thermal impedance of modules two and three was 0.36 K / W.

[0135] Since the thermal impedance deviation of module one is increasing in the positive direction, the controller adjusts the temperature weight of module one from the basic constant 0.5 to 0.65 and the corresponding current weight to 0.35 through the closed-loop adaptive correction equation set; the temperature weights of modules two and three are kept around 0.5.

[0136] In the thermoelectric coupling state assessment, Module 1, due to its faster temperature rise and increased temperature weight, calculates a higher value for the thermoelectric coupling state variable than the system average state variable, resulting in a positive state deviation. This positive state deviation is converted into a negative turn-on compensation and a positive turn-off compensation through mapping coefficient calculation. During execution in the underlying registers, the absolute on-time of Module 1 is shortened, and the instantaneous AC output current decreases from 50A to 42A; the absolute on-time of Modules 2 and 3 are correspondingly extended, and the instantaneous AC output current increases to 54A. This redistribution process directly limits the internal heat dissipation power of Module 1.

[0137] When the system was running for 50 seconds, an external step load was switched on, causing the DC bus voltage to drop from 800V to 720V within 2 milliseconds.

[0138] The digital signal processor calculated that the absolute value of the DC bus voltage change rate during this time period reached 40V / ms, which is greater than the set transient threshold (10V / ms).

[0139] At this point, the system triggers the feedforward compensation logic. For module three, which has a large parasitic inductance, the controller generates a negative feedforward timing compensation vector based on the negative sign of the inductance deviation and the DC bus voltage change rate. This advances the turn-on and turn-off times of module three on the time axis to compensate for the current response delay caused by the large inductance.

[0140] The test platform was run under both the traditional current sharing control strategy and the timing control strategy proposed in this invention, and physical measurement data were extracted and compared:

[0141] After running continuously at full load for 30 minutes, under the traditional strategy, the substrate temperature of module one reached 365K (exceeding the set threshold), while the temperatures of modules two and three remained at 345K, with a maximum temperature deviation of 20K.

[0142] After adopting the strategy of this invention, the temperature of the damaged module one was limited and stabilized below 352K, while the temperatures of modules two and three rose to 350K and 349K respectively, as they shared some of the current-carrying tasks. The maximum temperature deviation of the three modules was reduced to within 3K.

[0143] During the DC bus voltage change phase, the traditional strategy, which does not consider the difference in parasitic inductance, generates a high-frequency transient circulating current oscillation with a peak value of 12A between module one and module three.

[0144] After adopting the strategy of this invention, due to the application of nanosecond-level transient feedforward intervention based on voltage differential equations in the underlying driving timing, the current response between modules is forced to align on the time scale, and the measured transient circulating current peak is suppressed to within 1.5A.

[0145] Figure 2This is a comparison curve of substrate temperature distribution and transient circulating current of a multi-power module according to an embodiment of the present invention. Figure A shows the transient temperature change trajectory of the substrate of three modules with different heat dissipation physical states within 30 minutes after startup, under conventional control and the control strategy of the present invention. Figure B shows the evolution of transient circulating current generated by parallel branches within a local millisecond-level time window when a load step change occurs on the DC bus.

Claims

1. A timing control strategy for multiple modules of a flexible interconnected energy transfer device, characterized in that, Includes the following steps: The instantaneous AC output current, DC bus voltage, and transient temperature of the substrate of the power module in the energy transfer device are collected, and the reference duty cycle and reference carrier phase shift angle are extracted to construct the basic state parameters. The generated time offset sequence is superimposed on the preset base conduction time to form the disturbance time increment. The same frequency temperature and loss fluctuation are extracted to calculate the real-time transient thermal impedance. The current weight and temperature weight are updated to correct the thermoelectric parameters. The state deviation between the instantaneous output current of the AC side and the transient temperature of the substrate is calculated by weighting the current weight and the temperature weight, and mapped to the turn-on compensation amount and the turn-off compensation amount, which are used to generate the edge compensation timing. The DC bus voltage change rate is calculated. When the absolute value of the DC bus voltage change rate is greater than a set threshold, a feedforward timing compensation vector is generated in combination with the pre-stored parasitic inductance deviation to provide transient feedforward compensation. The basic turn-on time and basic turn-off time are generated based on the reference duty cycle and the reference carrier phase shift angle, and are superimposed with the disturbance time increment, the turn-on compensation amount, the turn-off compensation amount and the feedforward timing compensation vector to generate the absolute turn-on edge time and absolute turn-off edge time, which are written into the register to trigger the drive level to form a control closed loop.

2. The timing control strategy for multiple modules of a flexible interconnected energy transfer device according to claim 1, characterized in that, The specific basic state parameters for construction include: The instantaneous output current of the AC side of the power module in the energy transfer device and the DC bus voltage are synchronously obtained through the analog-to-digital conversion circuit. Temperature and voltage signals are collected by a thermistor network mounted on the surface of the insulating substrate of the power module, and the temperature and voltage signals are calculated into the transient temperature of the substrate. The reference duty cycle is read from the controller's preset storage space, and the reference carrier phase shift angle is calculated based on the mathematical ratio between the physical index number of the power module and the total number of modules.

3. The timing control strategy for multiple modules of a flexible interconnected energy transfer device according to claim 1, characterized in that, The step of superimposing the generated time offset sequence onto a preset base conduction time to form a disturbance time increment, and extracting the same-frequency temperature and loss fluctuations to calculate the real-time transient thermal impedance specifically includes: A pseudo-random orthogonal time offset sequence with a preset low frequency and a preset low amplitude is generated as the time offset sequence; The disturbance time increment is calculated by multiplying the time offset sequence with the set injection gain constant, and the disturbance time increment is superimposed on the basic conduction time of the power module. The perturbation generated by the high-frequency switching loss of the power module is extracted as the loss fluctuation. The transient temperature of the substrate is extracted by orthogonal demodulation using discrete Fourier transform, and the amplitude of the temperature fluctuation at the same frequency as the time offset sequence is obtained as the same frequency temperature. Calculate the ratio of the same-frequency temperature to the loss fluctuation, and use the ratio result as the real-time transient thermal impedance.

4. The timing control strategy for multiple modules of a flexible interconnected energy transfer device according to claim 1, characterized in that, The updated current weight and temperature weight specifically include: Obtain the factory-calibrated rated transient thermal resistance, the set base temperature weighting constant, and the set thermal resistance sensitivity ratio gain; The impedance deviation is obtained by subtracting the rated transient thermal impedance from the real-time transient thermal impedance. The dynamic compensation term is obtained by multiplying the impedance deviation by the thermal impedance sensitivity proportional gain. The temperature weight is calculated by adding the dynamic compensation term to the basic temperature weight constant. The current weight is calculated by subtracting the temperature weight from the value one, such that the sum of the current weight and the temperature weight equals one.

5. A timing control strategy for multiple modules of a flexible interconnected energy transfer device according to claim 1, characterized in that, The weighted calculation of the state deviation between the instantaneous output current of the AC side and the transient temperature of the substrate based on the current weight and the temperature weight specifically includes: The current normalization factor is obtained by calculating the ratio of the absolute value of the instantaneous output current on the AC side to the rated current capacity. The temperature normalization factor is obtained by calculating the ratio of the transient temperature of the substrate to the safe operating temperature threshold. The thermoelectric coupling state variables of the power module are calculated by adding the product of the current weight and the current normalization factor to the product of the temperature weight and the temperature normalization factor. The arithmetic mean of the thermoelectric coupling state variables of all power modules in the energy transfer device is calculated to obtain the system average state variables; The state deviation is calculated by subtracting the system average state variable from the thermoelectric coupling state variable of the power module.

6. The timing control strategy for multiple modules of a flexible interconnected energy transfer device according to claim 1, characterized in that, The mapping is defined as enabling compensation and disabling compensation, used to generate the edge compensation timing sequence, including: Obtain the preset on-proportion mapping coefficient and the preset off-proportion mapping coefficient in the digital controller; The opening ratio mapping coefficient is multiplied by the state deviation to obtain the opening compensation amount; The shutdown compensation amount is obtained by multiplying the negative shutdown ratio mapping coefficient with the state deviation.

7. A timing control strategy for multiple modules of a flexible interconnected energy transfer device according to claim 1, characterized in that, Calculating the DC bus voltage change rate, and when the absolute value of the DC bus voltage change rate is greater than a set threshold, generating a feedforward timing compensation vector in conjunction with the pre-stored parasitic inductance deviation specifically includes: The rate of change of the DC bus voltage is calculated by taking the time derivative of the DC bus voltage. When the absolute value of the DC bus voltage change rate is less than or equal to the set threshold, the feedforward timing compensation vector is set to zero. When the absolute value of the DC bus voltage change rate is greater than the threshold, the parasitic inductance deviation amount pre-stored in the memory is read, and the set feedforward compensation coefficient, the parasitic inductance deviation amount and the sign function of the DC bus voltage change rate are multiplied together to obtain the feedforward timing compensation vector.

8. A timing control strategy for multiple modules of a flexible interconnected energy transfer device according to claim 1, characterized in that, The basic turn-on time and basic turn-off time are generated based on the reference duty cycle and the reference carrier phase shift angle, including: Read the preset switching cycle parameters, and generate the basic turn-on time in a disturbance-free state based on the switching cycle parameters, the reference duty cycle and the reference carrier phase shift angle through digital time comparison logic; Based on the switching cycle parameters, the reference duty cycle, and the reference carrier phase shift angle, the basic off time in a disturbance-free state is generated through digital time comparison logic.

9. A timing control strategy for multiple modules of a flexible interconnected energy transfer device according to claim 1, characterized in that, The generation of absolute turn-on and absolute turn-off times by superimposing the disturbance time increment, the turn-on compensation amount, the turn-off compensation amount, and the feedforward timing compensation vector specifically includes: The absolute turn-on edge time is generated by adding the base turn-on time, the turn-on compensation amount, the feedforward timing compensation vector, and the disturbance time increment. The absolute turn-off edge time is generated by adding the base turn-off time, the turn-off compensation amount, and the feedforward timing compensation vector.

10. A timing control strategy for multiple modules of a flexible interconnected energy transfer device according to claim 1, characterized in that, The process of generating the absolute turn-on and absolute turn-off edges and writing them into the register to trigger the drive level to form a control closed loop specifically includes: The generated absolute turn-on edge time and absolute turn-off edge time are converted into corresponding digital count values ​​that can be recognized by the underlying hardware; The corresponding digital count value is written into the phase boundary and dead zone boundary register group of the high-resolution pulse width modulation module in the field programmable gate array processor, and the phase boundary and dead zone boundary register group is the register. The hardware comparison circuit within the field-programmable gate array processor determines the matching status between the real-time count value and the value in the register. When the values ​​match, the drive level of the gate of the power electronic device in the power module is triggered to flip.

Images