A high linearity SAR ADC based on DWA and a running method thereof
By introducing an index vector with adjustable update direction into the SAR ADC, the linearity degradation caused by capacitor mismatch is solved, achieving a high-precision SAR ADC with high linearity and low complexity, and improving signal distortion and noise reduction rate.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- SHANDONG UNIV
- Filing Date
- 2026-02-06
- Publication Date
- 2026-06-12
AI Technical Summary
The linearity of traditional SAR ADCs is severely limited by capacitor mismatch, which leads to increased chip area and reduced energy efficiency. Existing digital calibration techniques are complex and have poor long-term stability, while dynamic component matching techniques in SAR ADCs are complex in structure and have high power consumption.
An index vector with adjustable update direction is introduced. By selecting different weight units with positive and negative pairs, DAC mismatch error is reduced, system complexity is lowered, and it is highly integrated with SAR logic circuits.
It improves the linearity of SAR ADC, reduces system complexity, is suitable for high-precision SAR ADC design, and enhances signal distortion and noise reduction rate.
Smart Images
Figure CN122204040A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to a high linearity SAR ADC based on DWA and its operation method, belonging to the field of analog-to-digital converter technology. Background Technology
[0002] High-precision analog-to-digital converters (ADCs) are core components for implementing high-resolution analog front-end systems, playing a crucial role in medical equipment, test and measurement, and communication systems. Successive approximation register analog-to-digital converters (SAR ADCs) have become an important choice for medium- to high-precision applications due to their simple structure, low power consumption, and ease of integration. However, as resolution increases, the linearity of SAR ADCs is severely limited by the matching accuracy of the internal capacitive digital-to-analog converter (C-DAC). Traditional designs typically improve matching characteristics by increasing the area per unit capacitor, but this leads to a sharp increase in chip area, larger input load, and longer reference voltage settling time, thus affecting overall performance and energy efficiency.
[0003] To overcome the nonlinear errors caused by capacitor mismatch, common solutions include digital calibration and dynamic component matching techniques. Digital calibration estimates and compensates for the actual weight of capacitors through algorithms, which can effectively improve linearity. However, it often requires complex calibration logic, additional storage resources, and long calibration times, increasing system complexity and testing costs. Furthermore, calibration results may drift with environmental factors such as temperature and voltage, posing challenges to long-term stability.
[0004] The Data Weighted Averaging (DWA) algorithm in Dynamic Element Matching (DEM) has been widely used in Sigma Delta ADCs, but its direct application to SAR ADCs faces significant challenges. The main reasons are: firstly, the digital-to-analog converters in SAR ADCs are successive approximation type, generating input codewords bit by bit, with the number of selected units dynamically changing during the conversion process, unlike the flash quantizer in Sigma Delta ADCs which outputs all codewords at once; secondly, the CDAC in SAR ADCs is typically binary, with the weight of the selected unit being either positive or negative, resulting in bidirectional mismatch errors, while traditional DWA targets unit-weighted flash DACs. Therefore, directly applying traditional DWA to SAR ADCs requires an additional coarse ADC to synchronously acquire digital codes, leading to system complexity, increased power consumption, and limiting overall performance advantages. To address these issues, this invention is proposed. Summary of the Invention
[0005] To address the shortcomings of existing technologies, this invention provides a high-linearity SAR ADC based on DWA and its operation method. By introducing an index vector with an adjustable update direction and selecting different weight units based on positive and negative pairs, the linearity reduction of the SAR ADC caused by DAC mismatch error is reduced without relying on a coarse ADC, thus reducing system complexity. It can also be highly integrated with SAR logic circuits and is suitable for the design of high-precision SAR ADCs.
[0006] The technical solution of the present invention is as follows: A high-linearity SAR ADC based on DWA includes a first capacitor array, a second capacitor array, a comparator, a successive approximation register controller, a data weight averaging controller, a first sampling switch, and a second sampling switch, wherein... One end of the first capacitor array is connected to the first sampling switch and the positive input of the comparator, respectively. One end of the second capacitor array is connected to the second sampling switch and the negative input of the comparator, respectively. The first capacitor array and the second capacitor array are respectively connected to one end of the data weight averaging controller and the successive approximation register controller. The other end of the data weight averaging controller and the comparator output are connected to the successive approximation register controller.
[0007] According to a preferred embodiment of the present invention, the first capacitor array comprises binary capacitors CP1, CP2, CP3… CP connected in parallel. N-M-1 1 redundant unit capacitor CP0 and 2 M A parallel thermometer capacitor CP TA-1 To CP T01. First grounding wire, first common-mode voltage line, and first reference voltage line, 2 M A parallel thermometer capacitor CP TA-1 To CP T0 The thermometer's digital-to-analog converter is composed of parallel binary capacitors CP1, CP2, CP3... CP N-M-1 One redundant unit capacitor CP0 and the thermometer code capacitor digital-to-analog converter are connected at one end to the first sampling switch and the positive input of the comparator, and at the other end to the first ground line, the first common-mode voltage line or the first reference voltage line through a switching switch. The switching switch where the thermometer code capacitor digital-to-analog converter is located is connected to the data weight averaging controller, and the switching switch where the binary capacitor and the redundant unit capacitor are located is connected to the successive approximation register controller.
[0008] According to a preferred embodiment of the present invention, capacitors CP0, CP1, CP2, CP3...CP N-M-1 The capacitance values are Cu, Cu, 2Cu, 4Cu, 8Cu...2 N-M-2 Cu, the capacitance value of all capacitors in the thermometer code capacitor digital-to-analog converter is 2. N-M-1 Cu.
[0009] According to a preferred embodiment of the present invention, the second capacitor array comprises binary capacitors CN1, CN2, CN3… CN connected in parallel. N-M-1 1 redundant unit capacitor CP0 and 2 M A parallel thermometer capacitor CN TA-1 To CN T0 1. Second grounding wire, second common-mode voltage line, and second reference voltage line, 2 M A parallel thermometer capacitor CN TA-1 To CN T0 The thermometer's digital-to-analog converter is composed of parallel binary capacitors CN1, CN2, CN3... CN. N-M-1 One redundant unit capacitor CN0 and the thermometer code capacitor digital-to-analog converter are connected to a second sampling switch and the negative input of a comparator at one end, and to a second ground line, a second common-mode voltage line or a second reference voltage line at the other end through a switching switch. The switching switch where the thermometer code capacitor digital-to-analog converter is located is connected to a data weight averaging controller, and the switching switch where the binary capacitor and the redundant unit capacitor are located is connected to a successive approximation register controller.
[0010] According to a preferred embodiment of the present invention, capacitors CN0, CN1, CN2, CN3...CN N-M-1 The capacitance values are Cu, Cu, 2Cu, 4Cu, 8Cu...2 N-M-2 Cu, the capacitance value of all capacitors in the thermometer code capacitor digital-to-analog converter is 2. N-M-1 Cu.
[0011] The successive approximation register controller is used to output the capacitor switching control signals for the first capacitor array and the second capacitor array. The successive approximation register controller is also used to generate the input signal for the data weight averaging controller.
[0012] The data weight averaging controller is used to output control signals for switching the high effective bit capacitors of the first capacitor array and the second capacitor array to control the high effective bit capacitors to be connected to the ground line, common mode voltage line or reference voltage line. The data weight averaging controller is used to output high M-bit switching control signals for the first capacitor array and the second capacitor array to control the thermometer code capacitor digital-to-analog converter to be connected to the ground line, common-mode voltage line, or reference voltage line.
[0013] The above-described operation method for the DWA-based high-linearity SAR ADC consists of the following steps: S21: Connect the first analog input Vip to each capacitor of the first capacitor array, and connect all capacitors of the most significant bit (MSB), the second most significant bit (MSB-1), and the third most significant bit (MSB-2) of the first capacitor array to the common-mode voltage; connect the second analog input Vin to each capacitor of the second capacitor array, and connect all capacitors of the most significant bit (MSB), the second most significant bit (MSB-1), and the third most significant bit (MSB-2) of the second capacitor array to the common-mode voltage; S22: When the first analog input Vip input to the comparator is greater than the second analog input Vin, the most significant bit capacitor of the first capacitor array is grounded to GND, and the most significant bit capacitor of the second capacitor array is connected to the reference voltage Vref. S23: When the first analog input Vip is less than the second analog input Vin, connect the most effective bit capacitor of the first capacitor array to the reference voltage Vref, and connect the most effective bit capacitor of the second capacitor array to ground GND. The reference voltage is twice the common-mode voltage.
[0014] According to a preferred embodiment of the present invention, in step S22: S221: When the difference between the first analog input Vip and the second analog input Vin is greater than 1 / 2 of the reference voltage Vref, the second most effective capacitor of the first capacitor array is grounded to GND, and the second most effective capacitor of the second capacitor array is connected to the reference voltage Vref. S222: When the difference between the first analog input Vip and the second analog input Vin is less than 1 / 2 of the reference voltage Vref, half of the most significant bit of the first capacitor array is connected back to the common-mode voltage Vcm, and half of the most significant bit of the second capacitor array is connected back to the common-mode voltage Vcm.
[0015] According to a preferred embodiment of the present invention, in step S221, the comparator continues to compare: S2211: When the difference between the first analog input Vip and the second analog input Vin is greater than 3 / 4 of the reference voltage Vref, one capacitor of the third most significant bit of the first capacitor array is grounded to GND, and at the same time, one capacitor of the third most significant bit of the second capacitor array is connected to the reference voltage Vref. The comparator continues the comparison: S22111: When the difference between the first analog input Vip and the second analog input Vin is greater than 7 / 8 of the reference voltage Vref, keep all the capacitors of the most significant bit, the second most significant bit, and one capacitor of the third most significant bit of the first capacitor array grounded to GND, while keeping all the capacitors of the most significant bit, the second most significant bit, and one capacitor of the third most significant bit of the second capacitor array connected to the reference voltage Vref. S22112: When the difference between the first analog input Vip and the second analog input Vin is less than 7 / 8 of the reference voltage Vref, one capacitor of the third most significant bit of the first capacitor array is connected back to the common-mode voltage Vcm, and at the same time, one capacitor of the third most significant bit of the second capacitor array is connected back to the common-mode voltage Vcm. After steps S22111 and S22112, the most effective bit capacitor in the next conversion cycle changes and becomes the capacitor connected to the common mode voltage Vcm, and the other capacitors are shifted in sequence. S2212: When the difference between the first analog input Vip and the second analog input Vin is less than 3 / 4 of the reference voltage Vref, half of the capacitors of the second most effective bit of the first capacitor array are connected back to the common mode voltage Vcm, and half of the capacitors of the second most effective bit of the second capacitor array are connected back to the common mode voltage Vcm. The comparator continues the comparison: S22121: When the difference between the first analog input Vip and the second analog input Vin is greater than 5 / 8 of the reference voltage Vref, keep all the capacitors of the most significant bit of the first capacitor array and half of the capacitors of the second most significant bit grounded to GND, and at the same time keep all the capacitors of the most significant bit of the second capacitor array and half of the capacitors of the second most significant bit connected to the reference voltage Vref. S22122: When the difference between the first analog input Vip and the second analog input Vin is less than 5 / 8 of the reference voltage Vref, half of the capacitors of the second most effective bit of the first capacitor array are connected back to the common mode voltage Vcm, and half of the capacitors of the second most effective bit of the second capacitor array are connected back to the common mode voltage Vcm. After steps S22121 and S22122, the most effective bit capacitor of the next conversion cycle changes. The most effective bit capacitor of the next conversion cycle changes to the capacitor connected to the common mode voltage Vcm, and the remaining capacitors are shifted in sequence.
[0016] According to a preferred embodiment of the present invention, in step S222, the comparator continues to compare: S2221: When the difference between the first analog input Vip and the second analog input Vin is greater than 1 / 4 of the reference voltage Vref, the most significant 3 / 4 of the capacitors of the first capacitor array is grounded to GND, and the most significant 3 / 4 of the capacitors of the second capacitor array is connected to the reference voltage Vref. The comparator continues the comparison: S22211: When the difference between the first analog input Vip and the second analog input Vin is greater than 3 / 8 of the reference voltage Vref, keep 3 / 4 of the most significant bit of the first capacitor array grounded to GND, and at the same time keep 3 / 4 of the most significant bit of the second capacitor array connected to the reference voltage Vref. S22212: When the difference between the first analog input Vip and the second analog input Vin is less than 3 / 8 of the reference voltage Vref, connect 1 / 4 of the most significant bit of the first capacitor array back to the common mode voltage Vcm, and at the same time connect 1 / 4 of the most significant bit of the second capacitor array back to the common mode voltage Vcm. After steps S22211 and S22212, the most effective bit capacitor of the next conversion cycle changes, and the capacitor connected to the common mode voltage Vcm becomes the most effective bit capacitor, and the other capacitors are shifted in sequence. S2222: When the difference between the first analog input Vip and the second analog input Vin is less than 1 / 4 of the reference voltage Vref, connect 1 / 4 of the most significant bit of the first capacitor array back to the common mode voltage Vcm, and at the same time connect 1 / 4 of the most significant bit of the second capacitor array back to the common mode voltage Vcm. The comparator continues the comparison: S22221: When the difference between the first analog input Vip and the second analog input Vin is greater than 1 / 8 of the reference voltage Vref, keep 1 / 4 of the most significant bit of the first capacitor array grounded to GND, and at the same time keep 1 / 4 of the most significant bit of the second capacitor array connected to the reference voltage Vref. S22222: When the difference between the first analog input Vip and the second analog input Vin is less than 1 / 8 of the reference voltage Vref, connect 1 / 4 of the most significant bit of the first capacitor array back to the common mode voltage Vcm, and at the same time connect 1 / 4 of the most significant bit of the second capacitor array back to the common mode voltage Vcm. After step S22221, the most significant bit capacitor of the next conversion cycle changes, and the capacitor connected to the common mode voltage Vcm becomes the most significant bit capacitor, and the other capacitors are shifted in sequence. After step S22222, the most significant bit capacitance, the second most significant bit, and the third most significant bit remain unchanged in the next conversion cycle.
[0017] According to a preferred embodiment of the present invention, in step S23, the comparator continues to compare: S231: When the difference between the first analog input Vip and the second analog input Vin is greater than -1 / 2 of the reference voltage Vref, half of the most significant bit of the first capacitor array is connected back to the common mode voltage Vcm, and half of the most significant bit of the second capacitor array is connected back to the common mode voltage Vcm. S232: When the difference between the first analog input Vip and the second analog input Vin is less than -1 / 2 of the reference voltage Vref, connect all the capacitors of the second most significant bit of the first capacitor array to the reference voltage Vref, and at the same time connect all the capacitors of the second most significant bit of the second capacitor array to ground GND.
[0018] According to a preferred embodiment of the present invention, in step S231, the comparator continues to compare: S2311: When the difference between the first analog input Vip and the second analog input Vin is greater than -1 / 4 of the reference voltage Vref, connect 1 / 4 of the most significant bit of the first capacitor array back to the common mode voltage Vcm, and at the same time connect 1 / 4 of the most significant bit of the second capacitor array back to the common mode voltage Vcm. S23111 When the difference between the first analog input Vip and the second analog input Vin is greater than -1 / 8 of the reference voltage Vref, 1 / 4 of the most significant bit of the first capacitor array is connected back to the common mode voltage Vcm, and at the same time, 1 / 4 of the most significant bit of the second capacitor array is connected back to the common mode voltage Vcm. S23112: When the difference between the first analog input Vip and the second analog input Vin is less than -1 / 8 of the reference voltage Vref, keep 1 / 4 of the most significant bit of the first capacitor array connected to the reference voltage Vref, and at the same time keep 1 / 4 of the most significant bit of the second capacitor array grounded to GND. After step S23112, the most significant bit capacitor of the next conversion cycle changes, and the capacitor connected to the common mode voltage Vcm becomes the most significant bit capacitor, and the other capacitors are shifted in sequence. After step S23111, the most significant bit capacitor, the second most significant bit, and the third most significant bit remain unchanged in the next conversion cycle; S2312: When the difference between the first analog input Vip and the second analog input Vin is less than -1 / 4 of the reference voltage Vref, connect 3 / 4 of the most significant bit of the first capacitor array to the reference voltage Vref, and at the same time connect 3 / 4 of the most significant bit of the second capacitor array to ground GND. S23121: When the difference between the first analog input Vip and the second analog input Vin is greater than -3 / 8 of the reference voltage Vref, connect 1 / 4 of the most significant bit of the first capacitor array back to the common mode voltage Vcm, and at the same time connect 1 / 4 of the most significant bit of the second capacitor array back to the common mode voltage Vcm. S23122: When the difference between the first analog input Vip and the second analog input Vin is less than -3 / 8 of the reference voltage Vref, keep 3 / 4 of the most significant bit of the first capacitor array connected to the reference voltage Vref, and at the same time keep 3 / 4 of the most significant bit of the second capacitor array grounded to GND. After steps S23121 and S23122, the most effective bit capacitor of the next conversion cycle changes. The most effective bit capacitor of the next conversion cycle changes to the capacitor connected to the common mode voltage Vcm, and the remaining capacitors are shifted in sequence.
[0019] According to a preferred embodiment of the present invention, in step S232, the comparator continues to compare: S2321: When the difference between the first analog input Vip and the second analog input Vin is greater than -3 / 4 of the reference voltage Vref, half of the capacitors of the second most effective bit of the first capacitor array are connected back to the common mode voltage Vcm, and half of the capacitors of the second most effective bit of the second capacitor array are connected back to the common mode voltage Vcm. S23211: When the difference between the first analog input Vip and the second analog input Vin is greater than -5 / 8 of the reference voltage Vref, half of the capacitors of the second most effective bit of the first capacitor array are connected back to the common mode voltage Vcm, and half of the capacitors of the second most effective bit of the second capacitor array are connected back to the common mode voltage Vcm. S23212: When the difference between the first analog input Vip and the second analog input Vin is less than -5 / 8 of the reference voltage Vref, keep all the capacitors of the most significant bit of the first capacitor array and half of the capacitors of the second most significant bit connected to the reference voltage Vref, and at the same time keep all the capacitors of the most significant bit of the second capacitor array and half of the capacitors of the second most significant bit grounded to GND. After steps S23211 and S23212, the most effective bit capacitor of the next conversion cycle changes, and the capacitor connected to the common mode voltage Vcm becomes the most effective bit capacitor, and the other capacitors are shifted in sequence. S2322: When the difference between the first analog input Vip and the second analog input Vin is less than -3 / 4 of the reference voltage Vref, connect one capacitor of the third most significant bit of the first capacitor array to the reference voltage Vref, and at the same time connect one capacitor of the third most significant bit of the second capacitor array to ground GND. S23221: When the difference between the first analog input Vip and the second analog input Vin is greater than -7 / 8 of the reference voltage Vref, connect one capacitor of the third most significant bit of the first capacitor array back to the common-mode voltage Vcm, and at the same time connect one capacitor of the third most significant bit of the second capacitor array back to the common-mode voltage Vcm. S23222: When the difference between the first analog input Vip and the second analog input Vin is less than -7 / 8 of the reference voltage Vref, keep all the capacitors of the most significant bit, the second most significant bit, and one capacitor of the third most significant bit of the first capacitor array connected to the reference voltage Vref, while keeping all the capacitors of the most significant bit, the second most significant bit, and one capacitor of the third most significant bit of the second capacitor array grounded to GND.
[0020] After steps S23221 and S23222, the most effective bit capacitor of the next conversion cycle changes. The most effective bit capacitor of the next conversion cycle changes to the capacitor connected to the common mode voltage Vcm, and the remaining capacitors are shifted in sequence.
[0021] Figure 3 This graph compares the dynamic performance of a 14-bit successive approximation register analog-to-digital converter (SPD) using the DWA algorithm for the first five most significant bits (MSB~MSB-4) and the traditional MCS switching strategy for the remaining significant bits, at a relative mismatch of 5% per unit capacitor. The horizontal axis represents amplitude in dB, and the vertical axis represents the probability of occurrence. The comparison shows that this invention improves the average SFDR from 75dB to 86dB and the average SNDR from 69dB to 73dB, effectively enhancing the SFDR and SNDR of the successive approximation register analog-to-digital converter.
[0022] The beneficial effects of this invention are as follows: This invention introduces an index vector with an adjustable update direction. By selecting different weight units based on positive and negative pairs, it reduces the linearity decrease of the SAR ADC caused by DAC mismatch error without relying on a coarse ADC, thereby reducing system complexity. It can also be highly integrated with SAR logic circuits and is suitable for the design of high-precision SAR ADCs. Attached Figure Description
[0023] Figure 1This is a schematic diagram of the structure of the present invention; Figure 2 This is a schematic diagram of step S22 of the present invention; Figure 3 This is a schematic diagram of step S23 of the present invention; Figure 4 This is a comparison chart of the dynamic performance of the present invention and existing MCS switching methods, wherein, Figure 4 (a) is a statistical histogram of SFDR for the MCS capacitor switching strategy under 500 different capacitor mismatch values; Figure 4 (b) is a statistical histogram of SNDR for the MCS capacitor switching strategy under 500 different capacitor mismatch values. Figure 4 (c) is the statistical histogram of SFDR of the present invention under 500 different capacitor mismatch values. Figure 4 (d) is a statistical histogram of the SNDR of the present invention under 500 different capacitor mismatch values.
[0024] Wherein: 1. First capacitor array; 2. Second capacitor array; 3. First ground line; 4. First common-mode voltage line; 5. First reference voltage line; 6. Second ground line; 7. Second common-mode voltage line; 8. Second reference voltage line; 9. Comparator; 10. Successive approximation register controller; 11. Data weight averaging controller; 12. First sampling switch; 13. Second sampling switch; 14. Thermometer code capacitor digital-to-analog converter. Detailed Implementation
[0025] The present invention will be further described below with reference to the embodiments and accompanying drawings, but is not limited thereto.
[0026] Example 1: like Figure 1 As shown, this embodiment provides a high-linearity SAR ADC based on DWA, including a first capacitor array 1, a second capacitor array 2, a comparator 9, a successive approximation register controller 10, a data weight averaging controller 11, a first sampling switch 12, and a second sampling switch 13, wherein... One end of the first capacitor array 1 is connected to the positive input terminal of the first sampling switch 12 and the comparator 9, respectively. One end of the second capacitor array 2 is connected to the negative input terminal of the second sampling switch 13 and the comparator 9, respectively. The first capacitor array 1 and the second capacitor array 2 are respectively connected to one end of the data weight averaging controller 11 and the successive approximation register controller 10. The other end of the data weight averaging controller 11 and the output terminal of the comparator 9 are connected to the successive approximation register controller 10.
[0027] The first capacitor array 1 includes parallel binary capacitors CP1, CP2, CP3... CP N-M-1 1 redundant unit capacitor CP0 and 2M A parallel thermometer capacitor CP TA-1 To CP T0 1. First grounding wire 3, first common-mode voltage line 4, and first reference voltage line 5, 2 M A parallel thermometer capacitor CP TA-1 To CP T0 The thermometer code capacitor digital-to-analog converter 14 consists of binary capacitors CP1, CP2, CP3… connected in parallel. N-M-1 One end of the redundant unit capacitor CP0 and the thermometer code capacitor digital-to-analog converter 14 is connected to the first sampling switch and the positive input terminal of the comparator 9, and the other end is connected to the first ground line, the first common mode voltage line or the first reference voltage line through a switching switch. The switching switch where the thermometer code capacitor digital-to-analog converter 14 is located is connected to the data weight averaging controller 11, and the switching switch where the binary capacitor and the redundant unit capacitor are located is connected to the successive approximation register controller 10.
[0028] Capacitors CP0, CP1, CP2, CP3...CP N-M-1 The capacitance values are Cu, Cu, 2Cu, 4Cu, 8Cu...2 N-M-2 Cu, the capacitance value of all capacitors in the thermometer code capacitor digital-to-analog converter 14 is 2. N-M-1 Cu.
[0029] The second capacitor array 2 includes parallel binary capacitors CN1, CN2, CN3… CN N-M-1 1 redundant unit capacitor CP0 and 2 M A parallel thermometer capacitor CN TA-1 To CN T0 6. Second grounding wire, 7. Second common mode voltage line, 8. Second reference voltage line, 2 M A parallel thermometer capacitor CN TA-1 To CN T0 The thermometer's digital-to-analog converter is composed of parallel binary capacitors CN1, CN2, CN3... CN. N-M-1 One end of the redundant unit capacitor CN0 and the thermometer code capacitor digital-to-analog converter is connected to the negative input terminal of the second sampling switch 13 and the comparator 9, and the other end is connected to the second ground line 6, the second common mode voltage line 7 or the second reference voltage line 8 through a switching switch. The switching switch where the thermometer code capacitor digital-to-analog converter is located is connected to the data weight averaging controller 11, and the switching switch where the binary capacitor and the redundant unit capacitor are located is connected to the successive approximation register controller 10.
[0030] Capacitors CN0, CN1, CN2, CN3...CN N-M-1 The capacitance values are Cu, Cu, 2Cu, 4Cu, 8Cu...2 N-M-2Cu, the capacitance value of all capacitors in the thermometer code capacitor digital-to-analog converter is 2. N-M-1 Cu.
[0031] The successive approximation register controller is used to output the capacitor switching control signals for the first capacitor array and the second capacitor array. The successive approximation register controller is also used to generate the input signal for the data weight averaging controller.
[0032] The data weight averaging controller is used to output control signals for switching the high effective bit capacitors of the first capacitor array and the second capacitor array to control the high effective bit capacitors to be connected to the ground line, common mode voltage line or reference voltage line. The data weight averaging controller is used to output high M-bit switching control signals for the first capacitor array and the second capacitor array to control the thermometer code capacitor digital-to-analog converter to be connected to the ground line, common-mode voltage line, or reference voltage line.
[0033] The above-described operation method for the DWA-based high-linearity SAR ADC consists of the following steps: S21: Connect the first analog input Vip to each capacitor of the first capacitor array, and simultaneously connect the four capacitors of the most significant bit (MSB), the two capacitors of the second most significant bit (MSB-1), and the one capacitor of the third most significant bit (MSB-2) of the first capacitor array to the common-mode voltage; connect the second analog input Vin to each capacitor of the second capacitor array, and simultaneously connect the four capacitors of the most significant bit (MSB), the two capacitors of the second most significant bit (MSB-1), and the one capacitor of the third most significant bit (MSB-2) of the second capacitor array to the common-mode voltage; S22: When the first analog input Vip to the comparator is greater than the second analog input Vin, the four capacitors of the most significant bit of the first capacitor array are grounded to GND, and the four capacitors of the most significant bit of the second capacitor array are connected to the reference voltage Vref. Figure 2 Step S22).
[0034] S23: When the first analog input Vip is less than the second analog input Vin, connect the four most significant bits of the first capacitor array to the reference voltage Vref, and connect the four most significant bits of the second capacitor array to ground GND. Figure 3 In step S23), the reference voltage is twice the common-mode voltage.
[0035] In step S22: S221: When the difference between the first analog input Vip and the second analog input Vin is greater than 1 / 2 of the reference voltage Vref, the two capacitors of the second most significant bit of the first capacitor array are grounded to GND, and the two capacitors of the second most significant bit of the second capacitor array are connected to the reference voltage Vref. Figure 2 Step S221); S222: When the difference between the first analog input Vip and the second analog input Vin is less than 1 / 2 of the reference voltage Vref, connect the two most significant bits of the first capacitor array back to the common-mode voltage Vcm, and simultaneously connect the two most significant bits of the second capacitor array back to the common-mode voltage Vcm. Figure 2 Step S222).
[0036] In step S221, the comparator continues the comparison: S2211: When the difference between the first analog input Vip and the second analog input Vin is greater than 3 / 4 of the reference voltage Vref, one capacitor of the third most significant bit of the first capacitor array is grounded to GND, and simultaneously one capacitor of the third most significant bit of the second capacitor array is connected to the reference voltage Vref. Figure 2 Step S2211); The comparator continues the comparison: S22111: When the difference between the first analog input Vip and the second analog input Vin is greater than 7 / 8 of the reference voltage Vref, keep the four capacitors of the most significant bit, the two capacitors of the second most significant bit, and the one capacitor of the third most significant bit of the first capacitor array grounded to GND, while keeping the four capacitors of the most significant bit, the two capacitors of the second most significant bit, and the one capacitor of the third most significant bit of the second capacitor array connected to the reference voltage Vref. Figure 2 Step S22111); S22112: When the difference between the first analog input Vip and the second analog input Vin is less than 7 / 8 of the reference voltage Vref, connect one capacitor of the third most significant bit (MSB-2) of the first capacitor array back to the common-mode voltage Vcm, and simultaneously connect one capacitor of the third most significant bit of the second capacitor array back to the common-mode voltage Vcm. Figure 2 Step S22112); After step S22111, the most significant bit (MSB) capacitor of the next conversion cycle changes, and the capacitor connected to the common-mode voltage Vcm becomes the first MSB capacitor. The remaining capacitors are shifted sequentially. For example, the first to fourth capacitors are MSB, the fifth to sixth capacitors are MSB-1, the seventh capacitor is MSB-2, and the eighth capacitor combines the first to third capacitors being MSB, the fourth to fifth capacitors being MSB-1, and the sixth capacitor being MSB-2.
[0037] After step S22112, the most significant bit (MSB) capacitor of the next conversion cycle changes, and the capacitor connected to the common mode voltage Vcm becomes the most significant bit capacitor. The remaining capacitors are shifted sequentially. For example, from the first capacitor to the fourth capacitor is the MSB, from the fifth capacitor to the sixth capacitor is the MSB-1, and from the seventh capacitor is the MSB-2. Then, from the seventh capacitor to the eighth capacitor, the first capacitor to the second capacitor is the MSB, from the third capacitor to the fourth capacitor is the MSB-1, and from the fifth capacitor is the MSB-2.
[0038] S2212: When the difference between the first analog input Vip and the second analog input Vin is less than 3 / 4 of the reference voltage Vref, connect one capacitor of the second most significant bit of the first capacitor array back to the common-mode voltage Vcm, and simultaneously connect one capacitor of the second most significant bit of the second capacitor array back to the common-mode voltage Vcm. Figure 2 Step S2212); The comparator continues the comparison: S22121: When the difference between the first analog input Vip and the second analog input Vin is greater than 5 / 8 of the reference voltage Vref, the four capacitors of the most significant bit of the first capacitor array and one capacitor of the second most significant bit are grounded to GND. Simultaneously, the four capacitors of the most significant bit of the second capacitor array and one capacitor of the second most significant bit are connected to the reference voltage Vref. Figure 2 Step S22121); S22122: When the difference between the first analog input Vip and the second analog input Vin is less than 5 / 8 of the reference voltage Vref, connect one capacitor of the second most significant bit of the first capacitor array back to the common-mode voltage Vcm, and simultaneously connect one capacitor of the second most significant bit of the second capacitor array back to the common-mode voltage Vcm. Figure 2 Step S22122); After step S22121, the most significant bit (MSB) capacitor of the next conversion cycle changes. It becomes the capacitor connected to the common mode voltage Vcm that is initially the MSB capacitor, and then the four capacitors are sequentially shifted. For example, from the first capacitor to the fourth capacitor is MSB, from the fifth capacitor to the sixth capacitor is MSB-1, and from the seventh capacitor is MSB-2. Then, from the sixth capacitor to the eighth capacitor, the first capacitor is combined with MSB, from the second capacitor to the third capacitor is MSB-1, and from the fourth capacitor is MSB-2.
[0039] After step S22122, the most significant bit (MSB) capacitor of the next conversion cycle changes, and the capacitor connected to the common mode voltage Vcm becomes the most significant bit capacitor. The remaining capacitors are shifted sequentially. For example, from the first capacitor to the fourth capacitor is the MSB, from the fifth capacitor to the sixth capacitor is the MSB-1, and from the seventh capacitor is the MSB-2. Then, from the fifth capacitor to the eighth capacitor is the MSB, from the first capacitor to the second capacitor is the MSB-1, and from the third capacitor is the MSB-2.
[0040] In step S222, the comparator continues the comparison: S2221: When the difference between the first analog input Vip and the second analog input Vin is greater than 1 / 4 of the reference voltage Vref, the three capacitors of the most significant bit of the first capacitor array are grounded to GND, and the three capacitors of the most significant bit of the second capacitor array are connected to the reference voltage Vref. Figure 2 Step S2221); The comparator continues the comparison: S22211: When the difference between the first analog input Vip and the second analog input Vin is greater than 3 / 8 of the reference voltage Vref, keep the three capacitors of the most significant bit of the first capacitor array grounded to GND, and at the same time keep the three capacitors of the most significant bit of the second capacitor array connected to the reference voltage Vref. Figure 2 Step S22211); S22212: When the difference between the first analog input Vip and the second analog input Vin is less than 3 / 8 of the reference voltage Vref, connect one capacitor of the most significant bit of the first capacitor array back to the common-mode voltage Vcm, and simultaneously connect one capacitor of the most significant bit of the second capacitor array back to the common-mode voltage Vcm. Figure 2 Step S22212); After step S22211, the most significant bit (MSB) capacitor of the next conversion cycle changes. It becomes the capacitor connected to the common mode voltage Vcm, starting as the first capacitor, and then the next four capacitors are shifted sequentially. For example, the first to the fourth capacitor are MSB, the fifth to the sixth capacitor are MSB-1, and the seventh capacitor is MSB-2. Then, the fourth to the seventh capacitor are MSB, and the eighth capacitor is combined with the first capacitor as MSB-1 and the second capacitor as MSB-2.
[0041] After step S22212, the most significant bit (MSB) capacitor of the next conversion cycle changes. It becomes the capacitor connected to the common mode voltage Vcm that starts as the first one, and then the next four capacitors are shifted sequentially. For example, the first to fourth capacitors are MSB, the fifth to sixth capacitors are MSB-1, and the seventh capacitor is MSB-2. Then it becomes the third to sixth capacitors are MSB, the seventh to eighth capacitors are MSB-1, and the first capacitor is MSB-2.
[0042] S2222: When the difference between the first analog input Vip and the second analog input Vin is less than 1 / 4 of the reference voltage Vref, connect one capacitor of the most significant bit of the first capacitor array back to the common-mode voltage Vcm, and simultaneously connect one capacitor of the most significant bit of the second capacitor array back to the common-mode voltage Vcm. Figure 2 Step S2222); The comparator continues the comparison: S22221: When the difference between the first analog input Vip and the second analog input Vin is greater than 1 / 8 of the reference voltage Vref, keep one capacitor of the most significant bit of the first capacitor array grounded to GND, and simultaneously keep one capacitor of the most significant bit of the second capacitor array connected to the reference voltage Vref. Figure 2 Step S22221); S22222: When the difference between the first analog input Vip and the second analog input Vin is less than 1 / 8 of the reference voltage Vref, connect one capacitor of the most significant bit of the first capacitor array back to the common-mode voltage Vcm, and simultaneously connect one capacitor of the most significant bit of the second capacitor array back to the common-mode voltage Vcm. Figure 2 Step S22222); After step S22221, the most significant bit (MSB) capacitor of the next conversion cycle changes. It becomes the capacitor connected to the common mode voltage Vcm, starting as the first capacitor, and then the next four capacitors are shifted sequentially. For example, the first to the fourth capacitor is MSB, the fifth to the sixth capacitor is MSB-1, and the seventh capacitor is MSB-2. Then, the second to the fifth capacitor is MSB, the sixth to the seventh capacitor is MSB-1, and the eighth capacitor is MSB-2.
[0043] After step S22222, the most significant bit (MSB), the second most significant bit (MSB-1), and the third most significant bit (MSB-2) remain unchanged in the next conversion cycle.
[0044] In step S23, the comparator continues the comparison: S231: When the difference between the first analog input Vip and the second analog input Vin is greater than -1 / 2 of the reference voltage Vref, connect the two most significant bits of the first capacitor array back to the common-mode voltage Vcm, and simultaneously connect the two most significant bits of the second capacitor array back to the common-mode voltage Vcm. Figure 3 Step S231); S232: When the difference between the first analog input Vip and the second analog input Vin is less than -1 / 2 of the reference voltage Vref, connect the two capacitors of the second most significant bit of the first capacitor array to the reference voltage Vref, and simultaneously ground the two capacitors of the second most significant bit of the second capacitor array to GND. Figure 3 Step S232).
[0045] In step S231, the comparator continues the comparison: S2311: When the difference between the first analog input Vip and the second analog input Vin is greater than -1 / 4 of the reference voltage Vref, connect one capacitor of the most significant bit of the first capacitor array back to the common-mode voltage Vcm, and simultaneously connect one capacitor of the most significant bit of the second capacitor array back to the common-mode voltage Vcm. Figure 3 Step S2311); S23111 When the difference between the first analog input Vip and the second analog input Vin is greater than -1 / 8 of the reference voltage Vref, connect one capacitor of the most significant bit of the first capacitor array back to the common-mode voltage Vcm, and simultaneously connect one capacitor of the most significant bit of the second capacitor array back to the common-mode voltage Vcm. Figure 3 Step S23111); S23112: When the difference between the first analog input Vip and the second analog input Vin is less than -1 / 8 of the reference voltage Vref, keep one capacitor of the most significant bit of the first capacitor array connected to the reference voltage Vref, and simultaneously keep one capacitor of the most significant bit of the second capacitor array grounded to GND. Figure 3 Step S23112); After step S23112, the most significant bit (MSB) capacitance of the next conversion cycle changes. It becomes the capacitor connected to the common mode voltage Vcm, starting as the first capacitor, and then the next four capacitors are shifted sequentially. For example, the first to the fourth capacitor is MSB, the fifth to the sixth capacitor is MSB-1, and the seventh capacitor is MSB-2. Then, the second to the fifth capacitor is MSB, the sixth to the seventh capacitor is MSB-1, and the eighth capacitor is MSB-2.
[0046] After step S23111, the most significant bit (MSB), the second most significant bit (MSB-1), and the third most significant bit (MSB-2) remain unchanged in the next conversion cycle.
[0047] S2312: When the difference between the first analog input Vip and the second analog input Vin is less than -1 / 4 of the reference voltage Vref, connect the three most significant bits of the first capacitor array to the reference voltage Vref, and simultaneously ground the three most significant bits of the second capacitor array to GND. Figure 3 Step S2312); S23121: When the difference between the first analog input Vip and the second analog input Vin is greater than -3 / 8 of the reference voltage Vref, connect one capacitor of the most significant bit of the first capacitor array back to the common-mode voltage Vcm, and simultaneously connect one capacitor of the most significant bit of the second capacitor array back to the common-mode voltage Vcm. Figure 3 Step S23121); S23122: When the difference between the first analog input Vip and the second analog input Vin is less than -3 / 8 of the reference voltage Vref, keep the three most significant bits of the first capacitor array connected to the reference voltage Vref, and simultaneously keep the three most significant bits of the second capacitor array grounded GND. Figure 3 Step S23122); After step S23122, the most significant bit (MSB) capacitor of the next conversion cycle changes. It becomes the capacitor connected to the common mode voltage Vcm, starting as the first capacitor, and then the next four capacitors are shifted sequentially. For example, the first to the fourth capacitor are MSB, the fifth to the sixth capacitor are MSB-1, and the seventh capacitor is MSB-2. Then, the fourth to the seventh capacitor are MSB, and the eighth capacitor is combined with the first capacitor as MSB-1 and the second capacitor as MSB-2.
[0048] After step S23121, the most significant bit (MSB) capacitor of the next conversion cycle changes. It becomes the capacitor connected to the common mode voltage Vcm that is first, and then the next four capacitors are shifted sequentially. For example, the first to fourth capacitors are MSB, the fifth to sixth capacitors are MSB-1, and the seventh capacitor is MSB-2. Then the third to sixth capacitors are MSB, the seventh to eighth capacitors are MSB-1, and the first capacitor is MSB-2.
[0049] In step S232, the comparator continues the comparison: S2321: When the difference between the first analog input Vip and the second analog input Vin is greater than -3 / 4 of the reference voltage Vref, connect one capacitor of the second most significant bit of the first capacitor array back to the common-mode voltage Vcm, and simultaneously connect one capacitor of the second most significant bit of the second capacitor array back to the common-mode voltage Vcm. Figure 3 Step S2321); S23211: When the difference between the first analog input Vip and the second analog input Vin is greater than -5 / 8 of the reference voltage Vref, connect one capacitor of the second most significant bit of the first capacitor array back to the common-mode voltage Vcm, and simultaneously connect one capacitor of the second most significant bit of the second capacitor array back to the common-mode voltage Vcm. Figure 3 Step S23211); S23212: When the difference between the first analog input Vip and the second analog input Vin is less than -5 / 8 of the reference voltage Vref, keep the four most significant bits of the first capacitor array and one capacitor of the second most significant bit connected to the reference voltage Vref, and simultaneously keep the four most significant bits of the second capacitor array and one capacitor of the second most significant bit grounded to GND. Figure 3 Step S23212); After step S23212, the most significant bit (MSB) capacitor of the next conversion cycle changes. It becomes the capacitor connected to the common mode voltage Vcm, starting as the first capacitor, and then the next four capacitors are shifted sequentially. For example, the first to the fourth capacitor is the MSB, the fifth to the sixth capacitor is MSB-1, and the seventh capacitor is MSB-2. Then, the sixth to the eighth capacitors are combined with the first capacitor as the MSB, the second to the third capacitor is MSB-1, and the fourth capacitor is MSB-2.
[0050] After step S23211, the most significant bit (MSB) capacitance of the next conversion cycle changes. It becomes that the capacitor connected to the common mode voltage Vcm starts as the first one, and the next four capacitors are shifted sequentially. For example, the first to the fourth capacitor is MSB, the fifth to the sixth capacitor is MSB-1, and the seventh capacitor is MSB-2. Then it becomes that the fifth to the eighth capacitor is MSB, the first to the second capacitor is MSB-1, and the third capacitor is MSB-2. S2322: When the difference between the first analog input Vip and the second analog input Vin is less than -3 / 4 of the reference voltage Vref, connect one capacitor of the third most significant bit of the first capacitor array to the reference voltage Vref, and simultaneously ground one capacitor of the third most significant bit of the second capacitor array to GND. Figure 3 Step S2322); S23221: When the difference between the first analog input Vip and the second analog input Vin is greater than -7 / 8 of the reference voltage Vref, connect one capacitor of the third most significant bit of the first capacitor array back to the common-mode voltage Vcm, and simultaneously connect one capacitor of the third most significant bit of the second capacitor array back to the common-mode voltage Vcm. Figure 3 Step S23221); S23222: When the difference between the first analog input Vip and the second analog input Vin is less than -7 / 8 of the reference voltage Vref, keep the four capacitors of the most significant bit, the two capacitors of the second most significant bit, and the one capacitor of the third most significant bit of the first capacitor array connected to the reference voltage Vref, while keeping the four capacitors of the most significant bit, the two capacitors of the second most significant bit, and the one capacitor of the third most significant bit of the second capacitor array grounded to GND. Figure 3 Step S23222).
[0051] After step S23222, the most significant bit (MSB) capacitor of the next conversion cycle changes. It becomes the capacitor connected to the common mode voltage Vcm, starting as the first capacitor, and then the next four capacitors are shifted sequentially. For example, the first to the fourth capacitor is the MSB, the fifth to the sixth capacitor is the MSB-1, the seventh capacitor is the MSB-2, and the eighth capacitor combines the first to the third capacitor as the MSB, the fourth to the fifth capacitor as the MSB-1, and the sixth capacitor as the MSB-2.
[0052] After step S23221, the most significant bit (MSB) of the next conversion cycle changes. It becomes the capacitor connected to the common mode voltage Vcm that starts as the first capacitor, and then the next four capacitors are shifted sequentially. For example, the MSB is from the first capacitor to the fourth capacitor, the MSB is from the fifth capacitor to the sixth capacitor, and the MSB is from the seventh capacitor. Then, the MSB is from the seventh capacitor to the eighth capacitor combined with the MSB is from the first capacitor to the second capacitor, the MSB is from the third capacitor to the fourth capacitor, and the MSB is from the fifth capacitor.
[0053] Figure 4 This graph compares the dynamic performance of a 14-bit successive approximation register analog-to-digital converter (SPD) using the DWA algorithm for the first five most significant bits (MSB~MSB-4) and the traditional MCS switching strategy for the remaining significant bits, at a relative mismatch of 5% per unit capacitor. The horizontal axis represents amplitude in dB, and the vertical axis represents the probability of occurrence. The comparison shows that this invention improves the average SFDR from 75dB to 86dB and the average SNDR from 69dB to 73dB, effectively enhancing the SFDR and SNDR of the successive approximation register analog-to-digital converter.
Claims
1. A high-linearity SAR ADC based on DWA, characterized in that, It includes a first capacitor array, a second capacitor array, a comparator, a successive approximation register controller, a data weight averaging controller, a first sampling switch, and a second sampling switch, wherein, One end of the first capacitor array is connected to the first sampling switch and the positive input of the comparator, respectively. One end of the second capacitor array is connected to the second sampling switch and the negative input of the comparator, respectively. The first capacitor array and the second capacitor array are respectively connected to one end of the data weight averaging controller and the successive approximation register controller. The other end of the data weight averaging controller and the comparator output are connected to the successive approximation register controller.
2. The high linearity SAR ADC based on DWA as described in claim 1, characterized in that, The first capacitor array includes parallel binary capacitors CP1, CP2, CP3… CP N-M-1 1 redundant unit capacitor CP0 and 2 M A parallel thermometer capacitor CP TA-1 To CP T0 1. First grounding wire, first common-mode voltage line, and first reference voltage line, 2 M A parallel thermometer capacitor CP TA-1 To CP T0 The thermometer's digital-to-analog converter is composed of parallel binary capacitors CP1, CP2, CP3... CP N-M-1 One redundant unit capacitor CP0 and a thermometer code capacitor digital-to-analog converter are connected to a first sampling switch and the positive input of a comparator at one end, and the other end is connected to a first ground line, a first common-mode voltage line or a first reference voltage line through a switching switch. The switching switch where the thermometer code capacitor digital-to-analog converter is located is connected to a data weight averaging controller. The switching switch where the binary capacitor and the redundant unit capacitor are located is connected to a successive approximation register controller. Capacitors CP0, CP1, CP2, CP3...CP N-M-1 The capacitance values are Cu, Cu, 2Cu, 4Cu, 8Cu...2 N-M-2 Cu, the capacitance value of all capacitors in the thermometer code capacitor digital-to-analog converter is 2. N-M-1 Cu.
3. The high linearity SAR ADC based on DWA as described in claim 2, characterized in that, The second capacitor array includes parallel binary capacitors CN1, CN2, CN3… CN N-M-1 1 redundant unit capacitor CP0 and 2 M A parallel thermometer capacitor CN TA-1 To CN T0 1. Second grounding wire, second common-mode voltage line, and second reference voltage line, 2 M A parallel thermometer capacitor CN TA-1 To CN T0 The thermometer's digital-to-analog converter is composed of parallel binary capacitors CN1, CN2, CN3... CN. N-M-1 One redundant unit capacitor CN0 and a thermometer code capacitor digital-to-analog converter are connected to a second sampling switch and the negative input of a comparator at one end, and the other end is connected to a second ground line, a second common-mode voltage line or a second reference voltage line through a switching switch. The switching switch where the thermometer code capacitor digital-to-analog converter is located is connected to a data weight averaging controller. The switching switch where the binary capacitor and the redundant unit capacitor are located is connected to a successive approximation register controller. Capacitors CN0, CN1, CN2, CN3...CN N-M-1 The capacitance values are Cu, Cu, 2Cu, 4Cu, 8Cu...2 N-M-2 Cu, the capacitance value of all capacitors in the thermometer code capacitor digital-to-analog converter is 2. N-M-1 Cu.
4. The operation method of the DWA-based high-linearity SAR ADC as described in claim 3, characterized in that, The steps are as follows: S21: Connect the first analog input Vip to each capacitor of the first capacitor array, and connect all capacitors of the most significant bit, the second most significant bit, and the third most significant bit of the first capacitor array to the common mode voltage. Connect the second analog input Vin to each capacitor of the second capacitor array, and connect all capacitors of the most significant bit, the second most significant bit, and the third most significant bit of the second capacitor array to the common mode voltage. S22: When the first analog input Vip input to the comparator is greater than the second analog input Vin, the most significant bit capacitor of the first capacitor array is grounded to GND, and the most significant bit capacitor of the second capacitor array is connected to the reference voltage Vref. S23: When the first analog input Vip is less than the second analog input Vin, connect the most effective bit capacitor of the first capacitor array to the reference voltage Vref, and connect the most effective bit capacitor of the second capacitor array to ground GND. The reference voltage is twice the common-mode voltage.
5. The operation method of the DWA-based high-linearity SAR ADC as described in claim 4, characterized in that, In step S22: S221: When the difference between the first analog input Vip and the second analog input Vin is greater than 1 / 2 of the reference voltage Vref, the second most effective capacitor of the first capacitor array is grounded to GND, and the second most effective capacitor of the second capacitor array is connected to the reference voltage Vref. S222: When the difference between the first analog input Vip and the second analog input Vin is less than 1 / 2 of the reference voltage Vref, half of the most significant bit of the first capacitor array is connected back to the common-mode voltage Vcm, and half of the most significant bit of the second capacitor array is connected back to the common-mode voltage Vcm.
6. The operation method of the DWA-based high-linearity SAR ADC as described in claim 5, characterized in that, In step S221, the comparator continues the comparison: S2211: When the difference between the first analog input Vip and the second analog input Vin is greater than 3 / 4 of the reference voltage Vref, one capacitor of the third most significant bit of the first capacitor array is grounded to GND, and at the same time, one capacitor of the third most significant bit of the second capacitor array is connected to the reference voltage Vref. The comparator continues the comparison: S22111: When the difference between the first analog input Vip and the second analog input Vin is greater than 7 / 8 of the reference voltage Vref, keep all the capacitors of the most significant bit, the second most significant bit, and one capacitor of the third most significant bit of the first capacitor array grounded to GND, while keeping all the capacitors of the most significant bit, the second most significant bit, and one capacitor of the third most significant bit of the second capacitor array connected to the reference voltage Vref. S22112: When the difference between the first analog input Vip and the second analog input Vin is less than 7 / 8 of the reference voltage Vref, one capacitor of the third most significant bit of the first capacitor array is connected back to the common-mode voltage Vcm, and at the same time, one capacitor of the third most significant bit of the second capacitor array is connected back to the common-mode voltage Vcm. After steps S22111 and S22112, the most effective bit capacitor in the next conversion cycle changes and becomes the capacitor connected to the common mode voltage Vcm, and the other capacitors are shifted in sequence. S2212: When the difference between the first analog input Vip and the second analog input Vin is less than 3 / 4 of the reference voltage Vref, half of the capacitors of the second most effective bit of the first capacitor array are connected back to the common mode voltage Vcm, and half of the capacitors of the second most effective bit of the second capacitor array are connected back to the common mode voltage Vcm. The comparator continues the comparison: S22121: When the difference between the first analog input Vip and the second analog input Vin is greater than 5 / 8 of the reference voltage Vref, keep all the capacitors of the most significant bit of the first capacitor array and half of the capacitors of the second most significant bit grounded to GND, and at the same time keep all the capacitors of the most significant bit of the second capacitor array and half of the capacitors of the second most significant bit connected to the reference voltage Vref. S22122: When the difference between the first analog input Vip and the second analog input Vin is less than 5 / 8 of the reference voltage Vref, half of the capacitors of the second most effective bit of the first capacitor array are connected back to the common mode voltage Vcm, and half of the capacitors of the second most effective bit of the second capacitor array are connected back to the common mode voltage Vcm. After steps S22121 and S22122, the most effective bit capacitor of the next conversion cycle changes. The most effective bit capacitor of the next conversion cycle changes to the capacitor connected to the common mode voltage Vcm, and the remaining capacitors are shifted in sequence.
7. The operation method of the DWA-based high-linearity SAR ADC as described in claim 6, characterized in that, In step S222, the comparator continues the comparison: S2221: When the difference between the first analog input Vip and the second analog input Vin is greater than 1 / 4 of the reference voltage Vref, the most significant 3 / 4 of the capacitors of the first capacitor array is grounded to GND, and the most significant 3 / 4 of the capacitors of the second capacitor array is connected to the reference voltage Vref. The comparator continues the comparison: S22211: When the difference between the first analog input Vip and the second analog input Vin is greater than 3 / 8 of the reference voltage Vref, keep 3 / 4 of the most significant bit of the first capacitor array grounded to GND, and at the same time keep 3 / 4 of the most significant bit of the second capacitor array connected to the reference voltage Vref. S22212: When the difference between the first analog input Vip and the second analog input Vin is less than 3 / 8 of the reference voltage Vref, connect 1 / 4 of the most significant bit of the first capacitor array back to the common mode voltage Vcm, and at the same time connect 1 / 4 of the most significant bit of the second capacitor array back to the common mode voltage Vcm. After steps S22211 and S22212, the most effective bit capacitor of the next conversion cycle changes, and the capacitor connected to the common mode voltage Vcm becomes the most effective bit capacitor, and the other capacitors are shifted in sequence. S2222: When the difference between the first analog input Vip and the second analog input Vin is less than 1 / 4 of the reference voltage Vref, connect 1 / 4 of the most significant bit of the first capacitor array back to the common mode voltage Vcm, and at the same time connect 1 / 4 of the most significant bit of the second capacitor array back to the common mode voltage Vcm. The comparator continues the comparison: S22221: When the difference between the first analog input Vip and the second analog input Vin is greater than 1 / 8 of the reference voltage Vref, keep 1 / 4 of the most significant bit of the first capacitor array grounded to GND, and at the same time keep 1 / 4 of the most significant bit of the second capacitor array connected to the reference voltage Vref. S22222: When the difference between the first analog input Vip and the second analog input Vin is less than 1 / 8 of the reference voltage Vref, connect 1 / 4 of the most significant bit of the first capacitor array back to the common mode voltage Vcm, and at the same time connect 1 / 4 of the most significant bit of the second capacitor array back to the common mode voltage Vcm. After step S22221, the most significant bit capacitor of the next conversion cycle changes, and the capacitor connected to the common mode voltage Vcm becomes the most significant bit capacitor, and the other capacitors are shifted in sequence. After step S22222, the most significant bit capacitance, the second most significant bit, and the third most significant bit remain unchanged in the next conversion cycle.
8. The operation method of the DWA-based high-linearity SAR ADC as described in claim 7, characterized in that, In step S23, the comparator continues the comparison: S231: When the difference between the first analog input Vip and the second analog input Vin is greater than -1 / 2 of the reference voltage Vref, half of the most significant bit of the first capacitor array is connected back to the common mode voltage Vcm, and half of the most significant bit of the second capacitor array is connected back to the common mode voltage Vcm. S232: When the difference between the first analog input Vip and the second analog input Vin is less than -1 / 2 of the reference voltage Vref, connect all the capacitors of the second most significant bit of the first capacitor array to the reference voltage Vref, and at the same time connect all the capacitors of the second most significant bit of the second capacitor array to ground GND.
9. The operation method of the DWA-based high-linearity SAR ADC as described in claim 8, characterized in that, In step S231, the comparator continues the comparison: S2311: When the difference between the first analog input Vip and the second analog input Vin is greater than -1 / 4 of the reference voltage Vref, connect 1 / 4 of the most significant bit of the first capacitor array back to the common mode voltage Vcm, and at the same time connect 1 / 4 of the most significant bit of the second capacitor array back to the common mode voltage Vcm. S23111 When the difference between the first analog input Vip and the second analog input Vin is greater than -1 / 8 of the reference voltage Vref, 1 / 4 of the most significant bit of the first capacitor array is connected back to the common mode voltage Vcm, and at the same time, 1 / 4 of the most significant bit of the second capacitor array is connected back to the common mode voltage Vcm. S23112: When the difference between the first analog input Vip and the second analog input Vin is less than -1 / 8 of the reference voltage Vref, keep 1 / 4 of the most significant bit of the first capacitor array connected to the reference voltage Vref, and at the same time keep 1 / 4 of the most significant bit of the second capacitor array grounded to GND. After step S23112, the most significant bit capacitor of the next conversion cycle changes, and the capacitor connected to the common mode voltage Vcm becomes the most significant bit capacitor, and the other capacitors are shifted in sequence. After step S23111, the most significant bit capacitor, the second most significant bit, and the third most significant bit remain unchanged in the next conversion cycle; S2312: When the difference between the first analog input Vip and the second analog input Vin is less than -1 / 4 of the reference voltage Vref, connect 3 / 4 of the most significant bit of the first capacitor array to the reference voltage Vref, and at the same time connect 3 / 4 of the most significant bit of the second capacitor array to ground GND. S23121: When the difference between the first analog input Vip and the second analog input Vin is greater than -3 / 8 of the reference voltage Vref, connect 1 / 4 of the most significant bit of the first capacitor array back to the common mode voltage Vcm, and at the same time connect 1 / 4 of the most significant bit of the second capacitor array back to the common mode voltage Vcm. S23122: When the difference between the first analog input Vip and the second analog input Vin is less than -3 / 8 of the reference voltage Vref, keep 3 / 4 of the most significant bit of the first capacitor array connected to the reference voltage Vref, and at the same time keep 3 / 4 of the most significant bit of the second capacitor array grounded to GND. After steps S23121 and S23122, the most effective bit capacitor of the next conversion cycle changes. The most effective bit capacitor of the next conversion cycle changes to the capacitor connected to the common mode voltage Vcm, and the remaining capacitors are shifted in sequence.
10. The operation method of the DWA-based high linearity SAR ADC as described in claim 9, characterized in that, In step S232, the comparator continues the comparison: S2321: When the difference between the first analog input Vip and the second analog input Vin is greater than -3 / 4 of the reference voltage Vref, half of the capacitors of the second most effective bit of the first capacitor array are connected back to the common mode voltage Vcm, and half of the capacitors of the second most effective bit of the second capacitor array are connected back to the common mode voltage Vcm. S23211: When the difference between the first analog input Vip and the second analog input Vin is greater than -5 / 8 of the reference voltage Vref, half of the capacitors of the second most effective bit of the first capacitor array are connected back to the common mode voltage Vcm, and half of the capacitors of the second most effective bit of the second capacitor array are connected back to the common mode voltage Vcm. S23212: When the difference between the first analog input Vip and the second analog input Vin is less than -5 / 8 of the reference voltage Vref, keep all the capacitors of the most significant bit of the first capacitor array and half of the capacitors of the second most significant bit connected to the reference voltage Vref, and at the same time keep all the capacitors of the most significant bit of the second capacitor array and half of the capacitors of the second most significant bit grounded to GND. After steps S23211 and S23212, the most effective bit capacitor of the next conversion cycle changes, and the capacitor connected to the common mode voltage Vcm becomes the most effective bit capacitor, and the other capacitors are shifted in sequence. S2322: When the difference between the first analog input Vip and the second analog input Vin is less than -3 / 4 of the reference voltage Vref, connect one capacitor of the third most significant bit of the first capacitor array to the reference voltage Vref, and at the same time connect one capacitor of the third most significant bit of the second capacitor array to ground GND. S23221: When the difference between the first analog input Vip and the second analog input Vin is greater than -7 / 8 of the reference voltage Vref, connect one capacitor of the third most significant bit of the first capacitor array back to the common-mode voltage Vcm, and at the same time connect one capacitor of the third most significant bit of the second capacitor array back to the common-mode voltage Vcm. S23222: When the difference between the first analog input Vip and the second analog input Vin is less than -7 / 8 of the reference voltage Vref, keep all the capacitors of the most significant bit, the second most significant bit, and one capacitor of the third most significant bit of the first capacitor array connected to the reference voltage Vref, and at the same time keep all the capacitors of the most significant bit, the second most significant bit, and one capacitor of the third most significant bit of the second capacitor array grounded to GND. After steps S23221 and S23222, the most effective bit capacitor of the next conversion cycle changes. The most effective bit capacitor of the next conversion cycle changes to the capacitor connected to the common mode voltage Vcm, and the remaining capacitors are shifted in sequence.