PCIe firmware management method, processor, chip and electronic device

Abstract

Embodiments of the present disclosure provide a PCIe firmware management method, a processor, a chip and an electronic device. The PCIe firmware management method comprises: in a power-on starting process of a processor, performing, by an auxiliary processing unit, a PCIe controller subsystem initialization operation to generate PCIe configuration information; and delivering the PCIe configuration information to a main processing unit; acquiring, by the main processing unit, the PCIe configuration information and reporting the PCIe configuration information to an operating system, so that the operating system performs PCIe hardware management based on the reported PCIe configuration information. The PCIe firmware management scheme provided by the embodiments of the present disclosure helps to improve the starting speed of the PCIe function, and further enables the PCIe device based on the PCIe function to be quickly enabled; facilitates the later maintenance and debugging of the code, and flexibly realizes the extension and upgrade of the PCIe initialization code without interfering with the main processing unit; and reduces the processing burden of the main processing unit in the processor, so that it can focus on performing other important tasks.

Description

Technical Field

[0001] This disclosure relates to the field of chip technology, and in particular to a PCIe firmware management method, processor, chip, and electronic device. Background Technology

[0002] Peripheral Component Interconnect Express (PCIe) is a high-speed serial computer expansion bus standard that connects devices to the motherboard. PCIe allows for faster communication between the processor and various expansion cards, such as graphics cards, sound cards, and network adapters.

[0003] Inside the chip, the PCIe firmware is primarily responsible for initializing and configuring the PCIe controller, managing the loading of device drivers, and handling advanced error reporting. PCIe firmware management is a crucial step in ensuring the proper functioning of PCIe and system stability.

[0004] Currently, PCIe firmware management is primarily handled by the processor core responsible for various complex computational tasks such as operating system operation and application processing. However, this method of PCIe firmware management results in slow PCIe boot times and a longer time required to enable PCIe devices. Summary of the Invention

[0005] In view of this, embodiments of the present disclosure provide a PCIe firmware management method, processor, chip, and electronic device to at least solve or alleviate the above-mentioned problems.

[0006] According to a first aspect of the present disclosure, a PCIe firmware management method is provided, applied to a processor, the processor comprising: an auxiliary processing unit and a main processing unit, the method comprising:

[0007] During the processor power-on startup process, the auxiliary processing unit performs PCIe controller subsystem initialization operations to generate PCIe configuration information and then transmits the PCIe configuration information to the main processing unit.

[0008] The main processing unit obtains the PCIe configuration information and reports it to the operating system, so that the operating system can perform PCIe hardware management based on the reported PCIe configuration information.

[0009] According to a second aspect of the present disclosure, a processor is provided, including: an auxiliary processing unit and a main processing unit;

[0010] The auxiliary processing unit is used to perform PCIe controller subsystem initialization operations and generate PCIe configuration information during the processor power-on startup process; and to transmit the PCIe configuration information to the main processing unit.

[0011] The main processing unit is used to obtain the PCIe configuration information and report the PCIe configuration information to the operating system so that the operating system can perform PCIe hardware management based on the reported PCIe configuration information.

[0012] According to a third aspect of the present disclosure, a chip is provided, comprising: the processor described in the second aspect above.

[0013] According to a fourth aspect of the present disclosure, an electronic device is provided, comprising: the processor described in the second aspect above, or the chip described in the third aspect above.

[0014] According to the PCIe firmware management method provided in this disclosure embodiment, during the processor power-on startup process, the auxiliary processing unit in the processor performs the initialization operation of the PCIe controller subsystem and generates PCIe configuration information; then the main processing unit in the processor continues to perform subsequent PCIe hardware management operations based on the PCIe configuration information generated by the auxiliary processing unit.

[0015] In this embodiment, the complete PCIe firmware management process is broken down into smaller parts. The initial tasks of PCIe firmware management—PCIe controller subsystem initialization—are performed by an auxiliary processing unit with faster startup speed, while subsequent operations such as information reporting are performed by the main processing unit. Compared to the main processing unit, the auxiliary processing unit typically has a faster startup speed. Therefore, having the faster auxiliary processing unit perform the PCIe controller subsystem initialization task helps improve the startup speed of PCIe functionality, thereby enabling PCIe devices quickly and improving the overall processor performance.

[0016] In addition, by offloading the PCIe controller subsystem initialization operation from the main processing unit to the auxiliary processing unit, the PCIe initialization code is separated and decoupled from the ODM (Original Design Manufacturer) code used to implement other upper-layer functions. This facilitates later maintenance and debugging of the code, and allows for flexible expansion and upgrading of the PCIe initialization code without interfering with the main processing unit.

[0017] At the same time, assigning PCIe initialization tasks to auxiliary processing units can also reduce the processing burden on the main processing unit in the processor, allowing it to focus on performing other important tasks.

[0018] In summary, the PCIe firmware management method provided in this disclosure can improve the overall performance and efficiency of the processor. Attached Figure Description

[0019] To more clearly illustrate the technical solutions in the embodiments of this disclosure or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in the embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings.

[0020] Figure 1 This is a flowchart of a PCIe firmware management method according to an embodiment of this disclosure;

[0021] Figure 2 This is a schematic diagram of the internal structure of a processor according to an embodiment of the present disclosure;

[0022] Figure 3 This is a schematic diagram illustrating the interaction process between an auxiliary processing unit and a main processing unit in a processor according to an embodiment of the present disclosure. Detailed Implementation

[0023] Embodiments of this disclosure will now be described in more detail with reference to the accompanying drawings. While some embodiments of this disclosure are shown in the drawings, it should be understood that this disclosure can be implemented in various forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided to provide a more thorough and complete understanding of this disclosure. It should be understood that the accompanying drawings and embodiments of this disclosure are for illustrative purposes only and are not intended to limit the scope of protection of this disclosure.

[0024] It should be noted that the headings of any section / subsection provided herein are not limiting. Various embodiments are described throughout this document, and embodiments of any type may be included under any section / subsection. Furthermore, embodiments described in any section / subsection may be combined in any way with any other embodiments described in the same section / subsection and / or different sections / subsections.

[0025] In the description of embodiments of this disclosure, the term "comprising" and similar terms should be understood as open-ended inclusion, i.e., "including but not limited to". The term "based on" should be understood as "at least partially based on". The term "one embodiment" or "the embodiment" should be understood as "at least one embodiment". The term "some embodiments" should be understood as "at least some embodiments". Other explicit and implicit definitions may also be included below. The terms "first", "second", etc., may refer to different or the same objects. Other explicit and implicit definitions may also be included below.

[0026] The embodiments of this disclosure may involve user data, data acquisition, and / or use. All of these aspects comply with applicable laws, regulations, and relevant provisions. In the embodiments of this disclosure, all data collection, acquisition, processing, manipulation, forwarding, and use are conducted with the user's knowledge and confirmation. Accordingly, in implementing the embodiments of this disclosure, the type, scope of use, and usage scenarios of any data or information that may be involved should be communicated to the user and their authorization obtained in accordance with relevant laws and regulations through appropriate means. The specific methods of notification and / or authorization may vary depending on the actual situation and application scenario, and the scope of this disclosure is not limited in this respect.

[0027] In this specification and the embodiments, any processing of personal information will be carried out only under the premise of legality (such as obtaining the consent of the personal information subject, or being necessary for the performance of a contract), and will only be carried out within the scope stipulated or agreed upon. A user's refusal to process personal information other than that necessary for basic functions will not affect the user's use of basic functions.

[0028] Example 1

[0029] See Figure 1 , Figure 1 This is a flowchart of a PCIe firmware management method according to an embodiment of the present disclosure. This PCIe firmware management method can be executed by a processor internally configured with an auxiliary processing unit and a main processing unit. The auxiliary processing unit, also referred to as an auxiliary processor core or a small core, can handle low-complexity tasks, such as real-time clock management, low-level hardware monitoring, and simple data stream processing. The main processing unit, also referred to as a main processor core or a large core, can perform more complex tasks, such as complex computational tasks, application programs, and operating systems.

[0030] like Figure 1 As shown, this PCIe firmware management method includes the following steps:

[0031] Step 102: During the processor power-on startup process, the auxiliary processing unit performs the PCIe controller subsystem initialization operation to generate PCIe configuration information.

[0032] Specifically, the PCIe controller subsystem is a key hardware component enabling high-speed, flexible I / O operations for the processor. It allows the processor to connect to and utilize various high-speed peripheral devices, such as network cards and storage devices. Specifically, the PCIe controller subsystem is primarily responsible for managing the PCIe bus, handling functions such as data transfer, link initialization, error detection, and processing.

[0033] When the processor powers on, the auxiliary processing unit within the processor can initialize the PCIe controller subsystem to obtain initialization configuration information, i.e., PCIe configuration information. This may include: setting PCIe bus parameters, such as PCIe link speed, width, and error status; configuring the PCIe root component, such as setting the bus range, I / O port range, and configuring memory mapping for subsequent access by the operating system, etc. During the initialization process, the auxiliary processing unit can collect PCIe resource configuration information as the PCIe configuration information in this embodiment. Specifically, the PCIe resource configuration information may include: resource information in the PCIe controller subsystem, PCIe link status information, host bridge configuration information (e.g., memory-mapped I / O (MMIO) space), etc.

[0034] Step 104: The PCIe configuration information is transmitted to the main processing unit through the auxiliary processing unit.

[0035] Specifically, after the auxiliary processing unit completes the initialization operation of the PCIe controller subsystem and collects the aforementioned PCIe configuration information, it can transmit the PCIe configuration information to the main processing unit. Then, the underlying firmware in the main processing unit reports the PCIe configuration information to the operating system, so that the operating system can control, access, and perform other subsequent management of PCIe hardware such as the PCIe controller subsystem based on the PCIe configuration information.

[0036] In this embodiment, the specific transmission method used by the auxiliary processing unit to transmit PCIe configuration information to the main processing unit is not limited. It can be customized according to the actual situation.

[0037] Step 106: The main processing unit obtains PCIe configuration information and reports the PCIe configuration information to the operating system so that the operating system can perform PCIe hardware management based on the reported PCIe configuration information.

[0038] Specifically, as described above, after the main processing unit obtains the PCIe configuration information generated during the initialization process of the PCIe controller subsystem, it can manage and control the PCIe hardware such as the PCIe controller subsystem based on this information.

[0039] In this embodiment of the application, the specific reporting mechanism used by the main processing unit when reporting PCIe configuration information is not limited, and can be customized according to the actual situation.

[0040] Optionally, in some embodiments, the process of reporting PCIe configuration information to the operating system may specifically include:

[0041] An Advanced Configuration Power Interface (ACPI) table is generated based on the PCIe configuration information, and then reported to the operating system via the ACPI interface.

[0042] Specifically, ACPI (Advanced Configuration and Power Interface) is a power management and configuration interface specification used to manage communication and coordination between hardware devices, operating systems, and underlying firmware in a computer system. ACPI defines a standardized set of methods and data structures to implement functions such as power management, device control, and configuration.

[0043] In this embodiment, the PCIe configuration information obtained by the main processing unit is reported to the operating system through the ACPI mechanism, so that the operating system can perform subsequent PCIe hardware management. The specific reporting process may include:

[0044] An ACPI table is created based on the parsed PCIe configuration information. Once created, the ACPI table contains detailed information about the PCIe hardware configuration. The address information of the created ACPI table is provided to the operating system through the ACPI interface. Specifically, the address of the ACPI table can be added to the system table during system startup, so that the operating system can access these tables during the startup process.

[0045] After successful reporting, the operating system will parse the ACPI table and then construct the ACPI namespace based on the PCIe configuration information contained in the table. This namespace is a tree structure that reflects the system hardware configuration. Through the constructed namespace, the operating system can identify hardware, allocate necessary resources to the hardware, such as memory address space and I / O ports, and manage the hardware.

[0046] ACPI provides a standardized interface that allows operating systems to interact with hardware in a unified manner, regardless of hardware manufacturer. Furthermore, ACPI enhances hardware device compatibility across different operating systems and hardware platforms. Additionally, the ACPI mechanism supports plug-and-play devices, enabling the addition or removal of hardware devices without restarting the system. Based on these characteristics, this embodiment employs the ACPI mechanism for PCIe configuration information reporting, which improves the universality, compatibility, and convenience of the hardware management process.

[0047] Optionally, in some embodiments, step 104 above, the process of transferring PCIe configuration information to the main processing unit through the auxiliary processing unit, may specifically include:

[0048] Create the HOB data structure and populate it with PCIe configuration information:

[0049] Send the address information of the HOB data structure to the main processing unit;

[0050] Correspondingly, step 106, the process of obtaining PCIe configuration information through the main processing unit, may include:

[0051] The main processing unit reads the HOB data structure based on the address information and parses the HOB data structure to obtain the PCIe configuration information.

[0052] Specifically, UEFI (Unified Extensible Firmware Interface) is a firmware interface standard that provides a more robust, flexible, and secure environment for initializing and managing hardware resources during computer startup and supporting the loading of the operating system. During the computer startup process, UEFI is responsible for initializing the PCIe controller, enabling the operating system to recognize and use hardware devices connected to the PCIe bus. The HOB (Hand-Off Block) data structure is a mechanism used during UEFI startup to transfer information between different startup phases. In this specific solution, the HOB data structure can be used to transfer PCIe configuration information between the PCIe controller subsystem initialization phase and the PCIe hardware management phase.

[0053] In practice, the creation process of the HOB data structure may include: defining and creating the HOB data structure according to specific specifications and hardware requirements; populating the HOB data: populating the HOB data according to the PCIe configuration information generated during the PCIe controller initialization operation; adding the HOB to the HOB list: adding the created HOB to the HOB list of the preset storage area, and sending the corresponding storage address information to the main processing unit so that the main processing unit can read the HOB data structure through the above storage address information, and then obtain the above PCIe configuration information by parsing the HOB data structure.

[0054] HOB, as a data structure, is used to transfer information between different processing units, ensuring the continuity and integrity of the transferred information. Furthermore, transferring information via HOB improves transmission efficiency, allowing the operating system to manage PCIe hardware more quickly. Moreover, the HOB mechanism allows firmware developers to create custom HOBs as needed to support specific hardware configurations or operating system boot requirements, thus offering flexibility and scalability.

[0055] In this embodiment, the complete PCIe firmware management process is broken down into smaller parts. The initial tasks of PCIe firmware management—PCIe controller subsystem initialization—are performed by an auxiliary processing unit with faster startup speed, while subsequent operations such as information reporting are performed by the main processing unit. Compared to the main processing unit, the auxiliary processing unit typically has a faster startup speed. Therefore, having the faster auxiliary processing unit perform the PCIe controller subsystem initialization task helps improve the startup speed of PCIe functionality, thereby enabling PCIe devices quickly and improving the overall processor performance.

[0056] Furthermore, the main processing unit executes related technologies, including the PCIe controller subsystem initialization and subsequent information reporting. Therefore, from a program code perspective, the PCIe initialization code is integrated with the ODM code used to implement other upper-layer functions. This is not conducive to the hierarchical management of the PCIe initialization code, hindering code maintenance and later debugging. Additionally, the PCIe initialization code is low-level logic code for the SOC (System on Chip), and most ODM manufacturers have limited understanding of PCIe initialization and related content. The integration of PCIe initialization code with ODM code requires ODM manufacturers to possess additional knowledge of SOC low-level logic, meaning higher requirements are placed on them.

[0057] In this embodiment, by offloading the PCIe controller subsystem initialization operation from the main processing unit to the auxiliary processing unit, the PCIe initialization code and the ODM code used to implement other upper-layer functions are separated and decoupled. This facilitates later maintenance and debugging of the code, and allows for flexible expansion and upgrading of the PCIe initialization code without interfering with the main processing unit. On the other hand, ODM vendors do not need to consider the relevant content of the PCIe initialization code when processing ODM code, and therefore do not need to have certain knowledge of the underlying logic of the SOC, thus reducing the requirements for ODM vendors.

[0058] At the same time, assigning PCIe initialization tasks to auxiliary processing units can also reduce the processing burden on the main processing unit in the processor, allowing it to focus on performing other important tasks.

[0059] In summary, the PCIe firmware management method provided in this disclosure can improve the overall performance and efficiency of the processor.

[0060] Optionally, in some embodiments, the PCIe configuration information includes: PCIe resource configuration information and PCIe function configuration information;

[0061] The auxiliary processing unit performs PCIe controller subsystem initialization operations and generates PCIe configuration information, including:

[0062] The auxiliary processing unit performs the PCIe controller subsystem initialization operation and generates PCIe resource configuration information.

[0063] The auxiliary processing unit obtains a list of PCIe functions to be started; during the initialization process of the PCIe controller subsystem, it performs the corresponding PCIe function initialization operation according to the list of PCIe functions to be started, and generates PCIe function configuration information.

[0064] Specifically, various PCIe functions can be implemented based on the PCIe specification. Examples include: Error detection: checking for errors in data packets, such as CRC (Cyclic Redundancy Check) errors; detecting errors during transmission, such as data loss or transmission errors; monitoring errors at the link layer, such as link loss or retry errors. Error reporting: recording error information (such as error type, location, and timestamp) and reporting the error information to the host system or operating system using an error reporting register. Furthermore, generating an interrupt to notify the system administrator when a serious error is detected. Error handling and recovery: using error correction codes to detect and repair single-bit errors during data transmission; ensuring data transmission integrity through retry mechanisms for certain recoverable errors; isolating problematic devices or channels to avoid affecting other parts of the system. Hot-plug support: supporting device plugging and unplugging in a running system, ensuring that devices can be replaced without system interruption in case of failure. Fault isolation and isolation management functions: Through the hot-swapping functionality of the PCIe standard or other mechanisms, faulty devices can be isolated to reduce the impact on the system; device plugging and unplugging is supported while the system is running, which helps in repairing or replacing devices when faults are detected. Logging and auditing functions: All PCIe-related events and errors are logged for subsequent auditing and analysis; log data is managed, including storage, analysis, and reporting.

[0065] As mentioned above, there are many types of PCIe functions based on the PCIe specification. However, in practical application scenarios, it may not be necessary to configure all PCIe functions; instead, some PCIe functions may need to be selectively activated based on actual needs. Therefore, in this embodiment, the auxiliary processing unit can first obtain a list of PCIe functions to be activated. Then, during the initialization operation of the PCIe controller subsystem, it can perform the corresponding PCIe function initialization operation based on the obtained function list, activate the corresponding PCIe function, and generate PCIe function configuration information. The generated PCIe function configuration information and the PCIe resource configuration information generated during the initialization of the PCIe controller subsystem are sent as PCIe configuration information to the main processing unit, which then reports it to the operating system so that the operating system can manage the PCIe hardware and the activated PCIe functions.

[0066] In the above embodiments of this application, the corresponding PCIe function can be executed and started in a targeted manner by using the list of PCIe functions to be started, which improves the flexibility of PCIe function implementation and makes PCIe functions closer to actual needs.

[0067] In this embodiment, the specific source of the PCIe function list to be started is not limited. For example, it can be predetermined by the developers and stored in a preset storage area. When the processor powers on, the PCIe function list to be started can be read from the above area, and then the PCIe function can be started in a targeted manner according to the list. In this way, the PCIe function list obtained in each startup process may be the same. Alternatively, the PCIe function list can be edited during the previous startup, and then the PCIe function can be started again in the next startup process based on the previously edited PCIe function list. In this way, the PCIe function list obtained in each startup process may not be the same, and the PCIe function can be started flexibly according to the actual situation.

[0068] Optionally, in some embodiments, before obtaining the list of PCIe functions to be activated through the auxiliary processing unit, the method further includes:

[0069] The main processing unit controls the display unit to display the PCIe function selection interactive page;

[0070] In response to the interactive operation of the PCIe function selection page, a list of PCIe functions to be launched is generated;

[0071] The auxiliary processing unit obtains a list of PCIe functions to be started, including:

[0072] The auxiliary processing unit receives a list of PCIe functions to be started from the main processing unit.

[0073] Specifically, in the above embodiments of this application, the main processing unit can first control the control unit to display a PCIe function selection interaction page to the user, then detect the user's interaction with the page, and determine the PCIe function that the user wants to start based on the interaction, generating a list of PCIe functions to be started; then, the list of PCIe functions to be started generated according to the user's wishes is sent to the auxiliary processing unit, so that during the subsequent processor power-on startup process, the auxiliary processing unit can selectively start the PCIe function that the user wants to start according to the list.

[0074] In this embodiment, the PCIe function selection interaction page can refer to a page used to guide users in selecting PCIe functions. For example, it could be a page displaying multiple selectable PCIe functions, or a page displaying a text input box, etc. The specific content and form of the PCIe function selection interaction page are not limited here and can be customized according to actual conditions and user habits. For example, as mentioned above, there are many types of PCIe functions. Therefore, for a page displaying multiple selectable PCIe functions, to facilitate user selection, the PCIe function selection interaction page in the above embodiment of this application can specifically display multiple interactive components (such as virtual icons or virtual buttons, etc.). One interactive component corresponds to one PCIe function. Users can perform interactive operations on the interactive component corresponding to the target PCIe function according to their actual needs to add the target PCIe function to the list of PCIe functions to be launched. Similarly, for a page displaying a text input box, users can input their desired target PCIe function in the text input box, thereby adding the user-inputted target PCIe function to the list of PCIe functions to be launched.

[0075] Furthermore, in this embodiment, the specific content of the interactive operations for the PCIe function selection interaction page is not limited, and can be customized according to actual conditions. For example, for a PCIe function selection interaction page displaying multiple interactive components, the interactive operations can be clicking, double-clicking, or dragging the interactive components, etc.; for a PCIe function selection interaction page displaying a text input box, the interactive operations can be text input in the text input box, etc.

[0076] In the embodiments described above, by displaying a PCIe function selection interactive page to the user, the user's current PCIe function requirements can be obtained in a timely and flexible manner. This allows for targeted PCIe function initialization based on these requirements during the next processor startup. Therefore, the above solution can efficiently and flexibly achieve personalized PCIe function configuration, improving the user experience.

[0077] Optionally, in some embodiments, before reporting PCIe configuration information to the operating system so that the operating system can perform PCIe hardware management based on the reported PCIe configuration information, the method further includes:

[0078] The main processing unit performs a PCIe device enumeration operation to obtain PCIe device information.

[0079] The PCIe configuration information is reported to the operating system so that the operating system can perform PCIe hardware management based on the reported PCIe configuration information, including:

[0080] The PCIe configuration information and PCIe device information are reported to the operating system, so that the operating system can manage the PCIe controller subsystem based on the reported PCIe configuration information and manage the PCIe devices based on the reported PCIe device information.

[0081] Specifically, the PCIe device in this application embodiment can be a hardware device that communicates with the processor using a PCIe interface. Examples of common PCIe devices include: solid-state drives, network cards, sound cards, expansion cards, encryption cards, etc.

[0082] After the PCIe controller subsystem initializes and reports PCIe configuration information, the main processing unit can perform PCIe device enumeration operations. This involves: detecting PCIe devices, identifying all PCIe devices connected to the PCIe bus, obtaining basic information about each identified PCIe device such as device ID, vendor ID, and category code; configuring resources for each identified PCIe device, such as I / O ports, memory address space, and interrupts; and then generating PCIe device information based on the enumeration operations. This allows the operating system to manage both the PCIe controller subsystem based on the PCIe configuration information and the PCIe devices based on the enumeration information.

[0083] Optionally, in some embodiments, the processor is a RISC-V based processor; the main processing unit includes Coreboot firmware;

[0084] The main processing unit obtains PCIe configuration information and reports it to the operating system, including:

[0085] The PCIe configuration information is obtained through the Coreboot firmware in the main processing unit and then reported to the operating system.

[0086] Specifically, in this embodiment, the processor can be a processor based on the RISC-V instruction set architecture. RISC (Reduced Instruction Set Computer)-V is an open instruction set architecture (ISA) built on the principles of reduced instruction set computing. RISC (Reduced Instruction Set Computer) is a processor architecture that contrasts with CISC (Complex Instruction Set Computer). It breaks down longer instructions into several single instructions of the same length, making the processor's operation simpler, faster, and easier to design and develop. This RISC-V-based processor itself includes auxiliary processing units, also known as "small cores" (SCPs), and main processing units, also known as "big cores." "Small cores" refer to lightweight cores that can be used for specific low-power or real-time tasks. "Big cores," on the other hand, are more powerful and feature-rich cores capable of handling more complex computational tasks. Compared to "big cores," "small cores" have a faster startup speed.

[0087] In RISC-V architecture-based processors, the "big core" contains Coreboot firmware. Coreboot firmware is an open-source firmware project used to transfer system control to an executable program (called a payload) after the processor hardware initialization is complete. The main function of this executable program is to continue the system boot process, i.e., load and start the operating system. Coreboot firmware provides security features, such as encryption and signing, to prevent malicious software from tampering with the firmware. Furthermore, Coreboot typically contains only the code necessary for executing tasks, reducing the firmware's attack surface and improving boot speed. In this solution, during the computer boot process, after the PCIe controller subsystem initialization is complete, the PCIe configuration information generated during the PCIe controller subsystem initialization process can be reported to the operating system through the Coreboot firmware contained in the "big core." The operating system then controls the management of the PCIe hardware. This embodiment utilizes the unique structural characteristics of RISC-V architecture-based processors to achieve efficient, flexible, and secure PCIe firmware management.

[0088] Example 2

[0089] See Figure 2 , Figure 2 This is a schematic diagram of the structure of a processor according to an embodiment of the present disclosure. The processor 200 includes: an auxiliary processing unit 202 and a main processing unit 204;

[0090] The auxiliary processing unit 202 is used to perform PCIe controller subsystem initialization operations and generate PCIe configuration information during the processor power-on startup process; and to transmit the PCIe configuration information to the main processing unit 204.

[0091] The main processing unit 204 is used to obtain PCIe configuration information and report the PCIe configuration information to the operating system so that the operating system can perform PCIe hardware management based on the reported PCIe configuration information.

[0092] According to the processor provided in the embodiments of this disclosure, during the power-on startup process, the auxiliary processing unit in the processor performs the initialization operation of the PCIe controller subsystem and generates PCIe configuration information; then the main processing unit in the processor continues to perform subsequent PCIe hardware management operations based on the PCIe configuration information generated by the auxiliary processing unit.

[0093] In this embodiment, the complete PCIe firmware management process is broken down into smaller parts. The initial tasks of PCIe firmware management—PCIe controller subsystem initialization—are performed by an auxiliary processing unit with faster startup speed, while subsequent operations such as information reporting are performed by the main processing unit. Compared to the main processing unit, the auxiliary processing unit typically has a faster startup speed. Therefore, having the faster auxiliary processing unit perform the PCIe controller subsystem initialization task helps improve the startup speed of PCIe functionality, thereby enabling PCIe devices quickly and improving the overall processor performance.

[0094] Furthermore, the main processing unit executes related technologies, including the PCIe controller subsystem initialization and subsequent information reporting. Therefore, from a program code perspective, the PCIe initialization code is integrated with the ODM code used to implement other upper-layer functions. This is not conducive to the hierarchical management of the PCIe initialization code, hindering code maintenance and later debugging. Additionally, the PCIe initialization code is low-level logic code for the SOC (System on Chip), and most ODM manufacturers have limited understanding of PCIe initialization and related content. The integration of PCIe initialization code with ODM code requires ODM manufacturers to possess additional knowledge of SOC low-level logic, meaning higher requirements are placed on them.

[0095] In this embodiment, by offloading the PCIe controller subsystem initialization operation from the main processing unit to the auxiliary processing unit, the PCIe initialization code and the ODM code used to implement other upper-layer functions are separated and decoupled. This facilitates later maintenance and debugging of the code, and allows for flexible expansion and upgrading of the PCIe initialization code without interfering with the main processing unit. On the other hand, ODM vendors do not need to consider the relevant content of the PCIe initialization code when processing ODM code, and therefore do not need to have certain knowledge of the underlying logic of the SOC, thus reducing the requirements for ODM vendors.

[0096] At the same time, assigning PCIe initialization tasks to auxiliary processing units can also reduce the processing burden on the main processing unit in the processor, allowing it to focus on performing other important tasks.

[0097] In summary, the PCIe firmware management method provided in this disclosure can improve the overall performance and efficiency of the processor.

[0098] Optionally, in some embodiments, the auxiliary processing unit 202, when performing the step of transferring PCIe configuration information to the main processing unit, is specifically used for:

[0099] Create the HOB data structure and populate it with PCIe configuration information:

[0100] Send the address information of the HOB data structure to the main processing unit;

[0101] Correspondingly, when performing the step of obtaining PCIe configuration information, the main processing unit 204 is specifically used for:

[0102] The HOB data structure is read from the address information and parsed to obtain the PCIe configuration information.

[0103] Optionally, in some embodiments, the PCIe configuration information includes: PCIe resource configuration information and PCIe function configuration information;

[0104] The auxiliary processing unit 202, during the PCIe controller subsystem initialization operation and the step of generating PCIe configuration information, is specifically used for:

[0105] Perform PCIe controller subsystem initialization operations to generate PCIe resource configuration information;

[0106] Obtain the list of PCIe functions to be started; during the initialization process of the PCIe controller subsystem, perform the corresponding PCIe function initialization operation according to the list of PCIe functions to be started, and generate PCIe function configuration information.

[0107] Optionally, in some embodiments, the main processing unit 204 is further configured to:

[0108] The control display unit displays the PCIe function selection interactive page;

[0109] In response to the interactive operation of the PCIe function selection page, a list of PCIe functions to be launched is generated;

[0110] The auxiliary processing unit 202, when performing the step of obtaining the list of PCIe functions to be enabled, is specifically used for:

[0111] Receive the list of PCIe functions to be started sent by the main processing unit 204.

[0112] Optionally, in some embodiments, when performing the step of reporting PCIe configuration information to the operating system, the main processing unit 204 is specifically used for:

[0113] An Advanced Configuration Power Interface (ACPI) table is generated based on the PCIe configuration information, and then reported to the operating system via the ACPI interface.

[0114] Optionally, in some embodiments, the main processing unit 204, before executing the process of reporting PCIe configuration information to the operating system so that the operating system can perform PCIe hardware management based on the reported PCIe configuration information, is further configured to:

[0115] Perform a PCIe device enumeration operation to obtain PCIe device information;

[0116] Correspondingly, when the main processing unit 204 executes the step of reporting PCIe configuration information to the operating system so that the operating system can perform PCIe hardware management based on the reported PCIe configuration information, it is specifically used for:

[0117] The PCIe configuration information and PCIe device information are reported to the operating system, so that the operating system can manage the PCIe controller subsystem based on the reported PCIe configuration information and manage the PCIe devices based on the reported PCIe device information.

[0118] Optionally, in some embodiments, the processor is a RISC-V based processor; the main processing unit includes Coreboot firmware;

[0119] Correspondingly, when the main processing unit 204 performs the step of obtaining PCIe configuration information and reporting the PCIe configuration information to the operating system, it is specifically used for:

[0120] The PCIe configuration information is obtained through the Coreboot firmware in the main processing unit and then reported to the operating system.

[0121] It should be noted that the details of the processor 200 have been described in detail in conjunction with the flowchart in the above PCIe firmware management embodiment section. For specific details, please refer to the description in the above PCIe firmware management embodiment, and will not be repeated here.

[0122] See Figure 3 , Figure 3 This is a schematic diagram illustrating the interaction process between an auxiliary processing unit and a main processing unit in a processor according to an embodiment of this disclosure. To facilitate a better understanding of the PCIe firmware management scheme provided in this disclosure embodiment, the following is combined with... Figure 3 Explanation of the PCIe firmware management process:

[0123] During the processor power-on startup process, the auxiliary processing unit starts up before the main processing unit. Then, the auxiliary processing unit will perform the PCIe controller subsystem initialization operation and generate PCIe configuration information. Based on the generated PCIe configuration information, the auxiliary processing unit will create a PCIe HOB data structure and pass the created PCIe HOB data structure to the main processing unit. At this point, the PCIe firmware management task performed by the auxiliary processing unit ends, and the main processing unit will then perform other PCIe-related operations.

[0124] After receiving the PCIe HOB data structure sent by the auxiliary processing unit, the main processing unit performs a PCIe HOB data structure parsing operation to obtain PCIe configuration information. In addition, the main processing unit can also perform a PCIe device enumeration operation to obtain PCIe device information. After obtaining the PCIe configuration information and PCIe device information, the main processing unit can create an ACPI table based on the above two types of information, and then report the ACPI table to the operating system through the ACPI interface, so that the operating system can perform subsequent management of the PCIe device.

[0125] This disclosure also provides a chip, including the processor described in the above embodiments.

[0126] This disclosure also provides an electronic device, including: the processor in the above embodiments, or the chip in the above embodiments.

[0127] It should be understood that the various embodiments in this specification are described in a progressive manner, and the same or similar parts between the various embodiments can be referred to mutually. Each embodiment focuses on describing the differences from other embodiments. In particular, for the method embodiments, since they are basically similar to the methods described in the apparatus and system embodiments, the description is relatively simple, and relevant parts can be referred to the descriptions of other embodiments.

[0128] It should be understood that the foregoing describes specific embodiments of this specification. Other embodiments are within the scope of the claims. In some cases, the actions or steps recited in the claims may be performed in a different order than that shown in the embodiments and may still achieve the desired result. Furthermore, the processes depicted in the drawings do not necessarily require the specific or sequential order shown to achieve the desired result. In some embodiments, multitasking and parallel processing are also possible or may be advantageous.

[0129] It should be understood that the use of a singular form to describe an element or to show only one element in the accompanying drawings does not imply that the number of such element is limited to one. Furthermore, modules or elements described or shown as separate herein may be combined into a single module or element, and modules or elements described or shown as single herein may be broken down into multiple modules or elements.

[0130] It should also be understood that the terminology and expressions used herein are for descriptive purposes only, and one or more embodiments described herein should not be limited to these terms and expressions. The use of these terms and expressions does not exclude any illustrative and descriptive equivalent features (or parts thereof), and it should be recognized that various modifications that may exist should also be included within the scope of the claims. Other modifications, variations, and substitutions may also exist. Accordingly, the claims should be considered to cover all such equivalents.

Claims

1. A PCIe firmware management method applied to a processor, the processor comprising: an auxiliary processing unit and a main processing unit, the method comprising: During the processor power-on startup process, the auxiliary processing unit performs PCIe controller subsystem initialization operations and generates PCIe configuration information. And the PCIe configuration information is transmitted to the main processing unit; The main processing unit obtains the PCIe configuration information and reports it to the operating system, so that the operating system can perform PCIe hardware management based on the reported PCIe configuration information.

2. The method according to claim 1, wherein, The step of transmitting the PCIe configuration information to the main processing unit includes: Create a HOB data structure and populate the HOB data structure with the PCIe configuration information: The address information of the HOB data structure is sent to the main processing unit; The step of obtaining the PCIe configuration information through the main processing unit includes: The main processing unit reads the HOB data structure based on the address information and parses the HOB data structure to obtain the PCIe configuration information.

3. The method according to claim 1 or 2, wherein, The PCIe configuration information includes: PCIe resource configuration information and PCIe function configuration information; The auxiliary processing unit performs PCIe controller subsystem initialization operations and generates PCIe configuration information, including: The auxiliary processing unit performs the PCIe controller subsystem initialization operation and generates PCIe resource configuration information. The auxiliary processing unit obtains a list of PCIe functions to be started; during the initialization process of the PCIe controller subsystem, it performs the corresponding PCIe function initialization operation according to the list of PCIe functions to be started, and generates PCIe function configuration information.

4. The method according to claim 3, wherein, Before obtaining the list of PCIe functions to be activated through the auxiliary processing unit, the method further includes: The main processing unit controls the display unit to display the PCIe function selection interactive page; In response to the interactive operation of selecting the interactive page for the PCIe function, a list of PCIe functions to be launched is generated; The step of obtaining the list of PCIe functions to be activated through the auxiliary processing unit includes: The auxiliary processing unit receives a list of PCIe functions to be activated from the main processing unit.

5. The method according to claim 1 or 2, wherein, The step of reporting the PCIe configuration information to the operating system includes: An Advanced Configuration Power Interface (ACPI) table is generated based on the PCIe configuration information, and the ACPI table is reported to the operating system through the ACPI interface.

6. The method according to claim 1 or 2, wherein, Before reporting the PCIe configuration information to the operating system [P-137285-CN-PRI-1][HS2410989CCN] so that the operating system can perform PCIe hardware management based on the reported PCIe configuration information, the method further includes: The main processing unit performs a PCIe device enumeration operation to obtain PCIe device information. The step of reporting the PCIe configuration information to the operating system so that the operating system can perform PCIe hardware management based on the reported PCIe configuration information includes: The PCIe configuration information and the PCIe device information are reported to the operating system, so that the operating system can manage the PCIe controller subsystem based on the reported PCIe configuration information and manage the PCIe devices based on the PCIe device information.

7. The method according to claim 1 or 2, wherein, The processor is a RISC-V based processor; the main processing unit contains Coreboot firmware; The step of obtaining the PCIe configuration information through the main processing unit and reporting the PCIe configuration information to the operating system includes: The PCIe configuration information is obtained through the Coreboot firmware in the main processing unit, and the PCIe configuration information is reported to the operating system.

8. A processor, comprising: Auxiliary processing unit and main processing unit; The auxiliary processing unit is used to perform PCIe controller subsystem initialization operations and generate PCIe configuration information during the processor power-on startup process. And the PCIe configuration information is transmitted to the main processing unit; The main processing unit is used to obtain the PCIe configuration information and report the PCIe configuration information to the operating system so that the operating system can perform PCIe hardware management based on the reported PCIe configuration information.

9. A chip, comprising: The processor as described in claim 8.

10. An electronic device, comprising: The processor as described in claim 8, or the chip as described in claim 9.

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