Display motherboard, display panel and display device

Abstract

The present disclosure provides a display motherboard, a display panel and a display device, and relates to the technical field of display. The display motherboard comprises a plurality of display panels. The display panel comprises an electrostatic lead-out structure and a first signal transmission pin. The electrostatic lead-out structure is located in a non-display area, and the first signal transmission pin is located in a binding area. The electrostatic lead-out structure is electrically connected with the first signal transmission pin, and the first signal transmission pin receives a constant voltage signal. In a first direction, the electrostatic lead-out structures of two adjacent display panels are electrically connected through a first connecting line, and the first connecting line extends in the first direction. In a second direction, the electrostatic lead-out structures of two adjacent display panels are electrically connected through a second connecting line, and the second connecting line extends in the second direction. The present disclosure electrically connects each electrostatic lead-out structure by arranging the first connecting line and the second connecting line in the display motherboard, thereby providing electrostatic protection for the display motherboard and reducing the space occupied by the display motherboard.

Description

Technical Field

[0001] This disclosure relates to the field of display technology, and in particular to a display motherboard, a display panel, and a display device. Background Technology

[0002] With the development of display technology, Micro Light Emitting Diode (Micro LED) display products have attracted much attention due to their significant advantages in brightness, resolution, contrast ratio, energy consumption, and response speed. However, electrostatic discharge (ESD) is one of the high-risk factors causing damage to some display products. To mitigate ESD issues in the display motherboard, an anti-static metal ring is typically placed around its outer edge to discharge static electricity. However, this anti-static metal ring occupies space on the display motherboard, affecting its area utilization rate.

[0003] Therefore, how to improve the above problems has become one of the urgent technical issues to be addressed at this stage. Summary of the Invention

[0004] To address the aforementioned technical problems, this disclosure provides a display motherboard, a display panel, and a display device, which reduce the space occupied by the display motherboard while achieving electrostatic protection.

[0005] In a first aspect, this disclosure provides a display motherboard, comprising a plurality of display panels arranged in a matrix along a first direction and a second direction, wherein the first direction and the second direction intersect and are both parallel to the plane in which the display motherboard is located; The display panel includes a display area and a non-display area surrounding the display area, the non-display area including a binding area located on one side of the display area; The display panel further includes an electrostatic discharge structure and a first signal transmission pin. The electrostatic discharge structure is located in the non-display area, and the first signal transmission pin is located in the bonding area. The electrostatic discharge structure is electrically connected to the first signal transmission pin, and the first signal transmission pin receives a constant voltage signal. Along the first direction, the electrostatic discharge structures of two adjacent display panels are electrically connected by a first connecting line extending along the first direction; along the second direction, the electrostatic discharge structures of two adjacent display panels are electrically connected by a second connecting line extending along the second direction.

[0006] In a second aspect, this disclosure provides a display panel cut from the display motherboard of the first aspect.

[0007] Thirdly, this disclosure provides a display device, including the display panel described in the second aspect.

[0008] The technical solution provided in this disclosure has the following advantages compared with the prior art: This disclosure provides a display motherboard, a display panel, and a display device. The display motherboard includes multiple display panels, each of which includes an electrostatic discharge (ESD) structure. In the same row, the ESD structures of adjacent display panels are electrically connected via a first connecting line; in the same column, the ESD structures of adjacent display panels are electrically connected via a second connecting line. This disclosure uses first and second connecting lines in the display motherboard to electrically connect the various ESD structures, eliminating the need for additional borders or edge areas for the first and second connecting lines. This achieves ESD protection while reducing the space occupied on the display motherboard. Compared to related technologies that use an anti-static metal ring around the display motherboard, this disclosure eliminates the need for a large anti-static metal ring on the outermost edge of the display motherboard, allowing for a narrower edge area. Therefore, the freed-up edge space allows for a more compact arrangement of display panels, enabling the placement of more or larger display panels within the same size display motherboard. This improves the area utilization of the display motherboard and consequently enhances the production efficiency of display products. Meanwhile, the electrostatic discharge protection network formed by this disclosure is conducive to the current being diverted through multiple paths, thereby reducing the equivalent resistance and thus improving the electrostatic discharge efficiency. Attached Figure Description

[0009] The accompanying drawings, which are incorporated in and form a part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure.

[0010] To more clearly illustrate the technical solutions in the embodiments of this disclosure or the prior art, the accompanying drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, for those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0011] Figure 1 The image shown is a schematic diagram of a display motherboard in related technologies; Figure 2 The image shown is a plan view of a display motherboard provided in an embodiment of this disclosure; Figure 3 The diagram shown is another planar schematic of the display motherboard provided in an embodiment of this disclosure; Figure 4 The image shown is another planar schematic diagram of the display motherboard provided in an embodiment of this disclosure; Figure 5 The diagram shown is another plan view of the display motherboard provided in an embodiment of this disclosure; Figure 6 The diagram shown is another plan view of the display motherboard provided in an embodiment of this disclosure; Figure 7 The diagram shown is another plan view of the display motherboard provided in an embodiment of this disclosure; Figure 8 The figure shown is a cross-sectional schematic diagram of an electrostatic discharge structure provided in an embodiment of this disclosure; Figure 9 The diagram shown is a schematic diagram of a film layer of a display motherboard provided in an embodiment of this disclosure; Figure 10 The diagram shown is a schematic diagram of another film layer of the display motherboard provided in an embodiment of this disclosure; Figure 11 The image shown is a plan view of a display panel provided in an embodiment of this disclosure; Figure 12 The figure shown is a plan view of a display device provided in an embodiment of this disclosure. Detailed Implementation

[0012] To better understand the above-mentioned objectives, features, and advantages of this disclosure, the solutions disclosed herein will be further described below. It should be noted that, unless otherwise specified, the embodiments and features described herein can be combined with each other.

[0013] Numerous specific details are set forth in the following description in order to provide a full understanding of this disclosure, but this disclosure may also be implemented in other ways different from those described herein; obviously, the embodiments in the specification are only some, and not all, of the embodiments of this disclosure.

[0014] The inventors discovered in their research that electrostatic discharge (ESD) is one of the high-risk factors causing damage to display products. In the production process of display panels, a motherboard containing multiple display panels is typically manufactured first, and then cut and split into individual display panels. To improve the ESD problem in the motherboard, an anti-static metal ring is usually placed around its outer edge to discharge static electricity.

[0015] For example, Figure 1 The image shown is a schematic diagram of a display motherboard in related technologies. Please refer to it. Figure 1The display motherboard 000' includes multiple display panels 100'. An anti-static metal ring 20' is provided at the outer edge of the display motherboard 000', surrounding the multiple display panels 100'. The anti-static metal ring 20' provides electrostatic protection to the display motherboard 000' before cutting, discharging at least part of the static electricity generated during the manufacturing process of the display panels 100', thereby preventing the accumulation and discharge of static electricity in the display motherboard 000'. However, the anti-static metal ring 20' occupies space in the display motherboard 000', affecting the area utilization rate of the display motherboard.

[0016] In view of this, the present disclosure provides a display motherboard, a display panel, and a display device to reduce the space occupied by the display motherboard while achieving electrostatic protection.

[0017] Figure 2 The image shown is a plan view of a display motherboard provided in an embodiment of this disclosure. Please refer to it. Figure 2 This disclosure provides a display motherboard 000, which includes a plurality of display panels 100 arranged in a matrix along a first direction F1 and a second direction F2. The first direction F1 and the second direction F2 intersect and are all parallel to the plane where the display motherboard 000 is located.

[0018] The display panel 100 includes a display area AA and a non-display area NA surrounding the display area AA. The non-display area NA includes a bonding area NAb located on one side of the display area AA. The display panel 100 also includes an electrostatic discharge structure 10 and a first signal transmission pin 20. The electrostatic discharge structure 10 is located in the non-display area NA, and the first signal transmission pin 20 is located in the bonding area NAb. The electrostatic discharge structure 10 is electrically connected to the first signal transmission pin 20, and the first signal transmission pin 20 receives a constant voltage signal.

[0019] Along the first direction F1, the electrostatic discharge structures 10 of two adjacent display panels 100 are electrically connected by a first connecting line 31, which extends along the first direction F1; along the second direction F2, the electrostatic discharge structures 10 of two adjacent display panels 100 are electrically connected by a second connecting line 32, which extends along the second direction F2.

[0020] It should be noted that the accompanying drawings in this disclosure are for illustrative purposes only and do not represent the actual structure, size, or quantity of the display motherboard 000 and the display panel 100. For example, Figure 2The accompanying drawings only show four display panels 100 in the display motherboard 000 and do not represent the actual number of display panels 100 in the display motherboard 000. For example, the drawings in this disclosure only illustrate a rectangular display panel 100 as an example and do not limit the actual shape of the display panel 100. Optionally, the display panel 100 can also be a circle, a rounded rectangle, or any other feasible shape. Furthermore, the drawings in this disclosure only show a portion of the signal transmission pins in the bonding area NAb and do not represent the actual number of signal transmission pins. Also, the illustration only uses the example of a display panel 100 including two first signal transmission pins 20 and is not limited thereto.

[0021] Specifically, this disclosure provides a display motherboard 000, which includes a display panel 100. The display panel 100 includes an electrostatic discharge structure 10, which is electrically connected to a first signal transmission pin 20 in a bonding area NAb. The electrostatic discharge structure 10 is used to discharge at least a portion of the static electricity through the first signal transmission pin 20. Before the display motherboard 000 is cut into individual display panels 100, the electrostatic discharge structure 10 is used to provide electrostatic protection for the entire display motherboard 000. After the display motherboard 000 is cut into individual display panels 100, the electrostatic discharge structure 10 in each display panel 100 is used to provide electrostatic protection for the individual display panel 100. In other words, the electrostatic discharge structure 10 is used not only to provide electrostatic protection for the display motherboard 000 before cutting, but also to provide electrostatic protection for the individual display panels 100 after cutting. This configuration helps to provide electrostatic protection for the manufacturing process of the display panel 100 in the display motherboard 000, and also helps to provide continuous electrostatic protection for the individual display panel 100 during subsequent module assembly, transportation and use, thereby improving the reliability of the display product.

[0022] The electrostatic discharge structure 10 is connected to the first signal transmission pin 20, which receives a constant voltage signal. When the electrostatic discharge structure 10 guides electrostatic charge to the first signal transmission pin 20, the first signal transmission pin 20, which receives the constant voltage signal, can quickly, stably, and continuously absorb and neutralize these charges, thereby realizing electrostatic discharge and energy release.

[0023] Optionally, the electrostatic discharge structure 10 is located in the non-display area NA of the display panel 100. Placing the electrostatic discharge structure 10 in the non-display area NA helps avoid occupying space in the display area AA, thereby preventing adverse effects on the aperture ratio of the display panel 100. The aperture ratio of the display panel 100 directly affects the display effect of the display product. This disclosure places the electrostatic discharge structure 10 in the non-display area NA, achieving electrostatic discharge while minimizing the impact on the aperture ratio, thus further ensuring the display effect of the display product.

[0024] The display motherboard 000 includes multiple display panels 100, each display panel 100 including an electrostatic discharge structure 10. Along the first direction F1, the electrostatic discharge structures 10 of adjacent display panels 100 are interconnected via a first connecting line 31, i.e., as shown... Figure 2 From the shown perspective, the electrostatic discharge structures 10 of the horizontally arranged display panels 100 are connected by a first connecting line 31. Along the second direction F2, the electrostatic discharge structures 10 of adjacent display panels 100 are interconnected by a second connecting line 32, i.e., as shown... Figure 2 From the view shown, the static electricity discharge structure 10 of the vertically arranged display panel 100 is connected by the second connecting line 32.

[0025] In this embodiment, along the first direction F1, the electrostatic discharge structures 10 of adjacent display panels 100 in the same row are connected in series. This arrangement allows electrostatic charge to flow laterally and be evenly distributed among the multiple display panels 100, which helps prevent excessive accumulation of electrostatic charge in a single display panel 100 or region within the display motherboard 000. Similarly, along the second direction F2, the electrostatic discharge structures 10 of adjacent display panels 100 in the same column are connected in series. Thus, the electrostatic discharge structures 10 of each display panel 100 in the display motherboard 000 are electrically connected via the first connecting line 31 and the second connecting line 32 to form a grid-like electrostatic discharge network, which facilitates the discharge of static electricity from the display motherboard 000 and provides electrostatic protection for the display motherboard 000.

[0026] It should be noted that the first connecting line 31 and the second connecting line 32 are located in the area between the display areas AA of adjacent display panels 100. This area also includes cutting channels, which are sacrificial spaces reserved during the manufacturing of the display panels for subsequent cutting and separation. After the display motherboard 000 is cut along each cutting channel to form multiple independent display panels 100, the electrostatic discharge structures 10 corresponding to each display panel 100 are disconnected, providing electrostatic discharge and protection for each display panel 100. In this disclosure, the first connecting line 31 and the second connecting line 32 are provided in the display motherboard 000 to electrically connect each electrostatic discharge structure 10, and there is no need to add an extra frame or edge area for the first connecting line 31 and the second connecting line 32. This helps to reduce the space occupied by the display motherboard 000 while achieving electrostatic protection. Compared with the related technology that sets an anti-static metal ring around the display motherboard 000, this disclosure does not require a large anti-static metal ring on the outermost edge of the display motherboard 000, and the edge area of ​​the display motherboard 000 can be designed to be narrower. Therefore, the freed-up edge space allows for a more compact arrangement of the display panels 100, enabling the arrangement of more or larger display panels 100 within a display motherboard 000 of the same size. This improves the area utilization of the display motherboard 000, thereby enhancing the production efficiency of display products. Simultaneously, the electrostatic discharge protection network formed by this disclosure facilitates current diversion through multiple paths, reducing the equivalent resistance and thus improving electrostatic discharge efficiency.

[0027] Figure 3 The diagram shown is another planar schematic of the display motherboard provided in this embodiment. Please refer to [the diagram]. Figure 3 In one optional embodiment of this disclosure, a plurality of first connecting lines 31 are included between two adjacent display panels 100 along the first direction F1, and the first connecting lines 31 are electrically connected to the corresponding electrostatic discharge structure 10.

[0028] This embodiment provides a connection method between two adjacent display panels 100. Specifically, multiple first connecting lines 31 are used to connect the electrostatic discharge structures 10 of two adjacent display panels 100 along the first direction F1. Thus, the design of multiple connecting lines in this embodiment improves the connection reliability of the electrostatic discharge structures 10 corresponding to the two adjacent display panels 100. Simultaneously, the multiple first connecting lines 31 between the two adjacent display panels 100 form a parallel relationship, thereby creating multiple current branches. This helps optimize the electrostatic current distribution, disperse heat in the electrostatic discharge path, and thus helps avoid local overheating, further improving the electrostatic discharge and protection effects.

[0029] It should be noted that the accompanying drawings in this disclosure are only used as an example to illustrate the electrostatic discharge structure 10 between two adjacent display panels 100 along the first direction F1, which includes three first connecting lines 31, and are not limited thereto. The number of first connecting lines 31 can be designed according to the actual situation and requirements of the display product.

[0030] Figure 4 The diagram shown is another planar schematic of the display motherboard provided in this embodiment. Please refer to... Figure 4 Furthermore, this disclosure provides an optional implementation in which multiple first connecting lines 31 between two adjacent display panels 100 along the first direction F1 are arranged at equal intervals along the second direction F2. It should be noted that the accompanying drawings are intended to illustrate that the spacing between any two adjacent first connecting lines 31 is equal, and do not specifically limit the size of the spacing. The specific design can be based on the spacing between adjacent display panels 100 and the routing of the non-display area NA.

[0031] Specifically, in this embodiment, the multiple first connecting lines 31 of the electrostatic discharge structure 10 connecting two adjacent display panels 100 are arranged with equal spacing. In other words, this embodiment uniformly arranges multiple first connecting lines 31 that are connected in parallel with equal spacing. It should be noted that the electrostatic discharge current follows the path of least impedance. The equal spacing arrangement makes the parasitic resistance of each first connecting line 31 tend to be consistent, which helps to ensure that the total electrostatic current is evenly distributed to each first connecting line 31. That is, the current transmission area of ​​each first connecting line 31 is consistent, which helps to avoid overload or even breakage of a single first connecting line 31 due to excessive current. In addition, when the display motherboard 000 is cut into independent display panels 100, the cutting area will be subjected to mechanical stress, thermal stress, etc. from laser or mechanical scribing. The equal spacing arrangement of the first connecting lines 31 helps to distribute the stress generated by cutting more evenly throughout the entire area, thereby helping to avoid stress concentration in areas where the first connecting lines 31 are sparse or absent, reducing the risk of large-area cracks or edge chipping.

[0032] It should also be noted that the first connecting line 31 can be designed in the center to improve the symmetry of the overall wiring structure, which is also conducive to preventing heat accumulation and thus improving static electricity discharge and protection.

[0033] Figure 5 The diagram shown is another plan view of the display motherboard provided in this embodiment. Please refer to... Figure 5In one optional embodiment of this disclosure, the trace width of the first connecting line 31 is greater than the trace width of the electrostatic discharge structure 10. This embodiment differentiates the trace widths of the electrostatic discharge structure 10 and the first connecting line 31. Specifically, the trace width of the first connecting line 31 is set to be wider than the trace width of the electrostatic discharge structure 10, while the trace width of the electrostatic discharge structure 10 is set to be relatively thinner than the trace width of the first connecting line 31.

[0034] It should be noted that although electrostatic discharge (ESD) has a short duration, its peak current can be high. Heat is generated when current passes through metal traces. The narrower the trace width, the higher the current density and the more intense the localized temperature rise. Therefore, when the trace width is narrow, the trace is more prone to melting. This disclosure provides a relatively wide trace width for the first connecting line 31, which helps to increase the melting threshold of the first connecting line 31, enabling it to withstand higher peak currents without melting. This also helps to prevent disconnection between adjacent ESD discharge structures 10, thus improving the ESD protection effect of the display motherboard 000. Furthermore, the ESD discharge structure 10 occupies more space than the first connecting line 31. Although the ESD discharge structure 10 is located in the non-display area NA of the display panel 100, it may still interfere with other circuits or traces in the non-display area NA, which is detrimental to trace layout. This disclosure provides a relatively narrow trace width for the ESD discharge structure 10, resulting in a smaller space occupied by the ESD discharge structure 10 in the non-display area NA. This configuration helps save space in the non-display area NA, leaving more space for other structures such as the gate drive circuit. Therefore, this disclosure not only improves the electrostatic protection effect of the display motherboard 000, but also helps to achieve a narrow bezel design.

[0035] Please refer to Figure 2 In one optional embodiment of this disclosure, along a third direction, the projection of the electrostatic discharge structure 10 onto the plane where the display motherboard 000 is located is a continuous linear structure, and the electrostatic discharge structure 10 at least partially surrounds the display area AA; wherein, the third direction is perpendicular to the plane where the display motherboard 000 is located; and the two ends of the electrostatic discharge structure 10 are respectively connected to two different first signal transmission pins 20. This disclosure provides an implementation of the spatial form, layout range, and connection method of an electrostatic discharge structure 10. Specifically, a continuous linear electrostatic discharge structure 10, at least partially surrounding the display area AA, is provided within the non-display area NA of the display panel 100. The two ends of the linear electrostatic discharge structure 10 are respectively connected to two different constant voltage signal pins (first signal transmission pins 20). The continuous linear structure of the electrostatic discharge structure 10 facilitates the provision of a smooth discharge path for electrostatic charges, reducing charge accumulation at the trace tips and thus preventing the formation of localized strong electric fields at the trace tips. Simultaneously, the electrostatic discharge structure 10 is arranged along the outer contour of the display area AA, which helps prevent electrostatic intrusion from the edges of the display panel 100, thereby providing relatively comprehensive electrostatic protection for the display area AA. Furthermore, the connection of the two ends of the electrostatic discharge structure 10 to two different constant voltage signal pins further facilitates electrostatic discharge.

[0036] Figure 6 The diagram shown is another plan view of the display motherboard provided in this embodiment. Please refer to... Figure 6 In one optional embodiment of this disclosure, along the second direction F2, a bonding area NAb is included between the display areas AA of adjacent display panels 100; in two adjacent display panels 100 along the second direction F2, the electrostatic discharge structure 10 of one display panel 100 is directly connected to the first signal transmission pin 20 in the bonding area NAb, and the electrostatic discharge structure 10 of the other display panel 100 is connected to the first signal transmission pin 20 through the second connecting line 32.

[0037] Specifically, this embodiment provides a specific connection method for the electrostatic discharge structures 10 of two adjacent display panels 100 along the second direction F2. A bonding area NAb is provided between the display areas AA of the two adjacent display panels 100 along the second direction F2. This bonding area NAb is the bonding area NAb of one of the display panels 100. The electrostatic discharge structure 10 of the display panel 100 to which the bonding area NAb belongs is directly connected to the first signal transmission pin 20 in the bonding area NAb. The electrostatic discharge structure 10 of the other display panel 100 is connected to the first signal transmission pin 20 through a second connecting line 32. With this configuration, the two adjacent display panels 100 along the second direction F2 are connected to the same constant voltage pin. Therefore, the electrostatic discharge structures 10 of the two display panels 100 can be considered to be at the same potential. On the one hand, this helps to reduce the potential difference between the electrostatic discharge structures 10 of adjacent display panels 100, avoiding potential difference discharge; on the other hand, it forms an electrostatic discharge network for the display motherboard 000, which is beneficial for electrostatic discharge and protection of the display motherboard 000. Furthermore, compared to related technologies that involve setting an anti-static metal ring around the display motherboard 000, this disclosure eliminates the need for a large anti-static metal ring on the outermost edge of the display motherboard 000, allowing for a narrower edge design. Consequently, the freed-up edge space allows for a more compact arrangement of the display panels 100, enabling the placement of more or larger display panels 100 on a display motherboard 000 of the same size. This improves the area utilization rate of the display motherboard 000, thereby enhancing the production efficiency of display products.

[0038] Please refer to Figure 2 In one optional embodiment of this disclosure, in two adjacent display panels 100 along the second direction F2, the electrostatic discharge structures 10 of both display panels 100 are directly connected to the second connecting line 32. Specifically, in this embodiment, the second connecting line 32 serves as a common bridge, directly connecting to the electrostatic discharge structures 10 of both adjacent display panels 100 along the second direction F2. With this configuration, the second connecting line 32 does not need to be aligned with the first signal transmission pin 20, and its position is more flexible, improving wiring flexibility and reducing wiring complexity. This, in turn, enhances the reliability of the connection between the second connecting line 32 and the electrostatic discharge structure 10, thereby improving the electrostatic discharge and protection capabilities of the display motherboard 000.

[0039] Figure 7 The diagram shown is another plan view of the display motherboard provided in this embodiment. Please refer to it. Figure 7 In one optional embodiment of this disclosure, along the second direction F2, there are multiple second connecting lines 32 between the electrostatic discharge structures 10 of two adjacent display panels 100, and the multiple second connecting lines 32 are arranged along the first direction F1.

[0040] Specifically, the electrostatic discharge structures 10 of two adjacent display panels 100 along the first direction F1 are connected by a first connecting line 31, and the electrostatic discharge structures 10 of two adjacent display panels 100 along the second direction F2 are connected by a second connecting line 32, thereby forming an electrostatic discharge network that can provide electrostatic transmission and discharge for the display motherboard 000. In this embodiment, the electrostatic discharge structures 10 of two adjacent display panels 100 along the second direction F2 include multiple second connecting lines 32, which are connected in parallel. Electrostatic current can be conducted simultaneously through multiple parallel second connecting lines 32, significantly reducing the total impedance and accelerating the discharge speed, which is beneficial to improving the electrostatic discharge efficiency and thus improving the electrostatic protection capability of the display motherboard 000. At the same time, multiple second connecting lines 32 also help to avoid the inability to connect the electrostatic discharge structure 10 due to the failure of a single second connecting line 32, thereby improving the fault tolerance capability of the connection between the electrostatic discharge structure 10 and the second connecting line 32 and improving the overall reliability.

[0041] It should be noted that this embodiment is intended to illustrate that the electrostatic discharge structures 10 corresponding to two adjacent display panels 100 along the second direction F2 are connected by multiple second connecting lines 32. The second connecting lines 32 can be directly connected to the first signal transmission pin 20 or directly connected to the corresponding electrostatic discharge structure 10. This disclosure does not make any specific limitations.

[0042] Please continue to refer to this. Figure 7 In one optional embodiment of this disclosure, the display panel 100 includes a first center line 40 extending along a second direction F2; a plurality of second connecting lines 32 between two adjacent display panels 100 along the second direction F2 are symmetrically arranged on both sides of the first center line 40.

[0043] Specifically, the display panel 100 has at least one first center line 40 extending along the second direction F2 (vertical direction). The first center line 40 can be considered as the geometric axis of symmetry of the display panel 100 itself, passing through the center of the display area AA and dividing the panel into two symmetrical regions. In this embodiment, with the first center line 40 as the axis of symmetry, multiple second connecting lines 32 are distributed in a mirror-symmetrical manner on the left and right sides of the first center line 40. It should be noted that an asymmetrical arrangement will cause current to concentrate on the side with denser second connecting lines 32, while the sparse side may become a weak point in protection. The symmetrical arrangement corresponding to the embodiment of this disclosure eliminates this imbalance, making the current distribution carried by each second connecting line 32 more uniform. At the same time, it also helps to avoid current concentration, further improving the electrostatic protection and discharge effect of the display motherboard 000.

[0044] It should be noted that this disclosure Figure 7Four second connecting lines 32 are included between two adjacent display panels 100 along the second direction F2. Two of the second connecting lines 32 are directly connected to the first signal transmission pin 20, and two of the second connecting lines 32 are directly connected to the electrostatic discharge structure 10. This embodiment aims to illustrate that multiple second connecting lines 32 are symmetrically distributed on both sides of the first center line 40. It does not specifically limit the specific number of second connecting lines 32, nor does it limit whether the second connecting lines 32 are directly connected to the first signal transmission pin 20 or directly connected to the electrostatic discharge structure 10. The specific design can be made according to the actual situation.

[0045] Figure 8 The diagram shown is a cross-sectional schematic of an electrostatic discharge structure provided in an embodiment of this disclosure. Please refer to [the diagram]. Figure 2 and Figure 8 Optionally, the trace width of the electrostatic discharge structure 10 is S0, where S0 ≥ 10 μm. It should be noted that, due to... Figure 2 The trace width S0 of the electrostatic discharge structure 10 cannot be shown in the diagram. This disclosure... Figure 8 It shows Figure 2 A schematic cross-section of the electrostatic discharge structure 10 in the central region Q, wherein the third direction F3 is perpendicular to the plane where the display motherboard 000 is located, and S0 represents the trace width of the electrostatic discharge structure 10.

[0046] Specifically, when the trace width S0 of the electrostatic discharge structure 10 is less than 10 μm, the trace width is small, resulting in a larger resistance and lower electrostatic conduction efficiency. Simultaneously, the electrostatic current passing through the electrostatic discharge structure 10 generates heat, and with a smaller trace width, it is more easily melted. Therefore, this disclosure sets the trace width S0 of the electrostatic discharge structure 10 to S0 ≥ 10 μm. This setting results in a relatively larger trace width, leading to a smaller resistance and higher electrostatic conduction efficiency. This helps to shorten the time that static electricity remains inside the display panel 100 or display motherboard 000, thereby reducing the risk of device breakdown in the display product. Furthermore, a relatively larger trace width results in a larger cross-sectional area, which helps to increase the melting threshold of the electrostatic discharge structure 10, making it less prone to melting and further improving the electrostatic protection capability of the display product. This disclosure provides an optional embodiment in which the trace width S0 of the electrostatic discharge structure 10 is 12 μm; another optional embodiment in which the trace width S0 of the electrostatic discharge structure 10 is 15 μm; yet another optional embodiment in which the trace width S0 of the electrostatic discharge structure 10 is 16 μm; yet another optional embodiment in which the trace width S0 of the electrostatic discharge structure 10 is ≥20 μm; and yet another optional embodiment in which the trace width S0 of the electrostatic discharge structure 10 is ≥30 μm.

[0047] Please refer to Figure 2In one optional embodiment of this disclosure, the first signal transmission pin 20 is grounded. Specifically, the first signal transmission pin 20 is located within the bonding area NAb of the display panel 100 and is electrically connected to the electrostatic discharge structure 10 for receiving a constant voltage signal. In this embodiment, the first signal transmission pin 20 is grounded. It should be noted that the essence of electrostatic discharge is the rapid transfer of charge. In order to effectively protect the internal circuit, it is necessary to guide these excess charges to a node that can absorb charges infinitely while maintaining a constant potential. Systematically, this is precisely such an ideal electrostatic charge "absorption tank". After the first signal transmission pin 20 is grounded, the potential of the first signal transmission pin 20 is forcibly clamped at 0V and will not fluctuate due to the magnitude of the electrostatic current. With this setting, the potential of the electrostatic discharge structure 10 always tends to be close to 0V, thereby minimizing the voltage impact on the internal circuit during electrostatic discharge. At the same time, after the first signal transmission pin 20 is grounded, the electrostatic discharge structure 10 is 0V in a static state and will not generate a DC bias electric field on adjacent signal lines (such as data lines and scan lines), which further helps to reduce the adverse effects on other signal lines. In addition, the bonding area NAb usually already has at least two ground pins. Connecting the electrostatic discharge structure 10 directly to these existing ground pins does not require adding new signal types, nor does it occupy valuable non-ground pin resources.

[0048] Figure 9 The diagram shown is a schematic representation of a film layer of a display motherboard provided in an embodiment of this disclosure. Please refer to it. Figure 2 and Figure 9 In one optional embodiment of this disclosure, the display panel 100 includes a substrate 01 and a driving layer 02 stacked along a third direction F3, which is perpendicular to the plane where the display mother panel 000 is located. The driving layer 02 includes a polysilicon layer 021, a first insulating layer 022, a first metal layer 023, a second insulating layer 024, and a second metal layer 025.

[0049] Along the third direction F3, the polysilicon layer 021 is located on one side of the substrate 01, the first insulating layer 022 is located on the side of the polysilicon layer 021 away from the substrate 01, the first metal layer 023 is located on the side of the first insulating layer 022 away from the substrate 01, the second insulating layer 024 is located on the side of the first metal layer 023 away from the first metal layer 023, and the second metal layer 025 is located on the side of the second insulating layer 024 away from the second insulating layer 024; at least a portion of the electrostatic discharge structure 10 is located in the polysilicon layer 021.

[0050] Specifically, this embodiment provides a specific implementation of a film structure; please refer to [the relevant documentation]. Figure 9From the shown perspective, the display panel 100 includes a substrate 01, a polysilicon layer 021, a first insulating layer 022, a first metal layer 023, a second insulating layer 024, and a second metal layer 025 stacked from bottom to top. In an optional embodiment provided by this disclosure, the driving layer 02 includes a plurality of transistors T0, each transistor T0 including a gate G, a source S, and a drain D. The gate G is located on the first metal layer 023, and the source S and drain D are located on the second metal layer 025. The source S and drain D are connected to the polysilicon layer 021 through contact holes. Optionally, the substrate 01 is a glass substrate or a polyimide substrate, and the substrate 01 is used to support at least other film layers. The polysilicon layer 021 (Poly layer) forms the active region of the transistor T0 through crystallization and doping. The first insulating layer 022 can be a gate insulating layer (GI) used to isolate the polysilicon layer 021 and the first metal layer 023. The first metal layer 023 typically serves as the gate metal, forming the gate G of the transistor T0 and the gate signal line. The second insulating layer 024 can be an interlayer insulating layer (ILD) used to isolate the first metal layer 023 and the second metal layer 025. The second metal layer 025 is typically used as the source-drain metal (SD), forming the source S, drain D, and data signal lines of transistor T0.

[0051] It should be noted that the above-described film structure can form a top-gate transistor, that is, the gate G is located above the polysilicon layer 021. The polysilicon layer 021 is located at the bottom layer immediately adjacent to the substrate 01, and there are, in sequence, a gate insulating layer, a gate metal, an interlayer insulating layer, and source / drain metal on it. This disclosure is only described using the above embodiment as an example and is not limited thereto. For example, the transistor can also be a bottom-gate structure. The embodiments of this disclosure aim to illustrate that at least a portion of the electrostatic discharge structure 10 is located in the polysilicon layer 021, that is, at least a portion of the electrostatic discharge structure 10 is disposed in the same layer as the polysilicon layer 021. With this arrangement, moving the electrostatic discharge structure 10 into the polysilicon layer 021 is equivalent to using a layer that was originally mainly used to form the active region to undertake additional electrical functions, thereby freeing up the wiring space of the first metal layer 023 and the second metal layer 025, which is beneficial for optimizing signal transmission and circuit design in the first metal layer 023 and the second metal layer 025. Meanwhile, no additional metal layer or photomask is needed for the electrostatic discharge structure 10. At least a portion of the electrostatic discharge structure 10 can be completed in the existing polysilicon layer 021 photolithography process, which also helps to reduce production costs and improve production efficiency.

[0052] Please continue to refer to this. Figure 2 and Figure 9Furthermore, this disclosure provides an optional embodiment in which each region of the electrostatic discharge structure 10 is located within the polysilicon layer 021. Specifically, in this embodiment, the electrostatic discharge structure 10 is entirely located within the polysilicon layer 021, which further facilitates the release of wiring space in the first metal layer 023 and the second metal layer 025, and also avoids the need to add a separate film layer for the electrostatic discharge structure 10, thus reducing the number of metal layers required. In addition, the all-polysilicon electrostatic discharge structure 10 is less prone to open circuits or short circuits caused by electromigration even under multiple high-energy electrostatic discharge impacts, which helps to improve the reliability of the electrostatic discharge structure 10 and improve the electrostatic protection effect for display products.

[0053] Figure 10 The diagram shown is a schematic diagram of another film layer of the display motherboard provided in this embodiment. Please refer to... Figure 2 and Figure 10 In one optional embodiment of this disclosure, the electrostatic discharge structure 10 includes a first discharge portion 11 and a second discharge portion 12. The first discharge portion 11 is located in the polysilicon layer 021, and the second discharge portion 12 is located in the second metal layer 025. The first discharge portion 11 and the second discharge portion 12 are electrically connected through a via.

[0054] It should be noted that, Figure 9 and Figure 10 In order to distinguish the electrostatic discharge structure 10 from other structures, the electrostatic discharge structure 10 is filled, but the material of the electrostatic discharge structure 10 is not limited.

[0055] Specifically, in this embodiment, the electrostatic discharge structure 10 includes at least a first discharge portion 11 and a second discharge portion 12, which are distributed across at least two different film layers. For example, the first discharge portion 11 is disposed on the polysilicon layer 021, and the second discharge portion 12 is disposed on the second metal layer 025, forming a double-layer composite structure spanning the polysilicon layer 021 and the second metal layer 025. The two layers are electrically connected through vias to jointly complete the transmission and discharge of electrostatic charge. This embodiment distributes the electrostatic discharge structure 10 across two different film layers, thus allowing different areas of the electrostatic discharge structure 10 to be distributed on different film layers according to actual needs. This provides electrostatic protection for display products while also increasing the flexibility of wiring.

[0056] Based on the same inventive concept, this disclosure provides a display panel. Figure 11 The image shown is a plan view of a display panel provided in an embodiment of this disclosure. Please refer to... Figure 2 and Figure 11 The display panel 100 is cut from the display motherboard 000, which is any of the display motherboards 000 provided in the embodiments of this disclosure.

[0057] It should be noted that the implementation of the display panel 100 can refer to any implementation of the display motherboard 000 provided in this disclosure, and the repeated parts will not be described again in this disclosure.

[0058] Based on the same inventive concept, this disclosure provides a display device. Figure 12 The diagram shown is a plan view of a display device provided in an embodiment of this disclosure. Please refer to it. Figure 12 The display device 200 includes a display panel 100, which is any type of display panel 100 provided in the embodiments of this disclosure.

[0059] It should be noted that the embodiments of the display device 200 provided in this application can refer to the embodiments of the display panel 100 described above, and the repeated parts will not be described again in this disclosure. The display device 200 provided in this application can be any product and component with display function, such as a mobile phone, tablet computer, television, monitor, laptop computer, or navigator.

[0060] As can be seen from the above embodiments, the display motherboard, display panel, and display device provided in this disclosure achieve at least the following beneficial effects: This disclosure provides a display motherboard, a display panel, and a display device. The display motherboard includes multiple display panels, each of which includes an electrostatic discharge (ESD) structure. In the same row, the ESD structures of adjacent display panels are electrically connected via a first connecting line; in the same column, the ESD structures of adjacent display panels are electrically connected via a second connecting line. This disclosure uses first and second connecting lines in the display motherboard to electrically connect the various ESD structures, eliminating the need for additional borders or edge areas for the first and second connecting lines. This achieves ESD protection while reducing the space occupied on the display motherboard. Compared to related technologies that use an anti-static metal ring around the display motherboard, this disclosure eliminates the need for a large anti-static metal ring on the outermost edge of the display motherboard, allowing for a narrower edge area. Therefore, the freed-up edge space allows for a more compact arrangement of display panels, enabling the placement of more or larger display panels within the same size display motherboard. This improves the area utilization of the display motherboard and consequently enhances the production efficiency of display products. Meanwhile, the electrostatic discharge protection network formed by this disclosure is conducive to the current being diverted through multiple paths, thereby reducing the equivalent resistance and thus improving the electrostatic discharge efficiency.

[0061] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0062] The above description is merely a specific embodiment of this disclosure, enabling those skilled in the art to understand or implement it. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of this disclosure. Therefore, this disclosure is not to be limited to the embodiments described herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A display motherboard, characterized in that, It includes multiple display panels arranged in a matrix along a first direction and a second direction, wherein the first direction and the second direction intersect and are both parallel to the plane where the display mother panel is located; The display panel includes a display area and a non-display area surrounding the display area, the non-display area including a binding area located on one side of the display area; The display panel further includes an electrostatic discharge structure and a first signal transmission pin. The electrostatic discharge structure is located in the non-display area, and the first signal transmission pin is located in the bonding area. The electrostatic discharge structure is electrically connected to the first signal transmission pin, and the first signal transmission pin receives a constant voltage signal. Along the first direction, the electrostatic discharge structures of two adjacent display panels are electrically connected by a first connecting line, which extends along the first direction; Along the second direction, the electrostatic discharge structures of two adjacent display panels are electrically connected by a second connecting line extending along the second direction.

2. The display motherboard according to claim 1, characterized in that, A plurality of first connecting lines are included between two adjacent display panels along the first direction, and the first connecting lines are electrically connected to the corresponding electrostatic discharge structure.

3. The display motherboard according to claim 2, characterized in that, Multiple first connecting lines between two adjacent display panels along the first direction are arranged at equal intervals along the second direction.

4. The display motherboard according to claim 1, characterized in that, The width of the first connecting line is greater than the width of the electrostatic discharge structure.

5. The display motherboard according to claim 1, characterized in that, Along a third direction, the projection of the electrostatic discharge structure onto the plane of the display motherboard is a continuous linear structure, and the electrostatic discharge structure at least partially surrounds the display area; wherein, the third direction is perpendicular to the plane of the display motherboard; The electrostatic discharge structure is connected to two different first signal transmission pins at its two ends.

6. The display motherboard according to claim 5, characterized in that, Along the second direction, a bonding area is included between the display areas of adjacent display panels; In two adjacent display panels along the second direction, the electrostatic discharge structure of one display panel is directly connected to the first signal transmission pin in the bonding area, and the electrostatic discharge structure of the other display panel is connected to the first signal transmission pin through the second connecting line.

7. The display motherboard according to claim 5, characterized in that, In two adjacent display panels along the second direction, the electrostatic discharge structure of both display panels is directly connected to the second connecting line.

8. The display motherboard according to claim 5, characterized in that, Along the second direction, there are multiple second connecting lines between the electrostatic discharge structures of two adjacent display panels, and the multiple second connecting lines are arranged along the first direction.

9. The display motherboard according to claim 8, characterized in that, The display panel includes a first center line extending along a second direction; Multiple second connecting lines between two adjacent display panels along the second direction are symmetrically arranged on both sides of the first center line.

10. The display motherboard according to claim 1, characterized in that, The trace width of the electrostatic discharge structure is S0, where S0 ≥ 10 μm.

11. The display motherboard according to claim 1, characterized in that, The first signal transmission pin is grounded.

12. The display motherboard according to claim 1, characterized in that, The display panel includes a substrate and a driving layer stacked along a third direction, the third direction being perpendicular to the plane where the display mother panel is located; The driving layer includes a polysilicon layer, a first insulating layer, a first metal layer, a second insulating layer, and a second metal layer; Along the third direction, the polysilicon layer is located on one side of the substrate, the first insulating layer is located on the side of the polysilicon layer away from the substrate, the first metal layer is located on the side of the first insulating layer away from the substrate, the second insulating layer is located on the side of the first metal layer away from the first metal layer, and the second metal layer is located on the side of the second insulating layer away from the second insulating layer. At least a portion of the electrostatic discharge structure is located in the polycrystalline silicon layer.

13. The display motherboard according to claim 12, characterized in that, Each region of the electrostatic discharge structure is located in the polycrystalline silicon layer.

14. The display motherboard according to claim 12, characterized in that, The electrostatic discharge structure includes a first discharge section and a second discharge section. The first discharge section is located in the polysilicon layer, and the second discharge section is located in the second metal layer. The first discharge section and the second discharge section are electrically connected through a via.

15. The display motherboard according to claim 12, characterized in that, The driving layer includes a plurality of transistors, each transistor including a gate, a source, and a drain. The gate is located in the first metal layer, and the source and drain are located in the second metal layer. The source and drain are connected to the polysilicon layer through contact holes.

16. A display panel, characterized in that, It is cut from the display motherboard according to any one of claims 1 to 15.

17. A display device, characterized in that, Includes the display panel as described in claim 16.

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