A chip testing method based on three-dimensional flash chip defective distribution characteristics
By sampling and testing flash memory blocks and pages in high-defect-probability areas, setting thresholds to verify bit error rates and classifying them, the problems of long processing time and high cost in existing technologies are solved, achieving efficient and accurate chip testing, and improving production capacity and market competitiveness.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- CHIPMOS TECHNOLOGIES (SHANGHAI) LTD
- Filing Date
- 2026-03-31
- Publication Date
- 2026-06-16
AI Technical Summary
Existing 3D NAND flash memory chip testing methods are time-consuming and costly, and their accuracy is not high, failing to meet mass production requirements.
By selecting flash memory blocks and pages with high probability of defects for sampling tests, setting flash memory thresholds and performing bit error rate verification, determining the chip quality level based on the number of defective blocks, and performing full-block and full-page secondary screening and ECC error correction on Grade A chips.
It enables rapid, low-cost, and accurate chip testing, significantly increasing production capacity. It is highly applicable, meets the needs of different application scenarios, and enhances market competitiveness.
Smart Images
Figure CN122224261A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of chip testing technology, and more specifically to a chip testing method based on the defect distribution characteristics of three-dimensional flash memory chips. Background Technology
[0002] 3D NAND flash memory achieves high-density storage by stacking memory cell layers, but its complex manufacturing process results in inherent defective distribution characteristics within the chip die. Existing testing methods test all blocks and all pages to identify defects, which is time-consuming and costly. Alternatively, methods that randomly select a certain number of blocks and randomly select pages from those blocks for testing result in low accuracy and significant bias, failing to meet the high-efficiency requirements of mass production.
[0003] Therefore, there is a need for a chip testing method that can utilize the characteristics of poor distribution to achieve fast, low-cost, and accurate selection. Summary of the Invention
[0004] To address the problems mentioned in the background art, this invention provides a chip testing method based on the defect distribution characteristics of a three-dimensional flash memory chip, comprising the following steps: S1, selecting flash memory blocks with a high probability of defect occurrence as sampling blocks, specifically flash memory blocks in the stepped region of the three-dimensional flash memory chip and flash memory blocks at the four edges of the three-dimensional flash memory chip; S2, further selecting flash memory pages with a high probability of defect occurrence from each sampling block as sampling pages, specifically flash memory pages in the 0-10%, 45-55%, and 90-100% stacked layers of the three-dimensional flash memory chip from bottom to top; S3, further processing the sampling pages... The process involves a write-and-read verification operation, collecting the original bit error rate (BER), setting a flash memory threshold, and comparing the collected BER with the preset flash memory threshold. If the BER of any flash memory page exceeds the flash memory threshold, the flash memory block containing that page is marked as a defective flash memory block. S4: The number of defective flash memory blocks marked as defective in the tested chip is counted. Based on the relationship between the number of defective flash memory blocks and the total number of sampled flash memory blocks, the chip's quality level is determined and divided into four levels: A, B, C, and D. S5: For chips whose quality level is determined to be A in step S4, a second screening of all pages of the entire flash memory block is performed, along with ECC error correction. Chips that can be corrected are classified as A+ level.
[0005] In step S1, the flash memory blocks in the stepped area include at least one column and at least one row of flash memory blocks adjacent to the stepped window, and the flash memory blocks at the edge position include at least one row and at least one column of flash memory blocks around the outermost ring of the chip.
[0006] The total number of sampled flash memory blocks is the same as the number of sampled blocks in step S1.
[0007] In step S3, the flash memory threshold is set according to the flash memory manufacturer's technical instructions.
[0008] The quality grades in step 4 include: Grade A: number of defective flash memory blocks ≤ 10% of the total number of sampled flash memory blocks; Grade B: 10% of the total number of sampled flash memory blocks < number of defective flash memory blocks ≤ 25% of the total number of sampled flash memory blocks; Grade C: 25% of the total number of sampled flash memory blocks < number of defective flash memory blocks < total number of sampled flash memory blocks; Grade D: number of defective flash memory blocks = total number of sampled flash memory blocks.
[0009] Compared with existing technologies, this invention improves testing efficiency by precisely selecting blocks and pages with high defect probability for sampling and testing, avoiding full testing of a large number of low defect probability areas, saving a lot of time, significantly increasing production capacity, having strong applicability, flexible product grading, meeting the needs of different application scenarios, enhancing market competitiveness, and maximizing product value. Attached Figure Description
[0010] Figure 1 This is a schematic diagram of the chip testing method flow; Figure 2 This is a partial framework diagram of a 128-layer 3D flash memory chip; Detailed Implementation
[0011] The present invention will now be further described with reference to the accompanying drawings.
[0012] like Figure 1 A chip testing method based on the defect distribution characteristics of a 3D flash memory chip includes the following steps: S1, selecting flash memory blocks with high defect probability as sampling blocks, specifically the flash memory blocks in the stepped area of the 3D flash memory chip and the flash memory blocks at the four edges of the 3D flash memory chip; S2, further selecting flash memory pages with high defect probability from each sampling block as sampling pages, specifically the flash memory pages in the 0-10%, 45-55%, and 90-100% stacked layers of the 3D flash memory chip from bottom to top; S3, performing write-and-read verification operations on the sampling pages. The original bit error rate of the flash memory is collected, a flash memory threshold is set, and the collected original bit error rate is compared with the preset flash memory threshold. If the original bit error rate of any flash memory page exceeds the flash memory threshold, the flash memory block containing that flash memory page is marked as a defective flash memory block. S4. The number of flash memory blocks marked as defective in the tested chip is counted. Based on the relationship between the number of defective flash memory blocks and the total number of sampled flash memory blocks, the quality level of the chip is determined and divided into four levels: A, B, C, and D. S5. For the chips whose quality level is determined to be A in step S4, a second screening of all pages of the entire flash memory block is performed, and ECC error correction is carried out. The correctable chips are determined to be A+ level.
[0013] In step S1, the flash memory blocks in the stepped area include at least one column and at least one row of flash memory blocks adjacent to the stepped window, and the flash memory blocks at the edge position include at least one row and at least one column of flash memory blocks around the outermost ring of the chip.
[0014] The flash memory block in the stepped region of the three-dimensional flash memory chip is selected in step S1 because this region is the main area for the deposition of etching by-products (polymers) and the interlayer stress is also concentrated in this region. The stepped region is a double superposition area of "physical traps" of etching by-product deposition and "mechanical singularities" of stress concentration, which makes this region a high-incidence area of defective blocks in three-dimensional flash memory. The total number of sampled flash blocks is the same as the number of sampled blocks in step S1.
[0015] In step S2, flash memory pages of the 3D flash memory chip are selected from the bottom up, representing 0-10%, 45-55%, and 90-100% stacked layers. Flash memory pages with 0-10% stacked layers are selected because the bottom layer is the initial stacked layer adjacent to the silicon substrate, which is prone to defects due to the physical limits of etching, such as bottom drilling, reduced contact area between the ONO layer and the silicon channel, tilted hole bottom, word line coupling capacitor mismatch, and intrinsic defects at the substrate interface. Flash memory pages with 45-55% stacked layers are selected because the weight of the upper stacked layer and the constraint of the lower substrate cause the middle layer to bear bidirectional compressive stress, and the superposition of stress wave reflections at the ONO interface of multiple layers leads to local stress peaks, large step width deviations, and decreased hole uniformity, resulting in discrete cell threshold voltages, thus increasing the probability of defects. Flash memory pages with 90-100% stacked layers are selected because the top step etching is difficult to control, resulting in word line top breakage, contact hole and word line misalignment, plasma cumulative damage, and particulate contamination, thus increasing the probability of defects.
[0016] The total number of sampled flash blocks is the same as the number of sampled blocks in step S1.
[0017] In step S3, the flash memory threshold is set according to the flash memory manufacturer's technical instructions. For example, for consumer-grade TLC flash memory, the flash memory threshold is set as follows: .
[0018] The quality grades mentioned in step 4 include: Grade A: number of defective flash memory blocks ≤ 10% of the total number of sampled flash memory blocks; Grade B: 10% of the total number of sampled flash memory blocks < number of defective flash memory blocks ≤ 25% of the total number of sampled flash memory blocks; Grade C: 25% of the total number of sampled flash memory blocks < number of defective flash memory blocks < total number of sampled flash memory blocks; Grade D: number of defective flash memory blocks = total number of sampled flash memory blocks.
[0019] The chip testing method of the present invention will be described below with reference to specific examples.
[0020] like Figure 2The inspection focused on a 128-layer 3D flash memory chip. This chip contains 1024 flash memory blocks arranged in a 32x32 physical grid, with each block containing 1024 flash memory pages. Flash memory blocks with a high probability of defect occurrence were selected as sampling blocks, such as... Figure 2 The flash memory blocks in the stepped region of the 3D NAND flash chip are all the flash memory blocks in the 31st column (31, 63, 95...1023), totaling 32. The flash memory blocks at the edge of the 3D NAND flash chip are all the flash memory blocks in the 31st row (992-1022), totaling 31. The flash memory blocks in the 0th row (0-30), totaling 31, are also included, for a total of 94 sampling blocks. Then, from these 94 sampling blocks, the flash memory pages of the 0-1%, 49-51%, and 99-100% stacking layers of the 3D NAND flash chip are selected, specifically the flash memory pages 0-10, 502-522, and 1014-1024, totaling 40 sampling pages. Sampling is performed every 40 sampling pages from these 94 selected sampling blocks, collecting only the raw bit error rate (RBER), with a flash memory threshold set to... If the original bit error rate of any sampling page at the bottom, middle, or top level is greater than... Immediately mark the sampling block containing the sampled page as a defective flash memory block. Compared to testing all pages in all blocks, this saves approximately 99.64% of testing time. Based on the statistical results of the 94 sampled blocks, the following classifications were made: ≤10 defective flash memory blocks were classified as Grade A (full capacity); 10 < ≤24 defective flash memory blocks were classified as Grade B (full capacity); 24 < ≤94 defective flash memory blocks were classified as Grade C (insufficient capacity); and 94 defective flash memory blocks were classified as Grade D (defective). For Grade A (full capacity), a full-block, full-page testing scheme was adopted, and ECC error correction was enabled. Dies that passed full testing and were ECC-correctable were marked as Grade A+.
Claims
1. A chip testing method based on the defect distribution characteristics of three-dimensional flash memory chips, characterized in that: Includes the following steps: S1. Select flash memory blocks with a high probability of defect occurrence as sampling blocks. Specifically, these are flash memory blocks in the stepped area of the 3D flash memory chip and flash memory blocks at the four edges of the 3D flash memory chip. S2. Further select flash memory pages with a high probability of defect occurrence from each sampling block in S1. Specifically, these are flash memory pages in the 0-10%, 45-55%, and 90-100% stacking layers of the 3D flash memory chip from bottom to top. S3. Perform write-and-read verification operations on the sampling pages, collect their original bit error rate, and set a flash memory threshold. The collected raw bit error rate is compared with a preset flash memory threshold. If the raw bit error rate of any flash memory page exceeds the flash memory threshold, the flash memory block containing that flash memory page is marked as a defective flash memory block. S4: The number of flash memory blocks marked as defective in the tested chip is counted. Based on the relationship between the number of defective flash memory blocks and the total number of sampled flash memory blocks, the quality level of the chip is determined and divided into four levels: A, B, C, and D. S5: For the chips whose quality level is determined to be A in step S4, a second screening of all pages of the entire flash memory block is performed, and ECC error correction is carried out. Chips that can be corrected are judged to be A+ level.
2. The chip testing method based on the defect distribution characteristics of a three-dimensional flash memory chip according to claim 1, characterized in that: In step S1, the flash memory blocks in the stepped region include at least one column and at least one row of flash memory blocks adjacent to the steps, and the flash memory blocks at the edge position include at least one row and at least one column of flash memory blocks around the outermost perimeter of the chip.
3. The chip testing method based on the defect distribution characteristics of a three-dimensional flash memory chip according to claim 1, characterized in that: The total number of sampled flash memory blocks is the same as the number of sampled blocks in step S1.
4. The chip testing method based on the defect distribution characteristics of a three-dimensional flash memory chip according to claim 1, characterized in that: In step S3, the flash memory threshold is set according to the flash memory manufacturer's technical instructions.
5. The chip testing method based on the defect distribution characteristics of a three-dimensional flash memory chip according to claim 1, characterized in that: The quality grades in step 4 include: Grade A: number of defective flash memory blocks ≤ 10% of the total number of sampled flash memory blocks; Grade B: 10% of the total number of sampled flash memory blocks < number of defective flash memory blocks ≤ 25% of the total number of sampled flash memory blocks; Grade C: 25% of the total number of sampled flash memory blocks < number of defective flash memory blocks < total number of sampled flash memory blocks; Grade D: number of defective flash memory blocks = total number of sampled flash memory blocks.