A semiconductor device and a method of fabricating the same

Abstract

The application belongs to the technical field of semiconductor devices, and discloses a semiconductor device and a preparation method thereof. The method first selectively forms a pre-growth oxide layer on a substrate, so that the oxide layer grown subsequently is thicker in an NMOS region, thereby establishing a thickness compensation basis in an initial stage. Then, through the synergistic effect of cavity etching and Sigma etching, that is, using the thicker OX layer in the NMOS region as an etching stop layer, the substrate outside the NMOS gate region is protected from being damaged, at this time, the HMOX on the P / NMOS gate etches downward at the same time, which ensures that the gate heights of the two MOSs are basically flat, significantly improves the planarization degree of the gate structure, not only avoids the non-uniform polishing defects in the CMP process, eliminates the risk of polysilicon residue, but also guarantees the complete filling and interface quality of the metal gate, thereby greatly improving the electrical performance and long-term reliability of the semiconductor device.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor device technology, and relates to a semiconductor device and its preparation method. Background Technology

[0002] As semiconductor manufacturing processes iterate towards higher performance and lower power consumption, the refinement of device structures and the complexity of process steps continue to increase. The differences in manufacturing processes between P-type metal-oxide-semiconductor (PMOS) and N-type metal-oxide-semiconductor (NMOS) devices are gradually becoming a key factor affecting chip yield. The manufacturing processes of PMOS and NMOS differ significantly. PMOS introduces an additional silicon-germanium (SiGe) process compared to NMOS. The SiGe process has additional process effects on the hard mask oxide (HMOX) layer above the PMOS gate, such as HMOX consumption due to etching, ultimately resulting in a significantly lower HMOX height on the PMOS gate compared to NMOS. Figure 1 As shown, before inter-layer dielectric chemical mechanical polishing (ILD0 CMP), a portion of the oxide layer (OX) remains on the NMOS gate, while the OX on the PMOS gate has been completely consumed. This difference in HMOX height directly leads to inconsistent behavior between the two devices in the subsequent inter-layer dielectric chemical mechanical polishing (CMP) process, such as... Figure 2 As shown, during the CMP process, low-density regions and regions with relatively low gate height (corresponding to PMOS) are polished to the "dummy gate," i.e., the polysilicon gate, earlier. Meanwhile, high-density regions and regions with higher gate height (corresponding to NMOS) are only polished to the silicon nitride (SIN) layer. This asynchronous polishing result means that some polysilicon in the NMOS region cannot be completely removed in the subsequent dummy gate removal process. It is blocked by the top silicon nitride layer, and the remaining polysilicon occupies the filling space of the metal gate, preventing the metal gate from completely filling the predetermined structure. This, in turn, damages the device's electrical parameters, such as threshold voltage shift and drive current decrease, while also reducing the device's long-term reliability. Summary of the Invention

[0003] To address the problems existing in the prior art, the present invention provides a semiconductor device and its fabrication method, thereby solving the technical problem that in the prior art, the SiGe process with more PMOS than NMOS results in the HMOX height above the gate being lower than that of NMOS, which in turn leads to inconsistent polishing behavior of the two in the interlayer dielectric CMP process, causing polysilicon gate residue and poor metal gate filling in some NMOS, ultimately affecting the electrical performance and reliability of the device.

[0004] This invention is achieved through the following technical solution: A method for fabricating a semiconductor device includes the following steps: A substrate is provided on which N-type wells and P-type wells are formed, wherein the N-type wells and P-type wells are isolated from each other. A pre-grown oxide layer is grown on the substrate, and the pre-grown oxide layer is selectively etched. Specifically, the selective etching involves removing all the pre-grown oxide layer on the N-type well side and partially removing the pre-grown oxide layer on the P-type well side, with the center line of the isolation structure as the boundary. A gate oxide layer is grown on the substrate surface, making the total oxide layer thickness in the NMOS region greater than that in the PMOS region; An initial PMOS stack structure and an initial NMOS stack structure are formed in the N-type well and P-type well regions; The initial PMOS stack structure and the initial NMOS stack structure are subjected to Cavity etching and Sigma etching. The retained pre-grown oxide layer is used as a barrier layer to make the hard mask silicon oxide layer of the PMOS and NMOS regions ultimately have the same height.

[0005] Preferably, the partial removal specifically involves: retaining the pre-grown oxide layer on the substrate outside the gate region of the P-type well, and removing all the pre-grown oxide layers in the remaining regions.

[0006] Preferably, the thickness of the pre-grown oxide layer retained on the substrate outside the P-type well gate region is 40~70 Å.

[0007] Preferably, the step of growing the gate oxide layer is as follows: using an in-situ vapor generation oxidation process, a gate oxide layer is grown in the silicon region on the surface of both the N-type well and the P-type well.

[0008] Preferably, the initial PMOS stack structure and the initial NMOS stack structure each include, from bottom to top, a high dielectric layer, a titanium nitride layer, an amorphous silicon layer, a hard mask silicon nitride layer, and a hard mask silicon oxide layer; after forming the initial PMOS stack structure and the initial NMOS stack structure, an isolation wall SIN material layer is deposited and etched to form the isolation wall SIN.

[0009] Preferably, the specific steps of the Cavity etching include: sequentially depositing a buffer oxide layer and a silicon nitride sacrificial layer on the initial PMOS stack structure and the initial NMOS stack structure; simultaneously etching the initial PMOS stack structure and the initial NMOS stack structure using a dry etching process to form a Cavity trench; using the retained pre-grown oxide layer as a barrier layer to simultaneously etch the hard mask silicon oxide layer on the PMOS and NMOS gates downwards while protecting the substrate outside the NMOS gate region.

[0010] Preferably, the Sigma etching employs a composite technology of wet etching and real-time endpoint monitoring. During the etching process, the characteristic emission peaks of the hard mask silicon oxide layer are continuously monitored using a photoemission spectroscopy system. When the characteristic peaks of the PMOS region disappear, the etching endpoint is determined and the etching is stopped.

[0011] Preferably, the etching reagent used for the Sigma etching is a tetramethylammonium hydroxide solution.

[0012] Preferably, after Sigma etching, the height difference of the hard mask silicon oxide layer above the PMOS gate and the NMOS gate is ≤1 Å when re-examined by atomic force microscopy.

[0013] A semiconductor device, fabricated using the above method, comprises: A substrate having N-type wells and P-type wells divided thereon; A stepped oxide structure is formed on the surface of the substrate, including a gate oxide layer located in the gate regions of the N-type well and the P-type well, and a pre-grown oxide layer located on the substrate outside the gate region of the P-type well; A gate stack structure is formed on the gate oxide layer, including an initial PMOS stack structure and an initial NMOS stack structure; The planarized hard mask layer is located on top of the initial PMOS stack structure and the initial NMOS stack structure, wherein the hard mask silicon oxide layer of the PMOS and NMOS regions is at the same height.

[0014] Compared with the prior art, the present invention has the following beneficial technical effects: This invention discloses a method for fabricating a semiconductor device. The method first selectively forms a pre-grown oxide layer on a substrate, making the subsequently grown gate oxide layer thicker on the substrate outside the NMOS gate region, thus establishing a thickness compensation basis from the initial stage. Subsequently, through the synergistic effect of Cavity etching and Sigma etching, the initial thickness difference is used to achieve dynamic complementarity in etching amounts, making the hard mask oxide layer height on both gates tend to be consistent. This method uses the thicker OX layer in the NMOS region as an etch barrier layer to protect the silicon substrate outside the NMOS gate region from damage. At this time, the HMOX on the P / NMOS gates are simultaneously etched downwards, ensuring that the gate heights of the two MOS types are basically equal. This not only avoids non-uniform polishing defects during CMP and eliminates the risk of polysilicon residue, but also ensures complete filling and interface quality of the metal gate, thereby significantly improving the electrical performance and long-term reliability of the semiconductor device. Attached Figure Description

[0015] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of the present invention and should not be regarded as a limitation on the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0016] Figure 1 TEM images of the gate profiles of NMOS (a) and PMOS (b) before interlayer dielectric CMP; Figure 2 Schematic diagrams of the gate profiles of NMOS and PMOS before (a) and after (b) interlayer dielectric CMP; Figure 3 This is a schematic diagram of the structure for constructing a pre-grown oxide layer on a substrate in this invention; Figure 4 This is a schematic diagram of the structure in which a portion of the pre-grown oxide is selectively removed in this invention; Figure 5 This is a schematic diagram of the structure of the gate oxide layer grown in this invention; Figure 6 This is a schematic diagram of the structure of depositing a high-dielectric layer, a titanium nitride layer, an amorphous silicon layer, a hard mask silicon nitride layer, and a hard mask silicon oxide layer on the gate oxide layer in this invention. Figure 7 This is a schematic diagram of the structure after polysilicon etching in this invention; Figure 8 This is a schematic diagram of the structure after the deposition of the SIN material layer in the isolation wall according to the present invention; Figure 9 This is a schematic diagram of the structure forming the isolation wall SIN in this invention; Figure 10 This is a schematic diagram of the structure after depositing the buffer oxide layer and the silicon nitride sacrificial layer in this invention; Figure 11 This is a schematic diagram of the structure of the Cavity trench formed after Cavity etching in this invention; Figure 12 This is a schematic diagram of the structure of the Sigma trench formed by Sigma etching in this invention; Figure 13 This is a schematic diagram of the structure after removing the buffer oxide layer and the silicon nitride sacrificial layer in this invention.

[0017] Wherein: 101, substrate; 103, N-type well; 104, P-type well; 102, pre-grown oxide layer; 105, gate oxide layer; 106, isolation structure; 201, high dielectric layer; 202, titanium nitride layer; 203, amorphous silicon layer; 204, hard mask silicon nitride layer; 205, hard mask silicon oxide layer; 301, isolation wall SIN material layer; 302, isolation wall SIN; 303, buffer oxide layer; 304, silicon nitride sacrificial layer; 305, Cavity trench; 306, Sigma trench. Detailed Implementation

[0018] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. The components of the embodiments of the present invention described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.

[0019] Therefore, the following detailed description of the embodiments of the invention provided in the accompanying drawings is not intended to limit the scope of the claimed invention, but merely to illustrate selected embodiments of the invention. All other embodiments obtained by those skilled in the art based on the embodiments of the invention without inventive effort are within the scope of protection of the invention.

[0020] It should be noted that similar labels and letters in the following figures indicate similar items. Therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures.

[0021] In the description of the embodiments of the present invention, it should be noted that if terms such as "upper," "lower," "horizontal," or "inner" indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, or the orientation or positional relationship commonly used when the product of the invention is in use, they are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of the present invention. Furthermore, terms such as "first" and "second" are only used to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0022] Furthermore, the use of the term "horizontal" does not imply that the component must be absolutely horizontal, but rather that it can be slightly tilted. For example, "horizontal" simply means that its direction is more horizontal than "vertical," and does not mean that the structure must be completely horizontal, but can be slightly tilted.

[0023] In the description of the embodiments of the present invention, it should also be noted that, unless otherwise explicitly specified and limited, the terms "set," "install," "connect," and "link" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in the present invention according to the specific circumstances.

[0024] The present invention will now be described in further detail with reference to the accompanying drawings: A method for fabricating a semiconductor device includes the following steps: Step 1: Pre-growth of oxide layer like Figure 3 As shown, a substrate 101 is provided, on which an N-type well 103 and a P-type well 104 are formed, and the N-type well 103 and the P-type well 104 form an isolation structure 106. A pre-grown oxide layer 102 is formed on the surface of the substrate 101, and the pre-grown oxide layer 102 is selectively etched. Specifically, the selective etching involves removing all of the pre-grown oxide layer 102 on the side of the N-type well 103 and partially removing the pre-grown oxide layer 102 on the side of the P-type well 104, with the center line of the isolation structure 106 as the boundary. Specifically, the process is as follows: a substrate 101 is provided, which includes, from bottom to top, a deep N-type well (DNW), and an N-type well 103 (N WELL) and a P-type well 104 (P WELL) formed within the deep N-type well; wherein, the N WELL corresponds to the PMOS device fabrication area, the P WELL corresponds to the NMOS device fabrication area, and an isolation structure 106 is formed between the N-type well 103 and the P-type well 104; A pre-grown oxide layer 102 is formed on the substrate 101. That is, before the gate oxide (GOX) is formally grown, a uniform pre-grown oxide layer 102 (OX) is grown on the entire substrate 101, including the surface of the N-type well 103 and the P-type well 104, by means of a high-density plasma thermal oxidation (HTO) process.

[0025] In a specific embodiment, the core of this step is to construct the basic device structure and prepare a pre-tuned oxide layer, providing a prerequisite for subsequently eliminating the height difference of the gate silicon oxide layer. First, a substrate 101 is provided, which is made of high-purity single-crystal silicon material, and its crystal orientation is preferably... <100> This ensures the electrical performance stability of subsequent devices. Substrate 101 presents a layered well structure from bottom to top, with the bottom layer being a deep N-type well (DNW). This is formed by injecting high-concentration N-type impurities such as phosphorus (P) or arsenic (As) into the deep layers of the substrate through an ion implantation process. The implantation energy is controlled at 80~120keV. Its main function is to isolate the substrate from the upper-layer devices and reduce the risk of leakage.

[0026] On the surface of the deep N-type well, N-type well 103 (NWELL) and P-type well 104 (P WELL) are formed through photolithography, ion implantation and annealing activation processes, respectively. The N WELL corresponds to the PMOS device fabrication area and the implanted impurity is phosphorus, while the P WELL corresponds to the NMOS device fabrication area and the implanted impurity is boron (B). The junction depth of the two well regions is controlled at 0.5~1μm, and the sheet resistance difference is controlled at 50~100Ω / sq to meet the conductivity requirements of different devices.

[0027] Subsequently, a pre-grown oxide layer 102 is grown on the surface of substrate 101. This step is completed before the formal growth of the gate oxide (GOX). High-Density Plasma Thermal Oxidation (HTO) is selected as the process. Compared with traditional wet oxidation, the HTO process can generate a dense oxide layer at a lower temperature (600~750℃) and improve the oxidation rate uniformity by more than 30%. During the oxidation process, oxygen and nitrogen are used as reactants, with a gas flow ratio controlled at 3:1 and plasma power set at 200~300W. Finally, a uniform silicon dioxide pre-grown oxide layer 102 with a thickness of 40~70Å is formed on the surface of N-type well 103 and P-type well 104. This pre-grown oxide layer 102 will serve as a substrate barrier layer for subsequent selective etching, laying the foundation for differentiated control of the oxide layer in the PMOS and NMOS regions.

[0028] Step 2: Selectively remove some of the pre-grown oxides like Figure 4 As shown, the pre-grown oxide layer 102 is selectively etched. Specifically, the selective etching involves removing all of the pre-grown oxide layer 102 on the N-type well 103 side, with the center line of the isolation structure 106 as the boundary, and partially removing the pre-grown oxide layer 102 on the P-type well 104 side. During this partial removal process, only the pre-grown oxide layer 102 on the substrate other than the gate on the P-type well 104 is retained. Through etching, the pre-grown oxide layer in the N-type well 103 region corresponding to the PMOS is completely removed. Simultaneously, for the P-type well 104 surface corresponding to the NMOS, only the pre-grown oxide layer 102 on the substrate other than the gate is retained, thus increasing the physical height of the NMOS region. Removing the pre-grown oxide layer 102 in the gate region of the NMOS surface ensures the normal electrical thickness of the NMOS region. In other words, this process creates a difference in the thickness of the pre-grown oxide layer on the substrate between the PMOS and NMOS regions, providing a protective silicon oxide layer for the NMOS substrate to facilitate subsequent reduction of the hard mask oxide layer thickness for the gates of the PMOS and NMOS regions.

[0029] In one specific embodiment, the core of this step is to selectively etch the pre-grown oxide layer 102 to achieve differentiated retention, establishing a thickness reference for subsequent gate structure height compensation. Before the process starts, the substrate surface must be cleaned by immersion in a dilute hydrofluoric acid solution to remove the natural oxide layer and contaminants on the surface of the pre-grown oxide layer 102, ensuring the uniformity of the etching process. Subsequently, photoresist coating and patterning are performed. The PMOS corresponding area, i.e., the N-type well 103, is exposed and developed using photolithography, while the NMOS corresponding area, i.e., the P-type well 104, is retained with photoresist coverage, forming a precise etching mask.

[0030] The etching process employed a dry plasma etching technique, using a mixture of CF4 and O2 as the etchant. CF4 provides fluorine-based active particles for oxide etching, while O2 is used to adjust the plasma density and suppress polymer deposition. For the PMOS region, i.e., the N-type well 103, an over-etching strategy was employed, with the etching time set to 1.2 times the base etching time. This ensured that the pre-grown oxide layer 102 in this region was completely removed. After etching, ellipsometry was used to confirm that the substrate silicon surface in this region was exposed and that no oxide layer residue remained.

[0031] For the NMOS region, i.e., the P-type well 104, after etching the PMOS region, the photoresist mask is immediately removed, and the etching parameters are adjusted to reduce the gas flow rate and the etching rate, removing only the pre-grown oxide layer 102 in the NMOS gate region. The etching depth is controlled by a real-time endpoint detection system, ultimately retaining the pre-grown oxide layer 102 on the substrate outside the NMOS gate region. The thickness of this retained pre-grown oxide layer 102 is 40~70 Å, creating a thickness difference of 40~70 Å between the NMOS and PMOS regions. The core purpose of this differentiated design is that during subsequent growth of the hard mask silicon oxide layer (HMOX), the PMOS region has no underlying pre-grown oxide layer 102, while the NMOS region has the residual pre-grown oxide layer 102 for support. During the SiGe process, both PMOS and NMOS are fully on, laying a crucial foundation for achieving a highly consistent gate structure across the entire region.

[0032] Step 3: Grow a gate oxide layer of the target thickness 105 like Figure 5 As shown, a gate oxide layer 105 of the target thickness is grown on the substrate 101 and the retained pre-grown oxide layer 102. Specifically, an in-situ steam generation oxidation (ISSG) process is used to grow the gate oxide layer 105 of the required thickness on the surface of the substrate 101. At this time, because part of the pre-grown oxide layer 102 is retained in the NMOS region, the total thickness of the silicon oxide layer outside the final NMOS gate region will be thicker than that in the PMOS region, thus initially establishing a basis for compensating for the thickness difference.

[0033] In one specific embodiment, this step grows a gate oxide layer 105 on a differentiated substrate using a precise oxidation process. The core technology is in-situ steam generation oxidation (ISSG) to construct the oxide layer thickness difference between the NMOS and PMOS regions, achieving initial compensation. Before process startup, the substrate 101, processed in step 2, needs to be placed into a rapid thermal oxidation (RTO) reaction chamber for vacuum environment pretreatment. Under vacuum, nitrogen gas is introduced for purging to remove residual impurities within the chamber and prevent oxide layer defects.

[0034] Compared to traditional oxidation techniques, the ISSG process enhances the density of the oxide layer by generating high-purity vapor internally. The principle involves introducing hydrogen and oxygen into the reaction chamber, where a combustion reaction occurs at high temperatures to produce water vapor. This water vapor then reacts with silicon atoms on the substrate surface to form silicon dioxide. In this step, the reaction temperature is controlled at 900–1000°C, and the reaction pressure is maintained at 5–10 Torr. Through precise timing control of 10–20 seconds, a gate oxide layer 105 with a thickness of 11–15 Å is grown.

[0035] At this point, the substrates exhibit significant differences: the N-type well 103 region corresponding to the PMOS no longer has a pre-grown oxide layer 102, and the gate oxide layer 105 is grown directly on the silicon substrate surface, with a thickness of 11~15 Å, the same as that grown by the ISSG process; while the P-type well 104 region corresponding to the NMOS retains a 40~70 Å pre-grown oxide layer 102, thus making the oxide layer thickness in the P-type well 104 region greater than that in the N-type well 103 region. This substrate difference results in the total oxide layer thickness of the NMOS region, excluding the Poly region, being 30~50 Å thicker than that in the PMOS region, initially establishing a foundation for high compensation and ensuring the uniform fabrication of the subsequent high-dielectric layer and metal gate.

[0036] Step 4: Perform Poly Etch and OSW Etch like Figure 6 As shown, a high-k dielectric (HK) layer 201, a titanium nitride (TIN) layer 202, an amorphous silicon (A-Si) layer 203, a hard mask silicon nitride (HM SIN) layer 204, and a hard mask silicon oxide (HM OX) layer 205 are sequentially deposited on the gate oxide layer 105 at the N-type well 103 and the P-type well 104 to complete the gate stacking.

[0037] like Figure 7As shown, polysilicon etching (Poly Etch) is performed. At this point, the OX region of the NMOS region is thicker than the OX region of the PMOS region. Then, as... Figure 8 As shown, a spacer wall SIN material layer 301 is deposited, and spacer wall SIN 302 is formed by spacer wall etching (OxideSpacer Wall Etch, OSW Etch), as shown. Figure 9 As shown, at this time, an initial PMOS stack structure and an initial NMOS stack structure are formed at the N-type well 103 and the P-type well 104, respectively. The polysilicon etching process here etches the deposited amorphous silicon layer 203, i.e., the dummy gate, into a predetermined gate pattern, while preserving other layers of the gate stack, such as the deposited high-dielectric layer 201 and titanium nitride layer 202. Specifically, the amorphous silicon layer 203 can be oriented and etched using etching gas through dry etching, such as plasma etching.

[0038] The isolation wall etching process etches the isolation walls on both sides of the gate, while further adjusting the structural contour around the gate. Specifically, after Poly Etch, a dry etching process is used to etch the isolation wall material on both sides of the gate, making the shape and height of the isolation walls adapt to the requirements of subsequent processes, while ensuring the stability of the gate structure. At this point, the oxide layer thickness in the NMOS region is significantly thicker than that in the PMOS region, preparing for subsequent etching and leveling.

[0039] In one specific embodiment, this step is the core of the gate structure formation. It requires first completing the precise deposition of multiple gate stacks, then defining the device outline through two directional etching processes, ultimately forming an initial gate structure with differentiated thicknesses. The deposition stage employs a composite process of atomic layer deposition (ALD) and chemical vapor deposition (CVD) to ensure the density and thickness uniformity of each layer. First, a high-k dielectric (HK) layer 201 is deposited on the surface of the gate oxide layer 105 of the N-type well 103 and P-type well 104, using HfO2 as the core material. The ALD deposition temperature is controlled at 290°C, and the reaction gases are tetra(ethylmethylamino)hafnium and oxygen. The thickness is precisely controlled to 18–22 Å through 50–80 deposition cycles.

[0040] Next, a titanium nitride layer 202 is deposited on the surface of the high-dielectric layer 201. This layer serves a dual function of blocking and work function regulation. Physical vapor deposition (PVD) is employed, using 99.99% high-purity TiN as the target material, a deposition power of 350W, and argon as the sputtering gas. The thickness is controlled at 12–16 Å, effectively preventing subsequent metal atom diffusion into the substrate while simultaneously adjusting the work function of both PMOS and NMOS to the optimal range. Subsequently, an amorphous silicon layer 203, i.e., a dummy gate layer, is deposited using low-pressure chemical vapor deposition (LPCVD) with silane as the reaction source. The deposition temperature is 630℃, the pressure is 100 mTorr, and the thickness is set at 1200–1400 Å, providing sufficient margin for subsequent etching and patterning. The top hard mask silicon nitride layer 204 and hard mask silicon oxide layer 205 are both produced by plasma enhanced chemical vapor deposition (PECVD) with thicknesses of 60~70Å and 90~110Å, respectively. The former serves as an etching hard mask, while the latter enhances the oxidation resistance of the stacked structure.

[0041] After stacking and deposition, the polysilicon etching process begins. The core objective is to etch the A-Si dummy gate layer into the pre-defined gate pattern. The process employs plasma dry etching, using a mixture of HBr, CF4, and O2 as the etching gas. HBr provides the active particles required for silicon etching, CF4 enhances etching anisotropy, and O2 inhibits polymer deposition. After defining the gate region using a photoresist mask, primary etching is performed at a rate controlled at 95 Å / s. When the optical endpoint detection system captures the characteristic spectrum of the titanium nitride layer 202, the process switches to over-etching mode, with the over-etch amount controlled at 8%–10% to ensure complete removal of the amorphous silicon layer 203 without damaging the underlying high-dielectric layer 201. Post-etching SEM inspection shows a gate linewidth deviation ≤ ±4 nm and a sidewall perpendicularity ≥ 89°, meeting high-precision patterning requirements.

[0042] After Poly Etch is completed, as follows Figure 8 As shown, a barrier SIN material layer 301 is deposited, followed by barrier etching (OSW Etch) to form barrier SIN 302. Figure 9As shown. The primary task of this step is to remove the photoresist mask using an O2 plasma ashing process at 350℃ and 400W to ensure no residue. Subsequently, the silicon oxide isolation wall material on both sides of the gate is etched using a mixture of CHF3 and Ar as the etching gas. CHF3 provides fluorine-based etching particles, while Ar enhances the physical bombardment effect. AFM detection at this stage confirms that the total oxide layer thickness in the NMOS region (the sum of pre-grown OX and GOX) is 40-70 Å thick compared to the PMOS region (only GOX). This thickness difference lays a crucial foundation for the subsequent leveling processes of Cavity Etch and SIGMA Etch, ensuring a consistent final gate height.

[0043] Step 5: Cavity Etching like Figure 10 As shown, a buffer oxide layer 303 (Buffer OX) and a silicon nitride sacrificial layer 304 (SP1 SIN) are sequentially deposited on the initial PMOS stack structure and the initial NMOS stack structure, and then as follows... Figure 11 As shown, the gate structures of the initial PMOS stacked structure and the initial NMOS stacked structure, which have deposited a buffer oxide layer 303 and a silicon nitride sacrificial layer 304, are simultaneously subjected to a cavity etching process. That is, during cavity etching, both the PMOS and NMOS are etched downwards simultaneously, meaning their gate structures are etched downwards at the same time. Because the OX layer in the NMOS region is thicker, during simultaneous downward etching, the thick OX layer in the NMOS region becomes thinner after etching, while a cavity trench 305 is formed on the substrate on the Poly side of the PMOS region. The HMOX heights on the PMOS and NMOS gates are essentially the same. In other words, the pre-grown oxide layer 102 retained in the NMOS region is used as a dry etching barrier layer to protect the substrate outside the NMOS gate region from damage. At this time, the HMOX on the PMOS and NMOS gates are etched downwards simultaneously, ensuring that the gate heights of the two MOS types are essentially the same. In this invention, Cavity etching refers to selectively etching away a portion of the silicon substrate in a specific region of the device (usually at the source / drain positions on both sides of the gate structure) to form a recessed cavity or trench.

[0044] The core of this step is to reduce the oxide layer thickness difference between the PMOS and NMOS regions using a simultaneous cavity etching process, thus laying the foundation for the final height leveling. In one specific embodiment, the gate stack surface needs to be pretreated before the process starts. This involves immersing the surface in a diluted hydrofluoric acid solution to remove the native oxide layer and residual polymers, followed by rinsing with ultrapure water and drying with nitrogen to ensure a clean etching interface. The etching employs inductively coupled plasma (ICP) dry etching technology, which combines high etching rate with excellent anisotropy, allowing for precise control of the vertical etching depth.

[0045] The etching process uses a mixture of CF4, CH2F2, and Ar as reactive gases. The volume ratio of CF4 to CH2F2 is adjusted to control etching selectivity, while Ar enhances the plasma bombardment effect. The reaction chamber pressure is controlled at 8 mTorr, the ICP power is set to 600 W, and the RF bias is 150 W. The key process parameter is the etching time, which needs to be precisely set based on the thickness difference detected in step 4. If the oxide layer in the NMOS region is 50 Å thicker than that in the PMOS region, the etching time is controlled at 40-50 seconds by utilizing the selectivity ratio of silicon oxide to silicon in dry etching. This ensures that when the Cavity trench 305 is etched in the PMOS region, the pre-grown oxide layer 102 in the NMOS region is partially etched, but a relatively thin layer is still retained as a barrier layer to prevent the substrate 101 in the NMOS region from being etched by TMAH in the subsequent Sigma etching process.

[0046] The core logic behind the simultaneous downward etching of PMOS and NMOS in this step lies in utilizing the thicker silicon oxide layer of the NMOS, i.e., the retained pre-grown oxide layer 102, as a dry etching barrier layer. Through the high selectivity of dry etching, after the thicker silicon oxide layer in the NMOS region is removed, the PMOS substrate has already completed the Cavity trench etching. After etching, the difference in oxide layer thickness between the two can be reduced from the initial 8~22Å to 3~8Å by ellipsometry. Moreover, the high-dielectric layer 201 and titanium nitride layer 202 of the gate stack are not damaged.

[0047] Step 6: Sigma Etching like Figure 12 As shown, Sigma etching is performed to form Sigma trench 306 in the Cavity trench 305 of the PMOS, and then as follows... Figure 13As shown, the buffer oxide layer 303 and the silicon nitride sacrificial layer 304 are removed. As a necessary condition before SiGe growth, the NMOS region retains the pre-grown oxide layer 102 as an etch barrier layer, exhibiting high selectivity under Sigma etching conditions. This prevents the NMOS region from being etched, thus distinguishing PMOS from NMOS. The Sigma etching technique in this invention is a special etching technology that precisely controls the isotropic nature of the etching chemical reaction to perform slight lateral etching at the opening edge of the formed cavity, causing its sidewalls to exhibit an arc or inverted trapezoidal shape.

[0048] Sigma etching employs a combined technique of wet etching and real-time endpoint monitoring. The etching reagent used is tetramethylammonium hydroxide (TMAH).

[0049] During the etching process, the optical emission spectroscopy (OES) system continuously monitored the characteristic emission peaks of the hard mask silicon oxide layer 205, corresponding to a wavelength of 460 nm. When the characteristic peaks in the PMOS region disappeared, the system automatically triggered an etching pause. At this point, the NMOS region, due to its initial thicker HMOX, had been synchronously etched to the same height, completely eliminating the original height difference of 3–8 Å. Finally, re-examination using atomic force microscopy (AFM) showed that the height difference of the hard mask silicon oxide layer 205 above the PMOS and NMOS gates was ≤1 Å, achieving effective leveling. This result fundamentally solves the void problem caused by height differences during metal gate filling, ensuring the conductivity of subsequent metal wiring and device reliability.

[0050] This invention first grows a uniform pre-grown oxide layer 102 on a substrate 101 containing a deep N-type well, an N-type well 103, and a P-type well 104 using an HTO process. Then, through selective etching, the pre-grown oxide layer 102 in the PMOS region is completely removed, while other pre-grown oxide layers 102 on the substrate in the NMOS region (excluding the gate region) are retained, creating an initial thickness difference. Next, a gate oxide layer 105 is grown using an ISSG process, making the total oxide layer thickness in the NMOS region thicker than that in the PMOS region. Then, a high-dielectric layer 201, a titanium nitride layer 202, an amorphous silicon layer 203, a hard mask silicon nitride layer 204, and a hard mask silicon oxide layer 205 are deposited. After poly etching, an initial PMOS stack structure and an initial NMOS stack structure are formed. Then, an isolation wall SIN material layer 301 is deposited and etched to form an isolation wall SIN 302, forming the initial device structure. Finally, a Cavity... Simultaneous etching of the gates in both regions using the pre-grown oxide layer 102 retained in the NMOS region serves as a dry etching barrier layer, protecting the substrate outside the NMOS gate region from damage. Simultaneously, the HMOX on both the PMOS and NMOS gates is etched downwards, ensuring that the gate heights of the two MOS types are essentially equal. Finally, Sigma etching is used for fine leveling, ensuring that the height difference of the HMOX above the active regions of the two regions is ≤1 Å. This entire process, through differentiated control and step-by-step etching, ensures gate structure consistency, solves the problem of poor metal gate filling, and improves device conductivity and reliability.

[0051] The above are merely preferred embodiments of the present invention and are not intended to limit the present invention. Various modifications and variations can be made to the present invention by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A method for fabricating a semiconductor device, characterized in that, Includes the following steps: A substrate (101) is provided, on which an N-type well (103) and a P-type well (104) are formed. The N-type well (103) corresponds to the PMOS region, and the P-type well (104) corresponds to the NMOS region. An isolation structure (106) is formed between the N-type well (103) and the P-type well (104). A pre-grown oxide layer (102) is grown on the substrate (101), and the pre-grown oxide layer (102) is selectively etched. Specifically, the selective etching is performed by removing all the pre-grown oxide layer (102) on the side of the N-type well (103) and partially removing the pre-grown oxide layer (102) on the side of the P-type well (104) with the center line of the isolation structure (106) as the boundary. A gate oxide layer (105) is grown on the surface of the substrate (101) such that the total thickness of the oxide layer in the NMOS region is greater than the total thickness of the oxide layer in the PMOS region; an initial PMOS stack structure and an initial NMOS stack structure are formed in the N-type well (103) and P-type well (104) regions. Cavity etching is performed simultaneously on the gate structures of the initial PMOS stacked structure and the initial NMOS stacked structure. Then, Sigma etching is performed on the Cavity trench (305) of the PMOS region. The retained pre-grown oxide layer (102) is used as a barrier layer to make the hard mask silicon oxide layer (205) of the PMOS region and the hard mask silicon oxide layer (205) of the NMOS region have the same final height. The partial removal specifically means: retaining the pre-grown oxide layer (102) on the substrate outside the gate region on the P-type well (104), and removing all the pre-grown oxide layers (102) in the remaining regions.

2. The method for fabricating a semiconductor device according to claim 1, characterized in that, The thickness of the pre-grown oxide layer (102) retained on the substrate outside the gate region of the P-type well (104) is 40~70 Å.

3. The method for fabricating a semiconductor device according to claim 1, characterized in that, The step of growing the gate oxide layer (105) is as follows: using an in-situ vapor generation oxidation process, the gate oxide layer (105) is grown in the silicon region on the surface of both the N-type well (103) and the P-type well (104).

4. The method for fabricating a semiconductor device according to claim 1, characterized in that, The initial PMOS stack structure and the initial NMOS stack structure both include, from bottom to top, a high dielectric layer (201), a titanium nitride layer (202), an amorphous silicon layer (203), a hard mask silicon nitride layer (204), and a hard mask silicon oxide layer (205); after forming the initial PMOS stack structure and the initial NMOS stack structure, an isolation wall SIN material layer (301) is deposited and etched to form the isolation wall SIN (302).

5. The method for fabricating a semiconductor device according to claim 1, characterized in that, The specific steps of the Cavity etching include: depositing a buffer oxide layer (303) and a silicon nitride sacrificial layer (304) sequentially on the initial PMOS stack structure and the initial NMOS stack structure; simultaneously etching the initial PMOS stack structure and the initial NMOS stack structure using a dry etching process to form a Cavity trench (305); using the retained pre-grown oxide layer (102) as a barrier layer to simultaneously etch the hard mask silicon oxide layer (205) on the PMOS and NMOS gates downwards while protecting the substrate outside the NMOS gate region.

6. The method for fabricating a semiconductor device according to claim 1, characterized in that, The Sigma etching employs a combined technology of wet etching and real-time endpoint monitoring. During the etching process, the characteristic emission peaks of the hard mask silicon oxide layer (205) are continuously monitored using a light emission spectroscopy system. When the characteristic peaks of the PMOS region disappear, the etching endpoint is determined and the etching is stopped.

7. The method for fabricating a semiconductor device according to claim 1, characterized in that, The etching reagent used for the Sigma etching is a tetramethylammonium hydroxide solution.

8. The method for fabricating a semiconductor device according to claim 1, characterized in that, After etching by Sigma, the height difference between the hard mask silicon oxide layer (205) above the PMOS gate and the NMOS gate was ≤1 Å when examined by atomic force microscopy.

9. A semiconductor device, characterized in that, Prepared using the method described in any one of claims 1 to 8, comprising: Substrate (101), wherein N-type wells (103) and P-type wells (104) are divided on the substrate (101). A stepped oxide structure is formed on the surface of the substrate (101), including a gate oxide layer (105) located in the gate regions of the N-type well (103) and the P-type well (104), and a pre-grown oxide layer (102) located on the substrate outside the gate region of the P-type well (104). A gate stack structure is formed on the gate oxide layer (105), including an initial PMOS stack structure and an initial NMOS stack structure; The planarized hard mask layer is located on top of the initial PMOS stack structure and the initial NMOS stack structure, wherein the hard mask silicon oxide layer (205) of the PMOS and NMOS regions is highly connected.

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