Semiconductor device, electronic apparatus, and vehicle

Abstract

A semiconductor device (200) includes at least one voltage drive circuit (DRV1H) that drives a switching control signal (Vg) of, for example, a voltage and a current drive circuit (DRV2H) that drives a switching control signal (Vg) of a current. The at least one voltage drive circuit (DRV1H) is in an on state during part (T1, T2, T4) of a plurality of periods (T1 to T4) included in a logic level transition period (Ton_tr) of the switching control signal (Vg) and is in an off state during the other period (T3). The current drive circuit (DRV2H) is in an on state during all of the plurality of periods (T1 to T4).

Description

Technical Field

[0001] This disclosure relates to a semiconductor device, electronic equipment, and vehicle. Background Technology

[0002] Typically, signal transmission devices that transmit signals between primary and secondary circuit systems while isolating them are used in various applications (such as power supply equipment and motor drive equipment).

[0003] Note that, as an example of conventional techniques related to the above description, there is a patent document 1 in which the applicant has already applied.

[0004] Reference List

[0005] Patent documents

[0006] Patent document 1: WO 2022 / 070944. Summary of the Invention

[0007] In traditional signal transmission devices, there is room for optimization regarding the slew rate.

[0008] For example, a semiconductor device according to this disclosure includes at least one voltage drive circuit configured to drive a voltage-driven switch control signal, and a current drive circuit configured to drive a current-driven switch control signal. The at least one voltage drive circuit is in an ON state for a portion of a plurality of time periods included in the logic level transition period of the switch control signal, and in an OFF state for other time periods. The current drive circuit is in an ON state for all of the plurality of time periods. Attached Figure Description

[0009] Figure 1 It is a diagram showing the basic structure of a signal transmission device.

[0010] Figure 2 This is a diagram showing the basic structure of a transformer chip.

[0011] Figure 3 This is a three-dimensional view of a semiconductor device used as a dual-channel transformer chip.

[0012] Figure 4 yes Figure 3 A top view of the semiconductor device shown.

[0013] Figure 5 It means in Figure 3 A top view of a layer in a semiconductor device in which a low-potential coil is formed.

[0014] Figure 6 It means in Figure 3 A top view of a layer in a semiconductor device in which a high-potential coil is formed.

[0015] Figure 7 It is along Figure 6 The cross-sectional view of line VIII-VIII shown.

[0016] Figure 8 It means Figure 7 The diagram shows an enlarged view (separated structure) of region XIII.

[0017] Figure 9 This is a schematic diagram illustrating an example of the layout of a transformer chip.

[0018] Figure 10 This is a diagram illustrating a first comparative example of an electronic device.

[0019] Figure 11 This is a diagram illustrating a second comparative example of an electronic device.

[0020] Figure 12 This is a diagram illustrating a first embodiment of the electronic device.

[0021] Figure 13 This is a diagram illustrating the connection control of the first embodiment.

[0022] Figure 14 This is a diagram illustrating the connection control (modification) of the first embodiment.

[0023] Figure 15 This is a diagram illustrating the shutdown control of the first implementation scheme.

[0024] Figure 16 This is a diagram illustrating a second embodiment of the electronic device.

[0025] Figure 17 This is a diagram illustrating the connection control of the second implementation scheme.

[0026] Figure 18 This is a diagram illustrating the shutdown control of the second implementation scheme.

[0027] Figure 19 This is a diagram showing the exterior view of the vehicle. Detailed Implementation

[0028] <Signal Transmission Device (Basic Structure)>

[0029] Figure 1This diagram illustrates the basic structure of a signal transmission device. In this example, the signal transmission device 200 is a semiconductor integrated circuit device (so-called an insulated gate driver IC) that insulates the primary circuit system 200p (VCC1-GND1 system) from the secondary circuit system 200s (VCC2-GND2 system), and transmits pulse signals from the primary circuit system 200p to the secondary circuit system 200s to drive the gate of a switching element (not shown) disposed in the secondary circuit system 200s. For example, the signal transmission device 200 is formed by sealing the controller chip 210, driver chip 220, and transformer chip 230 into a single package.

[0030] The controller chip 210 is a semiconductor chip that operates by receiving a power supply voltage VCC1 (e.g., a maximum of 7V based on GND1). The controller chip 210 integrates, for example, a pulse transmitting circuit 211, buffers 212 and 213.

[0031] The pulse transmitting circuit 211 is a pulse generator that generates transmit pulse signals S11 and S21 based on the input pulse signal IN. More specifically, the pulse transmitting circuit 211 drives the transmit pulse signal S11 (single or multiple transmit pulse outputs) when the input pulse signal IN is high, and drives the transmit pulse signal S21 when the input pulse signal IN is low. That is, the pulse transmitting circuit 211 drives either the transmit pulse signal S11 or S21 according to the logic level of the input pulse signal IN.

[0032] The buffer 212 receives the input of the transmission pulse signal S11 from the pulse transmission circuit 211 and performs pulse driving on the transformer chip 230 (specifically the transformer 231).

[0033] The buffer 213 receives the input of the transmission pulse signal S21 from the pulse transmission circuit 211 and performs pulse driving on the transformer chip 230 (specifically the transformer 232).

[0034] The driver chip 220 is a semiconductor chip that operates by receiving a power supply voltage VCC2 (e.g., a maximum of 30V based on GND2). The driver chip 220 integrates, for example, buffers 221 and 222, a pulse receiving circuit 223, and a driver 224.

[0035] The buffer 221 shapes the waveform of the received pulse signal S12 induced in the transformer chip 230 (specifically the transformer 231) and outputs it to the pulse receiving circuit 223.

[0036] The buffer 222 shapes the waveform of the received pulse signal S22 induced in the transformer chip 230 (specifically the transformer 232) and outputs it to the pulse receiving circuit 223.

[0037] The pulse receiving circuit 223 drives the driver 224 based on the received pulse signals S12 and S22 input via buffers 221 and 222, thereby generating an output pulse signal OUT. More specifically, the pulse receiving circuit 223 drives the driver 224 in such a way that it receives the pulse of the received pulse signal S12 to raise the output pulse signal OUT to a high level, and on the other hand, it receives the pulse of the received pulse signal S22 to lower the output pulse signal OUT to a low level. That is, the pulse receiving circuit 223 switches the logic level of the output pulse signal OUT according to the logic level of the input pulse signal IN. Furthermore, an RS flip-flop can be appropriately used as the pulse receiving circuit 223, for example.

[0038] The driver 224 generates an output pulse signal OUT according to the drive control of the pulse receiving circuit 223.

[0039] Transformer chip 230 uses transformers 231 and 232 to DC-ground insulate the controller chip 210 from the driver chip 220, and outputs the transmit pulse signals S11 and S21 input from the pulse transmit circuit 211 as receive pulse signals S12 and S22 to the pulse receive circuit 223. Furthermore, in this specification, "DC-ground insulation" means that the two objects to be insulated are not connected by a conductor.

[0040] More specifically, transformer 231 outputs a receiving pulse signal S12 from secondary coil 231s based on the transmitting pulse signal S11 input to primary coil 231p. On the other hand, transformer 232 outputs a receiving pulse signal S22 from secondary coil 232s based on the transmitting pulse signal S21 input to primary coil 232p.

[0041] Thus, due to the characteristics of the spiral coil used for communication between insulators, the input pulse signal IN is separated into two transmission pulse signals S11 and S21 (equivalent to rising and falling signals), and then transmitted from the primary circuit system 200p to the secondary circuit system 200s via two transformers 231 and 232.

[0042] Furthermore, the signal transmission device 200 of this embodiment differs from the controller chip 210 and the driver chip 220 in that it independently has a transformer chip 230 that only carries transformers 231 and 232, and these three chips are sealed into a single package.

[0043] By adopting this structure, both the controller chip 210 and the driver chip 220 can be formed using general low- to medium-voltage processes (a few volts to tens of volts), thus eliminating the need for a dedicated high-voltage process (a few thousand volts), which reduces manufacturing costs.

[0044] Furthermore, the signal transmission device 200 can be appropriately utilized, for example, by a power supply device or an electric motor drive device of an on-board device mounted on the vehicle. In addition to engine-powered vehicles, the aforementioned vehicles also include electric vehicles (BEV [pure electric vehicle], HEV [hybrid electric vehicle], PHEV / PHV [plug-in hybrid electric vehicle], or FCEV / FCV [fuel cell electric vehicle], etc.).

[0045] <Transformer Chip (Basic Structure)>

[0046] Next, the basic structure of the transformer chip 230 will be explained. Figure 2 This diagram illustrates the basic structure of transformer chip 230. In the transformer chip 230 of this diagram, transformer 231 includes a primary side coil 231p and a secondary side coil 231s opposite each other in the vertical direction. Transformer 232 includes a primary side coil 232p and a secondary side coil 232s opposite each other in the vertical direction.

[0047] Primary side coils 231p and 232p are both formed on the first wiring layer (lower layer) 230a of the transformer chip 230. Secondary side coils 231s and 232s are both formed on the second wiring layer (upper layer in this figure) 230b of the transformer chip 230. Furthermore, the secondary side coil 231s is positioned directly above the primary side coil 231p, opposite to it. Similarly, the secondary side coil 232s is positioned directly above the primary side coil 232p, opposite to it.

[0048] The primary side coil 231p is arranged in a spiral pattern, starting from the first end connected to the internal terminal X21 and spiraling clockwise around the internal terminal X21, with its second end connecting to the internal terminal X22. Conversely, the primary side coil 232p is arranged in a spiral pattern, starting from the first end connected to the internal terminal X23 and spiraling counterclockwise around the internal terminal X23, with its second end connecting to the internal terminal X22. The internal terminals X21, X22, and X23 are arranged in a straight line in the order shown in the diagram.

[0049] Internal terminal X21 is connected to external terminal T21 of the second layer 230b via conductive wiring Y21 and through-hole Z21. Internal terminal X22 is connected to external terminal T22 of the second layer 230b via conductive wiring Y22 and through-hole Z22. Internal terminal X23 is connected to external terminal T23 of the second layer 230b via conductive wiring Y23 and through-hole Z23. Furthermore, external terminals T21 to T23 are arranged in a straight line for wire connection with the controller chip 210.

[0050] The secondary-side coil 231s is spirally arranged around the external terminal T24 in a counter-clockwise direction, starting from the first end connected to the external terminal T24, and the second end, corresponding to its endpoint, is connected to the external terminal T25. On the other hand, the secondary-side coil 232s is spirally arranged around the external terminal T26 in a clockwise direction, starting from the first end connected to the external terminal T26, and the second end, corresponding to its endpoint, is connected to the external terminal T25. Furthermore, the external terminals T24, T25, and T26 are arranged linearly in the order shown in the figure for wire connection to the driver chip 220.

[0051] Secondary coils 231s and 232s are AC connected to primary coils 231p and 232p via magnetic coupling, respectively, and are DC insulated from primary coils 231p and 232p. That is, driver chip 220 is AC connected to controller chip 210 via transformer chip 230, and is DC insulated from controller chip 210 via transformer chip 230.

[0052] <Transformer Chip (Dual-Channel Type)>

[0053] Figure 3 This is a perspective view of a semiconductor device 5 used as a dual-channel transformer chip. Figure 4 yes Figure 3 A top view of the semiconductor device 5 shown. Figure 5 It means in Figure 3 The diagram shows a top view of the semiconductor device 5 in which a low-potential coil 22 (equivalent to the primary coil of a transformer) is formed. Figure 6 It means in Figure 3 The diagram shows a top view of the layer in the semiconductor device 5 in which a high-potential coil 23 (equivalent to the secondary coil of a transformer) is formed. Figure 7 It is along Figure 6 The cross-sectional view of line VIII-VIII shown. Figure 8 It means Figure 7 The diagram shows an enlarged view of region XIII, which illustrates the separation structure 130.

[0054] Reference Figures 3-7The semiconductor device 5 includes a rectangular parallelepiped semiconductor chip 41. The semiconductor chip 41 includes at least one of silicon, a wide-bandgap semiconductor, and a compound semiconductor.

[0055] Wide bandgap semiconductors are composed of semiconductors with a bandgap exceeding that of silicon (approximately 1.12 eV). The bandgap of a wide bandgap semiconductor is preferably 2.0 eV or higher. Wide bandgap semiconductors can also be SiC (silicon carbide). Compound semiconductors can be III-V group compound semiconductors. Compound semiconductors can also contain at least one of AlN (aluminum nitride), InN (indium nitride), GaN (gallium nitride), and GaAs (gallium arsenide).

[0056] In this embodiment, the semiconductor chip 41 includes a silicon semiconductor substrate. The semiconductor chip 41 may also be an epitaxial substrate having a stacked structure comprising a silicon semiconductor substrate and a silicon epitaxial layer. The conductivity type of the semiconductor substrate may be n-type or p-type. The epitaxial layer may be n-type or p-type.

[0057] The semiconductor chip 41 has a first main surface 42 on one side, a second main surface 43 on the other side, and chip sidewalls 44A to 44D connecting the first main surface 42 and the second main surface 43. The first main surface 42 and the second main surface 43 are formed into a quadrilateral shape (rectangular shape in this embodiment) when viewed from their normal direction Z in a top view (hereinafter referred to as "top view").

[0058] The chip sidewalls 44A-44D include: a first chip sidewall 44A, a second chip sidewall 44B, a third chip sidewall 44C, and a fourth chip sidewall 44D. The first chip sidewall 44A and the second chip sidewall 44B form the long side of the semiconductor chip 41. The first chip sidewall 44A and the second chip sidewall 44B extend along a first direction X and are opposite each other along a second direction Y. The third chip sidewall 44C and the fourth chip sidewall 44D form the short side of the semiconductor chip 41. The third chip sidewall 44C and the fourth chip sidewall 44D extend along the second direction Y and are opposite each other along the first direction X. The chip sidewalls 44A-44D are formed by grinding surfaces.

[0059] The semiconductor device 5 further includes an insulating layer 51 formed on a first main surface 42 of the semiconductor chip 41. The insulating layer 51 has an insulating main surface 52 and insulating sidewalls 53A to 53D. In a top view, the insulating main surface 52 is formed as a quadrilateral shape (rectangular shape in this embodiment) that matches the first main surface 42. The insulating main surface 52 extends parallel to the first main surface 42.

[0060] The insulating sidewalls 53A-53D include: a first insulating sidewall 53A, a second insulating sidewall 53B, a third insulating sidewall 53C, and a fourth insulating sidewall 53D. The insulating sidewalls 53A-53D extend from the periphery of the insulating main surface 52 toward the semiconductor chip 41 and are connected to the chip sidewalls 44A-44D. Specifically, the insulating sidewalls 53A-53D are formed flush with the chip sidewalls 44A-44D. The insulating sidewalls 53A-53D form grinding surfaces flush with the chip sidewalls 44A-44D.

[0061] The insulating layer 51 is composed of a multilayer insulating stack structure including a lower insulating layer 55, an upper insulating layer 56, and multiple (11 layers in this embodiment) interlayer insulating layers 57. The lower insulating layer 55 is an insulating layer that directly covers the first main surface 42. The upper insulating layer 56 is an insulating layer that forms the insulating main surface 52. The multiple interlayer insulating layers 57 are insulating layers located between the lower insulating layer 55 and the upper insulating layer 56. In this embodiment, the lower insulating layer 55 has a single-layer structure containing silicon oxide. In this embodiment, the upper insulating layer 56 has a single-layer structure containing silicon oxide. The thickness of the lower insulating layer 55 and the thickness of the upper insulating layer 56 can be more than 1 μm and less than 3 μm (for example, about 2 μm).

[0062] The multiple interlayer insulating layers 57 each have a stacked structure comprising a first insulating layer 58 on the side of the lowest insulating layer 55 and a second insulating layer 59 on the side of the highest insulating layer 56. The first insulating layer 58 may also comprise silicon nitride. The first insulating layer 58 is formed as an etch stop layer relative to the second insulating layer 59. The thickness of the first insulating layer 58 may be greater than 0.1 μm and less than 1 μm (e.g., about 0.3 μm).

[0063] A second insulating layer 59 is formed on top of the first insulating layer 58. It comprises an insulating material different from the first insulating layer 58. The second insulating layer 59 may also comprise silicon oxide. The thickness of the second insulating layer 59 can be more than 1 μm and less than 3 μm (e.g., about 2 μm). Preferably, the thickness of the second insulating layer 59 exceeds the thickness of the first insulating layer 58.

[0064] The total thickness DT of the insulating layer 51 can be 5 μm or more and 50 μm or less. The total thickness DT of the insulating layer 51 and the number of layers of the interlayer insulating layer 57 are arbitrary and are adjusted according to the required insulation withstand voltage (insulation breakdown withstand capability). In addition, the insulating materials of the bottom insulating layer 55, the top insulating layer 56 and the interlayer insulating layer 57 are arbitrary and not limited to specific insulating materials.

[0065] The semiconductor device 5 includes a first functional device 45 formed on the insulating layer 51. The first functional device 45 includes one or more (in this embodiment, multiple) transformers 21 (equivalent to the previous transformers). That is, the semiconductor device 5 is a multi-channel device including multiple transformers 21. The multiple transformers 21 are formed at intervals and spaced apart from the insulating sidewalls 53A-53D inside the insulating layer 51. The multiple transformers 21 are formed at intervals and spaced apart along a first direction X.

[0066] Specifically, in the top view, the plurality of transformers 21 include a first transformer 21A, a second transformer 21B, a third transformer 21C, and a fourth transformer 21D, which are formed sequentially from the insulating sidewall 53C side toward the insulating sidewall 53D side. The plurality of transformers 21A to 21D each have the same construction. The construction of the first transformer 21A will be described below as an example. The description of the construction of the second transformer 21B, the third transformer 21C, and the fourth transformer 21D, applicable to the construction of the first transformer 21A, is omitted.

[0067] Reference Figures 5-7 The first transformer 21A includes a low-potential coil 22 and a high-potential coil 23. The low-potential coil 22 is formed within an insulating layer 51. The high-potential coil 23 is formed within the insulating layer 51 opposite to the low-potential coil 22 along the normal direction Z. In this embodiment, the low-potential coil 22 and the high-potential coil 23 are formed in the region sandwiched between the lowermost insulating layer 55 and the uppermost insulating layer 56 (i.e., multiple interlayer insulating layers 57).

[0068] The low-potential coil 22 is formed within the insulating layer 51 on the side of the lowest insulating layer 55 (semiconductor chip 41), and the high-potential coil 23 is formed within the insulating layer 51 relative to the low-potential coil 22 on the side of the uppermost insulating layer 56 (insulating main surface 52). That is, the high-potential coil 23 is positioned opposite the semiconductor chip 41, separated from the low-potential coil 22. The arrangement positions of the low-potential coil 22 and the high-potential coil 23 are arbitrary. In addition, the high-potential coil 23 only needs to be positioned opposite the low-potential coil 22, separated from it by one or more interlayer insulating layers 57.

[0069] The distance between the low-potential coil 22 and the high-potential coil 23 (i.e., the number of layers of interlayer insulation 57) is appropriately adjusted according to the insulation withstand voltage and electric field strength between the low-potential coil 22 and the high-potential coil 23. In this embodiment, the low-potential coil 22 is formed in the third layer of interlayer insulation 57 starting from the side of the bottommost insulation layer 55. In this embodiment, the high-potential coil 23 is formed in the first layer of interlayer insulation 57 starting from the side of the topmost insulation layer 56.

[0070] The low-potential coil 22 is embedded in the interlayer insulation layer 57, passing through the first insulation layer 58 and the second insulation layer 59. The low-potential coil 22 includes a first inner end 24, a first outer end 25, and a first helical portion 26 spirally wound between the first inner end 24 and the first outer end 25. In a top view, the first helical portion 26 is spirally wound in an elliptical shape (oblong shape). The portion forming the innermost periphery of the first helical portion 26 divides an elliptical first inner region 66 in a top view.

[0071] The number of turns in the first helical portion 26 can be 5 or more and 30 or less. The width of the first helical portion 26 can also be 0.1 μm or more and 5 μm or less. The width of the first helical portion 26 is preferably 1 μm or more and 3 μm or less. The width of the first helical portion 26 is defined by the width in the direction orthogonal to the helical direction. The first winding pitch of the first helical portion 26 can be 0.1 μm or more and 5 μm or less. The first winding pitch is preferably 1 μm or more and 3 μm or less. The first winding pitch is defined by the distance between two adjacent portions in the first helical portion 26 in the direction orthogonal to the helical direction.

[0072] The winding shape of the first spiral portion 26 and the planar shape of the first inner region 66 are arbitrary and not limited to any particular shape. Figure 5 As shown in the diagram. The first spiral portion 26 can also be wound into a polygonal shape such as a triangular shape or a quadrilateral shape or a circular shape in the top view. The first inner region 66 can also be divided into a polygonal shape such as a triangular shape or a quadrilateral shape or a circular shape in the top view according to the winding shape of the first spiral portion 26.

[0073] The low-potential coil 22 may also comprise at least one of titanium, titanium nitride, copper, aluminum, and tungsten. The low-potential coil 22 may also have a laminated structure comprising a barrier layer and a main body layer. The barrier layer divides recessed spaces within the interlayer insulating layer 57. The barrier layer may comprise at least one of titanium and titanium nitride. The main body layer may comprise at least one of copper, aluminum, and tungsten.

[0074] The high-potential coil 23 is embedded in the interlayer insulating layer 57, passing through the first insulating layer 58 and the second insulating layer 59. The high-potential coil 23 includes a second inner end 27, a second outer end 28, and a second spiral portion 29 wound in a spiral shape between the second inner end 27 and the second outer end 28. In a top view, the second spiral portion 29 is spirally wound in an elliptical shape (oblong shape). In this embodiment, the portion forming the innermost periphery of the second spiral portion 29 defines an elliptical second inner region 67 in a top view. The second inner region 67 of the second spiral portion 29 is opposite to the first inner region 66 of the first spiral portion 26 along the normal direction Z.

[0075] The number of turns in the second helical section 29 can be 5 or more and 30 or less. The number of turns in the second helical section 29 relative to the number of turns in the first helical section 26 is adjusted according to the voltage value to be boosted. Preferably, the number of turns in the second helical section 29 exceeds the number of turns in the first helical section 26. Of course, the number of turns in the second helical section 29 can be less than the number of turns in the first helical section 26, or it can be equal to the number of turns in the first helical section 26.

[0076] The width of the second helical portion 29 can be 0.1 μm or more and 5 μm or less. Preferably, the width of the second helical portion 29 is 1 μm or more and 3 μm or less. The width of the second helical portion 29 is defined by the width in the direction orthogonal to the helical direction. Preferably, the width of the second helical portion 29 is equal to the width of the first helical portion 26.

[0077] The second winding pitch of the second helical portion 29 can be 0.1 μm or more and 5 μm or less. Preferably, the second winding pitch is 1 μm or more and 3 μm or less. The second winding pitch is defined by the distance between two adjacent portions of the second helical portion 29 in a direction orthogonal to the helical direction. Preferably, the second winding pitch is equal to the first winding pitch of the first helical portion 26.

[0078] The winding shape of the second spiral section 29 and the planar shape of the second inner region 67 are arbitrary and not limited to... Figure 6 As shown in the diagram. The second spiral portion 29 can also be wound into a polygonal shape such as a triangle or a quadrilateral shape, or a circle in the top view. The second inner region 67 can also be divided into a polygonal shape such as a triangle or a quadrilateral shape, or a circle in the top view, depending on the winding shape of the second spiral portion 29.

[0079] The high-potential coil 23 is preferably formed of the same conductive material as the low-potential coil 22. That is, the high-potential coil 23 preferably includes a barrier layer and a main body layer in the same way as the low-potential coil 22.

[0080] Reference Figure 4 The semiconductor device 5 includes a plurality of (12 in this figure) low-potential terminals 11 and a plurality of (12 in this figure) high-potential terminals 12. The plurality of low-potential terminals 11 are electrically connected to the low-potential coils 22 of the corresponding transformers 21A to 21D. The plurality of high-potential terminals 12 are electrically connected to the high-potential coils 23 of the corresponding transformers 21A to 21D.

[0081] Multiple low-potential terminals 11 are formed on the insulating main surface 52 of the insulating layer 51. Specifically, the multiple low-potential terminals 11 are formed at intervals along the second direction Y and the multiple transformers 21A~21D in the region on the insulating sidewall 53B, and are arranged at intervals along the first direction X.

[0082] The plurality of low-potential terminals 11 includes: a first low-potential terminal 11A, a second low-potential terminal 11B, a third low-potential terminal 11C, a fourth low-potential terminal 11D, a fifth low-potential terminal 11E, and a sixth low-potential terminal 11F. In this embodiment, each of the plurality of low-potential terminals 11A to 11F is formed in twos. The number of the plurality of low-potential terminals 11A to 11F is arbitrary.

[0083] In the top view, the first low-potential terminal 11A is opposite to the first transformer 21A along the second direction Y. In the top view, the second low-potential terminal 11B is opposite to the second transformer 21B along the second direction Y. In the top view, the third low-potential terminal 11C is opposite to the third transformer 21C along the second direction Y. In the top view, the fourth low-potential terminal 11D is opposite to the fourth transformer 21D along the second direction Y. In the top view, the fifth low-potential terminal 11E is formed in the area between the first low-potential terminal 11A and the second low-potential terminal 11B. In the top view, the sixth low-potential terminal 11F is formed in the area between the third low-potential terminal 11C and the fourth low-potential terminal 11D.

[0084] The first low-potential terminal 11A is electrically connected to the first inner end 24 of the first transformer 21A (low-potential coil 22). The second low-potential terminal 11B is electrically connected to the first inner end 24 of the second transformer 21B (low-potential coil 22). The third low-potential terminal 11C is electrically connected to the first inner end 24 of the third transformer 21C (low-potential coil 22). The fourth low-potential terminal 11D is electrically connected to the first inner end 24 of the fourth transformer 21D (low-potential coil 22).

[0085] The fifth low-potential terminal 11E is electrically connected to the first outer end 25 of the first transformer 21A (low-potential coil 22) and the first outer end 25 of the second transformer 21B (low-potential coil 22). The sixth low-potential terminal 11F is electrically connected to the first outer end 25 of the third transformer 21C (low-potential coil 22) and the first outer end 25 of the fourth transformer 21D (low-potential coil 22).

[0086] Multiple high-potential terminals 12 and multiple low-potential terminals 11 are formed spaced apart on the insulating main surface 52 of the insulating layer 51. Specifically, the multiple high-potential terminals 12 are formed spaced apart from the multiple low-potential terminals 11 in the region of the insulating sidewall 53A, and are arranged spaced apart along the first direction X.

[0087] In the top view, multiple high-potential terminals 12 are respectively formed in areas close to the corresponding transformers 21A~21D. The high-potential terminals 12 are close to the transformers 21A~21D in the top view because the distance between the high-potential terminals 12 and the transformers 21 is less than the distance between the low-potential terminals 11 and the high-potential terminals 12.

[0088] Specifically, in the top view, a plurality of high-potential terminals 12 are formed at intervals along the first direction X, opposite to a plurality of transformers 21A-21D. More specifically, in the top view, the plurality of high-potential terminals 12 are formed at intervals along the first direction X, located in the second inner region 67 of the high-potential coil 23 and the region between adjacent high-potential coils 23. Thus, in the top view, the plurality of high-potential terminals 12 are arranged side by side in a row with the plurality of transformers 21A-21D along the first direction X.

[0089] The plurality of high-potential terminals 12 includes: a first high-potential terminal 12A, a second high-potential terminal 12B, a third high-potential terminal 12C, a fourth high-potential terminal 12D, a fifth high-potential terminal 12E, and a sixth high-potential terminal 12F. In this embodiment, each of the plurality of high-potential terminals 12A to 12F is formed in two. The number of the plurality of high-potential terminals 12A to 12F is arbitrary.

[0090] In the top view, a first high-potential terminal 12A is formed in the second inner region 67 of the first transformer 21A (high-potential coil 23). A second high-potential terminal 12B is formed in the second inner region 67 of the second transformer 21B (high-potential coil 23). A third high-potential terminal 12C is formed in the second inner region 67 of the third transformer 21C (high-potential coil 23). A fourth high-potential terminal 12D is formed in the second inner region 67 of the fourth transformer 21D (high-potential coil 23). A fifth high-potential terminal 12E is formed in the region between the first transformer 21A and the second transformer 21B in the top view. A sixth high-potential terminal 12F is formed in the region between the third transformer 21C and the fourth transformer 21D in the top view.

[0091] The first high-potential terminal 12A is electrically connected to the second inner end 27 of the first transformer 21A (high-potential coil 23). The second high-potential terminal 12B is electrically connected to the second inner end 27 of the second transformer 21B (high-potential coil 23). The third high-potential terminal 12C is electrically connected to the second inner end 27 of the third transformer 21C (high-potential coil 23). The fourth high-potential terminal 12D is electrically connected to the second inner end 27 of the fourth transformer 21D (high-potential coil 23).

[0092] The fifth high-potential terminal 12E is electrically connected to the second outer end 28 of the first transformer 21A (high-potential coil 23) and the second outer end 28 of the second transformer 21B (high-potential coil 23). The sixth high-potential terminal 12F is electrically connected to the second outer end 28 of the third transformer 21C (high-potential coil 23) and the second outer end 28 of the fourth transformer 21D (high-potential coil 23).

[0093] Reference Figures 5-7 The semiconductor device 5 includes a first low-potential wiring 31, a second low-potential wiring 32, a first high-potential wiring 33, and a second high-potential wiring 34, respectively formed within an insulating layer 51. In this embodiment, a plurality of first low-potential wirings 31, a plurality of second low-potential wirings 32, a plurality of first high-potential wirings 33, and a plurality of second high-potential wirings 34 are formed.

[0094] The first low-potential wiring 31 and the second low-potential wiring 32 fix the low-potential coil 22 of the first transformer 21A and the low-potential coil 22 of the second transformer 21B to the same potential. Furthermore, the first low-potential wiring 31 and the second low-potential wiring 32 fix the low-potential coil 22 of the third transformer 21C and the low-potential coil 22 of the fourth transformer 21D to the same potential. In this embodiment, the first low-potential wiring 31 and the second low-potential wiring 32 fix all the low-potential coils 22 of transformers 21A to 21D to the same potential.

[0095] The first high-potential wiring 33 and the second high-potential wiring 34 fix the high-potential coil 23 of the first transformer 21A and the high-potential coil 23 of the second transformer 21B to the same potential. Furthermore, the first high-potential wiring 33 and the second high-potential wiring 34 fix the high-potential coil 23 of the third transformer 21C and the high-potential coil 23 of the fourth transformer 21D to the same potential. In this embodiment, the first high-potential wiring 33 and the second high-potential wiring 34 fix all the high-potential coils 23 of transformers 21A to 21D to the same potential.

[0096] Multiple first low-potential wirings 31 are electrically connected to the corresponding low-potential terminals 11A-11D and the first inner ends 24 of the corresponding transformers 21A-21D (low-potential coils 22), respectively. The multiple first low-potential wirings 31 have the same structure. Hereinafter, the structure of the first low-potential wiring 31 connected to the first low-potential terminal 11A and the first transformer 21A will be described as an example. The description of the structure of the other first low-potential wirings 31 is omitted for the first low-potential wiring 31 connected to the first transformer 21A.

[0097] The first low-potential wiring 31 includes: a through wiring 71, a low-potential connection wiring 72, a lead wiring 73, a first connection plug electrode 74, a second connection plug electrode 75, one or more (in this embodiment, multiple) pad plug electrodes 76, and one or more (in this embodiment, multiple) substrate plug electrodes 77.

[0098] The through-wire 71, low-potential connection wire 72, lead-out wire 73, first connection plug electrode 74, second connection plug electrode 75, pad plug electrode 76, and substrate plug electrode 77 are preferably formed of the same conductive material as the low-potential coil 22. That is, the through-wire 71, low-potential connection wire 72, lead-out wire 73, first connection plug electrode 74, second connection plug electrode 75, pad plug electrode 76, and substrate plug electrode 77 are preferably the same as the low-potential coil 22, each including a barrier layer and a main body layer.

[0099] The through-wire 71 extends through multiple interlayer insulation layers 57 in the insulation layer 51, forming a columnar shape extending along the normal direction Z. In this embodiment, the through-wire 71 is formed in the region between the lowermost insulation layer 55 and the uppermost insulation layer 56 in the insulation layer 51. The through-wire 71 has an upper end portion on the side of the uppermost insulation layer 56 and a lower end portion on the side of the lowermost insulation layer 55. The upper end portion of the through-wire 71 is formed in the same interlayer insulation layer 57 as the high-potential coil 23 and is covered by the uppermost insulation layer 56. The lower end portion of the through-wire 71 is formed in the same interlayer insulation layer 57 as the low-potential coil 22.

[0100] In this embodiment, the through-wiring 71 includes a first electrode layer 78, a second electrode layer 79, and a plurality of wiring plug electrodes 80. In the through-wiring 71, the first electrode layer 78, the second electrode layer 79, and the wiring plug electrodes 80 are each formed of the same conductive material as the low-potential coil 22. That is, the first electrode layer 78, the second electrode layer 79, and the wiring plug electrodes 80, like the low-potential coil 22, each include a barrier layer and a main body layer.

[0101] The first electrode layer 78 forms the upper end of the through wiring 71. The second electrode layer 79 forms the lower end of the through wiring 71. The first electrode layer 78 is formed in an island shape and is opposite to the low potential terminal 11 (first low potential terminal 11A) along the normal direction Z. The second electrode layer 79 is formed in an island shape and is opposite to the first electrode layer 78 along the normal direction Z.

[0102] Multiple wiring plug electrodes 80 are embedded in multiple interlayer insulation layers 57 located between the first electrode layer 78 and the second electrode layer 79. The multiple wiring plug electrodes 80 are stacked from the lowest insulation layer 55 to the highest insulation layer 56 in an electrically interconnected manner, and electrically connect the first electrode layer 78 and the second electrode layer 79. Each of the multiple wiring plug electrodes 80 has a planar area smaller than the planar area of ​​the first electrode layer 78 and the planar area of ​​the second electrode layer 79.

[0103] Furthermore, the number of stacked layers of the plurality of wiring plug electrodes 80 is consistent with the number of stacked layers of the plurality of interlayer insulation layers 57. In this embodiment, six wiring plug electrodes 80 are embedded in each interlayer insulation layer 57, but the number of wiring plug electrodes 80 embedded in each interlayer insulation layer 57 is arbitrary. Of course, one or more wiring plug electrodes 80 that penetrate multiple interlayer insulation layers 57 can also be formed.

[0104] A low-potential connection wiring 72 is formed within the same interlayer insulation layer 57 as the low-potential coil 22 in the first inner region 66 of the first transformer 21A (low-potential coil 22). The low-potential connection wiring 72 is formed in an island shape, facing the high-potential terminal 12 (first high-potential terminal 12A) along the normal direction Z. The low-potential connection wiring 72 preferably has a planar area exceeding the planar area of ​​the wiring plug electrode 80. The low-potential connection wiring 72 is electrically connected to the first inner end 24 of the low-potential coil 22.

[0105] Lead-out wiring 73 is formed within interlayer insulating layer 57 in the region between semiconductor chip 41 and through wiring 71. In this embodiment, lead-out wiring 73 is formed within interlayer insulating layer 57, which is the first layer starting from the lowest insulating layer 55. Lead-out wiring 73 includes: a first end on one side, a second end on the other side, and a wiring portion connecting the first end and the second end. The first end of lead-out wiring 73 is located in the region between semiconductor chip 41 and the lower end of through wiring 71. The second end of lead-out wiring 73 is located in the region between semiconductor chip 41 and low-potential connection wiring 72. The wiring portion extends along the first main surface 42 of semiconductor chip 41 and extends in a strip shape in the region between the first end and the second end.

[0106] The first connection plug electrode 74 is formed within the interlayer insulating layer 57 in the region between the through wiring 71 and the lead wiring 73, and is electrically connected to the first end of the through wiring 71 and the lead wiring 73. The second connection plug electrode 75 is formed within the interlayer insulating layer 57 in the region between the low-potential connection wiring 72 and the lead wiring 73, and is electrically connected to the second end of the low-potential connection wiring 72 and the lead wiring 73.

[0107] Multiple pad plug electrodes 76 are formed within the uppermost insulating layer 56 in the region between the low-potential terminal 11 (first low-potential terminal 11A) and the through wiring 71, respectively, and are electrically connected to the upper ends of the low-potential terminal 11 and the through wiring 71. Multiple substrate plug electrodes 77 are formed within the lowermost insulating layer 55 in the region between the semiconductor chip 41 and the lead wiring 73. In this embodiment, the substrate plug electrodes 77 are formed in the region between the semiconductor chip 41 and the first ends of the lead wiring 73, respectively, and are electrically connected to the first ends of the semiconductor chip 41 and the lead wiring 73.

[0108] Reference Figure 6and Figure 7 Multiple first high-potential wirings 33 are electrically connected to the second inner ends 27 of the corresponding high-potential terminals 12A-12D and the corresponding transformers 21A-21D (high-potential coils 23), respectively. Each of the multiple first high-potential wirings 33 has the same structure. The following description uses the structure of the first high-potential wiring 33 connected to the first high-potential terminal 12A and the first transformer 21A as an example. The description of the structure of the other first high-potential wirings 33 is omitted for the first high-potential wiring 33 connected to the first transformer 21A.

[0109] The first high-potential wiring 33 includes a high-potential connection wiring 81 and one or more (in this embodiment, multiple) pad plug electrodes 82. The high-potential connection wiring 81 and the pad plug electrodes 82 are preferably formed of the same conductive material as the low-potential coil 22. That is, the high-potential connection wiring 81 and the pad plug electrodes 82 preferably include a barrier layer and a body layer, just like the low-potential coil 22.

[0110] The high-potential connection wiring 81 is formed within the same interlayer insulation layer 57 as the high-potential coil 23 in the second inner region 67 of the high-potential coil 23. The high-potential connection wiring 81 is formed in an island shape and is positioned opposite the high-potential terminal 12 (first high-potential terminal 12A) along the normal direction Z. The high-potential connection wiring 81 is electrically connected to the second inner end 27 of the high-potential coil 23. In the top view, the high-potential connection wiring 81 is formed with a gap from the low-potential connection wiring 72 and is not positioned opposite the low-potential connection wiring 72 along the normal direction Z. Therefore, the insulation distance between the low-potential connection wiring 72 and the high-potential connection wiring 81 is increased, and the insulation withstand voltage of the insulation layer 51 is improved.

[0111] Multiple pad plug electrodes 82 are formed within the uppermost insulating layer 56 in the region between the high-potential terminal 12 (first high-potential terminal 12A) and the high-potential connection wiring 81, respectively, and are electrically connected to the high-potential terminal 12 and the high-potential connection wiring 81. In a top view, each of the multiple pad plug electrodes 82 has a planar area smaller than the planar area of ​​the high-potential connection wiring 81.

[0112] Reference Figure 7Preferably, the distance D1 between the low-potential terminal 11 and the high-potential terminal 12 exceeds the distance D2 between the low-potential coil 22 and the high-potential coil 23 (D2 < D1). Distance D1 preferably exceeds the total thickness DT of the plurality of interlayer insulation layers 57 (DT < D1). The ratio of distance D2 to distance D1, D2 / D1, can be 0.01 or more and 0.1 or less. Distance D1 is preferably 100 μm or more and 500 μm or less. Distance D2 can be 1 μm or more and 50 μm or less. Distance D2 is preferably 5 μm or more and 25 μm or less. The values ​​of distance D1 and distance D2 are arbitrary and appropriately adjusted according to the insulation withstand voltage to be achieved.

[0113] Reference Figure 6 as well as Figure 7 In the top view, the semiconductor device 5 includes a dummy pattern 85 embedded in the insulating layer 51 in a manner that surrounds the transformers 21A to 21D.

[0114] The dummy pattern 85 is formed from a different pattern (a discontinuous pattern) than that of the high-potential coil 23 and the low-potential coil 22, and is independent of the transformers 21A-21D. That is, the dummy pattern 85 does not function as a component of the transformers 21A-21D. The dummy pattern 85 is formed as a shielding conductor layer that shields the electric field between the low-potential coil 22 and the high-potential coil 23 in the transformers 21A-21D, suppressing electric field concentration targeting the high-potential coil 23. In this embodiment, the dummy pattern 85 is wound with a linear density equal to that of the high-potential coil 23 per unit area. The linear density of the dummy pattern 85 being equal to that of the high-potential coil 23 means that the linear density of the dummy pattern 85 converges within ±20% of the linear density of the high-potential coil 23.

[0115] The depth of the dummy pattern 85 inside the insulating layer 51 is arbitrary and adjusted according to the electric field strength to be mitigated. The dummy pattern 85 is preferably formed in a region in the normal direction Z that is close to the low-potential coil 22 and the high-potential coil 23. Furthermore, "close to the high-potential coil 23 in the normal direction Z" means that the distance between the dummy pattern 85 and the high-potential coil 23 in the normal direction Z is less than the distance between the dummy pattern 85 and the low-potential coil 22.

[0116] In this case, electric field concentration against the high-potential coil 23 can be appropriately suppressed. The smaller the distance between the dummy pattern 85 and the high-potential coil 23 in the normal direction Z, the better the electric field concentration against the high-potential coil 23 can be suppressed. The dummy pattern 85 is preferably formed within the same interlayer insulating layer 57 as the high-potential coil 23. In this case, electric field concentration against the high-potential coil 23 can be suppressed more appropriately. The dummy pattern 85 comprises multiple dummy patterns with different electrical states. The dummy pattern 85 may also include a high-potential dummy pattern.

[0117] The depth of the high-potential dummy pattern 86 inside the insulating layer 51 is arbitrary and adjusted according to the electric field strength to be mitigated. The high-potential dummy pattern 86 is preferably formed in a region in the normal direction Z that is close to the high-potential coil 23 relative to the low-potential coil 22. "Close to the high-potential coil 23 in the normal direction Z" means that the distance between the high-potential dummy pattern 86 and the high-potential coil 23 in the normal direction Z is less than the distance between the high-potential dummy pattern 86 and the low-potential coil 22.

[0118] The dummy pattern 85 includes a suspended dummy pattern formed in the insulation layer 51 in an electrically suspended state, located around the transformers 21A to 21D.

[0119] In this embodiment, the suspended dummy pattern, in the top view, appears as a densely wound line that partially covers and exposes the area surrounding the high-potential coil 23. The suspended dummy pattern can be formed with ends or without ends.

[0120] The depth position of the suspended dummy pattern inside the insulating layer 51 is arbitrary and can be adjusted according to the electric field strength to be mitigated.

[0121] The number of levitation lines is arbitrary and can be adjusted according to the electric field to be mitigated. A levitation dummy pattern can also be composed of multiple levitation dummy patterns.

[0122] Reference Figure 7 The semiconductor device 5 includes a second functional device 60 formed in the device region 62 on the first main surface 42 of the semiconductor chip 41. The second functional device 60 is formed utilizing the surface portion of the first main surface 42 of the semiconductor chip 41 and / or the region above the first main surface 42 of the semiconductor chip 41, and is covered by an insulating layer 51 (lowest insulating layer 55). Figure 7 In the diagram, the second functional device 60 is simplified and shown through the dashed lines on the surface of the first main surface 42.

[0123] The second functional device 60 is electrically connected to the low-potential terminal 11 via a low-potential wiring and to the high-potential terminal 12 via a high-potential wiring. The low-potential wiring has the same structure as the first low-potential wiring 31 (second low-potential wiring 32), except that it is wound into the insulating layer 51 in order to connect to the second functional device 60. The high-potential wiring has the same structure as the first high-potential wiring 33 (second high-potential wiring 34), except that it is wound into the insulating layer 51 in order to connect to the second functional device 60. Detailed descriptions of the low-potential and high-potential wirings of the second functional device 60 are omitted.

[0124] The second functional device 60 may also include at least one of a passive device, a semiconductor rectifier, and a semiconductor switch. Among the passive devices, the second functional device 60 may also include a circuit network formed by selectively combining any two or more of the passive devices, semiconductor rectifiers, and semiconductor switch devices. The circuit network may also form part or all of an integrated circuit.

[0125] Passive devices may include semiconductor passive devices. Passive devices may also include any one or both of resistors and capacitors. Semiconductor rectifier devices may also include at least one of pn junction diodes, PIN diodes, Zener diodes, Schottky barrier diodes, and fast recovery diodes. Semiconductor switching devices may also include at least one of BJTs (bipolar junction transistors), MISFETs (metal-insulator field-effect transistors), IGBTs (insulated gate bipolar junction transistors), and JFETs (junction field-effect transistors).

[0126] Reference Figures 5-7 The semiconductor device 5 further includes a sealing conductor 61 embedded within an insulating layer 51. In a top view, the sealing conductor 61 is embedded in the insulating layer 51 in a wall-like manner, spaced apart from the insulating sidewalls 53A-53D, dividing the insulating layer 51 into a device region 62 and an outer region 63. The sealing conductor 61 inhibits the ingress of moisture from the outer region 63 into the device region 62 and the formation of cracks.

[0127] Device area 62 is the area that includes the following: first functional device 45 (multiple transformers 21), second functional device 60, multiple low-potential terminals 11, multiple high-potential terminals 12, first low-potential wiring 31, second low-potential wiring 32, first high-potential wiring 33, second high-potential wiring 34, and dummy pattern 85. Outer area 63 is the area outside device area 62.

[0128] The sealed conductor 61 is electrically isolated from the device region 62. Specifically, the sealed conductor 61 is electrically isolated from the first functional device 45 (multiple transformers 21), the second functional device 60, multiple low-potential terminals 11, multiple high-potential terminals 12, the first low-potential wiring 31, the second low-potential wiring 32, the first high-potential wiring 33, the second high-potential wiring 34, and the dummy pattern 85. More specifically, the sealed conductor 61 is fixed in an electrically levitated state. The sealed conductor 61 does not form a current path connected to the device region 62.

[0129] In the top view, the sealing conductor 61 is formed as a strip along the insulating sidewalls 53A-53D. In this embodiment, the sealing conductor 61 is formed as a four-sided ring (specifically, a rectangular ring) in the top view. Thus, the sealing conductor 61 divides the device region 62 into a four-sided (specifically, a rectangular) shape in the top view. In addition, the sealing conductor 61 divides the outer region 63 of the four-sided ring (specifically, a rectangular ring) surrounding the device region 62 in the top view.

[0130] Specifically, the sealing conductor 61 has an upper end portion on the insulating main surface 52 side, a lower end portion on the semiconductor chip 41 side, and a wall portion extending in a wall-like shape between the upper end portion and the lower end portion. In this embodiment, the upper end portion of the sealing conductor 61 is formed spaced apart from the insulating main surface 52 toward the semiconductor chip 41 side and is located within the insulating layer 51. In this embodiment, the upper end portion of the sealing conductor 61 is covered by the uppermost insulating layer 56. The upper end portion of the sealing conductor 61 may also be covered by one or more interlayer insulating layers 57. The upper end portion of the sealing conductor 61 may also be exposed from the uppermost insulating layer 56. The lower end portion of the sealing conductor 61 is formed spaced apart from the semiconductor chip 41 toward the upper end portion side.

[0131] Thus, in this embodiment, the sealing conductor 61 is embedded in the insulating layer 51 such that it is located on the semiconductor chip 41 side relative to the plurality of low-potential terminals 11 and the plurality of high-potential terminals 12. Furthermore, the sealing conductor 61 is positioned within the insulating layer 51 opposite to the first functional device 45 (the plurality of transformers 21), the first low-potential wiring 31, the second low-potential wiring 32, the first high-potential wiring 33, the second high-potential wiring 34, and the dummy pattern 85 in a direction parallel to the insulating main surface 52. Alternatively, the sealing conductor 61 may be positioned within the insulating layer 51 opposite to a portion of the second functional device 60 in a direction parallel to the insulating main surface 52.

[0132] The sealing conductor 61 comprises a plurality of sealing plug conductors 64 and one or more (in this embodiment, a plurality of) sealing through-hole conductors 65. The number of sealing through-hole conductors 65 is arbitrary. The uppermost sealing plug conductor 64 of the plurality of sealing plug conductors 64 forms the upper end of the sealing conductor 61. The plurality of sealing through-hole conductors 65 respectively form the lower end of the sealing conductor 61. The sealing plug conductors 64 and the sealing through-hole conductors 65 are preferably formed of the same conductive material as the low-potential coil 22. That is, the sealing plug conductors 64 and the sealing through-hole conductors 65 preferably include a barrier layer and a body layer, just like the low-potential coil 22.

[0133] Multiple hermetically sealed plug conductors 64 are embedded in multiple interlayer insulating layers 57, forming, in top view, four-sided rings (specifically rectangular rings) surrounding the device region 62. The multiple hermetically sealed plug conductors 64 are stacked from the bottom insulating layer 55 to the top insulating layer 56 in an interconnected manner. The number of stacks of the multiple hermetically sealed plug conductors 64 is the same as the number of stacks of the multiple interlayer insulating layers 57. Alternatively, one or more hermetically sealed plug conductors 64 may be formed that penetrate through multiple interlayer insulating layers 57.

[0134] If an assembly of multiple sealing plug conductors 64 forms a ring-shaped sealing conductor 61, it is not necessary for all of the multiple sealing plug conductors 64 to be formed in a ring shape. For example, at least one of the multiple sealing plug conductors 64 can also be formed in an end-shaped manner. Alternatively, at least one of the multiple sealing plug conductors 64 can also be divided into multiple end-shaped strips. However, given the risk of moisture ingress and crack formation within the device region 62, it is preferable that the multiple sealing plug conductors 64 be formed in an endless (ring-shaped) manner.

[0135] Multiple sealing via conductors 65 are formed in the lowermost insulating layer 55 in the region between the semiconductor chip 41 and the sealing plug conductor 64. The multiple sealing via conductors 65 are formed spaced apart from the semiconductor chip 41 and connected to the sealing plug conductor 64. The multiple sealing via conductors 65 have a planar area smaller than the planar area of ​​the sealing plug conductor 64. In the case where a single sealing via conductor 65 is formed, the single sealing via conductor 65 may also have a planar area greater than or equal to the planar area of ​​the sealing plug conductor 64.

[0136] The width of the sealing conductor 61 can be 0.1 μm or more and 10 μm or less. Preferably, the width of the sealing conductor 61 is 1 μm or more and 5 μm or less. The width of the sealing conductor 61 is defined by the width in a direction orthogonal to the direction in which the sealing conductor 61 extends.

[0137] Reference Figure 7 as well as Figure 8The semiconductor device 5 further includes a separation structure 130 located between the semiconductor chip 41 and the sealing conductor 61, electrically isolating the sealing conductor 61 from the semiconductor chip 41. The separation structure 130 preferably includes an insulator. In this embodiment, the separation structure 130 is formed of a field insulating film 131 formed on a first main surface 42 of the semiconductor chip 41.

[0138] The field insulating film 131 comprises at least one of an oxide film (silicon oxide film) and a nitride film (silicon nitride film). Preferably, the field insulating film 131 is composed of a LOCOS (Local Selective Oxidation of Silicon) film, which is an example of an oxide film formed by oxidation of the first main surface 42 of the semiconductor chip 41. The thickness of the field insulating film 131 is arbitrary, as long as it is sufficient to insulate the semiconductor chip 41 from the sealing conductor 61. The thickness of the field insulating film 131 can be 0.1 μm or more and 5 μm or less.

[0139] The separation structure 130 is formed on the first main surface 42 of the semiconductor chip 41 and extends in a strip shape along the sealing conductor 61 in a top view. In this embodiment, the separation structure 130 is formed as a four-sided ring (specifically a rectangular ring) in a top view. The separation structure 130 has a connection portion 132 that connects to the lower end of the sealing conductor 61 (sealing via conductor 65). The connection portion 132 may also be an anchoring portion recessed into the lower end of the sealing conductor 61 (sealing via conductor 65) toward the semiconductor chip 41. Of course, the connection portion 132 may also be formed flush with the main surface of the separation structure 130.

[0140] The separation structure 130 includes: an inner end portion 130A on the device region 62 side, an outer end portion 130B on the outer region 63 side, and a main body portion 130C between the inner end portion 130A and the outer end portion 130B. In the top view, the inner end portion 130A divides the region where the second functional device 60 is formed (i.e., device region 62). The inner end portion 130A may also be integrally formed with an insulating film (not shown) formed on the first main surface 42 of the semiconductor chip 41.

[0141] The outer end portion 130B exposes from and is connected to the chip sidewalls 44A-44D of the semiconductor chip 41. More specifically, the outer end portion 130B is formed flush with the chip sidewalls 44A-44D of the semiconductor chip 41. The outer end portion 130B forms a flush grinding surface between the chip sidewalls 44A-44D of the semiconductor chip 41 and the insulating sidewalls 53A-53D of the insulating layer 51. Of course, in other embodiments, the outer end portion 130B may also be formed spaced apart from the chip sidewalls 44A-44D within the first main surface 42.

[0142] The main body 130C has a flat surface that extends substantially parallel to the first main surface 42 of the semiconductor chip 41. The main body 130C has a connecting portion 132 that connects to the lower end of the sealing conductor 61 (sealing through-hole conductor 65). The connecting portion 132 is formed in the main body 130C in a portion spaced apart from the inner end portion 130A and the outer end portion 130B. The separation structure 130 can be implemented in various ways other than the field insulating film 131.

[0143] Reference Figure 7 The semiconductor device 5 further includes an inorganic insulating layer 140 formed on the insulating main surface 52 of the insulating layer 51 in a manner that covers the sealing conductor 61. The inorganic insulating layer 140 may also be referred to as a passivation layer. The inorganic insulating layer 140 protects the insulating layer 51 and the semiconductor chip 41 from the insulating main surface 52.

[0144] In this embodiment, the inorganic insulating layer 140 has a stacked structure comprising a first inorganic insulating layer 141 and a second inorganic insulating layer 142. The first inorganic insulating layer 141 may also comprise silicon oxide. Preferably, the first inorganic insulating layer 141 comprises undoped silicon oxide, i.e., USG (undoped silicon glass). The thickness of the first inorganic insulating layer 141 may be 50 nm or more and 5000 nm or less. The second inorganic insulating layer 142 may also comprise silicon nitride. The thickness of the second inorganic insulating layer 142 may be 500 nm or more and 5000 nm or less. By increasing the total thickness of the inorganic insulating layer 140, the insulation withstand voltage on the high-potential coil 23 can be improved.

[0145] When the first inorganic insulating layer 141 is made of USG and the second inorganic insulating layer 142 is made of silicon nitride, the insulation breakdown voltage (V / cm) of USG exceeds that of silicon nitride. Therefore, when the inorganic insulating layer 140 is made thicker, it is preferable to form a first inorganic insulating layer 141 that is thicker than the second inorganic insulating layer 142.

[0146] The first inorganic insulating layer 141 may also comprise at least one of BPSG (borosilicate glass) and PSG (phosphosilicate glass), which are examples of silicon oxide. However, in this case, impurities (boron or phosphorus) are contained in the silicon oxide. Therefore, it is particularly preferable to form the first inorganic insulating layer 141 composed of USG in order to improve the insulation withstand voltage on the high-potential coil 23. Of course, the inorganic insulating layer 140 may also have a single-layer structure composed of either the first inorganic insulating layer 141 or the second inorganic insulating layer 142.

[0147] The inorganic insulating layer 140 covers the entire area of ​​the sealing conductor 61 and has a plurality of low-potential pad openings 143 and a plurality of high-potential pad openings 144 formed outside the sealing conductor 61. The plurality of low-potential pad openings 143 expose a plurality of low-potential terminals 11 respectively. The plurality of high-potential pad openings 144 expose a plurality of high-potential terminals 12 respectively. The inorganic insulating layer 140 may also have an overlapping portion that overlaps the periphery of the low-potential terminals 11. The inorganic insulating layer 140 may also have an overlapping portion that overlaps the periphery of the high-potential terminals 12.

[0148] The semiconductor device 5 further includes an organic insulating layer 145 formed on the inorganic insulating layer 140. The organic insulating layer 145 may also contain a photosensitive resin. The organic insulating layer 145 may also contain at least one of polyimide, polyamide, and polybenzoxazole. In this embodiment, the organic insulating layer 145 contains polyimide. The thickness of the organic insulating layer 145 may be 1 μm or more and 50 μm or less.

[0149] The thickness of the organic insulating layer 145 is preferably greater than the total thickness of the inorganic insulating layer 140. Furthermore, the total thickness of the inorganic insulating layer 140 and the organic insulating layer 145 is preferably greater than the distance D2 between the low-potential coil 22 and the high-potential coil 23. In this case, the total thickness of the inorganic insulating layer 140 is preferably 2 μm or more and 10 μm or less. Additionally, the thickness of the organic insulating layer 145 is preferably 5 μm or more and 50 μm or less. Based on these structures, the thickening of the inorganic insulating layer 140 and the organic insulating layer 145 can be suppressed, while the insulation withstand voltage on the high-potential coil 23 can be appropriately increased through the laminated film of the inorganic insulating layer 140 and the organic insulating layer 145.

[0150] The organic insulating layer 145 includes a first portion 146 covering a region on the low-potential side and a second portion 147 covering a region on the high-potential side. The first portion 146 covers the sealing conductor 61 through the inorganic insulating layer 140. The first portion 146 has a plurality of low-potential terminal openings 148 in the region outside the sealing conductor 61, exposing a plurality of low-potential terminals 11 (low-potential pad openings 143). The first portion 146 may also have an overlap (overlap) that overlaps the periphery of the low-potential pad openings 143.

[0151] The second portion 147 is formed spaced apart from the first portion 146, such that the inorganic insulating layer 140 is exposed between the first portion 146 and the second portion 147. The second portion 147 has a plurality of high-potential terminal openings 149 that expose a plurality of high-potential terminals 12 (high-potential pad openings 144). The second portion 147 may also have an overlapping portion (overlapping portion) that overlaps the periphery of the high-potential pad openings 144.

[0152] Part 147 also covers transformers 21A-21D and dummy pattern 85. Specifically, Part 147 also covers multiple high-potential coils 23, multiple high-potential terminals 12, a first high-potential dummy pattern 87, a second high-potential dummy pattern 88, and a floating dummy pattern 121.

[0153] The present invention can also be implemented in other ways. In the described embodiments, an example having a first functional device 45 and a second functional device 60 has been illustrated. However, it is also possible to employ a configuration that does not have a first functional device 45 and only has a second functional device 60. In this case, the dummy pattern 85 can also be removed. According to this configuration, the second functional device 60 can achieve the same effect as described in the first embodiment (except for the effect of the dummy pattern 85).

[0154] That is, when a voltage is applied to the second functional device 60 via the low-potential terminal 11 and the high-potential terminal 12, undesirable conduction between the high-potential terminal 12 and the sealing conductor 61 can be suppressed. Furthermore, when a voltage is applied to the second functional device 60 via the low-potential terminal 11 and the high-potential terminal 12, undesirable conduction between the low-potential terminal 11 and the sealing conductor 61 can be suppressed.

[0155] Furthermore, in the described embodiment, an example with a second functional device 60 was given. However, the second functional device 60 is not necessary and may be omitted.

[0156] Furthermore, in the described embodiment, an example with a dummy pattern 85 was given. However, the dummy pattern 85 is not necessary and can be removed.

[0157] Furthermore, in the described embodiment, an example of a multi-channel type comprising multiple transformers 21 was given. However, a single-channel type comprising a single transformer 21 may also be used for the first functional device 45.

[0158] <Transformer Arrangement>

[0159] Figure 9 This is a top view (top view) schematically illustrating an example of the transformer arrangement in a dual-channel transformer chip 300 (equivalent to the previous semiconductor device 5). The transformer chip 300 in this figure includes: a first transformer 301, a second transformer 302, a third transformer 303, a fourth transformer 304, a first guard ring 305, a second guard ring 306, pads a1~a8, pads b1~b8, pads c1~c4, and pads d1~d4.

[0160] In the transformer chip 300, pads a1 and b1 are connected to one end of the secondary side coil L1s forming the first transformer 301, and pads c1 and d1 are connected to the other end of the secondary side coil L1s. Pads a2 and b2 are connected to one end of the secondary side coil L2s forming the second transformer 302, and pads c1 and d1 are connected to the other end of the secondary side coil L2s.

[0161] Additionally, pads a3 and b3 are connected to one end of the secondary coil L3s forming the third transformer 303, and pads c2 and d2 are connected to the other end of the secondary coil L3s. Pads a4 and b4 are connected to one end of the secondary coil L4s forming the fourth transformer 304, and pads c2 and d2 are connected to the other end of the secondary coil L4s.

[0162] Furthermore, the primary coils forming the first transformer 301, the second transformer 302, the third transformer 303, and the fourth transformer 304 are not explicitly shown in [the diagram / description]. Figure 9 However, the primary coils have essentially the same structure as the secondary coils L1s to L4s, and are arranged directly below each of the secondary coils L1s to L4s in a manner that is opposite to them.

[0163] That is, pads a5 and b5 are connected to one end of the primary coil forming the first transformer 301, and pads c3 and d3 are connected to the other end of the primary coil. In addition, pads a6 and b6 are connected to one end of the primary coil forming the second transformer 302, and pads c3 and d3 are connected to the other end of the primary coil.

[0164] Additionally, pads a7 and b7 are connected to one end of the primary winding of the third transformer 303, and pads c4 and d4 are connected to the other end of the primary winding. Similarly, pads a8 and b8 are connected to one end of the primary winding of the fourth transformer 304, and pads c4 and d4 are connected to the other end of the primary winding.

[0165] However, the aforementioned pads a5~a8, pads b5~b8, pads c3 and c4, and pads d3 and d4 are led out from the interior of the transformer chip 300 to the surface via through holes not shown.

[0166] Of the aforementioned pads, pads a1 to a8 correspond to the first current supply pads, and pads b1 to b8 correspond to the first voltage measurement pads. Additionally, pads c1 to c4 correspond to the second current supply pads, and pads d1 to d4 correspond to the second voltage measurement pads.

[0167] Therefore, in the case of the transformer chip 300 of this structural example, the series resistance of each coil can be accurately measured during defect inspection. Thus, not only can defective products with open circuits in each coil be rejected, but defective products with abnormal resistance values ​​in each coil (e.g., short circuits between coils) can also be appropriately rejected, thereby preventing defective products from entering the market.

[0168] Furthermore, for the transformer chip 300 that has passed the aforementioned defective product inspection, the aforementioned multiple pads can be used as connection units with the primary-side chip and the secondary-side chip (such as the previously mentioned controller chip 210 and driver chip 220).

[0169] Specifically, pads a1 and b1, pads a2 and b2, pads a3 and b3, and pads a4 and b4 can be connected to the signal input or signal output terminals of the secondary-side chip, respectively. In addition, pads c1 and d1, and pads c2 and d2 can be connected to the common voltage application terminal (GND2) of the secondary-side chip, respectively.

[0170] On the other hand, pads a5 and b5, pads a6 and b6, pads a7 and b7, and pads a8 and b8 can be connected to the signal input or signal output terminals of the primary-side chip, respectively. In addition, pads c3 and d3, and pads c4 and d4 can be connected to the common voltage application terminal (GND1) of the primary-side chip, respectively.

[0171] Here, as Figure 9 As shown, the first transformer 301 to the fourth transformer 304 are coupled together according to their respective signal transmission directions. Referring to this figure, for example, the first transformer 301 and the second transformer 302, which transmit signals from the primary side chip to the secondary side chip, form a first pair via the first guard ring 305. Furthermore, for example, the third transformer 303 and the fourth transformer 304, which transmit signals from the secondary side chip to the primary side chip, form a second pair via the second guard ring 306.

[0172] The reason for this coupling is to ensure a withstand voltage between the primary and secondary coils when the primary and secondary coils of the first transformer 301 to the fourth transformer 304 are stacked in a vertical configuration on the substrate of the transformer chip 300. However, the first guard ring 305 and the second guard ring 306 are not necessarily essential components.

[0173] In addition, the first protection ring 305 and the second protection ring 306 can be connected to low-impedance wiring such as the grounding terminal via pads e1 and e2, respectively.

[0174] Furthermore, in the transformer chip 300, pads c1 and d1 are shared between secondary-side coils L1s and L2s. Pads c2 and d2 are shared between secondary-side coils L3s and L4s. Pads c3 and d3 are shared between primary-side coils L1p and L2p. Pads c4 and d4 are shared with their respective primary-side coils. By adopting this structure, the number of pads can be reduced, enabling miniaturization of the transformer chip 300.

[0175] In addition, such as Figure 9 As shown, the primary and secondary coils of the first transformer 301 to the fourth transformer 304 are preferably wound in a rectangular shape (or a track-like shape with rounded corners) in the top view of the transformer chip 300. By arranging it in this way, the area of ​​the overlapping parts of the primary and secondary coils is increased, which can improve the transmission efficiency of the transformer.

[0176] Of course, the transformer arrangement in this diagram is just one example; the number, shape, and arrangement of the coils, as well as the arrangement of the pads, are arbitrary. Furthermore, the chip structure and transformer arrangement described so far can be applied to all semiconductor devices that integrate coils onto a semiconductor chip.

[0177] <Electronic Devices (First Comparative Example)>

[0178] Figure 10 This is a diagram illustrating a first comparative example of an electronic device (= an example of a general circuit configuration to be compared with the implementation described later). The electronic device A of this comparative example includes a switching element SW1, resistors R1H and R1L, a DC power supply E, and a signal transmission device 200.

[0179] As described above, the signal transmission device 200 can be a semiconductor device that transmits the switch control signal Vg from the primary circuit system 200p to the secondary circuit system 200s, while isolating the primary circuit system 200p and the secondary circuit system 200s (a so-called insulated gate driver IC). In this case, the switch control signal Vg corresponds to the aforementioned output pulse signal OUT.

[0180] In addition, the signal transmission device 200 has multiple external terminals (external terminals T11, T12, T13H and T13L in the figure) as a means for establishing a connection with the outside of the device.

[0181] The switching element SW1 can be a power device such as an IGBT (Insulated Gate Bipolar Transistor). The gate of the switching element SW1 is connected to the application terminal of the switching control signal Vg. The emitter of the switching element SW1 is connected to the application terminal of the ground voltage GND2 in the secondary circuit system 200s. The switching element SW1 is driven by the switching control signal Vg applied to the gate from the signal transmission device 200. For example, when the switching control signal Vg is high, the switching element SW1 is in the on state. On the other hand, when the switching control signal Vg is low, the switching element SW1 is in the off state.

[0182] DC power supply E generates power supply voltage VCC2 in secondary circuit system 200s. The positive terminal of DC power supply E (= the terminal for applying power supply voltage VCC2) is connected to the external terminal T11 of signal transmission device 200. The negative terminal of DC power supply E, together with the external terminal T12 of signal transmission device 200, is connected to the terminal for applying ground voltage GND2.

[0183] The first terminal of resistor R1H is connected to the external terminal T13H of signal transmission device 200. The first terminal of resistor R1L is connected to the external terminal T13L of signal transmission device 200. The second terminals of resistors R1H and R1L are both connected to the gate of switching element SW1 (= the application terminal of switch control signal Vg).

[0184] In this comparative example, the driver 224 integrated in the signal transmission device 200 can be understood as a voltage drive circuit configured to drive the switch control signal Vg. Referring to this figure, the driver 224 includes a transistor M1H (e.g., a P-channel MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor)) and a transistor M1L (e.g., an N-channel MOSFET).

[0185] Note that in this specification, a metal-oxide-semiconductor field-effect transistor (MOSFET) refers to a transistor having a gate structure comprising at least three layers: a "layer" made of a conductor or semiconductor (e.g., polycrystalline silicon with low resistance), an "isolation layer," and a "P-type, N-type, or intrinsic semiconductor layer." In other words, the gate structure of a MOSFET is not limited to a three-layer structure of metal, oxide, and semiconductor.

[0186] The source and back gate of transistor M1H are both connected to external terminal T11 (the terminal for applying power supply voltage VCC2). The drain of transistor M1H is connected to external terminal T13H. The source and back gate of transistor M1L are both connected to external terminal T12 (the terminal for applying ground voltage GND2). The drain of transistor M1L is connected to external terminal T13L.

[0187] When transistor M1H is in the ON state and transistor M1L is in the OFF state, the gate current IgH (= source current) flows from the power supply voltage VCC2 application terminal through transistor M1H and resistor R1H to the gate of switching element SW1. Therefore, the gate capacitor (not shown) is charged, and the switching control signal Vg rises from low to high. Consequently, switching element SW1 becomes ON.

[0188] On the other hand, when transistor M1H is in the off state and transistor M1L is in the on state, the gate current IgL (= sink current) flows from the gate of switching element SW1 through resistor R1L and transistor M1L to the applied terminal of ground voltage GND2. Therefore, the gate capacitor (not shown) is discharged, and thus the switch control signal Vg drops from high level to low level. Therefore, switching element SW1 becomes off.

[0189] <Electronic Devices (Second Comparative Example)>

[0190] Figure 11 This is a diagram illustrating a second comparative example of an electronic device (= another example of a general circuit configuration to be compared with the implementation described later).

[0191] The electronic device A in this comparative example includes a switching element SW1, a transistor M2H (e.g., a P-channel MOSFET), a transistor M2L (e.g., an N-channel MOSFET), resistors R2H and R2L, resistors R3H and R3L, a DC power supply E, and a signal transmission device 200. Additionally, the signal transmission device 200 has multiple external terminals (external terminals T11, T12, T14H, T14L, T15H, and T15L in this figure) as a means of establishing connections with the outside of the device.

[0192] Note that the components already described are derived from the above. Figure 10 The same numbers are used to omit duplicate descriptions and to focus on describing newly emerging components.

[0193] The first terminals of resistors R2H and R3H are each connected to the external terminal T11 of the signal transmission device 200 (the terminal for applying power supply voltage VCC2). The second terminal of resistor R2H, as well as the source and back gate of transistor M2H, are connected to the external terminal T15H of the signal transmission device 200 (the terminal for applying sense voltage V1H). The second terminal of resistor R3H and the gate of transistor M2H are both connected to the external terminal T14H of the signal transmission device 200 (the terminal for applying gate signal HG). The drain of transistor M2H is connected to the gate of switching element SW1 (the terminal for applying switch control signal Vg).

[0194] Note that resistor R2H is used as a sensing resistor to generate a sensing voltage V1H (=VCC2-R2H×IgH) corresponding to the gate current IgH flowing in transistor M2H. Furthermore, when external terminal T14H is in an open-circuit state (high impedance state), resistor R3H is used as a pull-up resistor to raise the gate signal HG to a high level (≈ supply voltage VCC2).

[0195] The first terminals of resistors R2L and R3L are each connected to the external terminal T12 of the signal transmission device 200 (the terminal for applying ground voltage GND2). The second terminal of resistor R2L, as well as the source and back gate of transistor M2L, are connected to the external terminal T15L of the signal transmission device 200 (the terminal for applying sense voltage V1L). The second terminal of resistor R3L and the gate of transistor M2L are both connected to the external terminal T14L of the signal transmission device 200 (the terminal for applying gate signal LG). The drain of transistor M2L is connected to the gate of switching element SW1 (the terminal for applying switch control signal Vg).

[0196] Note that resistor R2L is used as a sensing resistor to generate a sensing voltage V1L (=GND2+R2L×IgL) corresponding to the gate current IgL flowing in transistor M2L. Furthermore, when external terminal T14L is in an open-circuit state (high impedance state), resistor R3L is used as a pull-down resistor to reduce the gate signal LG to a low level (≈ ground voltage GND2).

[0197] In this comparative example, the driver 224 integrated in the signal transmission device 200 can be understood as a current-driven circuit configured to drive the switch control signal Vg. Referring to this figure, the driver 224 includes amplifiers A1H and A1L.

[0198] The inverting input terminal (-) of amplifier A1H is connected to the external terminal T15H (the terminal for applying the sensed voltage V1H). The non-inverting input terminal (+) of amplifier A1H is connected to the terminal for applying the reference voltage V2H (VCC2 - VrefH). The output terminal of amplifier A1H is connected to the external terminal T14H (the terminal for applying the gate signal HG).

[0199] When amplifier A1H is in the operating state, a gate signal HG is generated, causing the sensed voltage V1H (=VCC2-R2H×IgH) and the reference voltage V2H (=VCC2-VrefH) to be consistent with each other. In other words, output feedback control is performed so that the gate current IgH has the same value as the reference current IrefH (=VrefH / R2H). On the other hand, when amplifier A1H is in the non-operating state, the external terminal T14H is in the open circuit state (high impedance state).

[0200] The inverting input terminal (-) of amplifier A1L is connected to the external terminal T15L (the terminal for applying the sensed voltage V1L). The non-inverting input terminal (+) of amplifier A1L is connected to the terminal for applying the reference voltage V2L (GND2 + VrefL). The output terminal of amplifier A1L is connected to the external terminal T14L (the terminal for applying the gate signal LG).

[0201] When amplifier A1L is in the operating state, a gate signal LG is generated, causing the sensed voltage V1L (=GND2+R2L×IgL) and the reference voltage V2L (=GND2+VrefL) to be consistent with each other. In other words, output feedback control is performed so that the gate current IgL has the same value as the reference current IrefL (=VrefL / R2L). On the other hand, when amplifier A1L is in the non-operating state, the external terminal T14L is in the open circuit state (high impedance state).

[0202] When amplifier A1H is in the operating state and amplifier A1L is in the non-operating state, the gate current IgH (= source current) flows from the power supply voltage VCC2 application terminal through resistor R2H and transistor M2H to the gate of switching element SW1. Therefore, the gate capacitor (not shown) is charged, and the switching control signal Vg rises from low to high. Consequently, switching element SW1 becomes on.

[0203] On the other hand, when amplifier A1H is in a non-operating state and amplifier A1L is in an operating state, the gate current IgL (= sink current) flows from the gate of switching element SW1 through transistor M2L and resistor R2L to the applied terminal of ground voltage GND2. Therefore, the gate capacitor (not shown) is discharged, and thus the switching control signal Vg drops from a high level to a low level. Therefore, switching element SW1 becomes off.

[0204] <Optimization considering conversion rate>

[0205] As a general method for driving switching elements such as IGBTs, Si-MOSFETs, or SiC-MOSFETs, there is a method of applying a pulse voltage between the gate and source of the switching element via a gate resistor (the so-called voltage driving method), as in the first comparative example above. Figure 10 As shown in the figure.

[0206] In this voltage-driven method, the slewing rate (gradient) of the switch control signal can be controlled by adjusting the resistance of the gate resistors (e.g., resistors R1H and R1L). Note that the slewing rate of the switch control signal can be understood as the change in the gate current flowing in the switching element per unit time (di / dt), or the change in the gate voltage applied to the switching element per unit time (dv / dt).

[0207] Here, when the switching rate of the switching control signal decreases, output overshoot (= transient overcurrent or overvoltage) and EMI (electromagnetic interference) noise are suppressed, but the switching losses of the switching element may increase. On the other hand, when the switching rate of the switching control signal increases, the switching losses of the switching element decrease, but output overshoot and EMI noise may increase.

[0208] Therefore, in the voltage-driven method described above, given the aforementioned trade-offs, it is necessary to adjust the resistance of the gate resistor for each switching element to be driven. However, adjusting the resistance of the external gate resistor to accurately set the switching rate of the switch control signal is not always easy. Furthermore, it must be said that the degree of freedom in setting it is also very low.

[0209] On the other hand, compared with the above-mentioned voltage driving method ( Figure 10 Compared to the above-mentioned current-driven method, Figure 11 The switching rate of the switching control signal can be adjusted with high precision. However, the switching speed of the gate current is limited by the operating speed of the output feedback loop (such as amplifiers A1H and A1L mentioned above). Therefore, it is difficult to dynamically switch the gate current to optimize the switching rate of the switching control signal.

[0210] In view of the above considerations, a novel implementation scheme is proposed below, which can optimize the switching rate of the switching control signal Vg.

[0211] <Electronic Devices (First Implementation Scheme)>

[0212] Figure 12 This diagram illustrates a first embodiment of an electronic device. The electronic device A of this embodiment includes a switching element SW2, transistors M2H and M2L, resistors R1H and R1L, resistors R2H and R2L, resistors R3H and R3L, a DC power supply E, and a signal transmission device 200. Furthermore, the signal transmission device 200 has multiple external terminals (external terminals T11, T12, T13H, T13L, T14H, T14L, T15H, and T15L in this diagram) as a means of establishing connections with external devices. These components are disposed in a secondary circuit system 200s.

[0213] Switching element SW2 can be an N-channel Si-MOSFET or a SiC-MOSFET. The gate of switching element SW2 is connected to the application terminal of the switching control signal Vg. The source and back gate of switching element SW2 are connected to the application terminal of the ground voltage GND2 in the secondary circuit system 200s. Switching element SW2 is driven by the switching control signal Vg applied to its gate from the signal transmission device 200. For example, when the switching control signal Vg is high, switching element SW2 is in the on state. On the other hand, when the switching control signal Vg is low, switching element SW2 is in the off state. Switching element SW2 can be configured similarly to the first comparative example described above (…). Figure 10 ) and the second comparative example ( Figure 11 The same method is replaced by IGBT (=switching element SW1).

[0214] The signal transmission device 200 includes the aforementioned transistors M1H and M1L, and amplifiers A1H and A1L. Transistors M1H and M1L can be understood as voltage drive circuits DRV1H and DRV1L, respectively, configured to drive the voltage-driven switch control signal Vg. Furthermore, amplifiers A1H and A1L can be understood as current drive circuits DRV2H and DRV2L, respectively, configured to drive the current-driven switch control signal Vg.

[0215] Voltage drive circuit DRV1H and current drive circuit DRV2H form the upper driver 224H. The upper driver 224H raises the switch control signal Vg from low level to high level. Voltage drive circuit DRV1L and current drive circuit DRV2L form the lower driver 224L, which lowers the switch control signal Vg from high level to low level.

[0216] Note that the components already described are derived from the above. Figure 10 and Figure 11 The same numbers are used throughout to omit redundant descriptions. However, for ease of description, the gate current IgH described above can be understood as the sum of the gate current Ig1H generated by the voltage-driven circuit DRV1H and the gate current Ig2H generated by the current-driven circuit DRV2H. Similarly, the gate current IgL described above can be understood as the sum of the gate current Ig1L generated by the voltage-driven circuit DRV1L and the gate current Ig2L generated by the current-driven circuit DRV2L.

[0217] The pulse receiving circuit 223 receives pulse signals S12 and S22 (not shown) according to the pulse signals S12 and S22 (see... Figure 1 The upper driver 224H and the lower driver 224L are driven to generate a switch control signal Vg (= output pulse signal OUT).

[0218] The pulse receiving circuit 223 can function as a control circuit CTRL that arbitrarily adjusts the aforementioned reference current values ​​IrefH and IrefL. Furthermore, the pulse receiving circuit 223 can function as a control circuit CTRL that arbitrarily adjusts the time periods during which each of the voltage drive circuits DRV1H and DRV1L is set to the on state, and the time periods during which each of the current drive circuits DRV2H and DRV2L is set to the on state.

[0219] Note that the control circuit CTRL can perform the above adjustments based on register settings via SPI (Serial Peripheral Interface) communication, setting data read from internal non-volatile memory (not shown), or external analog input signals (such as PWM (Pulse Width Modulation) signals).

[0220] Furthermore, the control circuit CTRL can be set separately and independently from the pulse receiving circuit 223.

[0221] Therefore, electronic device A in this embodiment can be understood as the first comparative example mentioned above ( Figure 10 ) and the second comparative example ( Figure 11 () combination.

[0222] Specifically, in the signal transmission device 200, the on / off states of each of the voltage drive circuits DRV1H and DRV1L and the current drive circuits DRV2H and DRV2L are switched at appropriate timings, thus optimizing both on-control and off-control. A detailed description is given below with reference to the accompanying drawings.

[0223] Figure 13 This is a diagram illustrating the turn-on control of the first embodiment. In this diagram, the gate-source voltage Vgs, drain-source voltage Vds, drain-source current Ids, and gate current IgH of the switching element SW2, as well as the on / off states of the voltage drive circuit DRV1H and the current drive circuit DRV2H, are shown from top to bottom.

[0224] As shown in the figure, when the gate-source voltage Vgs of the switching element SW2 rises from a low level (=0V) to a high level (=Vdrv_on), the logic level transition period Ton_tr (=time points t1 to t5) includes four time periods T1, T2, T3 and T4.

[0225] For example, time period T1 (=time points t1 to t2) corresponds to the period from the start of charging the gate parasitic capacitance of switching element SW2 until the gate-source voltage Vgs of switching element SW2 rises to the turn-on threshold voltage Vth of switching element SW2.

[0226] For example, time period T2 (=time points t2 to t3) corresponds to the period from when the gate-source voltage Vgs of switching element SW2 exceeds the turn-on threshold voltage Vth until it rises to the mirror voltage Vm_on. From another perspective, time period T2 can be understood as the period during which the drain-source current Ids of switching element SW2 increases. Note that the drain-source voltage Vds of switching element SW2 decreases by the amount ΔVdrop during time period T2.

[0227] For example, time period T3 (=time points t3 to t4) corresponds to the period during which the gate-source voltage Vgs of switching element SW2 becomes constant due to the mirror effect (the so-called plateau region). Essentially, during time period T3, both the gate-source voltage Vgs and drain-source current Ids of switching element SW2 remain constant, while only the drain-source voltage Vds of switching element SW2 decreases. Note that during time period T3, as shown in the figure, overshoot may occur in the drain-source current Ids of switching element SW2.

[0228] For example, time period T4 (=time points t4 to t5) corresponds to the period after the gate-source voltage Vgs of switching element SW2 starts to rise again until it becomes high (=Vdrv_on). In this case, the drain-source voltage Vds of switching element SW2 decreases to the voltage value Vds_on (=Ids×Ron(SW2), where Ron(SW2) is the on-resistance of switching element SW2).

[0229] Here, the voltage drive circuit DRV1H is in the on state during some periods T1, T2, and T4 of the time period T1 to T4, and in the off state during another period T3. On the other hand, the current drive circuit DRV2H is in the on state during all periods T1 to T4.

[0230] In other words, during time periods T1 and T2 (t1 to t3) and time period T4 (t4 to t5), both the voltage drive circuit DRV1H and the current drive circuit DRV2H are in the on state. In this case, the gate current IgH has the sum of the gate currents Ig1H and Ig2H (IgH = Ig1H + Ig2H). Therefore, the rise rate of the gate-source voltage Vgs (= the switching control signal Vg) increases.

[0231] On the other hand, during time period T3 (time point t3 to t4), the voltage drive circuit DRV1H is in the off state, while the current drive circuit DRV2H is in the on state. In this case, only the gate current Ig2H flows as the gate current IgH. Therefore, the rise rate of the gate-source voltage Vgs (= switch control signal Vg) is reduced.

[0232] In this way, by using a gate driving method suitable for each of the four time periods T1 to T4, the optimal driving waveform for the switch control signal Vg can be generated. Referring to the figure, in the turn-on control of this embodiment, the gate current IgH of the switch control signal Vg (and therefore the rising transition rate of the switch control signal Vg) is dynamically switched from "large" to "small" to "large" during the logic level transition period Ton_tr.

[0233] Here, the current drive circuit DRV2H remains constantly on during time periods T1 to T4. In other words, the switching control of the gate current IgH is achieved through the on / off control of the voltage drive circuit DRV1H. Therefore, the problem of slow switching speed of the gate current Ig2H in the current drive circuit DRV2H can be solved. In particular, if the switching element SW2 is a power device that can be switched quickly (e.g., SiC-MOSFET), then the gate drive control of this implementation can be considered suitable.

[0234] Furthermore, as described above, parameters such as the amplitude of the reference current value IrefH (= gate current Ig2H) and the length (start and end) of the time period T1 to T4 can be arbitrarily adjusted based on SPI communication, non-volatile memory, or external analog input signals. For example, by adjusting the aforementioned parameters of each switching element SW2, the rising transition rate of the switching control signal Vg can be accurately set without adjusting the external resistors R1H and R2H. Therefore, output overshoot and EMI noise suppression, as well as switching losses, can be achieved.

[0235] Figure 14 This is a diagram illustrating the connection control (modification) of the first embodiment. (As described above...) Figure 13 Similarly, in this figure, the gate-source voltage Vgs, drain-source voltage Vds, drain-source current Ids, and gate current Ig of the switching element SW2H, as well as the on / off states of the voltage drive circuit DRV1H and the current drive circuit DRV2H, are shown from top to bottom.

[0236] In this variant, both the voltage drive circuit DRV1H and the current drive circuit DRV2H are in the on state during time periods T1 (= time points t1 to t2) and T4 (= time points t4 to t5). In this case, the gate current IgH has the sum of the gate currents Ig1H and Ig2H (IgH = Ig1H + Ig2H). Therefore, the rise rate of the gate-source voltage Vgs (= switching control signal Vg) increases.

[0237] On the other hand, during time periods T2 and T3 (time points t2 to t4), the voltage drive circuit DRV1H is in the off state, while the current drive circuit DRV2H is in the on state. In this case, only the gate current Ig2H flows as the gate current IgH. Therefore, the rise rate of the gate-source voltage Vgs (= the switching control signal Vg) is reduced.

[0238] In this way, the voltage drive circuit DRV1H can be in the on state during part of the time periods T1 and T4, and can be in the off state during the other time periods T2 and T3. On the other hand, the current drive circuit DRV2H is in the on state during all time periods T1 to T4.

[0239] Figure 15 This is a diagram illustrating the shutdown control of the first embodiment. In this diagram, the gate-source voltage Vgs, drain-source voltage Vds, drain-source current Ids, and gate current IgL of the switching element SW2, as well as the on / off states of the voltage drive circuit DRV1L and the current drive circuit DRV2L, are shown from top to bottom.

[0240] As shown in the figure, when the gate-source voltage Vgs of the switching element SW2 drops from a high level (=Vdrv_on) to a low level (=0V), the logic level transition period Toff_tr (=time point t6 to t10) includes four time periods T5, T6, T7 and T8.

[0241] For example, time period T5 (=time points t6 to t7) corresponds to the period from the start of discharging the gate parasitic capacitance of switching element SW2 until it decreases to the mirror voltage Vm_on. In this case, the drain-source voltage Vds of switching element SW2 remains at the voltage value Vds_on (=Ids×Ron(SW2)).

[0242] For example, time period T6 (=time points t7 to t8) corresponds to the period during which the gate-source voltage Vgs of switching element SW2 becomes constant due to the mirror effect (the so-called plateau region). Basically, during time period T6, the gate-source voltage Vgs and drain-source current Ids of switching element SW2 each remain constant, while only the drain-source voltage Vds of switching element SW2 increases.

[0243] For example, time period T7 (=time points t8 to t9) corresponds to the period after the gate-source voltage Vgs of switching element SW2 starts decreasing again until it becomes the turn-on threshold voltage Vth of switching element SW2. From another perspective, time period T7 can be understood as the period during which the drain-source current Ids of switching element SW2 decreases. Note that during time period T7, the drain-source voltage Vds of switching element SW2 may overshoot.

[0244] For example, time period T8 (=time points t9 to t10) corresponds to the period from when the gate-source voltage Vgs of the switching element SW2 becomes lower than the turn-on threshold voltage Vth until it becomes low (=0V).

[0245] Here, the voltage drive circuit DRV1L is in the on state during some periods T5, T7, and T8 within the time period T5 to T8, and in the off state during another period T6. On the other hand, the current drive circuit DRV2L is in the on state during all periods T5 to T8.

[0246] In other words, the voltage drive circuit DRV1L and the current drive circuit DRV2L are both in the on-state during time period T5 (time points t6 to t7) and during time periods T7 and T8 (time points t8 to t10). In this case, the gate current IgL has the sum of the gate currents Ig1L and Ig2L (IgL = Ig1L + Ig2L). Therefore, the rate of decrease of the gate-source voltage Vgs (= the switching control signal Vg) increases.

[0247] On the other hand, during time period T6 (=time points t7 to t8), the voltage drive circuit DRV1L is in the off state, while the current drive circuit DRV2L is in the on state. In this case, only the gate current Ig2L flows as the gate current IgL. Therefore, the rate of decrease of the gate-source voltage Vgs (=switching control signal Vg) is reduced.

[0248] In this way, by using a gate driving method suitable for each of the four time periods T5 to T8, the optimal drive waveform for the switch control signal Vg can be generated. Referring to the figure, in the turn-on control of this embodiment, the gate current IgL of the switch control signal Vg (and therefore the falling transition rate of the switch control signal Vg) dynamically switches from "large" to "small" to "large" during the logic level transition period Toff_tr.

[0249] Here, the current drive circuit DRV2L remains in the on state throughout the time period T5 to T8. In other words, the switching control of the gate current IgL is achieved through the on / off control of the voltage drive circuit DRV1L. Therefore, the problem of slow switching speed of the gate current Ig2L in the current drive circuit DRV2L can be solved. In particular, if the switching element SW2 is a power device that can be switched quickly (e.g., SiC-MOSFET), then the gate drive control of this embodiment can be said to be suitable.

[0250] Furthermore, as described above, parameters such as the amplitude of the reference current value IrefL (= gate current Ig2L) and the length (start and end) of the time period T5 to T8 can be arbitrarily adjusted based on SPI communication, non-volatile memory, or external analog input signals. For example, by adjusting the aforementioned parameters of each switching element SW2, the descent rate of the switching control signal Vg can be accurately set without adjusting the external resistors R1L and R2L. Therefore, output overshoot and EMI noise suppression, as well as switching losses, can be achieved.

[0251] Note that, although not shown again, the change is consistent with the above-mentioned conduction control ( Figure 14 Similarly, the voltage drive circuit DRV1L can be in the on state during part of the time periods T5 and T8, and can be in the off state during the other time periods T6 and T7. On the other hand, the current drive circuit DRV2L is in the on state during all time periods T5 to T8.

[0252] <Electronic Devices (Second Implementation Scheme)>

[0253] Figure 16 This is a diagram illustrating a second embodiment of the electronic device. In the electronic device A of this embodiment, although based on the first embodiment described above (… Figure 12 However, the configuration of the signal transmission device 200 and external components was modified.

[0254] Referring to this figure, the signal transmission device 200 includes transistors M1Ha and M1Hb (e.g., each a P-channel MOSFET) instead of transistor M1H. Furthermore, the signal transmission device 200 includes external terminals T13Ha and T13Hb instead of external terminal T13H.

[0255] The source and back gate of transistor M1Ha are both connected to external terminal T11. The drain of transistor M1Ha is connected to external terminal T13Ha. Resistor R1Ha is externally connected between external terminal T13Ha and the gate of switching element SW2. Transistor M1Ha connected as described above can be understood as voltage drive circuit DRV1Ha, which is configured to drive the switching control signal Vg via resistor R1Ha.

[0256] The source and back gate of transistor M1Hb are both connected to external terminal T11. The drain of transistor M1Hb is connected to external terminal T13Hb. Resistor R1Hb is externally connected between external terminal T13Hb and the gate of switching element SW2. Transistor M1Hb connected as described above can be understood as voltage drive circuit DRV1Hb, which is configured to drive the switch control signal Vg via resistor R1Hb, which is different from resistor R1Ha.

[0257] Note that the gate current Ig1H mentioned above is divided into two systems: the gate current Ig1Ha flowing in transistor M1Ha and the gate current Ig1Hb flowing in transistor M1Hb.

[0258] Furthermore, the signal transmission device 200 includes transistors M1La and M1Lb (e.g., N-channel MOSFETs) instead of transistor M1L. Additionally, the signal transmission device 200 includes external terminals T13La and T13Lb instead of external terminal T13L.

[0259] The source and back gate of transistor M1La are both connected to external terminal T12. The drain of transistor M1La is connected to external terminal T13La. Resistor R1La is externally connected between external terminal T13La and the gate of switching element SW2. Transistor M1La connected as described above can be understood as a voltage drive circuit DRV1La, which is configured to drive the switching control signal Vg via resistor R1La.

[0260] The source and back gate of transistor M1Lb are both connected to external terminal T12. The drain of transistor M1Lb is connected to external terminal T13Lb. Resistor R1Lb is externally connected between external terminal T13Lb and the gate of switching element SW2. The transistor M1Lb connected as described above can be understood as a voltage drive circuit DRV1Lb, which is configured to drive the switching control signal Vg via a resistor R1Lb, which is different from resistor R1La.

[0261] Note that the gate current Ig1L mentioned above is divided into two systems: the gate current Ig1La flowing in transistor M1La and the gate current Ig1Lb flowing in transistor M1Lb.

[0262] Figure 17 This is a diagram illustrating the turn-on control of the second embodiment. In this diagram, the gate-source voltage Vgs, drain-source voltage Vds, drain-source current Ids, and gate current IgH of the switching element SW2, as well as the on / off states of the voltage drive circuits DRV1Ha and DRV1Hb and the current drive circuit DRV2H, are shown from top to bottom.

[0263] Here, the first implementation scheme is described ( Figure 13 The switching control of the voltage drive circuit DRV1Ha occurs at different points. Referring to the diagram, the voltage drive circuit DRV1Ha is in the on state during periods T1 and T2 of time intervals T1 to T4, and in the off state during other periods T3 and T4. Similarly, the voltage drive circuit DRV1Hb is in the on state during a portion of period T4 of time intervals T1 to T4, and in the off state during other periods T1 to T3. On the other hand, the current drive circuit DRV2H is in the on state during all periods T1 to T4.

[0264] In other words, during time periods T1 and T2 (=time points t1 to t3), the voltage drive circuit DRV1Ha and the current drive circuit DRV2H are in the on state, while the voltage drive circuit DRV1Hb is in the off state. In this case, the gate current IgH has the sum of the gate currents Ig1Ha and Ig2H (IgH = Ig1Ha + Ig2H). Therefore, the rise rate of the gate-source voltage Vgs (=the switching control signal Vg) is set to the set value RSR1.

[0265] On the other hand, during time period T3 (=time point t3 to t4), both voltage drive circuits DRV1Ha and DRV1Hb are in the off state, while the current drive circuit DRV2H is in the on state. In this case, only the gate current Ig2H flows as the gate current IgH. Therefore, the rise rate of the gate-source voltage Vgs (=switching control signal Vg) decreases from the set value RSR1 to the set value RSR2.

[0266] During time period T4 (=time points t4 to t5), the voltage drive circuit DRV1Hb and the current drive circuit DRV2H are in the on state, while the voltage drive circuit DRV1Ha is in the off state. In this case, the gate current IgH has the sum of the gate currents Ig1Hb and Ig2H (IgH = Ig1Hb + Ig2H). Therefore, the rise rate of the gate-source voltage Vgs (=the switching control signal Vg) increases from the set value RSR2 to the set value RSR3 (≠RSR1 is possible).

[0267] In this manner, when multiple voltage drive circuits DRV1Ha and DRV1Hb are provided, compared with the above-described first embodiment ( Figure 12 ), the drive waveform of the switching control signal Vg can be finely optimized. Further, the same is true that during the logic level conversion period Ton_tr, the gate current IgH of the switching control signal Vg (and thus, the rising conversion rate of the switching control signal Vg) dynamically switches from "large" to "small" to "large".

[0268] Note that although not shown again, in the same manner as the above-described modification of the on control ( Figure 14 ), the voltage drive circuit DRV1Ha can be in the on state during a partial period T1 of the periods T1 to T4, and can be in the off state during the other periods T2 to T4.

[0269] Further, an example where Ig1Ha > Ig1Hb holds is shown in this figure, but conversely, it is possible that Ig1Ha < Ig1Hb holds.

[0270] Figure 18 FIG. is a diagram showing the off control of the second embodiment. In this figure, the gate-source voltage Vgs, drain-source voltage Vds, drain-source current Ids, and gate current IgH of the switching element SW2, and the on / off states of the voltage drive circuits DRV1La and DRV1Lb and the current drive circuit DRV2H are shown from top to bottom.

[0271] Here, the points different from the off control of the first embodiment ( Figure 15 are described. Referring to this figure, the voltage drive circuit DRV1La is in the on state during partial periods T7 and T8 of the periods T5 to T8, and is in the off state during the other periods T5 and T6. Further, the voltage drive circuit DRV1Lb is in the on state during a partial period T5 of the periods T5 to T8, and is in the off state during the other periods T6 to T8. On the other hand, the current drive circuit DRV2L is in the on state during all periods T5 to T8.

[0272] In other words, during the period T5 (= time points t6 to t7), the voltage drive circuit DRV1Lb and the current drive circuit DRV2L are in the on state, and the voltage drive circuit DRV1La is in the off state. In this case, the gate current IgL is the sum current value of the gate currents Ig1Lb and Ig2L (IgL = Ig1Lb + Ig2L). Therefore, the falling conversion rate of the gate-source voltage Vgs (= switching control signal Vg) is set to a set value FSR1.

[0273] On the other hand, during period T6 (= time points t7 to t8), both the voltage drive circuits DRV1La and DRV1Lb are in the off state, and the current drive circuit DRV2L is in the on state. In this case, only the gate current Ig2L flows as the gate current IgL. Therefore, the falling transition rate of the gate-source voltage Vgs (= switching control signal Vg) decreases from the set value FSR1 to the set value FSR2.

[0274] During periods T7 and T8 (= time points t8 to t10), the voltage drive circuit DRV1La and the current drive circuit DRV2L are in the on state, and the voltage drive circuit DRV1Lb is in the off state. In this case, the gate current IgL is the sum current value of the gate currents Ig1La and Ig2L (IgL = Ig1La + Ig2L). Therefore, the falling transition rate of the gate-source voltage Vgs (= switching control signal Vg) increases from the set value FSR2 to the set value FSR3 (it is possible that FSR3 ≠ FSR1).

[0275] In this way, when multiple voltage drive circuits DRV1La and DRV1Lb are provided, compared with the above first embodiment ( Figure 12 ), the drive waveform of the switching control signal Vg can be finely optimized. In addition, during the logic level transition period Toff_tr, the gate current IgL of the switching control signal Vg (and thus the falling transition rate of the switching control signal Vg) dynamically switches from "large" to "small" to "large" in the same manner.

[0276] Note that although not shown again, in the same manner as the above-described modification example of the on control ( Figure 14 ), the voltage drive circuit DRV1La can be in the on state during a partial period T8 in periods T5 to T8, and can be in the off state during the other periods T5 to T7.

[0277] In addition, in this figure, an example where Ig1La > Ig1Lb holds is shown, but conversely, it is possible that Ig1La < Ig1Lb holds.

[0278] <Applied to a vehicle>

[0279] Figure 19 is a view showing an external view of a vehicle. The vehicle B of this configuration example is equipped with various electronic devices that are supplied with power from a battery for operation.

[0280] In addition to engine vehicles, vehicle B also includes electric vehicles (xEVs, such as BEVs (battery electric vehicles), HEVs (hybrid electric vehicles), PHEVs / PHVs (plug-in hybrid electric vehicles) or FCEVs / FCVs (fuel cell electric vehicles)).

[0281] Note that the aforementioned signal transmission device 200 can be integrated into any electronic device built into vehicle B.

[0282] <Additional Notes>

[0283] According to this disclosure, the switching rate of the switching control signal can be optimized. Additional notes regarding this disclosure are given below.

[0284] [Additional Note 1]

[0285] A semiconductor device (200) includes:

[0286] At least one voltage drive circuit (DRV1H, DRV1Ha, DRV1Hb, DRV1L, DRV1La, DRV1Lb) is configured to voltage drive a switch control signal (Vg); and

[0287] The current drive circuits (DRV2H, DRV2L) are configured to drive the switch control signal (Vg) with current, wherein...

[0288] The at least one voltage drive circuit (DRV1H, DRV1L) is in an on state during a portion of the multiple time periods (T1 to T4, T5 to T8) included in the logic level transition period (Ton_tr, Toff_tr) of the switch control signal (Vg), and is in an off state during other time periods (e.g., T3, T6), and the current drive circuit (DRV2H, DRV2L) is in an on state during all of the multiple time periods (T1 to T4, T5 to T8).

[0289] [Additional Note 2]

[0290] According to the semiconductor device (200) described in Appendix 1, wherein

[0291] The at least one voltage drive circuit (DRV1Ha, DRV1Hb, DRV1La, DRV1Lb) includes: a first voltage drive circuit (DRV1Ha, DRV1La) configured to be connected to the application terminal of the switch control signal (Vg) via a first resistor (R1Ha, R1La); and a second voltage drive circuit (DRV1Hb, DRV1Lb) configured to be connected to the application terminal of the switch control signal (Vg) via a second resistor (R1Hb, R1Lb) different from the first resistor (R1Ha, R1La).

[0292] The logic level transition periods (Ton_tr, Toff_tr) include a first period (e.g., T1+T2, T7+T8), during which the first voltage drive circuit (DRV1Ha, DRV1La) and the current drive circuit (DRV2H, DRV2L) are in the on state, while the second voltage drive circuit (DRV1Hb, DRV1Lb) is in the off state; a second period (T3, T6), during which the current drive circuit (DRV2H, DRV2L) is in the on state, while the first voltage drive circuit (DRV1Ha, DRV1La) and the second voltage drive circuit (DRV1Hb, DRV1Lb) are in the off state; and a third period (T4, T5), during which the second voltage drive circuit (DRV1Hb, DRV1Lb) and the current drive circuit (DRV2H, DRV2L) are in the on state, while the first voltage drive circuit (DRV1Ha, DRV1La) is in the off state.

[0293] [Additional Note 3]

[0294] According to the semiconductor device (200) described in Appendix 1 or 2, the current drive circuit (DRV2H, DRV2L) performs output feedback control such that the current (Ig2H, Ig2L) flowing in the application terminal of the switch control signal (Vg) has the same value as the reference current value (IrefH, IrefL).

[0295] [Additional Note 4]

[0296] According to the semiconductor device (200) in Appendix 3, it also includes a control circuit (223, CTRL) configured to arbitrarily adjust the reference current value (IrefH, IrefL).

[0297] [Additional Note 5]

[0298] The semiconductor device (200) according to any one of the appended notes 1 to 4 further includes a control circuit (223, CTRL) configured to arbitrarily adjust the period during which each of at least one voltage drive circuit (DRV1H, DRV1Ha, DRV1Hb, DRV1L, DRV1La, DRV1Lb) and current drive circuit (DRV2H, DRV2L) is in the on state.

[0299] [Additional Note 6]

[0300] According to any one of the appended notes 1 to 5, the semiconductor device (200) wherein at least one voltage driving circuit (DRV1H, DRV1Ha, DRV1Hb, DRV1L, DRV1La, DRV1Lb) and current driving circuit (DRV2H, DRV2L) form at least one of an upper driver (224H) configured to raise the switch control signal (Vg) from a low level to a high level and a lower driver (224L) configured to lower the switch control signal (Vg) from a high level to a low level.

[0301] [Additional Note 7]

[0302] The semiconductor device (200) according to any one of the appendix notes 1 to 6, wherein

[0303] The semiconductor device (200) is a signal transmission device configured to transmit the switch control signal (Vg) from the primary circuit system (200p) to the secondary circuit system (200s), while maintaining insulation between the primary circuit system (200p) and the secondary circuit system (200s).

[0304] The at least one voltage drive circuit (DRV1H, DRV1Ha, DRV1Hb, DRV1L, DRV1La, DRV1Lb) and the current drive circuit (DRV2H, DRV2L) are each disposed in the secondary circuit system (200s).

[0305] [Additional Note 8]

[0306] An electronic device (A) includes:

[0307] Semiconductor device (200) according to any one of the appendix 1 to 7; and

[0308] Switching elements (SW1, SW2) are configured to be driven by the semiconductor device (200).

[0309] [Additional Note 9]

[0310] The electronic device (A) described in Additional Note 8, wherein the switching elements (SW1, SW2) are IGBTs, Si-MOSFETs, or SiC-MOSFETs.

[0311] [Additional Note 10]

[0312] A vehicle (B) equipped with electronic equipment (A) according to appendix 8 or 9.

[0313] <Other>

[0314] Note that, in addition to the embodiments described above, various technical features disclosed in this specification can be modified in various ways within the scope of this invention without departing from its spirit. In other words, the embodiments are merely examples of each aspect and should not be construed as limiting. Furthermore, the technical scope of this disclosure should be defined by the claims and should be understood to include all modifications within the meaning and scope equivalent to the claims.

[0315] Symbol Explanation

[0316] 5 Semiconductor Devices

[0317] 11, 11A~11F Low-potential terminals

[0318] 12, 12A~12F High-potential terminals

[0319] 21. Transformers 21A~21D

[0320] 22 Low-potential coil (primary side coil)

[0321] 23 High-potential coil (secondary coil)

[0322] 24 First inner end

[0323] 25 First lateral end

[0324] 26 First spiral section

[0325] 27 Second inner end

[0326] 28 Second lateral end

[0327] 29 Second spiral section

[0328] 31 First low-potential wiring

[0329] 32 Second Low Potential Wiring

[0330] 33 First High-Potential Wiring

[0331] 34 Second High Potential Wiring

[0332] 41 Semiconductor Chips

[0333] 42 First Main Face

[0334] 43 Second Main Face

[0335] 44A~44D chip sidewall

[0336] 45 First functional device

[0337] 51 Insulation layer

[0338] 52 Insulation Main Surface

[0339] 53A~53D Insulating sidewalls

[0340] 55 Bottom insulation layer

[0341] 56. Topmost insulating layer

[0342] 57 interlayer insulation

[0343] 58 First Insulation Layer

[0344] 59 Second Insulation Layer

[0345] 60 Secondary functional devices

[0346] 61 Sealed conductor

[0347] 62 Device Area

[0348] 63 Outer region

[0349] 64 Sealed plug conductor

[0350] 65 Sealed through-hole conductor

[0351] 66 First inner region

[0352] 67 Second inner region

[0353] 71 Through-wiring

[0354] 72 Low-potential connection wiring

[0355] 73 Lead-out wiring

[0356] 74 First connecting plug electrode

[0357] 75 Second connecting plug electrode

[0358] 76 Pad Plug Electrode

[0359] 77 Substrate plug electrode

[0360] 78 First Electrode Layer

[0361] 79 Second electrode layer

[0362] 80 Wiring plug electrode

[0363] 81 High-potential connection wiring

[0364] 82 Pad Plug Electrode

[0365] 85. Dummy Pattern

[0366] 86 High-potential dummy pattern

[0367] 87 First High Potential Dummy Pattern

[0368] 88 Second High Potential Dummy Pattern

[0369] 89 First District

[0370] 90 Second Zone

[0371] 91 Third Region

[0372] 92 First connecting part

[0373] 93 First Pattern

[0374] 94 Second Pattern

[0375] 95 Third Pattern

[0376] 96 First outer weekly line

[0377] 97 Second outer weekly line

[0378] 98 First median line

[0379] 99 First connecting line

[0380] 100 slits

[0381] 130 Separation Structure

[0382] 140 Inorganic Insulation Layer

[0383] 141 First Inorganic Insulation Layer

[0384] 142 Second Inorganic Insulation Layer

[0385] 143 Low-potential pad opening

[0386] 144 High-potential pad opening

[0387] 145 Organic Insulation Layer

[0388] 146 Part One

[0389] 147 Part Two

[0390] 148 Low-potential terminal opening

[0391] 149 High-potential terminal opening

[0392] 200 Signal Transmission Device

[0393] 200p primary circuit system

[0394] 200s secondary circuit system

[0395] 210 Controller Chip (First Chip)

[0396] 211 Pulse Transmission Circuit (Pulse Generator)

[0397] Buffers 212 and 213

[0398] 220 Driver Chip (Second Chip)

[0399] Buffers 221 and 222

[0400] 223 Pulse Receiving Circuit (RS Flip-Flop)

[0401] 224 drives

[0402] 224H Upper Driver

[0403] 224L Lower Drive

[0404] 230 Transformer Chip (Third Chip)

[0405] 230a First wiring layer (lower layer)

[0406] 230b Second wiring layer (upper layer)

[0407] Transformers 231 and 232

[0408] 231p, 232p primary side coil

[0409] 231s, 232s secondary coils

[0410] 300 Transformer Chip

[0411] 301 First Transformer

[0412] 302 Second Transformer

[0413] 303 Third Transformer

[0414] 304 Fourth Transformer

[0415] 305 First Protection Ring

[0416] 306 Second Protective Ring

[0417] pads a1~a8 (equivalent to pads for the first current supply)

[0418] pads b1~b8 (equivalent to pads used for the first voltage measurement)

[0419] C1~C4 pads (equivalent to pads for the second current supply)

[0420] d1~d4 pads (equivalent to the pads used for second voltage measurement)

[0421] e1, e2 pads

[0422] A electronic device

[0423] A1H and A1L amplifiers

[0424] Vehicle B

[0425] CTRL control circuit

[0426] DRV1H, DRV1Ha, DRV1Hb, DRV1L, DRV1La, DRV1Lb Voltage Drive Circuit

[0427] DRV2H and DRV2L current drive circuits

[0428] E DC power supply

[0429] L1p, L2p primary side coils

[0430] L1s, L2s, L3s, L4s secondary coils

[0431] Transistors M1H, M1Ha, M1Hb, M1L, M1La, M1Lb, M2H, M2L

[0432] Resistors R1H, R1Ha, R1Hb, R1L, R1La, R1Lb, R2H, R2L, R3H, R3L

[0433] SW1 and SW2 switching elements

[0434] T11, T12, T13H, T13Ha, T13Hb, T13L, T13La, T13Lb, T14H, T14L, T15H, T15L external terminals

[0435] T21, T22, T23, T24, T25, T26 external terminals

[0436] X First Direction

[0437] X21, X22, X23 internal terminals

[0438] Y Second Direction

[0439] Y21, Y22, Y23 wiring

[0440] Z-normal direction

[0441] Through holes Z21, Z22, and Z23.

Claims

1. A semiconductor device, comprising: At least one voltage drive circuit is configured to voltage drive a switch control signal; as well as A current drive circuit is configured to drive the switch control signal with current, wherein... The at least one voltage drive circuit is in an on state during a portion of the multiple time periods included in the logic level transition period of the switch control signal, and in an off state during other time periods. The current drive circuit is in the on state during all of the plurality of time periods.

2. The semiconductor device according to claim 1, wherein The at least one voltage driving circuit includes: A first voltage drive circuit is configured to be connected to the application terminal of the switch control signal via a first resistor; And, a second voltage drive circuit is configured to be connected to the application terminal of the switch control signal via a second resistor different from the first resistor, and The logic level transition periods include: a first period during which the first voltage driving circuit and the current driving circuit are in an on state, while the second voltage driving circuit is in an off state; a second period during which the current driving circuit is in an on state, while the first voltage driving circuit and the second voltage driving circuit are in an off state; and a third period during which the second voltage driving circuit and the current driving circuit are in an on state, while the first voltage driving circuit is in an off state.

3. The semiconductor device according to claim 1 or 2, wherein the current drive circuit performs output feedback control such that the current flowing in the application terminal of the switch control signal has the same value as the reference current value.

4. The semiconductor device of claim 3, further comprising a control circuit configured to arbitrarily adjust the reference current value.

5. The semiconductor device according to any one of claims 1 to 4, further comprising a control circuit configured to arbitrarily adjust the time period during which each of the at least one voltage drive circuit and the current drive circuit is in an on state.

6. The semiconductor device according to any one of claims 1 to 5, wherein the at least one voltage driving circuit and the current driving circuit form at least one of an upper driver configured to raise the switch control signal from a low level to a high level and a lower driver configured to lower the switch control signal from a high level to a low level.

7. The semiconductor device according to any one of claims 1 to 6, wherein The semiconductor device is a signal transmission device configured to transmit the switching control signal from a primary circuit system to a secondary circuit system, while maintaining insulation between the primary and secondary circuit systems. The at least one voltage driving circuit and the current driving circuit are each disposed in the secondary circuit system.

8. An electronic device, comprising: The semiconductor device according to any one of claims 1 to 7; as well as A switching element is configured to be driven by the semiconductor device.

9. The electronic device according to claim 8, wherein, The switching element is an IGBT, a Si-MOSFET, or a SiC-MOSFET.

10. A type of vehicle, Equipped with the electronic device according to claim 8 or 9.

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