Detection method and test system

Abstract

This application discloses a detection method and testing system, belonging to the field of chip testing technology. The detection method includes: providing a wafer, the wafer including multiple semiconductor device structures; during the wafer chip testing stage, applying a scanning voltage between the gate pad and drain pad of the semiconductor device structure and simultaneously measuring the capacitance to obtain a voltage-capacitance curve between the gate pad and drain pad; and determining whether each semiconductor device structure has gate oxide defects based on the voltage-capacitance curve. This allows for the early screening of semiconductor device structures with gate oxide defects with high detection accuracy; furthermore, repeated pressure application can utilize the accumulation effect to make the detection results more significant.

Description

Technical Field

[0001] This application belongs to the field of chip testing technology, and in particular relates to a testing method and testing system. Background Technology

[0002] In the manufacturing process of SiC (silicon carbide) power devices (such as SiC MOSFETs), gate oxide defects (such as interface states, oxide layer defects, impurities, or interface unevenness) can significantly affect key parameters such as device reliability, leakage current, and threshold voltage stability. However, current methods for screening gate oxide defects are not very accurate. Summary of the Invention

[0003] This invention aims to at least solve one of the technical problems existing in the prior art. To this end, this invention proposes a detection method and testing system that can screen out semiconductor device structures with gate oxide defects in advance with high detection accuracy.

[0004] Firstly, this application provides a detection method, including: Provide a wafer, the wafer comprising multiple semiconductor device structures; During the wafer chip testing phase, a scanning voltage is applied between the gate pads and drain pads of each semiconductor device structure and the capacitance is measured simultaneously to obtain the voltage-capacitance curve between the gate pads and drain pads. The presence of gate oxide defects in the structure of each semiconductor device is determined based on the voltage-capacitance curve.

[0005] According to one embodiment of this application, the scanning voltage applied to the gate pad during one scanning cycle changes from a first voltage to a second voltage, and then changes from the second voltage back to the first voltage, where the first voltage is a negative voltage and the second voltage is a positive voltage.

[0006] According to one embodiment of this application, the application period of the scanning voltage includes multiple scanning cycles, and the voltage-capacitance curve is determined based on the scanning result of the last scanning cycle during the application period.

[0007] According to one embodiment of this application, the voltage-capacitance curve includes two capacitance measurement results corresponding to a first voltage. Determining whether gate oxide defects exist in the structure of each semiconductor device based on the voltage-capacitance curve includes: Determine the capacitance difference between two capacitance measurements corresponding to the first voltage applied to the gate pad; When the capacitance difference is greater than or equal to a threshold, it is determined that there is a gate oxide defect in the semiconductor device structure; When the capacitance difference is less than the threshold, it is determined that there are no gate oxide defects in the semiconductor device structure.

[0008] According to one embodiment of this application, the first voltage is greater than or equal to -25V and less than or equal to -15V, the second voltage is greater than or equal to 15V and less than or equal to 25V, and the number of scan cycles is greater than or equal to 10.

[0009] According to one embodiment of this application, the signal frequency of the scanning voltage is greater than or equal to 100kHz.

[0010] According to one embodiment of this application, the drain pad of the semiconductor device structure is located on a first side of the wafer, and the gate pad of the semiconductor device structure is located on a second side of the wafer, with the first side being opposite to the second side. The scan voltage is applied in the following manner: A probe system is provided, comprising a first probe and a second probe disposed on both sides of a wafer; Connect the first probe to the drain pad of the semiconductor device structure; Connect the second probe to the gate pad of the semiconductor device structure; A scanning voltage is applied between the first and second probes using a probe system.

[0011] According to one embodiment of this application, connecting a first probe to the drain pad of a semiconductor device structure includes: The first side of the wafer is placed on the chuck so that the drain pads of each semiconductor device structure are in electrical contact with the chuck. Connect the chuck to the first probe electrically.

[0012] According to one embodiment of this application, the semiconductor device structure includes an epitaxial layer, a gate electrode layer, and a gate oxide layer. The epitaxial layer includes a channel region and a source region. The drain pad is located on a first side of the wafer and is arranged in contact with the epitaxial layer. The gate oxide layer is located on a second side of the wafer and is arranged in contact with the channel region and the source region in the epitaxial layer. The gate electrode layer is located on the side of the gate oxide layer away from the epitaxial layer. The gate pad is electrically connected to the gate electrode layer. The contact area between the gate oxide layer and the channel region is larger than the contact area between the gate oxide layer and the source region.

[0013] Secondly, this application provides a testing system, which includes a probe system and a wafer, the wafer including multiple semiconductor device structures, and the probe system configured to apply the aforementioned detection method.

[0014] According to the detection method and testing system of this application, CV testing is performed on each semiconductor device structure on the wafer during the wafer CP testing stage, and scanning voltage is applied to the gate and drain to screen out semiconductor device structures with gate oxide defects in advance, and the detection accuracy is high; in addition, the scanning voltage can be repeatedly applied to the semiconductor device structure, and the result of the last one is taken, and the detection result is more significant by utilizing the accumulation effect.

[0015] Additional aspects and advantages of this application will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of this application. Attached Figure Description

[0016] The above and / or additional aspects and advantages of the present invention will become apparent and readily understood from the description of the embodiments taken in conjunction with the following drawings, in which: Figure 1 This is a schematic diagram of the structure of the SiC-MOSFET provided in the embodiments of this application; Figure 2 This is a schematic flowchart of the detection method provided in the embodiments of this application; Figure 3 This is one of the schematic diagrams of voltage-capacitance curves provided in the embodiments of this application; Figure 4 This is a second schematic diagram of the voltage-capacitance curve provided in the embodiments of this application; Figure 5 This is a schematic diagram of the semiconductor device structure and probe system provided in the embodiments of this application.

[0017] Figure label: Substrate 10, drain layer 20, epitaxial layer 30, source region 40, P-type region 41, P+ region 42, N+ region 43, gate electrode layer 50, gate oxide layer 51, gate metal layer 52, first probe 61, second probe 62, third probe 63. Detailed Implementation

[0018] The embodiments of this application are described in detail below. Examples of these embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain this application, and should not be construed as limiting this application.

[0019] It should be understood that when a component or layer is referred to as being "on," "adjacent to," "connected to," or "coupled to" other components or layers, it may be directly on, adjacent to, connected to, or coupled to other components or layers, or there may be intervening components or layers. Conversely, when a component is referred to as being "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other components or layers, there are no intervening components or layers.

[0020] In the description, the terms "first," "second," etc., are used to distinguish similar objects, not to describe a specific order or sequence. It should be understood that such numerical descriptors can be interchanged where appropriate so that embodiments of this application can be implemented in orders other than those illustrated or described herein, and the objects distinguished by "first," "second," etc., are generally of the same class, not limited in number; for example, a first object can be one or more. Furthermore, in the specification and claims, "and / or" indicates at least one of the connected objects, and the character " / " generally indicates that the preceding and following objects are in an "or" relationship.

[0021] Furthermore, the use of terms such as "one embodiment," "some embodiments," "illustrative embodiment," "example," "specific example," or "some examples," etc., indicates that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of this application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0022] Reference Figure 1 , Figure 1 This is a schematic diagram of the structure of a SiC-MOSFET provided in an embodiment of this application. One embodiment of this application proposes a semiconductor device structure, which can be a silicon carbide-metal-Oxide-Semiconductor field-effect transistor (SIC-MOSFET).

[0023] In some embodiments, a SiC-MOSFET may include a substrate 10, a drain layer 20, an epitaxial layer 30, a source region 40, and a gate electrode layer 50. The drain layer 20 is located below the substrate 10, the epitaxial layer 30 is located above the substrate 10, the source region 40 may be formed by doping the epitaxial layer 30, and the gate electrode layer 50 is located above the epitaxial layer 30.

[0024] As an example, the substrate 10 and the epitaxial layer 30 can be formed by processes such as doping or growing silicon carbide. The substrate 10 can be N+ type, and the epitaxial layer 30 can be N type. The epitaxial layer 30 can be doped to form P-type regions 41, P+ regions 42, and N+ regions 43 to form source regions 40. A channel region 31 is formed between the two P-type regions 41, and the gate electrode layer 50 covers at least a portion of the channel region 31 and at least a portion of the two source regions 40.

[0025] The gate electrode layer 50 may include a gate oxide layer 51 and a gate metal layer 52. The gate oxide layer 51 at least partially covers the channel region 31 and at least partially covers portions of the two source regions 40. The gate metal layer 52 is located above the gate oxide layer 51. A source metal may be disposed above the source regions 40 for transmitting source current. The drain layer 20, the gate metal layer 52, and the source metal may all be made of metals such as silver or copper, depending on the requirements.

[0026] It should be noted that the detection method in this application embodiment can be applied to, for example, Figure 1 The SiC-MOSFET structure shown is, of course, not limited to, that... Figure 1 The structure shown can be used as long as it meets the application conditions of the detection method in the embodiments of this application. The following uses... Figure 1 The SiC-MOSFET structure shown is for illustrating the detection method of the embodiments of this application.

[0027] Reference Figure 2 , Figure 2 This is a schematic flowchart of the detection method provided in an embodiment of this application. In some embodiments, the detection method may include steps 10, 20, and 30.

[0028] Step 10: Provide a wafer, the wafer comprising multiple semiconductor device structures; Step 20: During the wafer chip testing phase, apply a scanning voltage between the gate and drain pads of each semiconductor device structure and simultaneously measure the capacitance to obtain a voltage-capacitance curve. Step 30: Determine whether there are gate oxide defects in the structure of each semiconductor device based on the voltage-capacitance curve.

[0029] In this embodiment, the wafer can be formed from a substrate material such as SiC, and multiple semiconductor device structures can be formed on it using semiconductor processes. These multiple semiconductor device structures on the wafer need to be diced into multiple independent semiconductor device structures in subsequent processes.

[0030] Before wafers are diced, they undergo a wafer probing or wafersort stage. This stage is the first electrical and performance test performed on each individual chip structure on the wafer after wafer manufacturing is completed and before packaging.

[0031] As an example, the wafer chip testing phase can be completed collaboratively using a tester, probe cards, and probe stations. The tester is responsible for generating the various signals (inputs) required for testing the die and receiving the signals returned by the die (outputs). The probe card connects the wafer and the tester; it consists of numerous extremely fine probes arranged to correspond to the die's pads. The probe station carries the wafer and precisely moves and positions it, accurately moving a specific die on the wafer beneath the probe card. Then, the wafer is raised or the probe card is lowered, allowing the probes to firmly anchor onto the die's pads, forming an electrical connection.

[0032] In this embodiment, CV (capacitance-voltage) testing is used to test the structure of each semiconductor device to detect gate oxide defects in the semiconductor device structure. (Refer to...) Figure 1 Gate oxide defects may include structural incompleteness or contamination within the gate oxide layer 51 itself; or gate oxide defects may also include interface defects between the gate oxide layer 51 and the epitaxial layer 30, such as interface state abnormalities and interface unevenness.

[0033] In the semiconductor device structure, the gate pad is electrically coupled to the gate electrode layer 50, and the drain pad is electrically coupled to the drain layer 20. Applying a scan voltage between the gate pad and the drain pad is equivalent to applying a scan voltage between the gate electrode layer 50 and the drain layer 20.

[0034] In CV testing, the testing of the gate and drain pads of a semiconductor device structure mainly targets the gate oxide portion and interface corresponding to region B, while the testing of the gate and source of a semiconductor device structure mainly targets the gate oxide portion and interface corresponding to region A.

[0035] This implementation performs CV testing on each semiconductor device structure on the wafer during the wafer chip testing stage. On the one hand, this can reduce the interference of subsequent packaging structures on CV testing. On the other hand, it can also screen semiconductor device structures with poor gate oxide quality in advance, reduce unnecessary packaging, and lower production costs.

[0036] In step 30, the actual measured voltage-capacitance curve can be compared with the ideal voltage-capacitance curve to determine whether there are gate oxide defects in the semiconductor device structure. The ideal voltage-capacitance curve refers to the voltage-capacitance curve of a semiconductor device structure with theoretical design parameters and gate oxide quality meeting requirements under CV testing.

[0037] Ideal voltage-capacitance curves can be obtained through simulation testing, or by performing CV tests on multiple qualified semiconductor device structures and then statistically calculating the voltage-capacitance curves. Alternatively, other methods can also be used to obtain these curves.

[0038] Reference Figure 3 , Figure 3 This is a schematic diagram of the voltage-capacitance curve provided in an embodiment of this application. As an example, the ideal voltage-capacitance curve may be as follows: Figure 3 As shown. The scanning voltage application process includes both the voltage ramp-up direction (as shown by curve ①) and the voltage drop direction (as shown by curve ②). In an ideal voltage-capacitance curve, curves ① and ② coincide, indicating that there is no flat band shift on the voltage axis and no hysteresis window.

[0039] As an example, comparing the actual measured voltage-capacitance curve with the ideal voltage-capacitance curve allows us to assess the degree of overlap between the two curves. The degree of overlap can be determined based on the distribution of the differences between the corresponding capacitance values ​​in the two curves at various voltages. If the degree of overlap is greater than or equal to the threshold, it can be determined that the SiC-MOSFET corresponding to the actual measured voltage-capacitance curve has a gate oxide defect; conversely, if the difference is less than the threshold, it can be determined that the SiC-MOSFET corresponding to the actual measured voltage-capacitance curve does not have a gate oxide defect.

[0040] As another example, comparing the actual measured voltage-capacitance curve with the ideal voltage-capacitance curve can primarily compare the capacitance values ​​at the corresponding voltages. For instance, if the difference between the capacitance value in the actual measured voltage-capacitance curve and the capacitance value in the ideal voltage-capacitance curve at a certain voltage is greater than or equal to a threshold, it can be determined that the SiC-MOSFET corresponding to the actual measured voltage-capacitance curve has a gate oxide defect; conversely, if the difference is less than the threshold, it can be determined that the SiC-MOSFET corresponding to the actual measured voltage-capacitance curve does not have a gate oxide defect.

[0041] According to the detection method and testing system of this application, CV testing is performed on the semiconductor device structures on the wafer during the wafer CP testing stage, and scanning voltage is applied to the gate and drain to screen out the chips with gate oxide defects in advance, and the detection accuracy is high.

[0042] In some embodiments, the contact interface area between the gate oxide layer 51 and the channel region in the semiconductor device structure is greater than the contact interface area between the gate oxide layer 51 and the source region 40.

[0043] The contact interface area between the gate oxide layer 51 and the channel region refers to the contact interface area corresponding to region A, and the contact interface area between the gate oxide layer 51 and the source region 40 refers to the contact interface area corresponding to region B. Since the contact interface area corresponding to region A is larger than that corresponding to region B, CV testing based on the gate and drain of the semiconductor device structure is more sensitive to gate oxide defects than CV testing based on the gate and drain of the semiconductor device structure. This is beneficial for improving detection sensitivity and effectively screening out semiconductor device structures with poor gate oxide quality.

[0044] In some embodiments, the application period of the scanning voltage includes multiple scanning cycles, and the voltage-capacitance curve is determined based on the scanning result of the last scanning cycle during the application period.

[0045] When applying a scanning voltage to each semiconductor device structure, the scanning voltage is periodically and repeatedly applied between the gate electrode layer 50 and the drain layer 20 of each semiconductor device structure. By repeatedly applying the voltage and taking the result of the last application, the accumulation effect is utilized to make the detection result more significant.

[0046] Within each cycle, the applied scanning voltage is the same; for example, the scanning voltage can be varied according to a set changing trend.

[0047] As an example, the scan voltage applied to the gate pad during one scan cycle changes from a first voltage to a second voltage, and then from the second voltage back to the first voltage, where the first voltage is negative and the second voltage is positive.

[0048] The scanning voltage starts from negative and gradually increases to positive, then gradually decreases back to negative. Under negative voltage, the device can be simulated and characterized as being completely off, while under positive voltage, it can be simulated and characterized as being in a strong inversion / channel-forming state. The intermediate changes demonstrate the transition from off to on, and from on to off, simulating and characterizing the switching behavior of the device in a real circuit.

[0049] In some embodiments, the number of scan cycles is greater than or equal to 10. For example, the number of scan cycles can be 10, 15, or 20, etc.

[0050] As mentioned earlier, the scan voltage simulates and characterizes the switching behavior of the device in a real circuit within each cycle; that is, one scan cycle is equivalent to one switch. Using multiple scan cycles can further simulate and characterize the repeated behavior of the device in a real circuit, and can simulate and characterize the continuous load or aging conditions of the device. Thus, subsequent scan cycles can expose potential problems in the semiconductor device structure.

[0051] This embodiment uses the scanning results of the last scanning cycle to determine the voltage-capacitance curve, and can also detect potential gate oxide defects in the semiconductor device structure, not limited to gate oxide defects in the production state, thereby improving the quality control of the semiconductor device structure.

[0052] In some embodiments, the first voltage is greater than or equal to -25V and less than or equal to -15V, and the second voltage is greater than or equal to 15V and less than or equal to 25V. For example, the first voltage can be -25V and the second voltage can be 25V; the first voltage can be -20V and the second voltage can be 20V; or the first voltage can be -15V and the second voltage can be 15V.

[0053] Reference Figure 4 , Figure 4 This is a schematic diagram of the voltage-capacitance curve provided in an embodiment of this application. As an example, within one scan cycle, the scan voltage first changes from -20V to 20V, corresponding to part ① of the voltage-capacitance curve; then the scan voltage changes from 20V to -20V again, corresponding to part ② of the voltage-capacitance curve.

[0054] In some embodiments, the signal frequency of the scanning voltage is greater than or equal to 100 kHz. The scanning voltage is applied as a high-frequency AC signal between the gate pad and the drain pad, and its frequency can be 100 kHz, 500 kHz, or 1 MHz, etc. Simultaneously, the amplitude of the AC signal changes relatively slowly to achieve voltage variation.

[0055] It should be noted that since the source region 40 has a P+ region 42 and an N+ region 43, the high-frequency capacitance (CV) and low-frequency capacitance (CV) in this part are basically the same, and CV testing cannot effectively reach the minimum capacitance value. Therefore, this embodiment performs CV testing on the gate oxide portion and interface corresponding to region B, which can effectively detect gate oxide defects in the semiconductor device structure.

[0056] Continue to refer to Figure 4 In some embodiments, determining whether a gate oxide defect exists in a semiconductor device structure based on a voltage-capacitance curve may include: determining the capacitance difference between two capacitance measurements corresponding to a first voltage applied to the gate pad; determining that a gate oxide defect exists in the semiconductor device structure when the capacitance difference is greater than or equal to a threshold; and determining that a gate oxide defect does not exist in the semiconductor device structure when the capacitance difference is less than the threshold.

[0057] As an example, the first voltage can be -20V, and the capacitance difference between the two capacitance measurements corresponding to -20V is represented as ΔC. The threshold can be set according to requirements, such as 0.5E-09F, 1.0E-09F, or 1.5E-09F. If ΔC is greater than or equal to the threshold, the semiconductor device structure is determined to have a gate oxide defect; if ΔC is less than the threshold, the semiconductor device structure is determined not to have a gate oxide defect.

[0058] -20V is well beyond the accumulation range of the semiconductor device structure, sufficient to ensure the device is in a stable, uncontroversial off state. At this stage, the fast interface states have completed their charge and discharge, and their influence diminishes. The capacitance difference observed at this point is primarily attributed to the slowest-responding and most difficult-to-handle near-interface traps. This can be used to reveal near-interface traps.

[0059] Of course, in the above steps of determining whether there is a gate oxide defect based on ΔC, other voltage positions such as -25V or -15V can be selected according to the voltage withstand performance of the semiconductor device structure itself, and the corresponding threshold can also be set according to the requirements. This embodiment does not make specific limitations on this.

[0060] In some embodiments, the drain layer 20 of the semiconductor device structure is located on a first side of the wafer, and the gate electrode layer 50 of the semiconductor device structure is located on a second side of the wafer, with the first side being opposite to the second side. (Refer to...) Figure 1 The structure shown illustrates a vertical semiconductor device structure. The substrate 10 can be formed based on the wafer material itself. The epitaxial layer 30 and the gate electrode layer 50 are located on the second side of the wafer, and the drain layer 20 is located on the first side of the wafer. Typically, when arranging the wafer, the gate electrode layer 50 of the semiconductor device structure is arranged upwards, meaning the second side of the wafer faces upwards, and the first side faces downwards.

[0061] Reference Figure 5 , Figure 5 This is a schematic diagram of the semiconductor device structure and probe system provided in the embodiments of this application. The scanning voltage is applied by: providing a probe system, the probe system including a first probe 61 and a second probe 62 disposed on both sides of the wafer; connecting the first probe 61 to the drain pad of the semiconductor device structure; connecting the second probe 62 to the gate pad of the semiconductor device structure; and applying a scanning voltage between the first probe 61 and the second probe 62 through the probe system.

[0062] The gate pad represents the gate electrode pad, the source pad represents the source electrode pad, and the drain pad represents the drain electrode pad. The gate pad is electrically coupled to the gate electrode layer 50, the drain pad is electrically coupled to the drain electrode layer 20, and the source pad is electrically coupled to the source region 40. The first probe 61 is connected to the drain, achieving an electrical connection with the gate electrode layer 50 of the semiconductor device structure; the second probe 62 is connected to the gate pad, achieving an electrical connection with the gate electrode layer 50 of the semiconductor device structure. The first probe 61 serves as a reference ground, and the probe system applies a scanning voltage between the gate electrode layer 50 and the drain electrode layer 20 of the semiconductor device structure by adjusting the voltage signal on the second probe 62.

[0063] In other embodiments, the probe system may further include a third probe 63, which is connected to the source pad to connect to the source region 40 of the semiconductor device structure. The probe system may also cooperate the first probe 61 and / or the second probe 62 with the third probe 63 to detect other characteristics of the semiconductor device structure.

[0064] The probe system may include the aforementioned tester, probe card, and probe station. The first probe 61 and the second probe 62 may be disposed on the probe card and / or probe station, and there may be one or more of them. The first probe 61 may be configured to simultaneously connect to the drain of multiple semiconductor device structures as a common electrode; there may be multiple second probes 62, thereby enabling simultaneous detection of multiple semiconductor device structures.

[0065] In some embodiments, connecting the first probe to the drain of a semiconductor device structure includes: arranging a first side of the wafer on a chuck such that the drain pads of each semiconductor device structure are electrically in contact with the chuck; and electrically connecting the chuck to the first probe 61.

[0066] The drain pads of each semiconductor device structure form a common electrode through a chuck. The number of first probes 61 can be one, thus simplifying their arrangement and reducing the difficulty of placing probes beneath the wafer. When performing CV testing on each semiconductor device structure on the wafer, the second probe 62 is selected to test different individuals, reducing the complexity of the testing operation.

[0067] Secondly, this application provides a testing system, which includes a probe system and a wafer, the wafer including multiple semiconductor device structures, and the probe system configured to apply the aforementioned detection method.

[0068] The specific structures of the probe system and the semiconductor device structures on the wafer can be referred to in the foregoing embodiments, and they also have the corresponding technical effects. By performing CV testing on each semiconductor device structure on the wafer during the wafer CP testing stage, and applying scanning voltage to the gate and drain, chips with gate oxide defects can be screened out in advance, and the detection accuracy is high.

[0069] In this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element. Furthermore, it should be noted that the scope of the methods and apparatuses in the embodiments of this application is not limited to performing functions in the order shown or discussed, but may also include performing functions substantially simultaneously or in the reverse order, depending on the functions involved. For example, the described methods may be performed in a different order than described, and various steps may be added, omitted, or combined. Additionally, features described with reference to certain examples may be combined in other examples.

[0070] Although embodiments of this application have been shown and described, those skilled in the art will understand that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of this application, the scope of which is defined by the claims and their equivalents.

Claims

1. A detection method, characterized in that, include: A wafer is provided, the wafer comprising a plurality of semiconductor device structures; During the wafer chip testing phase, a scanning voltage is applied between the gate pad and the drain pad of the semiconductor device structure and the capacitance is measured simultaneously to obtain the voltage-capacitance curve between the gate pad and the drain pad. The presence of gate oxide defects in each semiconductor device structure is determined based on the voltage-capacitance curves.

2. The detection method according to claim 1, characterized in that, The scanning voltage applied to the gate pad during one scan cycle changes from a first voltage to a second voltage, and then from the second voltage back to the first voltage, where the first voltage is negative and the second voltage is positive.

3. The detection method according to claim 2, characterized in that, The application period of the scanning voltage includes multiple scanning cycles, and the voltage-capacitance curve is determined based on the scanning result of the last scanning cycle during the application period.

4. The detection method according to claim 3, characterized in that, The voltage-capacitance curve includes the results of two capacitance measurements corresponding to the first voltage. The step of determining whether gate oxide defects exist in each of the semiconductor device structures based on the voltage-capacitance curve includes: Determine the capacitance difference between two adjacent capacitance measurements corresponding to the first voltage applied to the gate pad; When the capacitance difference is greater than or equal to a threshold, it is determined that the semiconductor device structure has a gate oxide defect; When the capacitance difference is less than the threshold, it is determined that the semiconductor device structure does not have gate oxide defects.

5. The detection method according to claim 2, characterized in that, The first voltage is greater than or equal to -25V and less than or equal to -15V, the second voltage is greater than or equal to 15V and less than or equal to 25V, and the number of scan cycles is greater than or equal to 10.

6. The detection method according to claim 4, characterized in that, The signal frequency of the scanning voltage is greater than or equal to 100kHz.

7. The detection method according to any one of claims 1-6, characterized in that, The drain pad of the semiconductor device structure is located on a first side of the wafer, and the gate pad of the semiconductor device structure is located on a second side of the wafer, with the first side being opposite to the second side. The scan voltage is applied in the following manner: A probe system is provided, the probe system including a first probe and a second probe disposed on both sides of the wafer; Connect the first probe to the drain pad of the semiconductor device structure; Connect the second probe to the gate pad of the semiconductor device structure; The scanning voltage is applied between the first probe and the second probe using the probe system.

8. The detection method according to claim 7, characterized in that, The step of connecting the first probe to the drain pad of the semiconductor device structure includes: The first side of the wafer is arranged on the chuck, such that the drain pads of each of the semiconductor device structures are in electrical contact with the chuck; The chuck is electrically connected to the first probe.

9. The detection method according to claim 7, characterized in that, The semiconductor device structure includes an epitaxial layer, a gate electrode layer, and a gate oxide layer. The epitaxial layer includes a channel region and a source region. The drain pad is located on a first side of the wafer and is arranged in contact with the epitaxial layer. The gate oxide layer is located on a second side of the wafer and is arranged in contact with the channel region and the source region in the epitaxial layer. The gate electrode layer is located on the side of the gate oxide layer away from the epitaxial layer. The gate pad is electrically connected to the gate electrode layer. Wherein, the contact interface area between the gate oxide layer and the channel region is greater than the contact interface area between the gate oxide layer and the source region.

10. A testing system, characterized in that, The testing system includes a probe system and a wafer, the wafer including multiple semiconductor device structures, and the probe system is configured to apply the detection method according to any one of claims 1-9.

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