Computer system and method for data migration
By using a multi-stage data transfer method executed collaboratively by multiple processing units, the problem of transfer failure in traditional computer systems under unstable environments is solved, achieving a higher success rate and system stability, and improving hardware resource utilization.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- 深圳市欣芯半导体有限公司
- Filing Date
- 2024-12-18
- Publication Date
- 2026-06-19
AI Technical Summary
Traditional computer systems cannot successfully complete memory content transfer tasks when the hardware environment is unstable or the signal is poor, which affects product status and reliability.
A multi-stage data transfer method is adopted, in which multiple processing units work together. The segmentation module assigns weight values to memory segments, and the dynamic allocation module and fault tolerance module ensure the completion of the data transfer work, including the transfer of the first stage and the transfer of the second stage. The second processing unit retryes the unfinished task.
It improves the success rate of data transfer and system reliability, ensures that important data is transferred first, and enhances the stability of the system and the utilization rate of hardware resources under abnormal environments.
Smart Images
Figure CN122240008A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of computer technology, and more particularly to a computer system and a method for transferring data thereon. Background Technology
[0002] In the field of memory data protection and transfer in computer systems, when a system becomes unstable or malfunctions, the contents of the memory are typically transferred to an external host or receiving terminal for subsequent analysis and recovery. However, traditional technologies have significant limitations when performing memory transfers, especially in unstable hardware environments or with poor signal strength, which may cause the system to fail to complete the transfer task and damage the product.
[0003] In known technologies, when a computer system malfunctions, the central processing unit (CPU) sequentially transfers data from various memory segments to an external host according to a fixed transfer list. However, if the CPU encounters instability or unresponsiveness while executing a certain memory segment, it will enter an unresponsive state, preventing the transfer task from completing and affecting the overall product performance and reducing reliability.
[0004] Therefore, providing a computer system and its data transfer method that can improve the above problems is one of the important topics at present. Summary of the Invention
[0005] To achieve the above objectives, the present invention provides a computer system and a data transfer method thereof, which can utilize all processing units to work collaboratively in the data transfer process to improve product reliability.
[0006] This invention provides a computer system comprising a memory unit, multiple processing units, and a logic control unit. The memory unit has multiple memory segments for storing data. The processing units include a first processing unit and a second processing unit, and are used to access the multiple memory segments in the memory unit. The logic control unit is configured to allocate one of the multiple processing units to perform data transfer operations on the memory segments in the event of an exception. The logic control unit includes a segmentation module, a dynamic allocation module, and a fault-tolerant module. The segmentation module assigns a weight value to each of the multiple memory segments of the memory unit according to a priority level. The dynamic allocation module allocates processing units to perform data transfer operations on the memory segments based on the weight values of the memory segments and a transfer status. Specifically, the first processing unit and the second processing unit sequentially perform a first-stage transfer, and the second processing unit performs a second-stage transfer. The fault-tolerant module records memory segments whose data transfer operations are not completed in the first-stage transfer and allocates the second processing unit to continue performing data transfer operations on the incomplete memory segments in the second-stage transfer.
[0007] In one embodiment, the fault-tolerant module is configured to record the state of the first processing unit and allocate a second processing unit to continue the data transfer operation if the transfer fails.
[0008] In one embodiment, the data transfer operation involves transferring data stored in a memory segment to a data receiving end.
[0009] In one embodiment, data stored in the memory segment is transferred to the data receiving end via a host interface unit.
[0010] In one embodiment, the dynamic allocation module further sorts multiple memory segments according to weight values and establishes a data transfer task list to perform data transfer operations.
[0011] In one embodiment, during the second-stage data transfer, the logic control unit stops the data transfer operation when the number of failed retry attempts reaches a preset number.
[0012] Furthermore, to achieve the above objectives, the present invention also provides a data transfer method for a computer system, applied to a computer system including multiple processing units, comprising the following steps: dividing a memory unit into multiple memory segments; assigning a weight value to each of the multiple memory segments according to a priority level; and performing a data transfer operation to transfer data in the multiple memory segments. The data transfer operation includes a first-stage transfer and a second-stage transfer. In the first-stage transfer, based on the weight values, a first processing unit and a second processing unit sequentially perform the transfer of all memory segments that have not yet been transferred. In the second-stage transfer, the second processing unit retryes the data transfer operation of the memory segments that failed to be transferred in the first-stage transfer.
[0013] In one embodiment, the data transfer method further includes sorting multiple memory segments according to weight values to establish a data transfer task list, which is used to execute data transfer operations in sequence.
[0014] In one embodiment, during the first stage of data transfer, if the first processing unit does not respond, the second processing unit takes over the data transfer process. Furthermore, during the second stage of data transfer, the data transfer process stops when the number of failed retries reaches a preset number.
[0015] As stated above, the computer system and data transfer method disclosed in this invention, through a multi-stage data transfer method, ensure that more data can be successfully transferred to the data receiving end, thereby improving the success rate of the overall transfer process. Attached Figure Description
[0016] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, the specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings, wherein:
[0017] Figure 1 This is a block diagram of a computer system according to a preferred embodiment of the present invention.
[0018] Figure 2 This is a schematic diagram of a data transfer task list according to a preferred embodiment of the present invention.
[0019] Figure 3 This is a flowchart of a data transfer method for a computer system according to a preferred embodiment of the present invention.
[0020] Figure 4 This is a detailed flowchart of the data transfer process in the data transfer method.
[0021] Figure label:
[0022] 10: Computer System
[0023] 11: Electronic devices
[0024] 12: Host terminal device
[0025] 111: First Processing Unit
[0026] 112: Second Processing Unit
[0027] 113: Memory unit
[0028] 114: Logic Control Unit
[0029] 115: Host Interface Unit
[0030] 1131~113k: Memory segment
[0031] 1141: Segmentation Module
[0032] 1142: Dynamic Allocation Module
[0033] 1143: Fault-tolerant module
[0034] TA: Data Transfer Task List
[0035] S1~S4, S41~S44: Steps Detailed Implementation
[0036] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Many specific details are set forth in the following description to provide a thorough understanding of the present invention. However, the present invention may also be implemented in other ways different from those described herein. Those skilled in the art can make similar extensions without departing from the spirit of the present invention. Therefore, the present invention is not limited to the specific embodiments disclosed below.
[0037] Figure 1 This is a block diagram of a computer system 10 according to a preferred embodiment of the present invention. The computer system 10 includes an electronic device 11 and a host device 12. In practice, the computer system 10 may be, for example, but not limited to, embedded systems, industrial automation equipment, automotive electronic systems, Internet of Things (IoT) systems, medical electronic devices, and security systems. In other embodiments, the electronic device 11 and the host device 12 may also be integrated into a single device, and this is not limited thereto.
[0038] like Figure 1 As shown, the electronic device 11 has a first processing unit 111, a second processing unit 112, a memory unit 113, a logic control unit 114, and a host interface unit 115 that are electrically coupled to each other.
[0039] The memory unit 113 has multiple memory segments 1131 to 113k for storing data. In this embodiment, the memory unit 113 is, for example, but not limited to, a buffer memory or a flash memory.
[0040] The first processing unit 111 and the second processing unit 112 are each a central processing unit (CPU), which can be two different processors or two different processing cores within the same processor. The first processing unit 111 and the second processing unit 112 are used to access memory segments 1131 to 113k in the memory unit 113 to perform access operations.
[0041] The logic control unit 114 includes a segmentation module 1141, a dynamic allocation module 1142, and a fault-tolerant module 1143. The logic control unit 114 can allocate the first processing unit 111 and the second processing unit 112 to perform data transfer operations of the memory unit 113, and allocate the other processing unit to continue performing the data transfer operation when one of the processing units fails.
[0042] The segmentation module 1141 assigns a weight value to the memory segments 1131 to 113k of the memory unit 113 according to their priority levels, and generates a data transfer task list TA accordingly. Figure 2 (As shown). In this embodiment, a smaller weight value indicates a higher priority, but this is not a limiting factor. Weight values can be assigned based on the importance of the stored data. For example, stored data related to system operation is assigned a higher weight value, while stored data related to general graphic and textual data is assigned a lower weight value.
[0043] The dynamic allocation module 1142 is used to allocate the first processing unit 111 and the second processing unit 112 to perform data transfer operations in memory segments 1131-113k based on the weight values of the memory segments 1131-113k and a transfer status. The transfer status here refers to whether the data transfer operation was successful or failed. Furthermore, in this embodiment, the first processing unit 111 and the second processing unit 112 are used to sequentially perform the first stage of transfer, while the second processing unit 112 is only used to perform the second stage of transfer.
[0044] The fault-tolerant module 1143 is used to record the memory segments in the first stage of data transfer that have not completed the data transfer work, and to allocate the second processing unit 112 to retry the data transfer work of the memory segments that have not completed the transfer work in the second stage of data transfer.
[0045] The host device 12 serves as a data receiving terminal and is electrically coupled to the host interface unit 115 of the electronic device 11. The first processing unit 111 and the second processing unit 112 transfer data from memory segments 1131 to 113k to the host device 12 via the host interface unit 115. In this embodiment, the electronic device 11 and the host device 12 are taken as independent devices, and therefore they are connected through the host interface unit 115. In other embodiments, when the host device 12 is a data receiving terminal for another memory unit (not shown) and is integrated into the same device, the host interface unit 115 can be omitted.
[0046] Next, please refer to Figure 3 The above description, in conjunction with the preceding text, illustrates a preferred embodiment of the data transfer method for a computer system according to the present invention. The control method of the flash memory controller in this embodiment includes steps S1 to S4.
[0047] Step S1 involves dividing the memory cell into multiple memory segments 1131 to 113k.
[0048] Step S2 is to assign weight values to memory segments 1131 to 113k according to their priority levels.
[0049] Step S3 involves sorting memory segments 1131 to 113k according to their weight values to establish a sequence of sequences. Figure 2 The data transfer task list TA is shown below. (For example...) Figure 2 As shown, for example, the weight value of memory segment 1134 is 1, and the weight value of memory segment 113k is 2. In this embodiment, the smaller the weight value, the higher its priority level.
[0050] Step S4 is to perform a data transfer operation, which involves transferring the data in memory segments 1131 to 113k to the host device 12. The data transfer operation includes a first-stage transfer and a second-stage transfer, detailed in the following description... Figure 4 As shown, it includes steps S41 to S44.
[0051] Step S41 involves performing the first-stage data transfer, which, based on weight values, sequentially uses the first processing unit 111 and the second processing unit 112 to perform data transfer operations on all memory segments that have not yet been transferred. Memory segments that have not yet been transferred can be obtained from the records of the fault-tolerant module 1143 of the logic control unit 114. In this embodiment, when the data transfer operation has been completed or the processing unit does not respond, the process proceeds to step S42.
[0052] Step S42 is to determine whether there are any untransferred memory segments. In this embodiment, the memory segments that have not completed the data transfer work in the first stage transfer can be obtained by the record of the fault tolerance module 1143. When the determination result is "yes", step S43 is executed, and when the determination result is "no", step S44 is executed.
[0053] Step S43 involves performing the second-stage transfer. In this embodiment, the second-stage transfer uses the second processing unit 112 to retry the data transfer of memory segments that failed to transfer in the first-stage transfer. On the other hand, in the second-stage transfer, when the second processing unit 112 has completed the data transfer operation, or when the number of failed transfer retries reaches a preset number, step S44 is entered, i.e., the data transfer operation is stopped.
[0054] It is worth mentioning that, in this embodiment, when the first processing unit 111 does not respond in the memory segment corresponding to a certain weight value during the first stage of transfer and the second processing unit 112 takes over the transfer work, after entering the second stage of transfer, the dynamic allocation module 1142 will allocate the second processing unit 112 to take over the data transfer work in the memory segment corresponding to the next weight value of a certain weight value according to the data transfer task list TA during the second stage of transfer.
[0055] The following three examples illustrate data transfer methods in computer systems. For ease of explanation, only examples of... Figure 2 The following example illustrates the data transfer operation performed in the memory segments corresponding to weight values 1 to 6.
[0056] Example 1 shows that no instability occurred during the data transfer process. The data transfer method is as follows: In the first stage of transfer, the first processing unit 111 sequentially transfers memory segments 1134, 113k, 1131, 1133, 1132, and 1136. The data transfer operation ends because there are no memory segments left to be transferred.
[0057] Example 2 shows that memory segment 1131 corresponding to weight value 3 caused both the first processing unit 111 and the second processing unit to fail to respond in the first and second stages, respectively. The data transfer process is described as follows: In the first stage of transfer, the first processing unit 111 sequentially transfers memory segments 1134 and 113k, and completes successfully. However, when transferring memory segment 1131, the first processing unit 111 fails to respond, causing the transfer of memory segment 1131 to be aborted. At this point, the second processing unit 112 takes over the subsequent transfer. The second processing unit 112 successfully completes the transfer of memory segments 1133, 1132, and 1136, and ends the first stage of transfer. Next, the second stage of transfer begins, and the second processing unit 112 begins to retry memory segment 1131, which failed in the first stage. However, after three retries and reaching a preset number of attempts, the second processing unit 112 still fails to successfully transfer memory segment 1131, thus ending the data transfer operation.
[0058] Example 3 shows that memory segment 1131, corresponding to weight value 3, was unstable and succeeded after two retries. The data transfer process is described as follows: In the first stage of transfer, the first processing unit 111 first sequentially transfers memory segments 1134 and 113k, and completes successfully. However, when transferring memory segment 1131, the first processing unit 111 cannot respond, causing the transfer of memory segment 1131 to be aborted. At this time, the second processing unit 112 continues to execute the subsequent transfer. The second processing unit 112 successfully completes the transfer of memory segments 1133, 1132, and 1136, and ends the first stage of transfer. Then, the second stage of transfer begins, and the second processing unit 112 begins to retry transferring the failed memory segment 1131. On the first attempt, the second processing unit 112 still does not respond due to signal instability; on the second retry, it still cannot respond. However, on the third retry, the second processing unit 112 successfully transfers the data of memory segment 1131. The entire data transfer process is now complete, and all data in all memory segments has been successfully transferred to the host device 12.
[0059] In summary, the computer system and data transfer method disclosed in this invention utilize multiple processing units in conjunction with multiple stages to collaboratively perform data transfer operations. This approach offers advantages such as improved stability and success rate of data transfer, enhanced system fault tolerance, and priority transfer of important data. The collaborative transfer across multiple stages and processing units ensures the system maintains stable operation even in abnormal environments, and guarantees that every available processing unit can participate in the transfer process. This reduces resource idleness or waste caused by the failure of a single processing unit, achieving higher hardware resource utilization.
[0060] The above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention in any way. Although the present invention has been disclosed above with reference to preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make some modifications or alterations to the methods and techniques disclosed above without departing from the scope of the present invention to create equivalent embodiments. Any simple modifications, equivalent changes and alterations made to the above embodiments based on the technical essence of the present invention without departing from the scope of the present invention shall still fall within the scope of the present invention.
Claims
1. A computer system, characterized by The method comprises the following steps: dividing a memory unit into a plurality of memory sections; assigning a weight value to each of the plurality of memory sections according to a priority level; performing a data migration work for migrating data in the plurality of memory sections, comprising: a first stage migration, sequentially using a first processing unit and a second processing unit to perform migration of all the memory sections that have not been migrated according to the weight values; and a second stage migration, using the second processing unit to retry the data migration work of the memory sections that have failed in the first stage migration.
2. The computer system of claim 1, wherein, The method further comprises the following steps:
3. The computer system of claim 1, wherein, sorting the plurality of memory sections according to the weight values to establish a data migration task list for performing the data migration work in sequence.
4. The computer system of claim 3, wherein, In the first stage migration, when the first processing unit does not respond, the second processing unit continues the data migration work.
5. The computer system of claim 1, wherein, In the second stage migration, when the number of retrying migration failures reaches a preset number, the data migration work is stopped.
6. The computer system of claim 1, wherein, The method further comprises the following steps:
7. A data transfer method for a computer system, applied to a computer system including multiple processing units, characterized in that, dividing a memory unit into a plurality of memory sections; assigning a weight value to each of the plurality of memory sections according to a priority level; performing a data migration work for migrating data in the plurality of memory sections, comprising: a first stage migration, sequentially using a first processing unit and a second processing unit to perform migration of all the memory sections that have not been migrated according to the weight values; and a second stage migration, using the second processing unit to retry the data migration work of the memory sections that have failed in the first stage migration. The method further comprises the following steps: sorting the plurality of memory sections according to the weight values to establish a data migration task list for performing the data migration work in sequence.
8. The method of claim 7, wherein, In the first stage migration, when the first processing unit does not respond, the second processing unit continues the data migration work. In the second stage migration, when the number of retrying migration failures reaches a preset number, the data migration work is stopped. 9. The method of claim 7, wherein, 10. The method of claim 9, wherein,