Storage system, control method and device for storage system

Abstract

This application discloses a storage system, a control method for the storage system, and an apparatus for the storage system, relating to the field of computer technology. The storage system includes a node scheduler and multiple processor nodes, each processor node including a processor core, a processor port, and candidate storage devices. The node scheduler is used to allocate a target processor node to a target request based on the received information of the target request and the target mapping relationship. The target processor core is used to determine the operation position of the target request based on the request information of the target request and to generate a target instruction based on the target request and the operation position. The target storage device is used to execute the target instruction and generate execution information of the target instruction. The target processor core is also used to update the metadata database based on the execution information and send the execution information to the sending interface. This application solves the technical problem of low response rate of the storage system to read and write requests, and achieves the technical effect of improving the response rate of the storage system to read and write requests.

Description

Technical Field

[0001] This application relates to the field of computer technology, and in particular to a storage system, a control method for the storage system, and an apparatus. Background Technology

[0002] Storage systems are widely used in various fields due to their efficient data storage and management capabilities and reliable data security. In related technologies, read and write requests to storage systems are typically randomly assigned to a core for initial processing. After the data is stored on the storage device, the initial execution result of the request is then randomly sent back to another core, which in turn sends the result back to the device that issued the request. This control process involves unnecessary loading of read and write request contexts, resulting in a low response rate for read and write requests in the storage system. Summary of the Invention

[0003] This application provides a storage system, a control method for the storage system, and an apparatus to at least solve the problem of low response speed of storage systems to read and write requests in related technologies.

[0004] This application provides a storage system, including: a node scheduler and multiple processor nodes, each processor node including a processor core, a processor port, and one or more candidate storage devices; the node scheduler is configured to allocate a target processor node for a target request from the multiple processor nodes according to the received information of the received target request and a target mapping relationship, wherein the received information is used to indicate the target receiving interface of the storage system to receive the target request, and the target mapping relationship is the correspondence between multiple receiving interfaces in the storage system and multiple processor nodes; and forward the target request to the target processor core in the target processor node; the target processor core is configured to determine, according to the request information of the target request, the operation requested by the target request in the target processor node. An operation location in one or more candidate storage devices within a processor node, wherein request information is used to indicate the status of the operation requested by the target request; a target instruction is generated based on the target request and the operation location; the target instruction is sent to the target storage device to which the operation location belongs via a target port on the target processor node, wherein the processor port includes a target port; the target storage device is used to execute the target instruction and generate execution information of the target instruction, wherein the execution information is used to indicate the execution result of the target instruction; the execution information is sent to the target processor core via the target port; the target processor core is also used to update the metadata database of the storage system based on the execution information and send the execution information to the sending interface corresponding to the target receiving interface.

[0005] This application provides a control method for a storage system, comprising: the storage system including a node scheduler and multiple processor nodes, each processor node including a processor core, a processor port, and one or more candidate storage devices; the method being applied to a target processor core in a target processor node among the multiple processor nodes; the method comprising: determining, based on request information of a received target request, the operation location of the operation requested by the target request in one or more candidate storage devices within the target processor node; wherein the request information is used to indicate the status of the operation requested by the target request; and the target request is allocated by the node scheduler to the target processor node and sent to the target processor core by the node scheduler according to the received information of the target request and the target mapping relationship. The process involves several steps: receiving information to instruct the storage system to accept the target request at the target receiving interface; the target mapping relationship is the correspondence between multiple receiving interfaces and multiple processor nodes in the storage system; generating target instructions based on the target request and operation location; sending the target instructions to the target storage device at the operation location via the target port on the target processor node, where the processor port includes the target port; the target storage device executing the target instructions, generating execution information for the target instructions, and sending the execution information to the target processor core via the target port; the execution information indicating the execution result of the target instructions; updating the storage system's metadata database based on the received execution information; and sending the execution information to the sending interface corresponding to the target receiving interface.

[0006] This application also provides a control device for a storage system. The storage system includes a node scheduler and multiple processor nodes. Each processor node includes a processor core, a processor port, and one or more candidate storage devices. The device is applied to a target processor core in a target processor node among the multiple processor nodes. The device includes a determination module, configured to determine the operation location in one or more candidate storage devices of the target processor node based on the request information of a received target request. The request information indicates the status of the operation requested by the target request. The target request is allocated to the target processor node and sent to the target processor core by the node scheduler based on the received information of the target request and the target mapping relationship. The received information is used for... The system comprises a target receiving interface that instructs the storage system to receive the target request, and a target mapping relationship that corresponds to multiple receiving interfaces and multiple processor nodes in the storage system; a generation module that generates target instructions based on the target request and the operation location; a first sending module that sends the target instructions to the target storage device to which the operation location belongs through the target port on the target processor node, wherein the processor port includes the target port, the target storage device executes the target instructions, generates execution information of the target instructions, and sends the execution information to the target processor core through the target port, and the execution information is used to indicate the execution result of the target instructions; and an update module that updates the metadata database of the storage system based on the received execution information and sends the execution information to the sending interface corresponding to the target receiving interface.

[0007] This application also provides an electronic device, including: a memory for storing a computer program; and a processor for implementing the control method of the above-described storage system when executing the computer program.

[0008] This application also provides a computer-readable storage medium storing a computer program, wherein the computer program, when executed by a processor, implements the steps of the control method of the above-described storage system.

[0009] This application describes a node scheduler that allocates a target processor node to a target request from multiple processor nodes based on the received information and target mapping relationship of the target request. The target request is then forwarded to the target processor core within the target processor node. Requests received by each interface are processed by their corresponding processor core, initially ensuring the locality of read / write request execution and avoiding cross-core data transfer. Upon receiving the target request, the target processor core determines the operation location of the requested operation in one or more candidate storage devices within the target processor node based on the request information. It then generates a target instruction based on the target request and operation location, and sends the target instruction to the target storage device at the operation location via the target port on the target processor node. The target storage device executes the target instruction and generates execution information, which is then sent back to the target processor core via the target port. The target processor core updates the storage system's metadata database and returns the execution result. This avoids cross-core operations during target request execution, prevents unnecessary context reloading of the target request, and improves the storage system's response rate. Therefore, this application solves the technical problem of slow read / write request response rates in related technologies, achieving the technical effect of improving the read / write request response rate of storage systems. Attached Figure Description

[0010] To more clearly illustrate the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0011] Figure 1 This is a schematic diagram of a storage system according to an embodiment of this application;

[0012] Figure 2 This is an architecture diagram of a high-performance data storage method according to an embodiment of this application;

[0013] Figure 3 This is a flowchart of a control method for a storage system according to an embodiment of this application;

[0014] Figure 4 This is a structural block diagram of a control device for a storage system according to an embodiment of this application. Detailed Implementation

[0015] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of this application.

[0016] It should be noted that, in the description of this application, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. The terms "first," "second," etc., in this application are used to distinguish similar objects and are not used to describe a specific order or sequence.

[0017] To enable those skilled in the art to better understand the present application, the present application will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0018] This embodiment provides a storage system. Figure 1 This is a schematic diagram of a storage system according to an embodiment of this application, such as... Figure 1 As shown, the storage system includes: a node scheduler and multiple processor nodes, each processor node including a processor core, a processor port, and one or more candidate storage devices; the node scheduler is used to allocate a target processor node for a target request from the multiple processor nodes according to the received information of the received target request and the target mapping relationship, wherein the received information is used to indicate the target receiving interface of the storage system to receive the target request, and the target mapping relationship is the correspondence between multiple receiving interfaces in the storage system and multiple processor nodes; the node scheduler forwards the target request to the target processor core in the target processor node; the target processor core is used to determine the operation requested by the target request in the target processor node according to the request information of the target request. An operation location in one or more candidate storage devices within a node, wherein request information is used to indicate the status of the operation requested by the target request; a target instruction is generated based on the target request and the operation location; the target instruction is sent to the target storage device to which the operation location belongs through a target port on the target processor node, wherein the processor port includes a target port; the target storage device is used to execute the target instruction and generate execution information of the target instruction, wherein the execution information is used to indicate the execution result of the target instruction; the execution information is sent to the target processor core through the target port; the target processor core is also used to update the metadata database of the storage system based on the execution information and send the execution information to the sending interface corresponding to the target receiving interface.

[0019] Through the aforementioned storage system, the node scheduler allocates a target processor node for the target request from multiple processor nodes based on the received information and target mapping relationship of the target request. The target request is then forwarded to the target processor core within the target processor node. Requests received by each interface are processed by the corresponding processor core, initially ensuring the locality of read / write request execution and avoiding cross-core data transfer. After receiving the target request, the target processor core determines the operation location of the requested operation in one or more candidate storage devices within the target processor node based on the request information. It generates a target instruction based on the target request and operation location, and sends the target instruction to the target storage device corresponding to the operation location through the target port on the target processor node. The target storage device executes the target instruction and generates execution information, which is then sent back to the target processor core through the target port. The target processor core updates the storage system's metadata database and returns the execution result. This avoids cross-core operations during target request execution and unnecessary repeated loading of the target request's context, improving the storage system's response rate. Therefore, it can solve the technical problem of slow read / write request response rates in related technologies, achieving the technical effect of improving the response rate of storage systems to read / write requests.

[0020] Optionally, in this embodiment, the storage system may include, but is not limited to, a node scheduler and multiple processor nodes. Each processor node may include, but is not limited to, a processor core, a processor port, and one or more candidate storage devices. For example, the storage system may include, but is not limited to, a node scheduler, processor node 1, and processor node 2. Processor node 1 may include, but is not limited to, processor core 1, processor port 1, candidate storage device 1-1, and candidate storage device 1-2. Processor node 2 may include, but is not limited to, processor core 2, processor port 2, and candidate storage device 2-1.

[0021] Optionally, in this embodiment, the node scheduler may be, but is not limited to, a component implemented in software or hardware, and the function of the node scheduler may be, but is not limited to, allocating a target processor node for each target request based on the received information of the target request and the target mapping relationship.

[0022] Optionally, in this embodiment, the receiving information may be, but is not limited to, used to instruct the storage system to receive the target receiving interface for the target request. For example, when receiving the target request over a network, the receiving information may be, but is not limited to, used to instruct the storage system to receive the network card for the target request. Or, for example, in a virtualization environment, each virtual machine or container has its own virtual network interface. In this case, the receiving information may be, but is not limited to, a unique identifier for the virtual interface, used to specify the target receiving interface in the storage system that handles requests from a specific virtual machine or container, ensuring the isolation and security of data operations from virtual resources.

[0023] Optionally, in this embodiment, the target mapping relationship may be, but is not limited to, a pre-set correspondence between multiple receiving interfaces and multiple processor nodes in the storage system. For example, the target mapping relationship may be, but is not limited to, a pre-set correspondence between multiple network cards and multiple processor nodes in the storage system. It may be, but is not limited to, assigning all requests received through a certain network card to the processor core in the processor node corresponding to that network card for processing.

[0024] Optionally, in this embodiment, the node scheduler may allocate a target processor node for the target request from multiple processor nodes based on the received information of the target request and the target mapping relationship, including but not limited to: the node scheduler matching the target receiving interface of the target request with the corresponding processor node from multiple receiving interfaces and multiple processor nodes with corresponding relationships, thereby obtaining the target processor node.

[0025] Optionally, in this embodiment, the target processor core may be, but is not limited to, the processor core within the target processor node. The target processor core may be, but is not limited to, responsible for parsing the request information of the target request (such as read / write type, data location, and size) and determining the operation location. This process may be, but is not limited to, querying the local metadata database or communicating with a dedicated metadata server. Once the operation location is determined, the target processor core may, but is not limited to, generate the corresponding target instruction and send it to the target storage device through the processor port bound to it, i.e., the target port. By directly binding the processor core to the storage device, the system can avoid cross-core communication and multiple data copies, thereby significantly reducing latency and improving efficiency.

[0026] Optionally, in this embodiment, the target processor core determining the operation location of the operation requested by the target request in one or more candidate storage devices on the target processor node based on the request information of the target request may include, but is not limited to: the target processor core extracting a logical address from the request information; if a logical address is extracted, extracting metadata related to the target request from the metadata database of the storage system based on the logical address, and extracting a physical address as the operation location from the metadata; if a logical address cannot be extracted, allocating a free physical address as the operation location for the target request based on the metadata database of the storage system. For example, this may be, but is not limited to, a storage system containing multiple processor nodes, each node equipped with a high-speed NVMe SSD (Non-Volatile Memory express Solid State Drive) storage device and an RDMA (Remote Direct Memory Access) network adapter. This system may, but is not limited to, use the SPDK (Storage Performance Development Kit) framework as the backend for its storage target service to achieve high-performance data access services. The target processor core receives a target request containing request information, which may explicitly specify an LBA (Logical Block Addressing) address. If the request includes an LBA, the core directly extracts the LBA from the request information as the logical address. If the logical address is available, the target processor core queries the storage system's metadata database to find the metadata record corresponding to the LBA. In the metadata database, the metadata record contains the mapping relationship between logical addresses and physical addresses, as well as other important information such as the data version number and replica location. The target processor core extracts the physical address from the metadata, determining which specific SSD device the data resides on and its exact location on the device; this physical location is the operation location. If the target request fails to provide a logical address (e.g., the request involves data creation or writing), the target processor core queries the metadata database to find a free physical address space. Based on the current usage of the SSD device, the target processor core dynamically allocates a free physical address as the new operation location for the upcoming write operation.

[0027] Optionally, in this embodiment, the target processor core generating target instructions based on the target request and operation location may include, but is not limited to, detecting the communication protocol of candidate storage devices; and generating target instructions that conform to the requirements of the communication protocol based on the communication protocol, the target request, and the operation location. For example, for the aforementioned storage system, when the target processor core receives a target request, it first needs to detect the communication protocols supported by the candidate storage devices involved in the target request. This step may be accomplished, but is not limited to, querying device capability information or device characteristics recorded in a metadata database, to ensure that the generated instructions are compatible with the storage device and fully utilize its performance advantages. Based on the detected communication protocol, the target processor core may, but is not limited to, generate target instructions that conform to the protocol specification according to the specific requirements of the target request (e.g., read or write operations) and the previously determined operation location (i.e., a specific physical address).

[0028] Optionally, in this embodiment, the target port may be, but is not limited to, the port through which the target processor core communicates with one or more candidate storage devices on the target processor node.

[0029] Optionally, in this embodiment, the target storage device may be, but is not limited to, one or more candidate storage devices of the target processor node. The target storage device may, but is not limited to, execute target instructions to read data or write data, obtain execution results, and generate execution information.

[0030] Optionally, in this embodiment, the target storage device may, but is not limited to, return execution information indicating the execution result of the target instruction to the target processor core through the target port after executing the target instruction.

[0031] Optionally, in this embodiment, the target processor core that originally processed the target request may continue to process the update of metadata related to the target request and the return of execution information. This can avoid other processor cores having to load the context of the target request again when processing the target request, thereby reducing the read and write latency of the storage system.

[0032] Optionally, in this embodiment, the target processor core updates the metadata database of the storage system based on the execution information. This may include, but is not limited to, storing the operation location allocated to the target request as metadata of the data to be written in the metadata database when the target request is a write request. The target processor core sends the execution information to the sending interface corresponding to the target receiving interface. This may include, but is not limited to, detecting whether the update operation on the metadata database of the storage system was successfully executed; if the update operation fails, modifying the "request execution success" in the execution information to "request execution failure," and sending the modified execution information to the sending interface; if the update operation is successful, sending the execution information to the sending interface corresponding to the target receiving interface. Through the above operations, the persistent state of data and metadata is coordinated through atomic transactions, ensuring the reliability of the metadata database.

[0033] As an optional implementation, to optimize the request processing efficiency of the storage system while ensuring balanced resource utilization, the aforementioned dedicated core processing and dynamic load balancing mechanisms can be combined, but are not limited to. The storage system can, but is not limited to, automatically select the most suitable processing strategy based on the characteristics of the requests: for specific types or high-priority requests, dedicated core processing is used to reduce latency; while for unbalanced load situations, processing tasks are redistributed through a dynamic load balancing mechanism to avoid resource waste and performance bottlenecks. Specifically, the storage system can, but is not limited to, also include: a request classifier and a load balancer.

[0034] Request classifier: This can be used, but is not limited to, to identify and classify different types of requests, such as read requests, write requests, and high-priority requests. The request classifier can, but is not limited to, label requests as "dedicated core processing" or "load balancing processing" based on request characteristics (such as request frequency, data size, priority, etc.). Specifically, the request classifier can, but is not limited to, label requests with a priority higher than a priority threshold as "dedicated core processing," and label requests with a priority lower than or equal to the priority threshold as "load balancing processing."

[0035] Load balancers can monitor, but are not limited to, the resource usage of the entire storage system, such as the load on processor cores and the I / O activity of storage devices. When a load imbalance is detected to reach a preset threshold (for example, the load difference between the processor node with the highest load and the processor node with the lowest load in the storage system is greater than or equal to the load difference threshold), the load balancer will adjust the target mapping relationship corresponding to "load balancing processing" (the target mapping relationship corresponding to "dedicated core processing" remains fixed), and reallocate the processor nodes corresponding to the interfaces (for example, changing part of the receiving interface corresponding to the processor node with the highest load to correspond to the processor node with the lowest load), reallocating requests to processor nodes with lower loads to achieve dynamic balancing of system resources.

[0036] Specifically, after receiving a target request, the request classifier determines whether the request is suitable for dedicated core processing based on request information (such as operation type, data volume, priority, etc.). If suitable, the node scheduler directly assigns the request to a pre-configured dedicated core; otherwise, it enters the dynamic load balancing process. For requests marked as "dedicated core processing," the target processor core directly determines the operation location based on the request information, generates the target instruction, and sends it to the designated storage device. This processing method reduces request processing latency and is particularly suitable for latency-sensitive scenarios. When the storage system detects that the load imbalance between processor nodes exceeds a set threshold, the load balancer intervenes and adjusts the target mapping relationship. It reallocates requests to processor nodes with lower loads to ensure balanced resource utilization. The load balancer also monitors cross-core communication latency. When it detects that increased latency is caused by cross-core task allocation, it optimizes the allocation strategy and reduces the frequency of cross-core tasks to lower latency. There is intelligent switching between the storage system's dynamic load balancing mechanism and the dedicated core processing mechanism. When the storage system is under low load or a high-priority request is detected, dedicated core processing is prioritized to ensure low latency for critical operations. When the system load increases or an imbalance in load is detected, a dynamic load balancing mechanism will be automatically activated to redistribute tasks and ensure the overall stability and efficiency of the system.

[0037] Through the above design, the dedicated core processing mechanism reduces processing latency for high-priority or critical requests, proving particularly effective for operations requiring low latency. The dynamic load balancing mechanism ensures balanced resource utilization, avoiding performance bottlenecks caused by excessive resource concentration and enhancing the overall stability and efficiency of the system. By optimizing request allocation strategies, the frequency of cross-core communication is reduced, lowering latency caused by cross-core communication and improving the overall system response speed. The combination of the request classifier and load balancer enables intelligent resource management, automatically adjusting processing strategies based on real-time workload and request characteristics, improving resource utilization efficiency and system adaptability.

[0038] By implementing the above solutions, the storage system can maintain high performance and low latency when processing various requests, while ensuring balanced resource utilization and avoiding performance bottlenecks caused by improper resource allocation, thus providing users with more stable and efficient services.

[0039] As an optional implementation, the target processor core includes: a monitor and a runner; the monitor is used to receive target requests; convert the target requests into target task descriptors, wherein the task descriptors include request information; create target coroutine tasks based on the target task descriptors; submit the target coroutine tasks to the runner's local task queue; the runner is used to extract the target coroutine tasks from the local task queue; run the target coroutine tasks to obtain the operation position; run the target coroutine tasks to obtain target instructions; suspend the target coroutine tasks and send the target instructions to the target storage device through the target port; the monitor is also used to monitor the execution information received by the target port; find the coroutine task corresponding to the execution information to obtain the target coroutine task; wake up the target coroutine task; the runner is also used to update the metadata database by running the woken-up target coroutine task and send the execution information to the sending interface.

[0040] Optionally, in this embodiment, the target processor core may include, but is not limited to, a monitor and a runner. The monitor may be responsible for receiving target requests and converting them into coroutine tasks, while the runner executes these tasks to ensure the efficiency of data operations. Through the use of coroutines, the storage system can respond to requests faster because the context switching overhead of coroutines is much lower than that of threads, and they can maintain an execution loop within a single core, reducing latency and resource contention in cross-core communication.

[0041] Optionally, in this embodiment, the node scheduler may, but is not limited to, receive target requests from the network. The request includes reception information indicating the source and type of the request, as well as a target mapping relationship, describing the correspondence between the receiving interface and the processor node. Based on the target mapping relationship, the node scheduler determines which processor node is the most suitable target node and forwards the target request to the target processor core in that node. The monitor in the target processor core first receives the target request forwarded by the node scheduler. The monitor parses the request information, converts it into a task descriptor containing specific operation information, and creates a target coroutine task based on this. The lightweight nature of coroutine tasks means that they can be quickly switched within the same processor core, reducing the overhead of context switching. The created target coroutine task is submitted to the runner's local task queue. The runner extracts the coroutine task from the local queue, responsible for executing the specific operations in the task (such as finding the operation location, generating instructions, etc.). The runner runs the extracted target coroutine task, determines the operation location based on the request information in the task, and generates the corresponding target instructions. This process fully utilizes the asynchronous execution capability of coroutines, ensuring the high efficiency of task execution. After generating the target instruction, the runner suspends the current target coroutine task to ensure atomicity and minimize resource consumption during instruction transmission. After suspending the coroutine task, the runner sends the target instruction to the target storage device through the target port to execute the requested storage operation. Once the target storage device has executed the instruction, it sends execution information to the target processor core through the target port. The monitor receives this information and monitors the completion status of the storage operation. The monitor locates the corresponding coroutine task based on the execution information and wakes it up, allowing the suspended coroutine to continue execution. After the coroutine task is woken up, the runner updates the storage system's metadata database based on the execution information to ensure data consistency with metadata. After updating the metadata database, the runner returns the execution information to the client or upper-layer service that initially initiated the request through the target processor node's sending interface, completing the entire request processing flow.

[0042] By leveraging the division of labor between the monitor and the runner, coroutine tasks can be managed and executed efficiently, reducing task scheduling latency and improving storage system response speed. Furthermore, the monitor and runner mechanism on each core ensures resource isolation within the core, avoiding cross-core resource contention and reducing storage system latency.

[0043] As an optional implementation, the runner is also configured to detect the target request type of the target coroutine task, wherein the request information includes the target request type; if the target request type is read, extract target address information from the request information, wherein the target address information is used to indicate the logical address of the data requested to be read by the target request; locate the target metadata of the target coroutine task based on the target address information to obtain the operation position; if the target request type is write, allocate an operation position to the target coroutine task; generate a target instruction based on the request information and the operation position; save the current status information of the target coroutine task and send the target instruction to the target storage device through the target port, wherein the current status information is used to indicate the current execution progress of the target coroutine task;

[0044] The monitor is also used to find the coroutine task corresponding to the execution information, obtain the target coroutine task, load the current status information, and send the target coroutine task to the runner.

[0045] The runner is also used to receive the target coroutine task; and to continue running the target coroutine task based on the current status information and execution information.

[0046] Optionally, in this embodiment, for read operations, the runner may, but is not limited to, look up the operation location from the mapping between logical addresses and physical addresses; while for write operations, it will directly allocate a physical address and generate the corresponding instructions. Saving and restoring the current state information ensures that even under high concurrency, the execution state of the coroutine task can be correctly recorded and restored, avoiding data loss or inconsistency.

[0047] Based on the above, read and write operations are handled according to request type, ensuring optimized data access paths, reducing unnecessary storage device accesses, and improving I / O efficiency. By saving and loading current state information, the continuity and consistency of the coroutine task's execution state in the storage system are guaranteed, ensuring the correctness and integrity of data operations even when tasks are suspended and resumed.

[0048] As an optional implementation, the target processor core also includes: a target memory, in which a target instruction queue is created;

[0049] The runner is also used to store target instructions in the target instruction queue; and to send target notifications to the target storage device through the target port, wherein the target notifications are used to notify the target storage device that there are operation instructions to be executed;

[0050] The target storage device is used to receive target notifications and retrieve target instructions from the target instruction queue.

[0051] The target storage device is also used to send the execution information through the target port after executing the target instruction and generating the execution information of the target instruction.

[0052] Optionally, in this embodiment, a target instruction queue may be created in the target memory of the target processor core to store instructions to be executed. After the executor stores the generated instructions in the queue, it sends a target notification to the target storage device through the target port, notifying it that there are new operation instructions to be executed. This mechanism reduces the time the storage device waits for instructions and improves the efficiency of instruction processing. The storage device then retrieves instructions from the instruction queue for execution, and after execution, sends execution information through the target port.

[0053] Through the above, the storage device can respond to instructions immediately via target notification and instruction queuing mechanisms, improving the immediacy of instruction processing and the throughput of the storage system.

[0054] As an optional implementation, the storage system further includes: a reference storage device; and the processor node further includes: a metadata port;

[0055] The runner is also used to look up target metadata from a reference storage device through a reference port on the target processor node based on the target address information, wherein the metadata port includes the reference port;

[0056] Reference storage device for storing metadata;

[0057] The runner is also used to generate updated metadata for the target coroutine task based on the operation location after receiving the target coroutine task, when the target request type is write; and to store the updated metadata to the reference storage device via the reference port.

[0058] Optionally, in this embodiment, the processor core in the processor node may, but is not limited to, access the reference storage device through the first channel to obtain and store metadata, and the processor core in the processor node may, but is not limited to, access each candidate storage device through the second channel to read and write data.

[0059] Optionally, in this embodiment, the reference storage device may be, but is not limited to, a distributed KV (Key-Value) cluster.

[0060] Optionally, in this embodiment, by creating a separate metadata port and reference storage device, the storage system can efficiently handle metadata queries and updates. In read request types, the runner queries the target metadata through the metadata port, while in write request types, updated metadata is stored in the reference storage device. This design ensures high availability and consistency of metadata while reducing the frequency of access to the main data storage device, thereby improving the performance of data operations.

[0061] As an optional implementation, the storage system also includes: multiple network interface cards (NICs), and a memory buffer created in the processor node;

[0062] The target network interface card (NIC) among multiple NICs is used as the target receiving interface to receive target requests. The target NIC is the NIC corresponding to the target processor node. If the target request type is write, the request data is stored in the target memory buffer of the target processor node corresponding to the target NIC, according to the target mapping relationship. The request data is the data requested by the target request to be written to the storage system. The target request is then forwarded to the node scheduler. If the target request type is read, the target request is also forwarded to the node scheduler.

[0063] The target storage device is further configured to: read requested data from the target memory buffer when the target request type is write; execute target instructions and generate execution information based on the requested data; send the execution information to the target processor core through the target port; execute target instructions and generate execution information when the target request type is read; store target data in the target memory buffer, wherein the target data is the data requested by the target request to be read from the storage system; and send the execution information to the target processor core through the target port.

[0064] The target network interface card is also used for: receiving execution information as a sending interface when the target request type is write; sending the execution information and target data to the target device that initiated the target request; receiving execution information as a sending interface when the target request type is read; reading target data from the target memory buffer; and sending the execution information and target data to the target device.

[0065] Optionally, in this embodiment, a memory buffer may be created in the processor node according to preset rules before using the storage system, but not limited to. In the case of applying the SPDK architecture, the preset rules may be, but are not limited to, the architecture of the SPDK architecture requesting a cache area. By creating a memory buffer according to the preset rules, the SPDK architecture and the network card can directly store data in the memory buffer, avoiding the copying operation of data from the network card's cache area to the SPDK's cache area.

[0066] Optionally, in this embodiment, the target network interface card (NIC) acts as the target receiving interface to receive the target request and stores the data in the target memory buffer or forwards it directly to the node scheduler depending on the request type (read or write). This mechanism utilizes the high-speed channel between the NIC and the processor node, reducing the number of data copies and improving data transmission speed. For read operations, the target data is read and stored in the memory buffer for quick return to the requester; for write operations, after receiving the execution information for the storage operation, the NIC sends the data along with the execution information to the requester.

[0067] By optimizing the use of network cards and memory buffers, the latency and overhead during data transmission and storage are reduced, thereby improving the efficiency of data operations and the overall performance of the storage system.

[0068] As an optional implementation, this application also provides a high-performance data storage method. Specifically, this method constructs a three-level processing architecture: the front-end access layer uses SPDK / NVMe-oF (Non-Volatile Memory Expressover Fabrics, a fast interface for non-volatile memory via network structure) to achieve RDMA network acceleration; the core processing layer implements a core-binding coroutine scheduling mechanism at the bdev (Block Device) layer; and the performance layer adopts a dual-channel separate storage mode for data and metadata. This architecture ensures high processing efficiency through thread-core binding and coroutine coordination, and delegates metadata management to an independent high-performance cluster. In a cluster environment composed of multiple nodes, it achieves performance indicators and latency stability far exceeding existing technologies. This architecture eliminates cross-core jitter through thread-core binding, avoids context switching overhead through coroutine coordination, and offloads metadata management to an independent high-performance cluster. In cluster testing, the metadata access latency is stable within 10μs (microseconds) with fluctuations not exceeding ±2μs, significantly better than hybrid architectures.

[0069] Figure 2 This is an architecture diagram of a high-performance data storage method according to an embodiment of this application. For example... Figure 2As shown, when the RDMA client establishes an NVMe (NVMe remote storage protocol based on RDMA) connection via the nvme connect command, the server achieves high-performance processing based on the SPDK-customized Target module. This module adopts a core binding strategy, mapping the RX (receive) / TX (transmit) queues of each physical network card to a specific CPU (Central Processing Unit) core to ensure isolation. During the initialization phase, an exclusive polling thread group is created, with each thread exclusively enjoying the DMA (Direct Memory Access) memory area, completely avoiding cache contention. By dynamically adjusting flow control parameters (such as window size and retransmission timeout), network layer throughput and latency are optimized, ensuring that NVMe-oF packet transmission efficiency remains stable above 95% while maintaining sub-millisecond tail latency. In the core layer of the bdev block device module (i.e., the asynchronous processing layer), an IO context layer (ioctx) is introduced as a high-performance coroutine scheduler. A completely independent and isolated ioctx scheduler instance (i.e., the aforementioned monitor) is deployed for each physical CPU core. When the SPDK framework (i.e., the aforementioned node scheduler) receives an incoming NVMe command (such as a read / write request) (i.e., the aforementioned target request) and routes it to the corresponding bdev target (i.e., the aforementioned processor node), the ioctx scheduler instance immediately intervenes. It encapsulates this raw IO request into a lightweight user-space coroutine task (i.e., the aforementioned target coroutine task). This encapsulation operation itself is extremely efficient, consuming only a small number of CPU cycles. After encapsulation, the coroutine is not suspended or handed over to other thread pools, but is immediately taken over by the thread on the current physical core (i.e., runtime) and begins execution synchronously. The coroutine's primary responsibility is to perform metadata prefetching: it needs to accurately determine the actual physical location (i.e., the operation location) of the data involved in the current IO request. To this end, the coroutine initiates a query request to the distributed key-value storage cluster (i.e., the aforementioned reference storage device) carrying global metadata through a highly optimized RPC (Remote Procedure Call) interface. Once the precise metadata information of the target data is successfully obtained (including but not limited to the physical device number of the SSD (Solid State Drive) where the data resides, the specific LBA (Logical Block Addressing) address range, and possible copy information), the coroutine has completed its core mission of metadata prefetching. At this point, it immediately triggers the subsequent local data operation execution flow. The coroutine does not directly operate on the underlying hardware, but instead uses a lock-free and high-throughput queue structure specifically designed for this core (i.e., the aforementioned target instruction queue) to precisely initiate actual data read and write operation requests to the performance layer module (i.e., to the storage device).This process is strictly guaranteed by locality: from the moment the coroutine is awakened to retrieve metadata, to the generation and queuing of a request, the entire logic is constrained to execute within the context of the current CPU core, completely eliminating cross-core thread migrations or scheduling switches that could incur significant overhead. After completing the actual I / O operation (i.e., executing the target instruction), the underlying SSD device (i.e., the target storage device) generates a completion event through SPDK's efficient event notification mechanism. Upon hearing this event, the Ioctx scheduler instance uses its sophisticated event callback mechanism to precisely wake up the specific coroutine that initiated the I / O request and was in a waiting state. The awakened coroutine then collects the operation results (success / failure status, read data, etc.) (i.e., execution information), and finally, the thread that initially carried the request and remains bound to the current physical core (i.e., the runner) returns the complete I / O completion response to the upper-layer application along the same path, creating an efficient closed loop for the entire request lifecycle.

[0070] Furthermore, memory copying can be avoided, but not limited to, by pre-registering a memory buffer (i.e., the aforementioned memory buffer), allowing write operations to directly reach the SSD controller. A Raft-based KV cluster can be created to store metadata such as file location and attributes. Metadata updates use a batch commit mode, adding CRC (Cyclic Redundancy Check) check bits and a data version stamp during the write process. The persistent state of data and metadata is coordinated through atomic transactions; the KV transaction log is synchronously committed after the NVMe (Non-Volatile Memory Express) write confirmation returns. When a node in the KV cluster fails, the distributed KV cluster elects a new leader based on Raft. Metadata discrepancies are quickly located through log comparison, and a data reconstruction service is started in the background: missing data is reconstructed from replica nodes according to the mapping table recorded in the KV cluster. The reconstruction process uses pipelined transmission, supporting a data synchronization rate of 2TB / hour. During client access interruptions, a metadata caching service is enabled, providing read-only access capabilities to ensure business continuity. By implementing the above solutions, CPU scheduling overhead can be reduced, the metadata cluster can be expanded independently, and the lifespan of storage devices is reduced by minimizing metadata writes and thus reducing wear and tear.

[0071] As an optional implementation, this application also provides a control method for a storage system, the storage system including: a node scheduler and multiple processor nodes, each processor node including a processor core, a processor port, and one or more candidate storage devices, the method being applied to a target processor core in a target processor node among the multiple processor nodes. Figure 3 This is a flowchart of a control method for a storage system according to an embodiment of this application, such as... Figure 3 As shown, the method includes:

[0072] Step S302: Determine the operation location of the operation requested by the target request in one or more candidate storage devices in the target processor node based on the request information of the received target request. The request information is used to indicate the operation requested by the target request. The target request is allocated to the target processor node and sent to the target processor core by the node scheduler according to the received information of the target request and the target mapping relationship. The received information is used to indicate the target receiving interface of the storage system to receive the target request. The target mapping relationship is the correspondence between multiple receiving interfaces in the storage system and multiple processor nodes.

[0073] Step S304: Generate target instructions based on the target request and operation location;

[0074] Step S306: The target instruction is sent to the target storage device to which the operation location belongs through the target port on the target processor node. The processor port includes the target port. The target storage device is used to execute the target instruction, generate execution information of the target instruction, and send the execution information to the target processor core through the target port. The execution information is used to indicate the execution result of the target instruction.

[0075] Step S308: Update the metadata database of the storage system according to the received execution information, and send the execution information to the sending interface corresponding to the target receiving interface.

[0076] Using the method described above, the node scheduler allocates a target processor node for the target request from multiple processor nodes based on the received information and target mapping relationship of the target request. The target request is then forwarded to the target processor core within the target processor node. Requests received by each interface are processed by the corresponding processor core, initially ensuring the locality of read / write request execution and avoiding cross-core data transfer. After receiving the target request, the target processor core determines the operation location of the requested operation in one or more candidate storage devices within the target processor node based on the request information. It generates a target instruction based on the target request and operation location, and sends the target instruction to the target storage device corresponding to the operation location through the target port on the target processor node. The target storage device executes the target instruction and generates execution information, which is then sent back to the target processor core through the target port. The target processor core updates the storage system's metadata database and returns the execution result. This avoids cross-core operations during target request execution and unnecessary repeated loading of the target request's context, improving the storage system's response rate. Therefore, this method can solve the technical problem of slow read / write request response rates in related technologies, achieving the technical effect of improving the read / write request response rate of storage systems.

[0077] In some embodiments, the target processor core includes: a monitor and a runner; determining the operation location of the operation requested by the target request in one or more candidate storage devices in the target processor node based on the request information of the received target request includes: the monitor receiving the target request; the monitor converting the target request into a target task descriptor, wherein the task descriptor includes request information; the monitor creating a target coroutine task based on the target task descriptor; the monitor submitting the target coroutine task to the runner's local task queue; the runner retrieving the target coroutine task from the local task queue; and the runner running the target coroutine task to obtain the operation location.

[0078] In some embodiments, generating target instructions based on target requests and operation locations includes: running a target coroutine task by an operator to obtain target instructions.

[0079] In some embodiments, sending the target instruction to the target storage device to which the operation location belongs via the target port on the target processor node includes: suspending the target coroutine task by the runner and sending the target instruction to the target storage device via the target port.

[0080] In some embodiments, updating the metadata database of the storage system based on the received execution information and sending the execution information to the sending interface corresponding to the target receiving interface includes: monitoring the execution information received by the target port by the monitor; finding the coroutine task corresponding to the execution information by the monitor and obtaining the target coroutine task; waking up the target coroutine task by the monitor; and updating the metadata database by running the woken-up target coroutine task and sending the execution information to the sending interface.

[0081] In some embodiments, the process of the runner executing the target coroutine task to obtain the operation position includes: the runner detecting the target request type of the target coroutine task, wherein the request information includes the target request type; the runner extracting target address information from the request information when the target request type is a read type, wherein the target address information is used to indicate the logical address of the data requested to be read by the target request; the runner searching for the target metadata of the target coroutine task based on the target address information to obtain the operation position; and the runner allocating the operation position to the target coroutine task when the target request type is a write type.

[0082] In some embodiments, the runner executes the target coroutine task to obtain the target instruction, including: the runner generates the target instruction based on the request information and the operation location.

[0083] In some embodiments, suspending the target coroutine task by the runner and sending the target instructions to the target storage device through the target port includes: the runner saving the current status information of the target coroutine task and sending the target instructions to the target storage device through the target port, wherein the current status information is used to indicate the current execution progress of the target coroutine task.

[0084] In some embodiments, waking up the target coroutine task by the monitor includes: loading the current status information by the monitor and sending the target coroutine task to the runner.

[0085] In some embodiments, the runner updates the metadata database by running the target coroutine task after it is woken up, and sends the execution information to the sending interface, including: the runner receiving the target coroutine task; and the runner continuing to run the target coroutine task based on the current status information and the execution information.

[0086] In some embodiments, the target processor core further includes: a target memory, in which a target instruction queue is created; sending target instructions to a target storage device through a target port, including: the runner storing the target instructions in the target instruction queue; the runner sending a target notification to the target storage device through the target port, wherein the target notification is used to notify the target storage device that there are operation instructions to be executed, and the target storage device is used to receive the target notification; retrieving the target instructions from the target instruction queue, and the target storage device is further used to send the execution information through the target port after executing the target instructions and generating the execution information of the target instructions.

[0087] In some embodiments, the storage system further includes: a reference storage device; a processor node further includes: a metadata port; the process of the runner searching for the target metadata of the target coroutine task based on the target address information to obtain the operation location includes: the runner searching for the target metadata from the reference storage device through the reference port on the target processor node based on the target address information, wherein the metadata port includes a reference port and the reference storage device is used to store the metadata database.

[0088] In some embodiments, when the target request type is write, the runner allocates an operation position for the target coroutine task, including: when the target request type is write, after receiving the target coroutine task, the runner generates updated metadata for the target coroutine task according to the operation position; and the runner stores the updated metadata to a reference storage device through a reference port.

[0089] In some embodiments, the storage system further includes: multiple network interface cards (NICs), and a memory buffer is created in the processor node; before determining the location of the operation requested by the target request in one or more candidate storage devices in the target processor node based on the request information of the received target request, the method further includes: receiving the target request by the target NIC as a target receiving interface, wherein the target NIC is a NIC corresponding to the target processor node; and storing the request data of the target request in the target memory buffer in the target processor node corresponding to the target NIC according to the target mapping relationship when the target request type of the target request is write type, wherein the request data is the data requested by the target request to be written to the memory buffer. The target storage device is configured to: 1) store data in the storage system; 2) forward the target request to the node scheduler via the target network interface card (NIC); 3) forward the target request to the node scheduler if the target request type is read; 4) further configure the target storage device to: 5) read the requested data from the target memory buffer if the target request type is write; 6) execute the target instruction and generate execution information based on the requested data; 7) send the execution information to the target processor core via the target port; 8) execute the target instruction and generate execution information if the target request type is read; 9) store the target data in the target memory buffer, where the target data is the data requested by the target request to be read from the storage system; and 10) send the execution information to the target processor core via the target port.

[0090] In some embodiments, after updating the metadata database of the storage system according to the received execution information and sending the execution information to the sending interface corresponding to the target receiving interface, the method further includes: the target network interface card (NIC) receiving the execution information as a sending interface when the target request type of the target request is write type; the target NIC sending the execution information and target data to the target device that initiated the target request; the target NIC receiving the execution information as a sending interface when the target request type of the target request is read type; the target NIC reading the target data from the target memory buffer; and the target NIC sending the execution information and target data to the target device.

[0091] For a description of the features in the embodiment corresponding to the control method of the storage system, please refer to the relevant description of the embodiment corresponding to the storage system, which will not be repeated here.

[0092] Through the above description of the embodiments, those skilled in the art can clearly understand that the methods according to the above embodiments can be implemented by means of software plus necessary general-purpose hardware platforms. Of course, they can also be implemented by hardware, but in many cases the former is a better implementation method.

[0093] Embodiments of this application also provide a control device for a storage system. The storage system includes a node scheduler and multiple processor nodes. Each processor node includes a processor core, a processor port, and one or more candidate storage devices. The aforementioned control device for the storage system is applied to a target processor core in a target processor node among the multiple processor nodes. Figure 4 This is a structural block diagram of a control device for a storage system according to an embodiment of this application, such as... Figure 4 As shown, the device includes:

[0094] The determination module 402 is used to determine the operation location of the operation requested by the target request in one or more candidate storage devices in the target processor node based on the request information of the received target request. The request information is used to indicate the operation requested by the target request. The target request is allocated to the target processor node and sent to the target processor core by the node scheduler according to the received information of the target request and the target mapping relationship. The received information is used to indicate the target receiving interface of the storage system to receive the target request. The target mapping relationship is the correspondence between multiple receiving interfaces in the storage system and multiple processor nodes.

[0095] Generation module 404 is used to generate target instructions based on the target request and operation location;

[0096] The first sending module 406 is used to send the target instruction to the target storage device to which the operation location belongs through the target port on the target processor node. The processor port includes the target port. The target storage device is used to execute the target instruction, generate the execution information of the target instruction, and send the execution information to the target processor core through the target port. The execution information is used to indicate the execution result of the target instruction.

[0097] The update module 408 is used to update the metadata database of the storage system according to the received execution information, and send the execution information to the sending interface corresponding to the target receiving interface.

[0098] Through the above device, the node scheduler allocates a target processor node for the target request from multiple processor nodes based on the received target request information and target mapping relationship. The target request is forwarded to the target processor core within the target processor node. Requests received by each interface are processed by the corresponding processor core, initially ensuring the locality of read / write request execution and avoiding cross-core data transmission. After receiving the target request, the target processor core determines the operation location of the requested operation in one or more candidate storage devices within the target processor node based on the request information. It generates a target instruction based on the target request and operation location, and sends the target instruction to the target storage device corresponding to the operation location through the target port on the target processor node. The target storage device executes the target instruction and generates execution information, which is then sent back to the target processor core through the target port. The target processor core updates the storage system's metadata database and returns the execution result. This avoids cross-core operations during target request execution and unnecessary repeated loading of the target request context, improving the storage system's response rate. Therefore, it can solve the technical problem of slow read / write request response rates in related technologies, achieving the technical effect of improving the read / write request response rate of storage systems.

[0099] In some embodiments, the target processor core includes: a monitor and a runner; the determination module is further configured to: receive a target request by the monitor; convert the target request into a target task descriptor by the monitor, wherein the task descriptor includes request information; create a target coroutine task by the monitor based on the target task descriptor; submit the target coroutine task to the runner's local task queue by the monitor; extract the target coroutine task from the local task queue by the runner; and run the target coroutine task by the runner to obtain the operation position.

[0100] In some embodiments, the generation module is further configured to: run the target coroutine task by the runner to obtain the target instruction.

[0101] In some embodiments, the first sending module is further configured to: suspend the target coroutine task by the runner and send the target instruction to the target storage device through the target port.

[0102] In some embodiments, the update module is further configured to: monitor the execution information received by the target port by the monitor; find the coroutine task corresponding to the execution information by the monitor and obtain the target coroutine task; wake up the target coroutine task by the monitor; and update the metadata database by running the woken-up target coroutine task and sending the execution information to the sending interface.

[0103] In some embodiments, the determining module is further configured to: detect the target request type of the target coroutine task by the runner, wherein the request information includes the target request type; extract target address information from the request information by the runner when the target request type is a read type, wherein the target address information is used to indicate the logical address of the data requested to be read by the target request; find the target metadata of the target coroutine task based on the target address information to obtain the operation position; and allocate the operation position to the target coroutine task by the runner when the target request type is a write type.

[0104] In some embodiments, the generation module is further configured to: generate target instructions by the runner based on request information and operation location.

[0105] In some embodiments, the first sending module is further configured to: save the current status information of the target coroutine task by the runner and send the target instruction to the target storage device through the target port, wherein the current status information is used to indicate the current execution progress of the target coroutine task.

[0106] In some embodiments, the update module is further configured to: load current status information by the monitor and send the target coroutine task to the runner.

[0107] In some embodiments, the update module is further configured to: receive the target coroutine task from the runner; and continue to run the target coroutine task from the runner based on the current status information and execution information.

[0108] In some embodiments, the target processor core further includes: a target memory, in which a target instruction queue is created; and a first sending module, further configured to: store target instructions in the target instruction queue by the runner; send a target notification to the target storage device through a target port by the runner, wherein the target notification is used to notify the target storage device that there are operation instructions to be executed, and the target storage device is used to receive the target notification; extract target instructions from the target instruction queue, and the target storage device is further configured to send the execution information through the target port after executing the target instructions and generating the execution information of the target instructions.

[0109] In some embodiments, the storage system further includes: a reference storage device; a processor node further includes: a metadata port; and a determination module is further configured to: have the runner retrieve target metadata from the reference storage device through the reference port on the target processor node based on target address information, wherein the metadata port includes a reference port, and the reference storage device is used to store a metadata database.

[0110] In some embodiments, the determining module is further configured to: generate update metadata of the target coroutine task based on the operation location after receiving the target coroutine task, when the target request type is write type; and store the update metadata to the reference storage device through the reference port.

[0111] In some embodiments, the storage system further includes: multiple network interface cards (NICs), and a memory buffer is created in the processor node; the aforementioned control device further includes: a first receiving module, configured to receive the target request by a target NIC as a target receiving interface before determining the operation location of the operation requested by the target request in one or more candidate storage devices in the target processor node based on the request information of the received target request, wherein the target NIC is a NIC corresponding to the target processor node; and a storage module, configured to store the request data of the target request into the target memory buffer in the target processor node corresponding to the target NIC according to the target mapping relationship when the target request type of the target request is write type, wherein the request data is the data requested to be written by the target request. The storage system contains data; a first forwarding module, used by the target network interface card (NIC) to forward the target request to the node scheduler; a second forwarding module, used by the target NIC to forward the target request to the node scheduler when the target request type is read, wherein the target storage device is further configured to: read the requested data from the target memory buffer when the target request type is write; execute the target instruction and generate execution information based on the requested data; send the execution information to the target processor core through the target port; execute the target instruction and generate execution information when the target request type is read; store the target data in the target memory buffer, wherein the target data is the data requested by the target request to be read from the storage system; and send the execution information to the target processor core through the target port.

[0112] In some embodiments, the aforementioned control device further includes: a second receiving module, configured to receive the execution information by the target network interface card (NIC) as a sending interface when the target request type of the target request is write, after updating the metadata database of the storage system according to the received execution information and sending the execution information to the sending interface corresponding to the target receiving interface; a second sending module, configured to send the execution information and target data to the target device that initiated the target request by the target NIC; a third receiving module, configured to receive the execution information by the target NIC as a sending interface when the target request type of the target request is read; a reading module, configured to read the target data from the target memory buffer by the target NIC; and a third sending module, configured to send the execution information and target data to the target device by the target NIC.

[0113] For a description of the features of the control device of the storage system in the corresponding embodiment, please refer to the relevant description of the corresponding embodiment of the storage system, which will not be repeated here.

[0114] Embodiments of this application also provide an electronic device, including a memory and a processor, wherein the memory stores a computer program and the processor is configured to run the computer program to perform the steps in any of the above-described control method embodiments of the storage system.

[0115] Embodiments of this application also provide a computer-readable storage medium storing a computer program, wherein the computer program is configured to execute the steps in any of the above-described storage system control method embodiments when running.

[0116] In one exemplary embodiment, the aforementioned computer-readable storage medium may include, but is not limited to, various media capable of storing computer programs, such as a USB flash drive, read-only memory (ROM), random access memory (RAM), portable hard disk, magnetic disk, or optical disk.

[0117] Embodiments of this application also provide a computer program product, which includes a computer program that, when executed by a processor, implements the steps in any of the above-described storage system control method embodiments.

[0118] Embodiments of this application also provide another computer program product, including a non-volatile computer-readable storage medium storing a computer program, which, when executed by a processor, implements the steps in any of the above-described storage system control method embodiments.

[0119] Those skilled in the art will further recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of the various examples have been generally described in terms of functionality in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0120] The foregoing has provided a detailed description of a storage system, a control method for the storage system, and an apparatus for the storage system. Specific examples have been used to illustrate the principles and implementation methods of this application. The descriptions of the embodiments above are only intended to help understand the method and core ideas of this application. It should be noted that those skilled in the art can make various improvements and modifications to this application without departing from its principles, and these improvements and modifications also fall within the protection scope of the claims of this application.

Claims

1. A storage system, characterized in that, include: A node scheduler and multiple processor nodes, each processor node including a processor core, a processor port, and one or more candidate storage devices; The node scheduler is configured to allocate a target processor node for the target request from the plurality of processor nodes according to the received information of the target request and the target mapping relationship, wherein the received information is used to instruct the storage system to receive the target receiving interface of the target request, and the target mapping relationship is the correspondence between the plurality of receiving interfaces in the storage system and the plurality of processor nodes; and forward the target request to the target processor core in the target processor node; The target processor core is configured to determine, based on the request information of the target request, the operation location of the operation requested by the target request in one or more candidate storage devices within the target processor node; generate a target instruction based on the target request and the operation location; and send the target instruction to the target storage device to which the operation location belongs via a target port on the target processor node, wherein the processor port includes the target port. The target storage device is configured to execute the target instruction and generate execution information for the target instruction, wherein the execution information indicates the execution result of the target instruction; and to send the execution information to the target processor core through the target port. The target processor core is also used to update the metadata database of the storage system according to the execution information, and send the execution information to the sending interface corresponding to the target receiving interface.

2. The storage system according to claim 1, characterized in that, The target processor core includes: a monitor and a runner; The monitor is configured to receive the target request; convert the target request into a target task descriptor, wherein the task descriptor includes the request information; create a target coroutine task based on the target task descriptor; and submit the target coroutine task to the runner's local task queue. The runner is configured to: extract the target coroutine task from the local task queue; run the target coroutine task to obtain the operation position; run the target coroutine task to obtain the target instruction; suspend the target coroutine task and send the target instruction to the target storage device through the target port; The monitor is also used to monitor the execution information received by the target port; find the coroutine task corresponding to the execution information to obtain the target coroutine task; and wake up the target coroutine task. The runner is also used to update the metadata database by running the target coroutine task after it is woken up, and to send the execution information to the sending interface.

3. The storage system according to claim 2, characterized in that, The runner is further configured to detect the target request type of the target coroutine task, wherein the request information includes the target request type; if the target request type is a read type, extract target address information from the request information, wherein the target address information is used to indicate the logical address of the data requested to be read by the target request; find the target metadata of the target coroutine task based on the target address information to obtain the operation position; if the target request type is a write type, allocate the operation position to the target coroutine task; generate the target instruction based on the request information and the operation position; save the current status information of the target coroutine task and send the target instruction to the target storage device through the target port, wherein the current status information is used to indicate the current execution progress of the target coroutine task; The monitor is further configured to, after finding the coroutine task corresponding to the execution information and obtaining the target coroutine task, load the current status information and send the target coroutine task to the runner; The runner is also configured to receive the target coroutine task and continue to run the target coroutine task based on the current status information and the execution information.

4. The storage system according to claim 3, characterized in that, The target processor core also includes a target memory, in which a target instruction queue is created; The runner is further configured to store the target instruction in the target instruction queue; and send a target notification to the target storage device through the target port, wherein the target notification is used to notify the target storage device that there is an operation instruction to be executed; The target storage device is used to receive the target notification and extract the target instruction from the target instruction queue. The target storage device is further configured to send the execution information through the target port after the target instruction is executed and the execution information of the target instruction is generated.

5. The storage system according to claim 3, characterized in that, The storage system further includes: a reference storage device; the processor node further includes: a metadata port; The runner is further configured to retrieve the target metadata from the reference storage device through a reference port on the target processor node based on the target address information, wherein the metadata port includes the reference port; The reference storage device is used to store the metadata database; The runner is further configured to, when the target request type is write type, generate update metadata of the target coroutine task according to the operation position after receiving the target coroutine task; and store the update metadata to the reference storage device through the reference port.

6. The storage system according to claim 1, characterized in that, The storage system also includes: multiple network interface cards (NICs), and a memory buffer is created in the processor node; A target network interface card (NIC) among the plurality of NICs is used as the target receiving interface to receive the target request, wherein the target NIC is the NIC corresponding to the target processor node; when the target request type of the target request is write type, the request data of the target request is stored in the target memory buffer in the target processor node corresponding to the target NIC according to the target mapping relationship, wherein the request data is the data requested by the target request to be written to the storage system; the target request is forwarded to the node scheduler; when the target request type is read type, the target request is forwarded to the node scheduler. The target storage device is further configured to: read the requested data from the target memory buffer when the target request type is the write type; execute the target instruction and generate the execution information according to the request data; send the execution information to the target processor core through the target port; execute the target instruction and generate the execution information when the target request type is the read type; store the target data in the target memory buffer, wherein the target data is the data requested by the target request to be read from the storage system; and send the execution information to the target processor core through the target port. The target network interface card is further configured to: receive the execution information as the sending interface when the target request type of the target request is write type; send the execution information and the target data to the target device that initiated the target request; receive the execution information as the sending interface when the target request type of the target request is read type; read the target data from the target memory buffer; and send the execution information and the target data to the target device.

7. A control method for a storage system, characterized in that, The storage system includes a node scheduler and multiple processor nodes, each processor node including a processor core, a processor port, and one or more candidate storage devices. The method is applied to a target processor core in a target processor node among the multiple processor nodes, and the method includes: The operation requested by the target request is determined based on the request information received in the target request, and the operation location of the operation requested by the target request is determined in one or more of the candidate storage devices in the target processor node. The request information is used to indicate the operation requested by the target request. The target request is allocated to the target processor node and sent to the target processor core by the node scheduler according to the received information of the target request and the target mapping relationship. The received information is used to indicate the target receiving interface of the storage system to receive the target request. The target mapping relationship is the correspondence between multiple receiving interfaces in the storage system and multiple processor nodes. Generate target instructions based on the target request and the operation location; The target instruction is sent to the target storage device to which the operation location belongs through the target port on the target processor node, wherein the processor port includes the target port, the target storage device is used to execute the target instruction, generate execution information of the target instruction, and send the execution information to the target processor core through the target port, and the execution information is used to indicate the execution result of the target instruction; The metadata database of the storage system is updated according to the received execution information, and the execution information is sent to the sending interface corresponding to the target receiving interface.

8. A control device for a storage system, characterized in that, The storage system includes a node scheduler and multiple processor nodes, each processor node including a processor core, a processor port, and one or more candidate storage devices. The device is applied to a target processor core in a target processor node among the multiple processor nodes. The device includes: The determination module is used to determine the operation location of the operation requested by the target request in one or more candidate storage devices in the target processor node based on the request information of the received target request. The request information is used to indicate the operation requested by the target request. The target request is allocated to the target processor node and sent to the target processor core by the node scheduler according to the received information of the target request and the target mapping relationship. The received information is used to indicate the target receiving interface of the storage system to receive the target request. The target mapping relationship is the correspondence between multiple receiving interfaces in the storage system and multiple processor nodes. The generation module is used to generate target instructions based on the target request and the operation location; The first sending module is used to send the target instruction to the target storage device to which the operation location belongs through the target port on the target processor node, wherein the processor port includes the target port, the target storage device is used to execute the target instruction, generate execution information of the target instruction, and send the execution information to the target processor core through the target port, and the execution information is used to indicate the execution result of the target instruction; The update module is used to update the metadata database of the storage system according to the received execution information, and send the execution information to the sending interface corresponding to the target receiving interface.

9. An electronic device, characterized in that, include: Memory, used to store computer programs; A processor, configured to implement the steps of the control method for the storage system as described in claim 7 when executing the computer program.

10. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program, wherein the computer program, when executed by a processor, implements the steps of the control method for the storage system as described in claim 7.

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