Adaptive cascode gate bias generation circuit

Abstract

This disclosure relates to an adaptive cascode gate bias generation circuit. The circuit includes a first resistor, a second resistor, a current source, and a transistor. The first resistor is located between a voltage rail and a drive interconnect. The drive interconnect and the voltage rail are electrically connected to the first resistor. The second resistor is located between the drive interconnect and ground. Ground and the drive interconnect are electrically connected to the second resistor. The current source is located between the voltage rail and the drive interconnect. The drive interconnect and the voltage rail are electrically connected to the current source. The transistor is located between the drive interconnect and a snubber interconnect. The drive interconnect and the snubber interconnect are electrically connected to the transistor.

Description

Technical Field

[0001] This disclosure generally relates to communication systems, and more particularly to an adaptive cascode gate bias generation circuit. Background Technology

[0002] High-swing serial link transmitters are dedicated circuits used in high-speed communication systems. These dedicated circuits are designed to transmit data over a serial link, with a large output voltage swing. To improve the signal-to-noise ratio (SNR) by minimizing distortion over long distances or lossy channels, high-swing serial link transmitters implement differential signal transmission and reception, pre-emphasis, and impedance matching to enhance signal integrity. Summary of the Invention

[0003] One embodiment of this disclosure provides a circuit. The circuit includes: a first resistor located between a voltage rail and a drive interconnect, the drive interconnect and the voltage rail being electrically connected to the first resistor; a second resistor located between the drive interconnect and ground, the ground and the drive interconnect being electrically connected to the second resistor; a current source located between the voltage rail and the drive interconnect, the drive interconnect and the voltage rail being electrically connected to the current source; and a transistor located between the drive interconnect and a snubber interconnect, the drive interconnect and the snubber interconnect being electrically connected to the transistor.

[0004] Another embodiment of this disclosure provides a transmitter. The transmitter includes a gate bias generator and an output driver. The gate bias generator includes: a current source located between a voltage rail and a drive interconnect, the drive interconnect and the voltage rail being electrically connected to the current source; a diode-connected transistor located between the drive interconnect and a snubber interconnect, the diode-connected transistor being electrically connected to the drive interconnect and the snubber interconnect; and a current sink located between the snubber interconnect and ground, ground and the snubber interconnect being electrically connected to the current sink. The output driver includes: an output transistor electrically connected in series with a cascode transistor and ground, the gate of the diode-connected transistor being directly electrically connected to the gate of the output transistor. Attached Figure Description

[0005] The accompanying drawings, which are incorporated in and form a part of this specification, illustrate examples of this disclosure and, together with the description, explain the principles of the examples.

[0006] Figure 1 The illustration depicts an exemplary high-swing serial link transmitter according to one or more embodiments of the present disclosure.

[0007] Figure 2The illustration shows an exemplary gate bias generator and output driver according to one or more embodiments of the present disclosure.

[0008] Figure 3 The illustration depicts an exemplary gate bias generator according to one or more embodiments of the present disclosure.

[0009] Figure 4 The illustration depicts an exemplary output driver according to one or more embodiments of the present disclosure.

[0010] Figure 5 The illustration depicts an exemplary gate bias generator according to one or more embodiments of the present disclosure.

[0011] Figure 6 The illustration depicts an exemplary gate bias generator according to one or more embodiments of the present disclosure.

[0012] Figure 7 The illustrations illustrate exemplary comparisons based on one or more embodiments of this disclosure.

[0013] Figure 8 The illustrations illustrate exemplary comparisons based on one or more embodiments of this disclosure.

[0014] Figure 9 The illustrations illustrate exemplary comparisons based on one or more embodiments of this disclosure.

[0015] In the accompanying drawings, similar reference numerals and numbers indicate identical or similar components. For consistency, similar elements in each figure are represented by similar reference numerals and numbers. Unless otherwise indicated, similar elements and method steps are represented by similar reference numerals. Detailed Implementation

[0016] The technical solutions in this specification are described below with reference to the accompanying drawings. Exemplary embodiments are described in detail with reference to the accompanying drawings.

[0017] The terminology used herein is for illustrative purposes only and is not intended to limit this disclosure. Unless otherwise defined, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains and upon understanding the disclosure of this application.

[0018] Terms such as those defined in commonly used dictionaries will be interpreted as having meanings consistent with their meanings in the relevant field and in the context of the disclosure of this application. Although the art has been described with reference to certain examples, those skilled in the art will recognize that changes in form and detail may be made without departing from the scope of the discussion.

[0019] In long-distance serial link applications with significant channel losses, high-swing transmission with peak-to-peak swings exceeding 1.5 V is typically required. High-swing serial link transmitters often incorporate an output cascode amplifier in their output drivers to protect the core device's reliability and improve transmission linearity. The gate bias of the output cascode amplifier is crucial for meeting linearity specifications and maintaining the reliability of the high-swing serial link transmitter. Conventional cascode gate biasing techniques are either sensitive to process and temperature corners or to resistance corners and input bias currents. Therefore, an improved gate bias generator is needed in the art.

[0020] refer to Figure 1 The diagram illustrates an exemplary high-swing serial link transmitter 100. The high-swing serial link transmitter 100 may include a gate bias generator 110, an output driver 120, and a voltage rail 130. The voltage rail 130 is a wiring network that distributes the supply voltage VDD through the high-swing serial link transmitter 100. The supply voltage VDD is a potential higher than ground. Ground serves as a zero-voltage reference point in the high-swing serial link transmitter 100. Those skilled in the art will appreciate that additional components may be present in the high-swing serial link transmitter 100.

[0021] Now transferred to Figure 2 Gate bias generator 110 is a circuit designed to generate a gate bias voltage V (bias). Thus, gate bias generator 110 may be a device in itself. Gate bias generator 110 may include a current source 211, a transistor QP23, and a current sink 212. Gate bias generator 110 also includes resistors R21 and R22. Those skilled in the art will understand that additional components may be present in gate bias generator 110.

[0022] Current source 211 is a current mirror comprising a reference transistor QP21 and a mirror transistor QP22. The gates of transistors QP21 and QP22 are connected together. Similarly, the sources of transistors QP21 and QP22 are also connected together.

[0023] Current source 211 converts the supply voltage VDD from voltage rail 130 into a stable reference current I(ref). Current source 211 pushes the reference current I(ref) onto reference interconnect 221. Reference interconnect 221 is wiring in gate bias generator 110. For example, transistor QP21 is shown in a diode-connected configuration with its drain shorted to its gate, allowing the reference current I(ref) from voltage rail 130 to flow through transistor QP21.

[0024] Because current source 211 is a current mirror, mirror transistor QP22 can replicate or scale the reference current I(ref) to push drive current I(drive) onto drive interconnect 222.

[0025] In such examples, the drive current I(drive) may be exactly proportional to the reference current I(ref). The drive interconnect 222 is wired within the gate bias generator 110. For example... Figure 2 As illustrated in the diagram, a portion of the drive interconnect 222 extends from the mirror transistor QP22, while another portion of the drive interconnect 222 extends from resistors R21 and R22.

[0026] Transistor QP23 is shown as a diode-connected transistor, where the drain and gate of transistor QP23 are shorted together. As a diode-connected transistor, transistor QP23 can behave like a diode. For example, the source of transistor QP23 can act as the anode of a diode, while the cathode of the diode acts as both the drain and gate of transistor QP23. Behaving like a diode, current can flow through transistor QP23 in one direction, from the source to the drain of transistor QP23.

[0027] Current sink 212 is a current mirror containing bias transistor QN20 and mirror transistors QN21 and QN22. The gates of transistors QN20, QN21, and QN22 are connected together. Similarly, the sources of transistors QN20, QN21, and QN22 are also connected together. Current sink 212 draws a fixed amount of bias current I (bias) to ground in bias interconnect 231. Bias interconnect 231 is the wiring in gate bias generator 110, such as... Figure 2 The diagram illustrates this. For example, the drain and gate of transistor QN20 are shorted together, and transistor QN20 is shown in a diode-connected configuration so that the bias current I(bias) from voltage rail 130 can flow through transistor QN20 to ground.

[0028] The mirror transistor QN21 can replicate or scale the bias current I(bias) to pull a fixed amount of reference current I(ref) in the reference interconnect 221 to ground. Figure 2 In the example, the mirror transistor QN21 and the reference transistor QP21 are directly connected in series. A certain amount of reference current I(ref) from the reference transistor QP21 can flow along the reference interconnect 221 to the mirror transistor QN21.

[0029] Reference transistor QP21 may attempt to push a specific amount of reference current I(ref) from voltage rail 130 onto reference interconnect 221, while mirror transistor QN21 may simultaneously attempt to pull a set amount of reference current I(ref) from reference interconnect 221 to ground. This push-pull dynamic between reference transistor QP21 and mirror transistor QN21 ensures that the combination of reference transistor QP21 and mirror transistor QN21 in series can regulate the amount of reference current I(ref) in reference interconnect 221. For example, in some embodiments where mirror transistor QN21 can pull a smaller amount of reference current I(ref) from reference interconnect 221 than reference transistor QP21 pushes onto reference interconnect 221, mirror transistor QN21 can limit the amount of reference current I(ref) flowing in reference interconnect 221 to an amount that varies proportionally to bias current I(bias). In other embodiments where the mirror transistor QN21 can draw a larger amount of reference current I(ref) from the reference interconnect 221 than the reference transistor QP21 pushes onto the reference interconnect 221, the reference transistor QP21 can limit the amount of reference current I(ref) flowing in the reference interconnect 221 to the amount drawn from the voltage rail 130.

[0030] The mirror transistor QN22 can replicate or scale the bias current I(bias) to pull a fixed amount of sink current I(sink) from the drain of transistor QP23 to ground in the sink interconnect 232. For example... Figure 2 As illustrated in the diagram, the absorption interconnect 232 is wired in the gate bias generator 110.

[0031] exist Figure 2 In this example, transistor QP23 is electrically connected in series with mirror transistors QP22 and QN22. Mirror transistor QP22 replicates or scales a reference current I(ref) to generate a drive current I(drive) in the drive interconnect 222 of gate bias generator 110. In this example, the drive current I(drive) may be exactly proportional to the reference current I(ref). Mirror transistor QN22 replicates or scales a bias current I(bias) to generate a sink current I(sink) in the sink interconnect 232 of gate bias generator 110. In this example, the sink current I(sink) may be exactly proportional to the bias current I(bias).

[0032] Mirror transistor QP22 may attempt to push a specific amount of drive current I from voltage rail 130 onto drive interconnect 222, while mirror transistor QN22 may simultaneously attempt to pull a set amount of sink current I from sink interconnect 232 to ground. This push-pull dynamic between mirror transistors QP22 and QN22 ensures that the combination of mirror transistor QP22 in series with mirror transistor QN22 can regulate the amount of current flowing from the source of transistor QP23 through transistor QP23 to the drain of transistor QP23. For example, in some embodiments where mirror transistor QN22 draws a smaller amount of sink current I from sink interconnect 232 than it can push onto drive interconnect 222, mirror transistor QN22 can limit the current flowing through transistor QP23 to an amount proportional to the bias current I. In other embodiments where the mirror transistor QN22 can draw a larger amount of sink current I from the sink interconnect 232 than the mirror transistor QP22 pushes onto the drive interconnect 222, the mirror transistor QP22 can limit the amount of current that can flow through the transistor QP23 to the amount of drive current I drawn from the voltage rail 130.

[0033] The gate bias generator 110 also includes resistors R21 and R22. Resistor R21 is a passive electronic component whose resistance value can be adjusted manually and / or electronically. Resistor R22 is another passive electronic component whose resistance value can be adjusted manually and / or electronically. The resistance values ​​of resistors R21 and R22 can be adjusted independently of each other. Resistors R21 and R22 in the gate bias generator 110 can exist as a resistive voltage divider circuit, wherein resistor R21 is directly electrically connected to voltage rail 130, and resistor R22 is directly electrically connected to resistor R21 and ground.

[0034] exist Figure 2 In the example, transistors QP21, QP22, and QP23 have the same conductivity type. For example, current source 211 can exist as a PMOS current source with P-type transistors QP21 and QP22. Transistor QP23 is depicted as a PMOS diode-connected transistor. Transistors QN21, QN22, and QN23 have the same conductivity type. Current sink 212 is depicted as an NMOS current sink with N-type transistors QN20, QN21, and QN22. Those skilled in the art will understand that the conductivity types of transistors QP21, QP22, and QP23 are opposite to those of transistors QN20, QN21, and QN22.

[0035] and Figure 2 Compared to the example, Figure 3The diagram illustrates a gate bias generator 110A. The gate bias generator 110A may include a current sink 311, a transistor QN33, and a current source 312. The gate bias generator 110A also includes resistors R31 and R32. The current sink 311... Figure 3 The current source 312 is depicted as an NMOS current sink with N-type transistors QN31, QN32, and QN33. The current source 312 is depicted as a PMOS current source with P-type transistors QP30, QP31, and QP32. Those skilled in the art will understand that additional components may be present in the gate bias generator 110A.

[0036] The output driver 120 of the high-swing serial link transmitter 100 can drive a load. (Reference) Figure 2 The output driver 120 may contain a plurality of identical unit cells 121(1)-(N), where “N” is an integer. The unit cells 121(1)-(N) may be collectively referred to as “unit cell 121”. Any one of the unit cells 121(1)-(N) may be individually referred to as “unit cell 121”. The unit cells 121(1)-(N) are electrically connected in parallel with each other.

[0037] Each of unit cells 121(1)-(N) may contain P-type transistors QP24, QP25, and QP26. Enable signals may include enable 122(1)-(N). Figure 2 In the example, unit cell 121(1) is one of unit cells 121(1)-(N). Turning off transistor QP24 in unit cell 121(1) activates unit cell 121(1). Similarly, turning off transistor QP24 in unit cell 121(1) deactivates unit cell 121(1). The number of unit cells 121 activated during any given time period is a user-selectable parameter. Specifically, enable 122(1) is one of the enable signals (enable 122(1)-(N)). Turning QP24 off and on in unit cell 121(1) occurs in response to enable 122(1). For example, enabling 122(1) at a certain logic level causes QP24 to close. Conversely, enabling 122(1) at another logic level causes QP24 to open.

[0038] Common-source cascode transistors QP25 and QP26 can form a differential pair of input devices in a common-source configuration. Common-source cascode transistors QP25 and QP26 can operate in differential mode. For example, input D(1) is applied to the gate of common-source cascode transistor QP25. Input Db(1) is applied to the gate of common-source cascode transistor QP26. Inputs D(1) and Db(1) may be complementary signals (input Db(1) = "NOT" input D(1)). As complementary signals, one of inputs D(1) and Db(1) is logic high, while the other of inputs D(1) is logic low at any given time. As a result of the complementary nature of inputs D(1) and Db(1), common-source cascode transistors QP25 and QP26 can drive current I(+) or current I(-) at any given time. For example, common-source cascode transistor QP25 is not turned on at any given time that common-source cascode transistor QP26 is turned on. Similarly, the cascode transistor QP25 is turned on at any given time when the cascode transistor QP26 is not turned on.

[0039] Output driver 120 may also include drive circuitry 123. Drive circuitry 123 may include load resistors R23 and R24 and output transistors QP27 and QP28. Output transistors QP27 and QP28 may form a differential pair of output devices in a common-gate configuration. The term "current swing" as used herein refers to the change in current when the input signal changes. Output transistors QP27 and QP28 reduce any swing in the common-mode voltages Vcom(+) and Vcom(-) to prevent large voltage swings at the drains of cascode transistors QP25 and QP26 in unit cell 121. This prevents device breakdown in unit cell 121 and also helps maintain the linearity of the differential voltages TX(+) and TX(-).

[0040] like Figure 2 As illustrated in the example, output transistors QP27 and QP28 are connected in series with common-source and common-gate transistors QP25 and QP26 and ground, respectively.

[0041] The gate of transistor QP23 is directly electrically connected to the gates of output transistors QP27 and QP28. Transistors QP27 and QP28 can replicate or scale the sink current I to pull out a fixed amount of output current out(+) and out(-) from unit cell 121, respectively.

[0042] The drains of output transistors QP27 and QP28 can be used as differential outputs. The drive circuit 123 can output differential voltages TX(+) and TX(-) from the drains of output transistors QP27 and QP28, respectively. For example, the output from the drive circuit 123 is located at the drains of output transistors QP27 and QP28, where output transistors QP27 and QP28 can convert common-mode voltages Vcom(+) and Vcom(-) into differential voltages TX(+) and TX(-), respectively. The drain of transistor QP23 is directly electrically connected to the gates of output transistors QP27 and QP28. Those skilled in the art will understand that additional components may be present in the drive circuit 123.

[0043] exist Figure 2 In the example, those skilled in the art will understand that the output driver 120 can exist as a P-type output driver 120 having P-type transistors QP24-QP28. Figure 2 Compared to the example, Figure 4 The diagram illustrates an N-type output driver 120(A). Output driver 120(A) may include resistors R43, R44 and N-type transistors QN44 to QN48. Those skilled in the art will appreciate that additional components may be present in output driver 120(A).

[0044] Maintaining stable and consistent common-mode voltages Vcom(+) and Vcom(-) is crucial for the linearity and reliability of the output driver 120. For example, higher common-mode voltage levels Vcom(+) and Vcom(-) degrade the linearity of unit cell 121, while lower common-mode voltage levels degrade the linearity of drive circuit 123. Furthermore, higher common-mode voltage levels Vcom(+) and Vcom(-) can increase the drain-source voltage across each output transistor QP27 and QP28, while lower common-mode voltage levels can increase the voltage across unit cell 121, posing a risk of device breakdown in unit cell 121. Therefore, the optimal common-mode voltage levels Vcom(+) and Vcom(-) are critical for the overall linearity and reliability of the high-swing serial link transmitter 100.

[0045] To maintain optimal linearity and reliability of the high-swing serial link transmitter 100 during process and temperature fluctuations, it is crucial that the common-mode voltages Vcom(+) and Vcom(-) remain constant during these periods. Therefore, the gate bias generator 110 must be configured to minimize the impact of process and temperature variations.

[0046] Now transferred to Figure 5The diagram illustrates a gate bias generator comparison example 510. Gate bias generator comparison example 510 may include resistors R51 and R52. For simplicity and ease of understanding, the common-mode voltages Vcom(+) and Vcom(-) may each be labeled "V(com)", making... Figure 5 The gate bias voltage V(bias) is given by the following formula:

[0047]

[0048] in,

[0049] “VGS(casc)” refers to the average gate-source voltage of transistors QP27 and QP28.

[0050] As a drawback of the gate bias generator comparison example 510, VGS(casc) in equation (1) may vary significantly during process and temperature fluctuations.

[0051] Now transferred to Figure 6 The diagram illustrates a gate bias generator comparison example 610. Gate bias generator comparison example 610 may include a transistor QP61 and resistors R61 and R62. Transistor QP61 is shown as a diode-connected transistor, with its drain and gate shorted together. For simplicity and ease of understanding, the common-mode voltages Vcom(+) and Vcom(-) can each be labeled "V(com)", making... Figure 6 The gate bias voltage V(bias) is given by the following formula:

[0052]

[0053] in,

[0054] “VGS(61)” is the gate-source voltage of transistor QP61.

[0055] “VGS(casc)” refers to the average gate-source voltage of transistors QP27 and QP28.

[0056] As a drawback of the gate bias generator comparative example 610, VGS(casc) in equation (2) may vary significantly during process and temperature fluctuations. For example, in equation (2) As implied, V(com) strongly depends on the bias current I(bias) and the values ​​of resistors R61 and R62. Consequently, the gate bias generator comparison example 610 is sensitive to the accuracy of the bias current I(bias) and the resistor corners. Typically, Figure 6In the example, the bias current I (bias) is generated by a bandgap circuit. This bandgap circuit is typically located far from the output driver 120 and may happen to generate a significant amount of bias current for all the transmitter and receiver circuitry on the integrated circuit chip. Figure 6 In the example, each bias current on the integrated circuit chip can flow through many current mirrors. Generally, unless complex digital calibration is performed, otherwise... Figure 6 The bias current I(bias) value in the example is inaccurate. The values ​​of resistors R61 and R62 vary by up to 20% across different resistance corners. Therefore, in Figure 6 Additional resistor calibration may be required in some examples, which increases the design complexity of gate bias generator comparison example 610.

[0057] As an alternative Figure 2 The gate bias generator 110 is compared with gate bias generator comparison examples 510 and 610. (See reference) Figure 2 Resistors R21 and R22 in the gate bias generator 110 can function as a resistive voltage divider circuit, where resistor R21 is directly electrically connected to the voltage rail 130, and resistor R22 is directly electrically connected to resistor R21 and ground. For simplicity and ease of understanding, the common-mode voltages Vcom(+) and Vcom(-) can each be labeled "V(com)", such that:

[0058]

[0059] in,

[0060] “VGS(23)” is the gate-source voltage of transistor QP23.

[0061] “VGS(casc)” refers to the average gate-source voltage of transistors QP27 and QP28.

[0062] “I(n)” represents the sink current I(sink).

[0063] "I(p)" represents the drive current I(drive).

[0064] Since both the current source 211 and the current sink 212 are current mirrors, the values ​​of the drive current I(drive) and the sink current I(sink) are almost the same, resulting in:

[0065]

[0066] The difference between the sink current I and the drive current I is approximately zero; almost no current flows from the source of transistor QP23 into the voltage divider R21 and R22. Because... It is approximately 0, therefore the gate voltage in equation (3) is The term is approximately 0, resulting in a gate voltage independent of the resistor corners, thus making calibration of resistors R21 and R22 unnecessary. Similarly, in equation (1), VGS(23) and VGS(casc) cancel each other out, since transistors QP23, QP27, and QP26 exhibit the same performance characteristics under similar operating conditions.

[0067] Now transferred to Figure 7 , 8 Figure 9 illustrates a comparison of the effectiveness of the techniques used in the bias output transistors QP27 and QP28 of the drive circuit 123. Evaluation metrics may include changes in the common-mode voltages Vcom(+) and Vcom(-), collectively referred to as "V(com)".

[0068] refer to Figure 7 The diagram illustrates the comparison between common-mode voltage V(com) and process / temperature variations. Figure 7 The vertical axis of the graph represents the common-mode voltage V(com). Figure 7 The code shown at the level of the diagram describes a simulated scenario that takes into account process (P) variations that may occur during the semiconductor fabrication of the exemplary high-swing serial link transmitter 100 and temperature (T) variations during the operation of the exemplary high-swing serial link transmitter 100.

[0069] Figure 7 The process codes can include typical-typical (TT) for nominal transistor performance, slow-slow (SS) for slow NMOS and PMOS performance, fast-fast (FF) for fast NMOS and PMOS performance, fast-slow (FS) for fast NMOS and slow PMOS performance, and slow-fast-fast (SF) for slow NMOS and fast PMOS performance. Temperature codes can include nominal temperature (NT) for room temperature (~25°C), low temperature (LT) for extremely cold conditions (e.g., -40°C), and high temperature (HT) for high temperatures (e.g., 125°C). These codes can be mixed to produce combinations such as TT NT (typical process, nominal temperature), SSLT (slow process, low temperature), FF HT (fast process, high temperature), and SF NT (slow NMOS, fast PMOS at nominal temperature).

[0070] exist Figure 7In the comparisons, the dashed lines representing data points for gate bias generator comparison example 510 indicate a lack of process / temperature tracking, as evidenced by the significant variation in common-mode voltage V(com). Both the dashed lines representing data points for gate bias generator comparison example 610 and the solid lines representing data points for gate bias generator 110 indicate similarly effective process / temperature tracking, resulting in improved linearity across manufacturing process and operating temperature variations.

[0071] Figure 8 The diagram illustrates the comparison between the common-mode voltage V(com) and the bias current I(bias). Figure 9 middle, Figure 9 The diagram illustrates the comparison between the common-mode voltage V(com) and the resistor corner. Figure 9 The Rlow, Rmid, and Rhigh resistor corners represent the minimum (Rlow), nominal (Rmid), and maximum (Rhigh) resistance values ​​caused by variations in manufacturing process and temperature. The Rlow, Rmid, and Rhigh resistor corners indicate the circuit reliability and performance under worst, typical, and best resistance variations due to differences in manufacturing process and temperature. The dashed line representing the data points of gate bias generator comparison example 610 is compared with the solid line representing the data points of gate bias generator 110. Figure 8 and 9 This indicates that gate bias generator 110 is less sensitive to resistor corners than gate bias generator comparison example 610, and is also much less affected by the bias current I (bias) value.

[0072] like Figure 7 , 8 As shown in comparison 9, gate bias generator 110 is superior to both gate bias generator comparative example 510 and gate bias generator comparative example 610. Therefore, gate bias generator 110 can eliminate the shortcomings of the comparative examples by being insensitive to any changes in process and temperature corners, to any changes in resistor corners, and to any changes in bias current I (bias).

[0073] In some configurations, transistors QP21, QP22, QN21, and QN22 may reside in the same block of an integrated circuit chip. In those instances, the mismatch (if any) between the sink current I and the drive current I may depend solely on the current mirror accuracy of transistors QP21, QP22, QN21, and QN22. Consequently, the common-mode voltages Vcom(+) and Vcom(-) may happen to be insensitive to any fluctuations in the bias current I(bias).

[0074] Those skilled in the art will also understand that the arrangement or interconnection of components, such as those described as “coupled,” “connected,” “above,” “below,” or similar terms, allows for indirect connections or the insertion of components or layers.

[0075] Certain operations of the methods according to this technology or the systems performing those methods may be schematically illustrated in the accompanying drawings or otherwise discussed herein. Unless otherwise specified or limited, the representation of specific operations in a particular spatial order in the accompanying drawings may not necessarily require those operations to be performed in a specific order corresponding to that spatial order. Accordingly, certain operations illustrated in the accompanying drawings or disclosed herein may be performed in a different order than explicitly stated or described, as appropriate for specific examples of this technology. Furthermore, in some examples, certain operations may be performed in parallel or partially in parallel, including by dedicated parallel processing devices or independent computing devices configured to interoperate as part of a large system.

[0076] As used herein, unless otherwise specified or defined, “or” indicates a non-exclusive list of components or operations that may exist in any kind of combination, rather than an exclusive list of components that exist only as substitutes for each other. For example, a list of “A, B, or C” indicates the following options: A; B; C; A and B; A and C; B and C; and A, B, and C.

[0077] Accordingly, as used herein, the term “or” is intended to indicate an exclusive choice only when preceded by an exclusive term, such as “any one,” “only one of,” or “exact one of.” Furthermore, a list beginning with “one or more” (and variations thereof) and containing “or” to separate the listed elements indicates an option for one or more of any or all of the listed elements.

[0078] For example, the phrases “one or more of A, B or C” and “at least one of A, B or C” indicate the following options: one or more A; one or more B; one or more C; one or more A and one or more B; one or more B and one or more C; one or more A and one or more C; and one or more of A, B and C.

[0079] Similarly, a list beginning with "multiple" (and its variations) and containing "or" to separate the listed elements indicates an option for multiple instances of any or all of the listed elements. For example, the phrases "multiple of A, B, or C" and "two or more of A, B, or C" indicate the following options: A and B; B and C; A and C; and A, B, and C.

[0080] Generally, as used herein, when preceded by an exclusive term such as “any one,” “only one of,” or “exact one of,” the term “or” indicates only an exclusive alternative (e.g., “one or another but not both”).

[0081] Any marks mentioned herein may be registered trademarks under common law or by third parties, whether associated with or not with the applicant or assignee. The use of these marks is exemplary and should not be construed as descriptive or limiting the scope of the disclosed or claimed embodiments to the material associated only with these marks.

[0082] Unless the context clearly indicates otherwise, the articles “a” and “the” are also intended to include the plural form.

[0083] The terms “comprising,” “including,” and “having” specify the presence of the stated features, numbers, operations, components, elements, and / or combinations thereof, but do not exclude the presence or addition of one or more other features, numbers, operations, components, elements, and / or combinations thereof.

[0084] Throughout the application, ordinal numbers (e.g., first, second, third, etc.) may be used as adjectives for elements (i.e., any noun in the application).

[0085] Although terms such as “first,” “second,” and “third” may be used herein to describe various components, assemblies, regions, layers, or sections, such components, assemblies, regions, layers, or sections are not limited by these terms.

[0086] Instead, these terms are used only to distinguish one component, assembly, region, layer, or section from another component, assembly, region, layer, or section.

[0087] Unless explicitly stated otherwise, such as through the use of the terms “before,” “after,” “single,” and other such terms, the use of ordinal numbers does not imply or create any particular order of elements, nor does it limit any element to merely a single element.

[0088] Conversely, ordinal numbers are used to distinguish between components.

[0089] For example, the first element is different from the second element, and the first element may encompass more than one element and is located after (or before) the second element in the element order.

[0090] Therefore, without departing from the teachings of the examples, the first component, assembly, region, layer, or section mentioned in the examples described herein may also be referred to as the second component, assembly, region, layer, or section.

Claims

1. A circuit comprising: A first resistor is located between a voltage rail and a drive interconnect, wherein the drive interconnect and the voltage rail are electrically connected to the first resistor. A second resistor is located between the drive interconnect and ground, and ground and the drive interconnect are electrically connected to the second resistor; A current source is located between the voltage rail and the drive interconnect, the drive interconnect and the voltage rail being electrically connected to the current source; and A transistor is located between the drive interconnect and the absorber interconnect, which are electrically connected to the transistor.

2. The circuit according to claim 1, further comprising: A current absorber is located between the absorber interconnect and ground, and ground and the absorber interconnect are electrically connected to the current absorber.

3. The circuit according to claim 2, wherein the current absorber is directly electrically connected to the voltage rail.

4. The circuit of claim 2, wherein the current absorber is configured to draw the absorbed current from the absorber interconnect to ground.

5. The circuit of claim 2, wherein the current sink is located between a reference interconnect and ground, and the reference interconnect is electrically connected to the current sink.

6. The circuit of claim 5, wherein the current source is located between the voltage rail and the reference interconnect, and the reference interconnect is electrically connected to the current source.

7. The circuit according to claim 1, wherein the transistor is a diode-connected transistor.

8. The circuit of claim 1, wherein the drain of the transistor is shorted to the gate.

9. The circuit of claim 1, wherein the current source is configured to push drive current from the voltage rail to the drive interconnect.

10. The circuit of claim 1, wherein the current source is configured to mirror a reference current to generate a drive current.

11. The circuit of claim 10, wherein the current source is configured to generate the drive current by replicating the reference current.

12. The circuit of claim 10, wherein the current source is configured to generate the drive current by scaling the reference current proportionally.

13. A transmitter comprising: A gate bias generator, the gate bias generator comprising: A current source is located between a voltage rail and a drive interconnect, wherein the drive interconnect and the voltage rail are electrically connected to the current source; A diode-connected transistor is located between the drive interconnect and the snub interconnect, the diode-connected transistor being electrically connected to both the drive interconnect and the snub interconnect. A current absorber is located between the absorption interconnect and ground, and ground and the absorption interconnect are electrically connected to the current absorber; and Output driver, the output driver comprising: An output transistor is electrically connected in series with a common-source, common-gate transistor and ground, and the gate of the diode-connected transistor is directly electrically connected to the gate of the output transistor.

14. The transmitter of claim 13, further comprising: A first resistor is located between the voltage rail and the drive interconnect, and the drive interconnect and the voltage rail are electrically connected to the first resistor. and A second resistor is located between the drive interconnect and ground, and ground and the drive interconnect are electrically connected to the second resistor.

15. The transmitter of claim 13, wherein the drain and gate of the diode-connected transistor are shorted together.

16. The transmitter of claim 13, wherein the output transistor and the diode-connected transistor have the same conductivity type.

17. The transmitter of claim 13, wherein the current absorber is directly electrically connected to the voltage rail.

18. The transmitter of claim 13, wherein the current absorber is configured to draw the absorbed current from the absorber interconnect to ground.

19. The transmitter of claim 13, wherein the current absorber is located between a reference interconnect and ground, the reference interconnect being electrically connected to the current absorber.

20. The transmitter of claim 19, wherein the current source is located between the voltage rail and the reference interconnect, the reference interconnect being electrically connected to the current source.

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