Analog-digital conversion device and analog-digital conversion method
By employing two current sources to alternately generate slope signals in a time-interleaved slope analog-to-digital converter, the nonlinearity problem of the current source is solved, thereby improving conversion accuracy and stability.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- REALTEK SEMICON CORP
- Filing Date
- 2024-12-18
- Publication Date
- 2026-06-19
Smart Images
Figure CN122247421A_ABST
Abstract
Description
Technical Field
[0001] This disclosure relates to analog-to-digital conversion apparatus and methods, and more particularly to analog-to-digital conversion apparatus and methods that can improve the nonlinearity of the current source of a slope signal generator. Background Technology
[0002] Analog-to-digital converters (ADCs) are commonly used in electronic devices to convert analog signals into digital signals that the devices can process. A time-interleaved slope ADC is one type of ADC. The slope generator of a time-interleaved slope ADC typically uses a metal-oxide-semiconductor field-effect transistor (MOSFET) as its current source. Due to the channel length modulation effect and short channel effects, the current provided by this current source is related to VSD (source-drain voltage). Taking a PMOS (P-type metal-oxide-semiconductor field-effect transistor) current source as an example, the higher the slope signal, the smaller the VSD and the smaller the current |IDS|. The formula for the slope signal is as follows:
[0003]
[0004] In Equation 1, Vslope is the slope signal, I is the current, t is the time, and C is the capacitance value. Assuming that the time t and the capacitance value C are fixed, if the current I is not a fixed value and changes with VSD, then the slope signal Vslope is not a charging curve with a fixed slope, and it introduces a nonlinear component. Summary of the Invention
[0005] In view of the shortcomings of the prior art, one of the objectives of this disclosure is (but not limited to) to provide an analog-to-digital conversion apparatus and an analog-to-digital conversion method to improve the shortcomings of the prior art.
[0006] In some embodiments, the analog-to-digital conversion device includes a slope signal generator and a comparator. The slope signal generator is used to generate a slope signal based on a first current source in a first sub-voltage range of the voltage range, and to generate a slope signal based on a second current source in a second sub-voltage range of the voltage range, wherein the slope signal rises and falls back within the voltage range with at least one slope. The comparator is used to generate an output signal based on the slope signal and an input signal.
[0007] In some embodiments, the analog-to-digital conversion method includes: generating a slope signal in a first sub-voltage range of a voltage range based on a first current source using a slope signal generator, and generating a slope signal in a second sub-voltage range of a voltage range based on a second current source, wherein the slope signal rises and falls back and forth in the voltage range with at least one slope; and generating an output signal using a comparator based on the slope signal and an input signal.
[0008] The technical means embodied in the embodiments of this disclosure can improve at least one of the shortcomings of the prior art. The analog-to-digital conversion apparatus and analog-to-digital conversion method of this disclosure can improve the nonlinearity of the current source of the slope signal generator.
[0009] The features, implementation, and technical effects of this disclosure are described in detail below with reference to the accompanying drawings. Attached Figure Description
[0010] Figure 1 This is a schematic diagram of an analog-to-digital converter according to some embodiments of the present disclosure;
[0011] Figure 2 This is a flowchart illustrating an analog-to-digital conversion method according to some embodiments of this disclosure;
[0012] Figure 3 A timing diagram of an analog-to-digital converter is shown according to some embodiments of this disclosure;
[0013] Figure 4 This is a schematic diagram of a current source drawn according to some embodiments of this disclosure;
[0014] Figure 5 A schematic diagram of the current and voltage of a slope signal generator according to some embodiments of this disclosure; and
[0015] Figure 6 This is a schematic diagram of a current source drawn according to some embodiments of this disclosure.
[0016] Symbol Explanation
[0017] 100: Analog-to-digital converter
[0018] 110: Slope signal generator
[0019] 120: Comparator
[0020] 200: Method
[0021] 210-220: Steps
[0022] A1~A4: Period
[0023] C1, C2: Period
[0024] CS1: First current source
[0025] CS2: Second current source
[0026] Cs3: Capacitor
[0027] CSA, CSB, CSC, CSD: Current Source
[0028] cmpN: Output signal
[0029] DFFN: Flip-Flop
[0030] D[3:0]: Data signal
[0031] Dcnt[3:0]: Count value
[0032] D1~DN: Data signals
[0033] Dout: Data signal
[0034] Ia, Ib: Current
[0035] Id1, Id2: Current
[0036] Iref: Current
[0037] M1~M6: Metal-oxide-semiconductor field-effect transistors
[0038] P1~P4: Points
[0039] Out: Output terminal
[0040] SW1: First switch
[0041] SW2: Second switch
[0042] SW3: Third switch
[0043] Scon1: First control signal
[0044] Scon2: Second control signal
[0045] Sre: Reset signal
[0046] T1~T3: Period
[0047] Vslope: Slope signal
[0048] Vi,1, Vi,2, Vi,N, Vi,p, Vi,n: input signal
[0049] VDD: Current source supply voltage
[0050] Vref: Reference voltage
[0051] V1~V3: Voltage Levels
[0052] Vr: Voltage range
[0053] Vr1: First sub-voltage range
[0054] Vr2: Second sub-voltage range
[0055] ΔI1, ΔI1', ΔI2: Current difference Detailed Implementation
[0056] All terms used herein have their ordinary meanings. The definitions of the terms above in commonly used dictionaries, and the examples of any term used in this disclosure, are merely illustrative and should not be construed as limiting the scope or meaning of this disclosure. Similarly, this disclosure is not limited to the various embodiments shown in this specification.
[0057] As used herein, “coupled” or “connected” can refer to two or more components making direct physical or electrical contact with each other, or indirectly making direct physical or electrical contact with each other, or to two or more components operating or acting on each other. As used herein, “circuit” can refer to a device consisting of at least one transistor and / or at least one active or passive component connected in a certain manner to process signals.
[0058] As used herein, the term "and / or" includes any combination of one or more of the listed related items. The terms first, second, third, etc., are used herein to describe and identify individual elements. Therefore, a first element herein may also be referred to as a second element without departing from the intent of this disclosure. For ease of understanding, similar elements in the figures will be designated with the same reference numerals.
[0059] To improve the nonlinearity of slope signals in the prior art, this disclosure proposes an analog-to-digital conversion device and an analog-to-digital conversion method, which are described in detail below.
[0060] Figure 1 This is a schematic diagram of an analog-to-digital converter 100 according to some embodiments of the present disclosure. As shown, the analog-to-digital converter 100 includes a slope signal generator 110, a comparator 120, a capacitor Cs3, and a flip-flop DFFN.
[0061] In some embodiments, the analog-to-digital converter 100 may be, but is not limited to, a time-interlaced slope analog-to-digital converter, the operation of which is described below. The analog-to-digital converter 100 may sample the input signal using capacitor Cs3, and then comparator 120 compares the sampled signal with the slope signal Vslope generated by slope signal generator 110. Before comparator 120 generates a comparison result, the counter value Dcnt[3:0] continues to count until comparator 120 generates a comparison result. When the positive terminal (positive pole) of comparator 120 is greater than the negative terminal (negative pole), the output signal cmpN generated by comparator 120 changes from negative to positive. The rising edge of the output signal cmpN changing from negative to positive triggers flip-flop DFFN, which stores the current counting result Dcnt[3:0] and subsequently outputs the data signal D[3:0]. As described above, the analog-to-digital converter 100 completes one conversion process.
[0062] To illustrate how the analog-to-digital converter 100 of this disclosure improves the nonlinearity of the slope signal Vslope, please also refer to... Figure 2 and Figure 3 , Figure 2 This is a flowchart illustrating an analog-to-digital conversion method 200 according to some embodiments of this disclosure. Figure 3 This is a timing diagram of an analog-to-digital converter 100 drawn according to some embodiments of the present disclosure.
[0063] Please see Figure 2 Step 210 involves generating a slope signal in the first sub-voltage region of the voltage range based on a first current source, and in the second sub-voltage region of the voltage range based on a second current source, using a slope signal generator. The slope signal rises and falls back and forth within the voltage range with at least one slope. For example, please refer to... Figure 1 , Figure 3 The slope signal generator 110 generates a slope signal Vslope (as shown by the dashed line portion of the slope signal Vslope) in the first sub-voltage interval Vr1 of the voltage interval Vr according to the first current source CS1, and generates a slope signal Vslope (as shown by the solid line portion of the slope signal Vslope) in the second sub-voltage interval Vr2 of the voltage interval Vr according to the second current source CS2. This slope signal Vslope rises with one slope and falls with another slope in the voltage interval Vr to complete one round of rise and fall, and the slope signal Vslope rises and falls back and forth in the voltage interval Vr repeatedly.
[0064] Please see Figure 2 Step 220 involves using a comparator to generate an output signal based on the slope signal and the input signal. For example, please refer to... Figure 1 , Figure 3 Taking the input signal Vi,1 as an example, the comparator 120 generates the output signal cmp1 based on the slope signal Vslope and the input signal Vi,1.
[0065] In some embodiments, the voltage range Vr includes a low voltage level V1 and a high voltage level V3, and at least one slope of the slope signal Vslope includes a positive slope and a negative slope. The slope signal Vslope rises from the low voltage level V1 to the high voltage level V3 with a positive slope, and then falls from the high voltage level V3 to the low voltage level V1 with a negative slope.
[0066] In some embodiments, the first sub-voltage interval Vr1 includes a low voltage level V1, the boundary between the first sub-voltage interval Vr1 and the second sub-voltage interval Vr2 includes an intermediate voltage level V2, and at least one slope of the slope signal Vslope includes a positive slope and a negative slope. During a first period A1, the slope signal Vslope is increased from the low voltage level V1 to the intermediate voltage level V2 with a positive slope according to the first current source CS1 (as shown by the dashed line portion of the slope signal Vslope).
[0067] In some embodiments, the second sub-voltage range Vr2 includes a high voltage level V3. During the second period, the slope signal Vslope is raised from the intermediate voltage level V2 to the high voltage level V3 with a positive slope according to the second current source CS2 (as shown by the solid line portion of the slope signal Vslope).
[0068] In some embodiments, the slope signal Vslope decreases from a high voltage level V3 to an intermediate voltage level V2 with a negative slope during a third period A3, based on a second current source CS2 (as shown by the solid line portion of the slope signal Vslope). In another embodiment, the slope signal Vslope decreases from an intermediate voltage level V2 to a low voltage level V1 with a negative slope during a fourth period A4, based on a first current source CS1 (as shown by the dashed line portion of the slope signal Vslope). In some embodiments, the first period A1, the second period A2, the third period A3, and the fourth period A4 are executed sequentially.
[0069] In some embodiments, please refer to Figure 1The slope signal generator 110 includes a first current source CS1, an output terminal Out, a first switch SW1, and a second switch SW2. In some embodiments, the first current source CS1 may be implemented by a transistor. The first switch SW1 includes a first terminal (as shown above) and a second terminal (as shown below). The first terminal (as shown above) of the first switch SW1 is coupled to the first current source CS1. The second terminal (as shown below) of the first switch SW1 is coupled to the output terminal Out. The second switch SW2 includes a first terminal (as shown above) and a second terminal (as shown below). The first terminal (as shown above) of the second switch SW2 is coupled to the output terminal Out. The second terminal (as shown below) of the second switch SW2 is used to receive... Figure 3 The low voltage level V1 is shown. First switch SW1 and second switch SW2 output slope signal Vslope according to first control signal Scon1 and reset signal Sre. For timing diagrams of first control signal Scon1 and reset signal Sre in some embodiments, please refer to [reference needed]. Figure 1 However, this disclosure is not limited to the above embodiments, which are merely illustrative of one implementation of this disclosure. Other suitable circuit architectures and timings may also be used, depending on actual needs.
[0070] In some embodiments, please refer to Figure 1 The slope signal generator 110 includes a second current source CS2 and a third switch SW3. In some embodiments, the second current source CS2 may be implemented by a transistor. The third switch SW3 includes a first terminal (as shown above) and a second terminal (as shown below). The first terminal (as shown above) of the third switch SW3 is coupled to the second current source CS2. The second terminal (as shown below) of the third switch SW3 is coupled to the output terminal Out. The third switch SW3 outputs a slope signal Vslope according to a second control signal Scon2. In some embodiments, the timing diagram of the second control signal Scon2 is shown below. Figure 1 However, this disclosure is not limited to the above embodiments, which are merely illustrative of one implementation of this disclosure. Other suitable circuit architectures and timings may also be used, depending on actual needs.
[0071] In some embodiments, please refer to Figure 3The first sub-voltage interval Vr1 and the second sub-voltage interval Vr2 do not overlap. For example, the first sub-voltage interval Vr1 includes a low voltage level V1 and an intermediate voltage level V2. Furthermore, the second sub-voltage interval Vr2 includes an intermediate voltage level V2 and a high voltage level V3. In this embodiment, the upper limit voltage level (e.g., the intermediate voltage level V2) of the first sub-voltage interval Vr1 is the same as the lower limit voltage level (e.g., the intermediate voltage level V2) of the second sub-voltage interval Vr2. Therefore, the first sub-voltage interval Vr1 and the second sub-voltage interval Vr2 do not overlap. For example, the aforementioned intermediate voltage level V2 can be taken as the midpoint between the low voltage level V1 and the high voltage level V3, and the formula for voltage level V2 is as follows:
[0072]
[0073] However, the intermediate voltage level V2 of this disclosure is not limited to the above embodiments, and other suitable values may be adopted depending on actual needs.
[0074] Figure 4 As shown in some embodiments of this disclosure Figure 1 A schematic diagram of the current source of the slope signal generator 110 shown. Figure 1 The current sources CS1 and CS2 of the slope signal generator 110 can be implemented using metal-oxide-semiconductor field-effect transistors (MOSFETs). For example, please refer to... Figure 4 The current source CS1 or CS2 of the slope signal generator 110 can be a current source CSA implemented by metal-oxide-semiconductor field-effect transistors M1 and M2, or the current source CS1 or CS2 of the slope signal generator 110 can be a current source CSB implemented by metal-oxide-semiconductor field-effect transistors M3 to M6. In some embodiments, the slope signal Vslope of this disclosure is not limited to a rising slope or a falling slope. If the slope signal Vslope is a falling slope, an NMOS (N-type metal-oxide-semiconductor field-effect transistor) can be used to implement the current source.
[0075] Figure 5 A drawing based on some embodiments of this disclosure, such as Figure 1The diagram shows the current and voltage of the slope signal generator 110. As shown, if only a single current source is used, the current Ib will generate a current difference ΔI1' due to the change in VDS (drain-source voltage). Furthermore, if divided into periods C1 and C2, period C1 generates a current difference ΔI1 from one current source, and period C2 generates a current difference ΔI2 from another current source. As can be seen from the diagram, the total current difference generated by the two current sources is the sum of the current difference ΔI1 and the current difference ΔI2. This total current difference (ΔI1 + ΔI2) is less than the current difference ΔI1' generated by a single current source. Therefore, the analog-to-digital converter 100 of this disclosure can reduce the aforementioned current difference by using two current sources, thereby improving the nonlinearity of the current source of the slope signal generator 110 of this disclosure.
[0076] For example, Figure 5 The current Ib can be obtained from Figure 4 The current source CSB provides the current, which is a cascode current source. The current source CSB requires a large |VDS| to operate in the saturation region and has a slight channel length modulation effect, so the slope is relatively gentle. Figure 5 The current Ia can be obtained from Figure 4 The current source CSA is provided. The CSA is a simple current source with a significant channel length modulation effect, resulting in a steeper slope, but it requires only a small |VDS| to operate in the saturation region. Furthermore, Figure 5 The currents Ia and Ib can also be obtained from Figure 6 The current sources CSC and CSD are provided. The present disclosure allows for the design of metal-oxide-semiconductor field-effect transistors M2 and M4 for the current sources CSC and CSD, such that they have different Vsg (source-gate voltage) and different W / L (width-to-length ratio) to provide currents Ia and Ib, wherein Vsg1 of the current source CSC is not equal to Vsg2 of the current source CSD, and (W / L)2 of the current source CSC is not equal to (W / L)4 of the current source CSD.
[0077] It should be noted that this disclosure does not imply... Figures 1 to 6 The embodiments shown are limited and are merely illustrative of one implementation of this disclosure to facilitate understanding of the technology. The scope of this disclosure is defined by the claims. Modifications and refinements made by those skilled in the art to the embodiments of this disclosure without departing from the concept of this disclosure still fall within the scope of the claims.
[0078] In summary, the technical means embodied in the embodiments of this disclosure can improve at least one of the shortcomings of the prior art. The analog-to-digital conversion apparatus and analog-to-digital conversion method of this disclosure can improve the nonlinearity of the current source of the slope signal generator.
[0079] Although the embodiments of this disclosure are described above, these embodiments are not intended to limit this disclosure. Those skilled in the art can make changes to the technical features of this disclosure based on its express or implied content. All such changes may fall within the scope of patent protection sought by this disclosure. In other words, the scope of patent protection of this disclosure shall be determined by the claims of this specification.
Claims
1. An analog-to-digital converter, comprising: A slope signal generator is configured to generate a slope signal in a first sub-voltage interval of a voltage range based on a first current source, and in a second sub-voltage interval of the same voltage range based on a second current source, wherein the slope signal rises and falls back within the voltage range with at least one slope; and A comparator is used to generate an output signal based on the slope signal and an input signal.
2. The analog-to-digital converter of claim 1, wherein the voltage range includes a low voltage level and a high voltage level, and the at least one slope includes a positive slope and a negative slope, wherein the slope signal is raised from the low voltage level to the high voltage level with the positive slope, and then lowered from the high voltage level to the low voltage level with the negative slope.
3. The analog-to-digital converter of claim 1, wherein the first sub-voltage range includes a low voltage level, an intersection of the first sub-voltage range and the second sub-voltage range includes an intermediate voltage level, and the at least one slope includes a positive slope and a negative slope, wherein the slope signal is boosted from the low voltage level to the intermediate voltage level with the positive slope according to the first current source during a first period.
4. The analog-to-digital converter of claim 3, wherein the second sub-voltage range includes a high voltage level, wherein the slope signal is boosted from the intermediate voltage level to the high voltage level with the positive slope according to the second current source during a second period.
5. The analog-to-digital converter of claim 4, wherein the slope signal decreases from the high voltage level to the intermediate voltage level with the negative slope according to the second current source during a third period.
6. The analog-to-digital converter of claim 5, wherein the slope signal decreases from the intermediate voltage level to the low voltage level with the negative slope according to the first current source during a fourth period.
7. The analog-to-digital conversion apparatus of claim 6, wherein the first period, the second period, the third period, and the fourth period are executed sequentially.
8. The analog-to-digital conversion apparatus of claim 2, wherein the slope signal generator includes the first current source, the first current source includes at least one first transistor, and the slope signal generator further includes: One output terminal; A first switch, comprising: One terminal is coupled to the first current source; and A second terminal, coupled to the output terminal; and A second switch, comprising: One of the first terminals is coupled to the output terminal; and The second terminal is used to receive the low voltage level; The first switch and the second switch output the slope signal according to a first control signal and a reset signal.
9. The analog-to-digital conversion apparatus of claim 8, wherein the slope signal generator includes the second current source, the second current source includes at least one second transistor, and the slope signal generator further includes: A third switch, comprising: A first terminal is coupled to the second current source; and The second terminal is coupled to the output terminal; The third switch outputs the slope signal based on a second control signal.
10. An analog-to-digital conversion method, comprising: A slope signal is generated by a slope signal generator in a first sub-voltage range of a voltage range based on a first current source, and in a second sub-voltage range of the same voltage range based on a second current source, wherein the slope signal rises and falls back within the voltage range with at least one slope; and A comparator generates an output signal based on the slope signal and an input signal.