Output voltage control method and battery device

Abstract

An output voltage control method for a battery device includes detecting signal states of a data communication line and a clock communication line of a communication interface, and determining whether to enter a first stage shutdown mode to control an output voltage of the battery device according to the signal states of the data communication line and the clock communication line and a first duration.

Description

Technical Field

[0001] This invention relates to an output voltage control method and a battery device, and more particularly to an output voltage control method and a battery device that provide safety in use. Background Technology

[0002] With the development of technology, mobile devices have become increasingly common, such as laptops, tablets, mobile phones, and mobile communication devices. Mobile devices are typically equipped with batteries to store power for operation. Due to continuously increasing performance demands and related applications, the power consumption of mobile devices has also increased significantly. Therefore, it is necessary to replace the battery to extend the operating time of the mobile device. In this context, the need for users to replace batteries themselves has also increased significantly. Furthermore, the battery output needs to be turned off during battery replacement to maintain safety and protect the battery from damage. Current methods control the battery output voltage through commands issued by the system host device. However, in daily use, users typically do not actively operate the system host device to execute this command. Therefore, the battery continues to provide output during replacement, potentially leading to the risk of electric shock or short circuit. Thus, how to ensure user safety during battery replacement without affecting system device functionality has become a key issue of concern in the industry. Summary of the Invention

[0003] To address the aforementioned problems, the present invention provides an output voltage control method and battery device that offer safe operation, thereby resolving the aforementioned issues.

[0004] The present invention provides an output voltage control method for a battery device, comprising: detecting the signal states of a data communication line and a clock communication line of a communication interface; and determining whether to enter a first-stage shutdown mode based on the signal states of the data communication line and the clock communication line and a first duration to control an output voltage of the battery device.

[0005] The present invention also provides a battery device, comprising: a battery pack for outputting an output voltage; a communication interface including a data communication line and a clock communication line; a battery identification pin; and a processor for executing the above-described output voltage control method according to the signal states of the data communication line and the clock communication line. Attached Figure Description

[0006] Figure 1 This is a schematic diagram of an electronic system according to an embodiment of the present invention.

[0007] Figure 2 and Figure 3 This is a schematic diagram of a process according to an embodiment of the present invention.

[0008] The reference numerals in the attached figures are explained as follows:

[0009] 1: Electronic System

[0010] 2: Process

[0011] 10: Battery device

[0012] 100: Battery Pack

[0013] 102: Processor

[0014] 104: Communication Interface

[0015] 1040: Data communication line

[0016] 1042: Clock communication line

[0017] 106: Battery identification pin

[0018] 108: Cache

[0019] 110: Voltage measuring device

[0020] 112: Current measuring device

[0021] 20: Host System

[0022] S200, S202, S204, S206, S208, S210, S212, S214, S216, S218, S220, S222, S224: Steps Detailed Implementation

[0023] Certain terms are used in the specification and subsequent claims to refer to specific components. Those skilled in the art will understand that hardware manufacturers may use different names to refer to the same component. This specification and subsequent claims do not distinguish components by differences in name, but rather by differences in function. The terms "comprising" or "including" used throughout the specification and subsequent claims are open-ended and should be interpreted as "comprising but not limited to." Furthermore, the term "coupled" here includes any direct and indirect electrical connection means. Therefore, if a first device is described as coupled to a second device, it means that the first device can be directly electrically connected to the second device, or indirectly electrically connected to the second device through other devices or connection means.

[0024] Please refer to Figure 1 , Figure 1This is a schematic diagram of an electronic system 1 according to an embodiment of the present invention. Electronic system 1 may be a laptop computer, tablet computer, mobile phone, mobile communication device, wearable device, drone, etc., but is not limited thereto. Electronic system 1 includes a battery device 10 and a host system 20. Battery device 10 provides the power required for the operation of electronic system 1. For example, battery device 10 may output an output voltage to provide electrical energy to host system 20. Battery device 10 includes a battery pack 100, a processor 102, a communication interface 104, a battery identification (ID) pin 106, a buffer 108, a voltage measurement device 110, and a current measurement device 112. Battery pack 100 may output an output voltage to provide electrical energy. Battery pack 100 may include one or more batteries. The number of batteries and the connection method can be designed according to system requirements. The batteries in battery pack 100 may be lithium iron phosphate batteries, nickel-cadmium batteries, nickel-metal hydride batteries, lithium-ion batteries, sodium-based batteries, lead-acid batteries, but are not limited thereto. The processor 102 may be a microprocessor control unit (MCU), a central processing unit (CPU), a microprocessor, or an embedded controller (EC), but is not limited thereto.

[0025] The battery device 10 can communicate with the host system 20 or external devices via the communication interface 104. The communication interface 104 includes a data communication line 1040 and a clock communication line 1042. The processor 102 can be coupled to the communication interface 104 to detect the signal status of the data communication line 1040 and the clock communication line 1042. The processor 102 can receive relevant communication information transmitted through the communication interface 104. For example, the communication information can be data, instructions, messages, or any other information related to the communication interface. The communication interface 104 can be a System Management Bus (SMBus), an Inter-Integrated Circuit Bus (I2C Bus), or a Universal Serial Bus (USB), but is not limited thereto. The battery device 10 can also communicate with the host system 20 or external devices via the battery identification pin 106. The processor 102 can be coupled to the battery identification pin 106 to detect the signal status of the battery identification pin 106. A buffer 108 is used to store relevant information about the battery device 10. Voltage measuring device 110 is used to measure the voltage of battery pack 100. Current measuring device 112 is used to measure the current of battery pack 100.

[0026] For the output voltage control method of the battery device 10 in this embodiment of the invention, please refer to... Figure 2 and Figure 3 , Figure 2 and Figure 3 This is a schematic diagram of process 2 in an embodiment of the present invention. Figure 2 and Figure 3 The process 2 shown can correspond to Figure 1 The operation of the battery device 10. According to process 2, in step S202, the processor 102 detects the signal status of the data communication line 1040 and the clock communication line 1042 in the communication interface 104. The processor 102 can determine whether to enter a first-stage shutdown mode based on the signal status of the data communication line 1040 and the clock communication line 1042 and a first duration, thereby controlling the output voltage of the battery device 10. The processor 102 can determine whether the signal levels of the data communication line 1040 and the clock communication line 1042 are both at a first level (e.g., a low logic level). When it is determined that the signal levels of the data communication line 1040 and the clock communication line 1042 are both at the first level, the processor 102 can determine whether the duration for which the signal levels of the data communication line 1040 and the clock communication line 1042 are at the first level exceeds a first duration. When it is determined that the duration of the data communication line 1040 and the clock communication line 1042 being in the first position is greater than the first duration, step S206 is executed. The processor 102 can control the battery device 10 to enter the first stage shutdown mode and turn off the output voltage of the battery device 10, so that the battery device 10 does not output the output voltage during the first stage shutdown mode.

[0027] In step S202, when the processor 102 determines that the data communication line 1040 and the clock communication line 1042 are not both at the first level (i.e., at least one of the signal levels of the data communication line 1040 and the clock communication line 1042 is at a second level (e.g., a high logic level)), the battery device 10 continues to operate normally to output the output voltage, and step S204 is executed. Furthermore, when the processor 102 determines that the duration for which both the data communication line 1040 and the clock communication line 1042 are at the first level is less than or equal to a first duration, the battery device 10 continues to operate normally to output the output voltage, and step S204 is executed.

[0028] In step S204, the processor 102 can determine whether to enter the first-stage shutdown mode based on the signal state of the battery identification pin 106 and a second duration, so as to control the output voltage of the battery device 10. The processor 102 can detect the signal state of the battery identification pin 106. The processor 102 can determine whether the signal level of the battery identification pin 106 is at a first pin level (e.g., a low logic level). The processor 102 can determine whether the duration for which the signal level of the battery identification pin 106 is at the first pin level exceeds the second duration. When it is determined that the duration for which the signal level of the battery identification pin 106 is at the first pin level is greater than the second duration, step S206 is executed, and the processor 102 can control the battery device 10 to enter the first-stage shutdown mode and turn off the output voltage of the battery device 10, so that the battery device 10 does not output the output voltage during the first-stage shutdown mode. In step S204, when the processor 102 determines that the battery identification pin 106 is at the second level (e.g., a high logic level), the battery device 10 continues to operate normally to output the output voltage, and returns to step S202. When the processor 102 determines that the duration for which the battery identification pin 106 is at the first level (e.g., a low logic level) is less than or equal to the second duration, the battery device 10 continues to operate normally to output the output voltage, and returns to step S202.

[0029] In step S206, the processor 102 controls the battery device 10 to enter a first-stage shutdown mode and shuts off the output voltage of the battery device 10, so that the battery device 10 does not output the output voltage during the first-stage shutdown mode. In short, when the battery device 10 enters the first-stage shutdown mode, the processor 102 controls the battery pack 100 of the battery device 10 to stop outputting voltage. Thus, during the first-stage shutdown mode, the battery device 10 does not generate or output the output voltage. When the user replaces the battery, they can operate safely without the risk of electric shock, avoiding unnecessary trouble and loss.

[0030] For example, communication interface 104 is a system management bus. The first level can be a low logic level, and the second level can be a high logic level. Processor 102 can determine whether the signal levels of data communication line 1040 and clock communication line 1042 are both low logic levels. Then, processor 102 can determine whether data communication line 1040 and clock communication line 1042 are both at low logic levels and have been in this state for more than a first duration (step S202). When processor 102 determines that the duration for which data communication line 1040 and clock communication line 1042 are both at low logic levels is greater than the first duration, processor 102 controls battery device 10 to enter a first-stage shutdown mode and shuts off the output voltage of battery device 10, so that battery device 10 does not output the output voltage during the first-stage shutdown mode (step S206). For example, the first pin level can be a low logic level, and the second pin level can be a high logic level. Processor 102 can determine whether battery identification pin 106 is at a low logic level and has been there for more than a second duration (step S204). When processor 102 determines that the duration of battery identification pin 106 being at a low logic level is greater than the second duration, processor 102 can control battery device 10 to enter a first-stage shutdown mode and turn off the output voltage of battery device 10, so that battery device 10 does not output the output voltage during the first-stage shutdown mode (step S206).

[0031] Since the battery device 10 has entered the first-stage shutdown mode in step S206, in step S208, during the first-stage shutdown mode, the processor 102 can determine whether a first release condition is met based on at least one of the following: the data communication line 1040 and clock communication line 1042 of the communication interface 104, the battery identification pin 106, and the communication information of the communication interface 104. For example, the first release condition includes at least one of the following: during the first-stage shutdown mode, the signal level of at least one of the data communication line 1040 and clock communication line 1042 is at a second level (e.g., a high logic level); during the first-stage shutdown mode, there is communication information in the communication interface 104; and during the first-stage shutdown mode, the battery identification pin 106 is at a second pin level (e.g., a high logic level). For example, if the communication interface 104 is a system management bus, during the first-stage shutdown mode, the processor 102 continuously monitors the data communication line 1040 and clock communication line 1042. When it is determined that the signal level of either data communication line 1040 or clock communication line 1042 is a high logic level, or when it is determined that the signal levels of both data communication line 1040 and clock communication line 1042 are high logic levels, the processor 102 determines that the first release condition has been met. For example, during the first-stage shutdown mode, the processor 102 can continuously monitor the battery identification pin 106. When it is determined that the signal level of the battery identification pin 106 is a high logic level, the processor 102 determines that the first release condition has been met. For example, the processor 102 can detect whether any communication information is being transmitted in the communication interface 104. The communication information can be data, instructions, messages, or any other information related to the communication interface. When the processor 102 receives communication information from the communication interface 104 or detects any communication information being transmitted in the communication interface, this indicates that communication information exists in the communication interface 104, and the processor 102 determines that the first release condition has been met.

[0032] In step S208, when it is determined that any one of the first release conditions is met, the processor 102 can control the battery device 10 to switch to a normal operation mode (i.e., switch from the first stage shutdown mode to the normal operation mode) and turn on the output voltage of the battery device 10, so that the battery device 10 operates normally to output the output voltage, and then execute step S210. When the processor 102 determines that any one of the first release conditions is not met (i.e., all the first release conditions are not met), then step S212 is executed. At this time, the battery device 10 is still in the first stage shutdown mode.

[0033] In step S210, the battery device 10 is in normal operating mode and the output voltage is turned on, and the battery device 10 can generate the output voltage to provide electrical energy.

[0034] In step S212, the battery device 10 remains in the first-stage shutdown mode. In the first-stage shutdown mode, the processor 102 determines whether the duration of the first-stage shutdown mode is greater than a first-stage period threshold. The duration of the first-stage shutdown mode is the time from the point when the battery device 10 enters the first-stage shutdown mode to the current time, and during this duration, the battery device 10 remains in the first-stage shutdown mode. If it is determined that the duration of the first-stage shutdown mode is greater than the first-stage period threshold, step S214 is executed, and the processor 102 controls the battery device 10 to enter a second-stage shutdown mode and a low-power mode. If it is determined that the duration of the first-stage shutdown mode is less than or equal to the first-stage period threshold, step S218 is executed.

[0035] In step S214, the processor 102 controls the battery device 10 to enter the second stage shutdown mode and low power consumption mode, and shuts off the output voltage of the battery device 10, so that the battery device 10 does not output the output voltage. In this case, since the battery device 10 enters the low power consumption mode, the power consumption of the battery device 10 can be further reduced.

[0036] Since the battery device 10 has entered the second-stage shutdown mode in step S214, in step S216, during the second-stage shutdown mode, the processor 102 can determine whether a second release condition is met based on at least one of the communication information of the data communication line 1040 and clock communication line 1042, the battery identification pin 106, and the communication interface 104 of the communication interface 104. For example, the second release condition includes at least one of the following: a change in the signal level of at least one of the data communication line 1040, clock communication line 1042, and battery identification pin 106 during the second-stage shutdown mode; a wake-up program being executed during the second-stage shutdown mode; and communication information being present in the communication interface 104 during the second-stage shutdown mode. When it is determined that any of the second release conditions are met, the processor 102 can control the battery device 10 to switch to a normal operation mode (i.e., switch from the second-stage shutdown mode to the normal operation mode) and turn on the output voltage of the battery device 10, so that the battery device 10 operates normally to output the output voltage, and execute step S210. If the processor 102 determines that any one of the second release conditions is not met (i.e., all the second release conditions are not met), then step S216 is executed again. That is, if it is determined that any one of the second release conditions is not met, step S216 is executed repeatedly until the processor 10 determines that any one of the second release conditions is met.

[0037] In step S218, the battery device 10 remains in the first-stage shutdown mode. In the first-stage shutdown mode, the processor 102 determines whether the duration of the first-stage shutdown mode is greater than a second-stage period threshold, where the second-stage period threshold is less than the first-stage period threshold. For example, the time unit of the first-stage period threshold is days, and the time unit of the second-stage period threshold is hours. For example, the first-stage period threshold is 1 day, and the second-stage period threshold is 1 hour. If it is determined that the duration of the first-stage shutdown mode is greater than the second-stage period threshold, step S220 is executed, and the processor 102 controls the battery device 10 to enter a third-stage shutdown mode. If it is determined that the duration of the first-stage shutdown mode is less than or equal to the second-stage period threshold, the process returns to step S202, and the battery device 10 remains in the first-stage shutdown mode.

[0038] In step S220, the processor 102 can control the battery device 10 to enter the third-stage shutdown mode and turn off the output voltage of the battery device 10, so that the battery device 10 does not output the output voltage during the third-stage shutdown mode. Since the battery device 10 has entered the third-stage shutdown mode in step S220, in step S222, during the third-stage shutdown mode, the processor 102 can determine whether a third release condition is met based on at least one of the communication information of the data communication line 1040 and clock communication line 1042, the battery identification pin 106, and the communication information of the communication interface 104. For example, the third release condition includes at least one of the following: the signal level of at least one of the data communication line 1040, clock communication line 1042, and battery identification pin 106 changes during the third-stage shutdown mode, and there is communication information in the communication interface 104 during the third-stage shutdown mode. When it is determined that any one of the third release conditions is met, the processor 102 can control the battery device 10 to switch to a normal operation mode (i.e., switch from the third stage shutdown mode to the normal operation mode) and turn on the output voltage of the battery device 10, so that the battery device 10 operates normally to output the output voltage, and execute step S210. When the processor 102 determines that any one of the third release conditions is not met (i.e., all the third release conditions are not met), it returns to step S202.

[0039] Those skilled in the art can combine, modify, or change the embodiments described above in accordance with the spirit of the present invention, but are not limited thereto. All the descriptions, steps, and / or processes (including suggested steps) above can be implemented by hardware, software, firmware (i.e., a combination of hardware devices and computer instructions, where the data in the hardware device is read-only software data), electronic systems, or combinations of the above devices. Hardware may include analog, digital, and mixed-signal circuits (i.e., microcircuits, microchips, or silicon chips). Electronic systems may include system-on-chip (SoC), system-in-package (SiP), computer-on-module (CoM), and electronic system 1. The process steps and embodiments of the present invention can exist in the form of program code or instructions and be stored in a storage device. The storage device may be a computer-readable recording medium, and may include, but is not limited to, read-only memory (ROM), flash memory, random-access memory (RAM), a subscriber identity module (SIM), a hard disk, a floppy disk, or an optical disk read-only memory (CD-ROM / DVD-ROM / BD-ROM). The above processes and embodiments may be compiled into program code or instructions and stored in the storage device. The processor 102 may be used to read and execute the program code or instructions stored in the storage device to implement all the aforementioned steps and functions.

[0040] In summary, this invention provides a method for controlling the output voltage of a battery device. When the battery device is disconnected from the host system, it automatically shuts off the output voltage. This ensures safe operation without the risk of electric shock when the user replaces the battery, guaranteeing safety during use and avoiding unnecessary trouble and losses. More importantly, since the battery identification pin, data communication line, and clock communication line used in this invention are all components used in existing battery system architectures, no additional hardware circuitry is required, effectively saving manufacturing costs.

[0041] The above description is merely a preferred embodiment of the present invention and is not intended to limit the invention. Various modifications and variations can be made to the present invention by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. An output voltage control method for a battery device, characterized in that, include: Detect the signal status of a data communication line and a clock communication line of a communication interface; as well as Based on the signal states of the data communication line and the clock communication line, and a first duration, it is determined whether to enter a first-stage shutdown mode to control an output voltage of the battery device.

2. The output voltage control method according to claim 1, characterized in that, Also includes: Determine whether the signal levels of the data communication line and the clock communication line are both at the first level. When it is determined that the signal levels of the data communication line and the clock communication line are both at the first level, it is determined whether the duration for which the signal levels of the data communication line and the clock communication line are at the first level exceeds the first duration. as well as When it is determined that the duration for which the signal level of the data communication line and the clock communication line is at the first level is greater than the first duration, the battery device is controlled to enter the first stage shutdown mode and the output voltage of the battery device is turned off, so that the battery device does not output the output voltage.

3. The output voltage control method according to claim 1, characterized in that, Also includes: When it is determined that the signal level of at least one of the data communication line and the clock communication line is not at a first level, or the duration for which the signal level of the data communication line and the clock communication line is at the first level is less than or equal to the first duration, the signal state of a battery identification pin is detected to determine whether the signal level of the battery identification pin is at a first pin level. When it is determined that the signal level of the battery identification pin is at the first pin level and the duration of the signal level of the battery identification pin being at the first pin level is greater than a second duration, the battery device is controlled to enter the first stage shutdown mode and the output voltage of the battery device is turned off, so that the battery device does not output the output voltage.

4. The output voltage control method according to claim 1, characterized in that, Also includes: The battery device enters the first-stage shutdown mode; In the first stage shutdown mode, it is determined whether a first release condition is met based on at least one of the data communication line and clock communication line of the communication interface, a battery identification pin, and the communication information of the communication interface. as well as When it is determined that the first release condition is met, the battery device is controlled to switch to a normal operation mode and the output voltage of the battery device is turned on, so that the battery device can operate normally to output the output voltage.

5. The output voltage control method according to claim 4, characterized in that, The first release condition includes at least one of the following: during the first phase shutdown mode, the signal level of at least one of the data communication line and the clock communication line is at a second level; during the first phase shutdown mode, there is communication information in the communication interface; and during the first phase shutdown mode, a battery identification pin is at a second pin level.

6. The output voltage control method according to claim 1, characterized in that, Also includes: The battery device is in the first-stage shutdown mode; In the first-stage shutdown mode, it is determined whether the duration of the first-stage shutdown mode is greater than a first-stage period threshold value; and When it is determined that the duration of the first stage shutdown mode is greater than the first stage period threshold, the battery device is controlled to enter a second stage shutdown mode and a low power consumption mode, and the output voltage of the battery device is turned off so that the battery device does not output the output voltage.

7. The output voltage control method according to claim 6, characterized in that, Also includes: In the second-stage shutdown mode, it is determined whether a second release condition is met based on at least one of the data communication line and clock communication line of the communication interface, a battery identification pin, and the communication information of the communication interface. as well as When it is determined that the second release condition is met, the battery device is controlled to switch to a normal operation mode and the output voltage of the battery device is turned on, so that the battery device can operate normally to output the output voltage.

8. The output voltage control method according to claim 7, characterized in that, The second release condition includes at least one of the following: a change in the signal level of at least one of the data communication line, the clock communication line, and the battery identification pin during the second phase shutdown mode; a wake-up procedure being executed during the second phase shutdown mode; and communication information being present in the communication interface during the second phase shutdown mode.

9. The output voltage control method according to claim 6, characterized in that, Also includes: When it is determined that the duration of the first stage shutdown mode is less than or equal to the first stage period threshold, it is determined whether the duration of the first stage shutdown mode is greater than a second stage period threshold, wherein the second stage period threshold is less than the first stage period threshold. When it is determined that the duration of the first stage shutdown mode is greater than the threshold value of the second stage period, the battery device is controlled to enter a third stage shutdown mode and the output voltage of the battery device is turned off, so that the battery device does not output the output voltage.

10. The output voltage control method according to claim 9, characterized in that, Also includes: In the third-stage shutdown mode, it is determined whether a third release condition is met based on at least one of the data communication line and clock communication line of the communication interface, a battery identification pin, and the communication information of the communication interface. as well as When it is determined that the third release condition is met, the battery device is controlled to switch to a normal operation mode and the output voltage of the battery device is turned on, so that the battery device can operate normally to output the output voltage.

11. The output voltage control method according to claim 10, characterized in that, The third release condition includes at least one of the following: a change in the signal level of at least one of the data communication line, the clock communication line, and the battery identification pin during the second phase shutdown mode, and communication information in the communication interface during the second phase shutdown mode.

12. The output voltage control method according to claim 1, characterized in that, The communication interface is a system management bus.

13. A battery device, characterized in that, include: A battery pack used to output an output voltage; A communication interface, including a data communication line and a clock communication line; One battery identification pin; as well as A processor for executing the output voltage control method of any one of claims 1 to 12 based on the signal states of the data communication line, the clock communication line and the battery identification pin.

Images