Base station chip prototype verification method, adapter, system, medium and product

Abstract

The present disclosure provides a base station chip prototype verification method, an adapter, a system, a medium and a product. The base station chip prototype verification method comprises: receiving a first data stream from a terminal simulation model, wherein the terminal simulation model is obtained by loading a bit stream file on a chip prototype verification platform, and the first data stream comprises one or more first time stamps; converting the first data stream into one or more first data packets based on the one or more first time stamps; and transmitting the one or more first data packets to a base station chip prototype. The method can facilitate the implementation of data transmission between the terminal simulation model and the base station chip prototype, thereby facilitating the implementation of the verification operation of the base station chip prototype.

Description

Technical Field

[0001] This disclosure relates to the field of wireless communication technology, and in particular to a method for prototyping a base station chip, an adapter, a system, a medium, and a product. Background Technology

[0002] Chip prototyping verification is a crucial step in the integrated circuit design process, involving the pre-verification of the chip's functionality, performance, and reliability through simulation before tape-out. It typically employs prototyping platforms or dedicated simulation tools to map the Register Transfer Level (RTL) design into executable hardware logic, simulating real-world application scenarios (such as communication protocol interaction and data processing) to verify timing convergence, power consumption, and system-level compatibility. This stage effectively reduces tape-out risks and shortens product development cycles.

[0003] The inventors of this disclosure discovered that the terminal simulation model and the base station chip prototype have different frequencies, which leads to difficulties in data transmission between the terminal simulation model and the base station chip prototype during the verification process. Summary of the Invention

[0004] One technical problem addressed by this disclosure is that, in related technologies, the difference in frequencies between the terminal simulation model and the base station chip prototype leads to difficulties in data transmission between them during the base station chip prototype verification process.

[0005] According to one aspect of this disclosure, a base station chip prototype verification method is provided, comprising: receiving a first data stream from a terminal simulation model, wherein the terminal simulation model is obtained by loading a bitstream file on a chip prototype verification platform, the first data stream including one or more first timestamps; converting the first data stream into one or more first data packets based on the one or more first timestamps; and transmitting the one or more first data packets to a base station chip prototype.

[0006] In some embodiments, receiving a first data stream from a terminal simulation model includes: receiving the first data stream from the terminal simulation model through a first FIFO module; transmitting the one or more first data packets to a base station chip prototype includes: transmitting the one or more first data packets to the base station chip prototype through a second FIFO module.

[0007] In some embodiments, converting the first data stream into one or more first data packets based on the one or more first timestamps includes: receiving the first data stream from the first FIFO module through a processing module, wherein the data format of the first data stream is a first data format; converting the first data stream from the first data format to a second data format; obtaining one or more first timestamps from the first data stream having the second data format; determining one or more first data headers based on the one or more first timestamps; and converting the first data stream into one or more first data packets based on the one or more first data headers.

[0008] In some embodiments, the base station chip prototype verification method further includes: receiving one or more second data packets from the base station chip prototype; converting the one or more second data packets into a second data stream based on one or more second timestamps; and transmitting the second data stream to the terminal simulation model.

[0009] In some embodiments, receiving one or more second data packets from the base station chip prototype includes: receiving one or more second data packets from the base station chip prototype through a second FIFO module; transmitting the second data stream to the terminal simulation model includes: transmitting the second data stream to the terminal simulation model through a first FIFO module.

[0010] In some embodiments, the chip prototype verification platform is a field-programmable gate array (FPGA).

[0011] According to another aspect of this disclosure, an adapter is provided, comprising: a first FIFO module for receiving a first data stream from a terminal emulation model, wherein the terminal emulation model is obtained by loading a bitstream file on a chip prototype verification platform, and the first data stream includes one or more first timestamps; a processing module for converting the first data stream into one or more first data packets based on the one or more first timestamps; and a second FIFO module for transmitting the one or more first data packets to a base station chip prototype.

[0012] In some embodiments, the processing module is configured to receive the first data stream from the first FIFO module, wherein the data format of the first data stream is a first data format, convert the first data stream from the first data format to a second data format, obtain one or more first timestamps from the first data stream having the second data format, determine one or more first data headers based on the one or more first timestamps, and convert the first data stream into one or more first data packets based on the one or more first data headers.

[0013] In some embodiments, the second FIFO module is further configured to receive one or more second data packets from the base station chip prototype; the processing module is further configured to convert the one or more second data packets into a second data stream based on one or more second timestamps; and the first FIFO module is further configured to transmit the second data stream to the terminal simulation model.

[0014] According to another aspect of this disclosure, an adapter is provided, comprising: a memory; and a processor coupled to the memory, the processor being configured to execute the base station chip prototyping method as described above based on instructions stored in the memory.

[0015] According to another aspect of this disclosure, a base station chip prototyping system is provided, comprising: an adapter as described above; and a terminal simulation model, wherein the terminal simulation model is obtained by loading a bitstream file on a chip prototyping platform.

[0016] In some embodiments, the terminal simulation model includes: a physical layer signal processing module for performing physical layer signal processing through the hardware of the chip prototype verification platform; a physical layer control module for performing physical layer scheduling on the chip prototype verification platform; and a protocol stack module for implementing protocol stack processing on the chip prototype verification platform.

[0017] According to another aspect of this disclosure, a computer-readable storage medium is provided having computer instructions stored thereon that, when executed by a processor, implement the base station chip prototype verification method as described above.

[0018] According to another aspect of this disclosure, a computer program product is provided, comprising a computer program or instructions that, when executed by a processor, implement the base station chip prototype verification method as described above.

[0019] In the above method, the data stream received from the terminal simulation model can be converted into data packets that can be received and processed by the base station chip prototype, and these data packets can be transmitted to the base station chip prototype. This facilitates the data transmission between the terminal simulation model and the base station chip prototype during the base station chip prototype verification process, thereby facilitating the verification operation of the base station chip prototype.

[0020] Other features and advantages of this disclosure will become clear from the following detailed description of exemplary embodiments with reference to the accompanying drawings. Attached Figure Description

[0021] The accompanying drawings, which form part of this specification, illustrate embodiments of this disclosure and, together with the specification, serve to explain the principles of this disclosure.

[0022] This disclosure will become clearer with reference to the accompanying drawings and the following detailed description, wherein: Figure 1 This is a flowchart illustrating a base station chip prototype verification method according to some embodiments of the present disclosure; Figure 2 This is a flowchart illustrating a base station chip prototype verification method according to other embodiments of this disclosure; Figure 3 This is a schematic block diagram illustrating the structure of an adapter according to some embodiments of the present disclosure; Figure 4 This is a schematic block diagram illustrating the structure of an adapter according to other embodiments of the present disclosure; Figure 5 This is a schematic block diagram illustrating the structure of an adapter according to other embodiments of the present disclosure; Figure 6 This is a schematic block diagram illustrating the structure of a base station chip prototype verification system according to some embodiments of the present disclosure. Detailed Implementation

[0023] Various exemplary embodiments of the present disclosure will now be described in detail with reference to the accompanying drawings. It should be noted that, unless otherwise specifically stated, the relative arrangement, numerical expressions, and values ​​of the components and steps set forth in these embodiments do not limit the scope of the present disclosure.

[0024] At the same time, it should be understood that, for ease of description, the dimensions of the various parts shown in the accompanying drawings are not drawn according to actual scale.

[0025] The following description of at least one exemplary embodiment is merely illustrative and is in no way intended to limit this disclosure or its application or use.

[0026] Techniques, methods, and equipment known to those skilled in the art may not be discussed in detail, but where appropriate, such techniques, methods, and equipment should be considered part of the specification.

[0027] In all examples shown and discussed herein, any specific values ​​should be interpreted as merely exemplary and not as limitations. Therefore, other examples of exemplary embodiments may have different values.

[0028] It should be noted that similar labels and letters in the following figures indicate similar items; therefore, once an item is defined in one figure, it does not need to be discussed further in subsequent figures.

[0029] In the field of base station chip prototype verification, the following technologies exist: (1) Terminal Emulator A terminal emulator is a testing tool used to simulate the behavior and communication protocols of terminal devices (such as smartphones and IoT devices). By generating standardized data streams (such as 5G NR (5G New Radio) signaling and TCP / IP (Transmission Control Protocol / Internet Protocol) data packets), the emulator establishes an end-to-end connection with the base station under test, verifying its protocol stack compatibility, data transmission integrity, and multi-scenario interaction capabilities. For example, in 5G base station verification, it can simulate a terminal initiating a voice call or video transmission request to test the base station's link scheduling and resource management functions.

[0030] (2) RTL (Register Transfer Level) RTL (Random Level Transmission) is one of the abstraction levels in digital circuit design. It describes circuit functions using hardware description languages ​​(such as Verilog and VHDL, or VHSICH Hardware Description Language), focusing on data transfer logic between registers and combinational logic operations. RTL code is the core input for chip design and needs to be converted into a gate-level netlist using logic synthesis tools, ultimately mapping it to FPGA or ASIC (Application-Specific Integrated Circuit) hardware. In prototype verification, the completeness and correctness of the RTL directly affect the feasibility of subsequent physical implementation.

[0031] (3) FPGA (Field-Programmable Gate Array) An FPGA is a semi-custom integrated circuit that can be programmed to implement specific digital circuit logic. In chip prototyping, FPGAs are often used to carry the hardware description language code (such as Verilog / VHDL) of the chip design to be verified, accelerating functional verification through hardware simulation and helping to discover design defects before tape-out. Its core advantages lie in its reprogrammability and parallel computing capabilities.

[0032] (4) Bitfile (bit stream file) A bitfile is a binary configuration file generated by FPGA development tools (such as Vivado and Quartus), containing logic cell placement and routing information as well as hardware function configuration data. During verification, the bitfile is downloaded to the FPGA via a high-speed interface, mapping its internal programmable resources to the equivalent circuit of the chip under verification, thus enabling dynamic reconfiguration of the hardware logic.

[0033] (5) Data call (closed-loop data link connection) Data call is one of the test scenarios in communication chip verification, referring to the process of establishing a stable data transmission channel in a simulated or real network environment. For example, in 5G chip verification, data call requires steps such as protocol stack activation and radio resource allocation to realize uplink and downlink data transmission between the terminal and the base station, used to verify the chip's link stability, modulation and demodulation performance, and power consumption.

[0034] During the prototype verification phase of base station chips, testing data link connections (data calls) with terminals can significantly improve the probability of detecting hardware defects, thereby ensuring chip tape-out quality. Currently, the main implementation methods include the following two.

[0035] Implementation Option 1: Connect to a terminal emulator a) The base station chip design RTL generates the corresponding bitfile using tools and runs it on the chip prototyping platform (FPGA).

[0036] b) Load and run the corresponding software on the running bitfile.

[0037] c) The terminal emulator connects to the chip prototype platform via a high-speed interface and ensures clock signal synchronization.

[0038] d) The terminal emulator initiates a data call to perform data call testing with the base station chip design.

[0039] Solution 2: Connect to PC (Personal Computer) emulation software a) The base station chip design RTL generates the corresponding bitfile using tools and runs it on the chip prototyping platform (FPGA).

[0040] b) Load and run the corresponding software on the running bitfile.

[0041] c) The PC connects to the chip prototype platform via a high-speed interface and ensures clock signal synchronization.

[0042] d) Run the simulation model software on the PC and simulate the terminal to initiate a data call to perform data call testing with the base station chip design.

[0043] The inventors of this disclosure have discovered some shortcomings in the prototype verification process of the aforementioned base station chip. For example, terminal instrument verification only supports standard protocols and cannot verify custom communication protocols. Also, the software simulation of PC software verification is difficult to match the high-speed performance of the prototype verification platform, resulting in low verification efficiency.

[0044] To this end, the inventors of this disclosure propose that a terminal simulation model can be obtained by loading a bitstream file on a chip prototype verification platform, and a base station chip prototype can be obtained by loading another bitstream file on another chip prototype verification platform. By using the terminal simulation model and the base station chip prototype to perform base station chip prototype verification, custom communication protocols can be verified and verification efficiency can be improved.

[0045] However, the inventors of this disclosure further discovered that the frequency of the aforementioned terminal simulation model is different from that of the aforementioned base station chip prototype, which leads to difficulties in data transmission between the terminal simulation model and the base station chip prototype during the verification process.

[0046] In view of this, the inventors of this disclosure further propose a base station chip prototype verification method to facilitate data transmission between the terminal simulation model and the base station chip during the base station chip prototype verification process. The base station chip prototype verification method according to some embodiments of this disclosure is described in detail below with reference to the accompanying drawings.

[0047] Figure 1 This is a flowchart illustrating a base station chip prototype verification method according to some embodiments of the present disclosure. An adapter can be provided between a terminal simulation model and a base station chip prototype, and the base station chip prototype verification method can be implemented in this adapter. Figure 1 As shown, the method includes steps S102 to S106.

[0048] In step S102, a first data stream is received from the terminal simulation model, wherein the terminal simulation model is obtained by loading a bitstream file on a chip prototype verification platform, and the first data stream includes one or more first timestamps. Here, the bitstream file is the bitstream file corresponding to the terminal simulation model.

[0049] For example, the chip prototyping platform is an FPGA (Field-Programmable Gate Array). The bitstream file mentioned above can be downloaded to the FPGA, allowing the FPGA to load the bitstream file and obtain a terminal simulation model. This terminal simulation model may include, for example, a physical layer signal processing module, a physical layer control module, and a protocol stack module. These modules will be described later.

[0050] In the steps described above, the adapter can receive a first data stream from the terminal emulation model, which includes one or more first timestamps. The terminal emulation model and the adapter can share a clock to ensure timing consistency. That is, the timing of the terminal emulation model and the timing of the adapter are consistent.

[0051] In some embodiments, step S102 includes receiving a first data stream from the terminal simulation model via a first FIFO (First In First Out) module. This first FIFO module is located in the adapter. The first FIFO module allows the receiving of the data stream from the terminal simulation model, which improves the stability of data transmission.

[0052] Here, FIFO is one of the fundamental modules in digital circuit and FPGA design. It is a dedicated data buffer that has no address lines and is read in the order it is written.

[0053] In step S104, the first data stream is converted into one or more first data packets based on one or more first timestamps.

[0054] In some embodiments, step S104 includes: receiving a first data stream from a first FIFO module via a processing module, the first data stream having a first data format; converting the first data stream from the first data format to a second data format; obtaining one or more first timestamps from the first data stream having the second data format; determining one or more first data headers based on the one or more first timestamps; and converting the first data stream into one or more first data packets based on the one or more first data headers.

[0055] Here, the processing module is a module within the adapter. This processing module receives a first data stream from the first FIFO module. The first data stream uses a first data format. The processing module converts this first data format into a second data format that is easier for the processing module to handle, for example, converting a 16-bit valid data format (as the first data format) into a 12-bit valid data format (as the second data format). Then, it obtains one or more first timestamps from the first data stream and determines a first data header based on these first timestamps. Here, the number of first data headers matches the number of first timestamps. Then, based on the obtained first data headers, it converts the first data stream into one or more first data packets, the number of first data packets matching the number of first data headers. This achieves the purpose of converting the first data stream into one or more first data packets.

[0056] In step S106, one or more first data packets are transmitted to the base station chip prototype.

[0057] In some embodiments, step S106 includes transmitting one or more first data packets to the base station chip prototype via a second FIFO module. The second FIFO module is located in the adapter. This second FIFO module facilitates the transmission of the obtained first data packets to the base station chip prototype, which can eliminate short-term clock differences and improve the stability of data transmission.

[0058] For example, the aforementioned base station chip prototype is a base station chip prototype (as the object under test) obtained by loading another bitstream file onto another chip prototype verification platform. Here, the other bitstream file is the bitstream file corresponding to the base station chip prototype.

[0059] This provides a base station chip prototype verification method according to some embodiments of the present disclosure. The method includes: receiving a first data stream from a terminal emulation model, wherein the terminal emulation model is obtained by loading a bitstream file on a chip prototype verification platform, and the first data stream includes one or more first timestamps; converting the first data stream into one or more first data packets based on the one or more first timestamps; and transmitting the one or more first data packets to a base station chip prototype. In this embodiment, by using an adapter disposed between the terminal emulation model and the base station chip prototype, the above method can be implemented. This allows the data stream received from the terminal emulation model to be converted into data packets that the base station chip prototype can receive and process, and these data packets to be transmitted to the base station chip prototype. This facilitates data transmission between the terminal emulation model and the base station chip prototype during the base station chip prototype verification process, thereby facilitating the verification operation of the base station chip prototype.

[0060] The above describes the process of transmitting data from the terminal simulation model to the base station chip prototype. The following describes the process of transmitting data from the base station chip prototype to the terminal simulation model.

[0061] Figure 2 This is a flowchart illustrating a base station chip prototyping method according to some other embodiments of the present disclosure. This base station chip prototyping method is implemented in an adapter. Figure 2 As shown, the method includes steps S202 to S206.

[0062] In step S202, one or more second data packets are received from the base station chip prototype.

[0063] In some embodiments, step S202 includes receiving one or more second data packets from the base station chip prototype via a second FIFO module. This second FIFO module facilitates the reception of data packets from the base station chip prototype, which can eliminate short-term clock differences and improve data transmission stability.

[0064] In step S204, one or more second data packets are converted into a second data stream based on one or more second timestamps.

[0065] Because the adapter contains a clock, it can add a timestamp (here, a second timestamp) to one or more second data packets, thereby converting these packets into a second data stream.

[0066] In step S206, the second data stream is transmitted to the terminal simulation model.

[0067] In some embodiments, step S206 includes: transmitting the second data stream to the terminal simulation model via the first FIFO module. The first FIFO module facilitates the transmission of the second data stream to the terminal simulation model, which improves the stability of data transmission.

[0068] This provides a base station chip prototype verification method according to other embodiments of the present disclosure. The method includes: receiving one or more second data packets from a base station chip prototype; converting the one or more second data packets into a second data stream based on one or more second timestamps; and transmitting the second data stream to a terminal simulation model. This realizes the process of transmitting data from the terminal simulation model to the base station chip prototype. In this embodiment, by using an adapter disposed between the terminal simulation model and the base station chip prototype, the above method can be implemented, allowing one or more second data packets received from the base station chip prototype to be converted into a second data stream and transmitted to the terminal simulation model. This facilitates data transmission between the base station chip prototype and the terminal simulation model during base station chip prototype verification, thereby facilitating the verification operation of the base station chip prototype.

[0069] Figure 3 This is a schematic structural block diagram illustrating an adapter according to some embodiments of the present disclosure. Figure 3 As shown, the adapter includes a first FIFO module 302, a processing module 304, and a second FIFO module 306.

[0070] The first FIFO module 302 is used to receive a first data stream from the terminal emulation model. The terminal emulation model is obtained by loading a bitstream file on a chip prototyping platform. The first data stream includes one or more first timestamps.

[0071] The processing module 304 is used to convert the first data stream into one or more first data packets based on the one or more first timestamps.

[0072] The second FIFO module 306 is used to transmit the one or more first data packets to the base station chip prototype.

[0073] Therefore, an adapter according to some embodiments of this disclosure is provided. This adapter is disposed between a terminal emulation model and a base station chip prototype. The adapter includes: a first FIFO module for receiving a first data stream from the terminal emulation model, wherein the terminal emulation model is obtained by loading a bitstream file on a chip prototype verification platform, and the first data stream includes one or more first timestamps; a processing module for converting the first data stream into one or more first data packets based on the one or more first timestamps; and a second FIFO module for transmitting the one or more first data packets to the base station chip prototype. In this embodiment, by using the adapter disposed between the terminal emulation model and the base station chip prototype, the data stream received from the terminal emulation model is converted into data packets that the base station chip prototype can receive and process, and these data packets are transmitted to the base station chip prototype. This facilitates data transmission between the terminal emulation model and the base station chip prototype during the base station chip prototype verification process, thereby facilitating the verification operation of the base station chip prototype.

[0074] In some embodiments, the processing module is configured to receive a first data stream from a first FIFO module, the first data stream having a first data format, convert the first data stream from the first data format to a second data format, obtain one or more first timestamps from the first data stream having the second data format, determine one or more first data headers based on the one or more first timestamps, and convert the first data stream into one or more first data packets based on the one or more first data headers. This achieves the purpose of converting the first data stream into one or more first data packets.

[0075] In some embodiments, the second FIFO module 306 is further configured to receive one or more second data packets from the base station chip prototype; the processing module 304 is further configured to convert the one or more second data packets into a second data stream based on one or more second timestamps; and the first FIFO module 302 is further configured to transmit the second data stream to the terminal simulation model. In this embodiment, by using an adapter disposed between the terminal simulation model and the base station chip prototype, one or more second data packets received from the base station chip prototype can be converted into a second data stream and transmitted to the terminal simulation model. This facilitates data transmission between the base station chip prototype and the terminal simulation model during the base station chip prototype verification process, thereby facilitating the verification operation of the base station chip prototype.

[0076] Figure 4 This is a schematic block diagram illustrating the structure of an adapter according to other embodiments of the present disclosure. The adapter includes a memory 410 and a processor 420. Wherein: The memory 410 can be a disk, flash memory, or any other non-volatile storage medium. The memory is used for storing... Figure 1and / or Figure 2 The instructions in the corresponding embodiment.

[0077] Processor 420 is coupled to memory 410 and can be implemented as one or more integrated circuits, such as a microprocessor or microcontroller. Processor 420 executes instructions stored in memory, facilitating data transfer between the terminal simulation model and the base station chip prototype during base station chip prototype verification, thereby simplifying the verification operation of the base station chip prototype.

[0078] In some embodiments, it may also be as follows Figure 5 As shown, the adapter 40 includes a memory 410 and a processor 420. The processor 420 is coupled to the memory 410 via a BUS bus 430. The adapter 40 can also be connected to an external storage device 450 via a storage interface 440 to access external data, and can also be connected to a network or another computer system (not shown) via a network interface 460, which will not be described in detail here.

[0079] In this embodiment, data instructions are stored in a memory and then processed by a processor. This facilitates data transmission between the terminal simulation model and the base station chip prototype during the base station chip prototype verification process, thereby facilitating the verification operation of the base station chip prototype.

[0080] Figure 6 This is a schematic block diagram illustrating the structure of a base station chip prototype verification system according to some embodiments of the present disclosure.

[0081] like Figure 6 As shown, the base station chip prototype verification system includes an adapter 70 and a terminal simulation model 50. For example, the adapter 70 can be as follows: Figure 3 Adapters, such as Figure 4 adapters or such Figure 5 The adapter 40 is shown. The terminal simulation model 50 is obtained by loading a bitstream file on a chip prototyping platform. For example, the chip prototyping platform is an FPGA. For example, the terminal simulation model can be a satellite terminal simulation model.

[0082] in addition, Figure 6 The diagram also shows a base station chip prototype 60. As previously mentioned, this base station chip prototype 60 can be a base station chip prototype obtained by loading another bitstream file onto another chip prototype verification platform. This other bitstream file is a bitstream file corresponding to the base station chip prototype. This base station chip prototype is the object under test. For example, the base station chip prototype can be a satellite base station chip prototype.

[0083] In some embodiments, such as Figure 6As shown, the terminal simulation model 50 includes: a physical layer signal processing module 510, a physical layer control module 520, and a protocol stack module 530. The physical layer signal processing module 510 performs physical layer signal processing via the hardware of the chip prototype verification platform. The physical layer control module 520 performs physical layer scheduling on the chip prototype verification platform. The protocol stack module 530 implements protocol stack processing on the chip prototype verification platform.

[0084] In related technologies, terminal instrument verification has the following drawbacks: it only supports standard protocols and cannot verify custom communication protocols; the instruments are costly and inflexible, making it difficult to meet customized verification needs. PC software verification has the following drawbacks: software simulation is difficult to match the high-speed performance of the prototype verification platform, resulting in low verification efficiency; it cannot accurately reflect the terminal's runtime sequence, and the verification results deviate from actual operation.

[0085] The system described in this disclosure implements a hardware and software joint base station chip prototype verification system, which can support closed-loop data link connection (data call) verification of custom communication protocols, improve verification efficiency, and accurately reflect the terminal's runtime sequence. For example, this system can be a prototype verification system for a custom protocol base station chip, mainly comprising a simplified satellite terminal simulation model and an adaptation interface.

[0086] In the above system, the terminal simulation model can be simplified. As mentioned above, the terminal simulation model is designed in modules, namely the physical layer signal processing module, the physical layer control module (or physical layer scheduling module), and the protocol stack module.

[0087] Physical layer signal processing module: By generating bitfiles, physical layer signal processing is implemented on FPGA hardware (e.g., physical layer signal processing for satellite terminals), reducing the burden of software simulation.

[0088] Physical layer control module: Generates a high-performance CPU core bitfile and runs it on FPGA hardware, on which simplified physical layer scheduling (e.g., satellite terminal physical layer scheduling) is implemented in software, reducing implementation complexity.

[0089] Protocol stack module: Generates a high-performance CPU core bitfile and runs it on FPGA hardware, on which a simplified protocol stack (e.g., satellite terminal protocol stack) is implemented in software, reducing the model size.

[0090] In addition, in the above system, an adapter was used to implement the adaptation interface.

[0091] RTL simplification: Remove the RF front-end of the base station (e.g., satellite base station) and terminal chip (e.g., satellite terminal chip), and simplify the interface design by connecting via I / Q data.

[0092] Common clock design: The terminal bitfile and the adapter share a clock to ensure timing consistency.

[0093] Adapter Design: An adapter is added between the terminal bitfile and the base station bitfile to match the input and output signals at both ends, including data format and pinout. A FIFO can also be incorporated into the adapter to eliminate short-term clock differences and ensure stable data transmission.

[0094] The above system enables joint hardware and software verification. That is, physical layer signal processing is implemented through hardware, and scheduling and protocol stack are implemented through software. Customized communication protocol closed-loop data link connection verification can be achieved without being limited by instruments, thus improving verification efficiency and accuracy.

[0095] Furthermore, the aforementioned system can simplify the terminal simulation model, that is, by implementing terminal functions through hardware (FPGA) and software collaboration, maintaining the flexibility of implementation, and reducing model complexity and maintenance difficulty.

[0096] The system also implements an adapter interface design, which simplifies RTL design, clock sharing, and adapters to ensure efficient connection between the base station chip prototype and the terminal simulation model.

[0097] The system described in this embodiment of the disclosure has the following advantages: (1) Support for custom protocol verification: By simplifying the terminal simulation model, the verification of custom communication protocols is supported, which solves the limitation of terminal instruments in verifying closed-loop data link connections. In some cases, by upgrading the terminal bitfile and software, base stations with more communication protocols can be verified.

[0098] (2) Improve verification efficiency: Implement physical layer signal processing through hardware to reduce the burden of software simulation and improve verification efficiency.

[0099] (3) Realistically reflect the terminal's runtime sequence: Through joint verification of software and hardware, the terminal's runtime sequence is accurately reflected, thereby improving the accuracy of the verification results.

[0100] The working process of the above system is described in detail below.

[0101] Phase 1: The terminal simulation model is powered on and provides a clock signal to the object under test (base station chip prototype) through the adapter signal.

[0102] The adapter connects the base station's digital signal input / output port and the terminal's digital signal input / output port, and the exchanged signals are as follows: Terminal sends to base station: data valid indication pulse (sample level), data value signal, FIFO (First In First Out queue) for flow rate control of data stream.

[0103] From base station to terminal: Base station data preparation completion indication (pulse signal), data value signal, FIFO (First In First Out queue) is used to control the flow rate of data stream.

[0104] By controlling the terminal clock frequency, access registration and interaction between different cell bandwidths can be achieved. In the future, the simulated Doppler channel can also be extended to add frequency offset to the interaction data.

[0105] Phase Two: Power-on, Cell Search and Synchronization (Acquiring MIB (Master Information Block)) 1. Terminal simulation model startup: Protocol stack module, physical layer control module, and physical layer signal processing module are initialized.

[0106] 2. Frequency scanning: The physical layer control module of the terminal simulation model schedules the physical layer signal processing module to scan on the supported frequency bands according to its capabilities.

[0107] 3. Synchronization signal detection (physical layer core processing): (1) The physical layer signal processing module reads the data sent by the object under test (base station chip prototype) from the adapter FIFO.

[0108] (2) Synchronization: The physical layer signal processing module searches for the primary synchronization signal (PSS) and secondary synchronization signal (SSS) in the time domain. It finds them through related operations, thereby completing: timing synchronization of symbols, time slots, and frames; obtaining the physical layer cell ID; and preliminary frequency synchronization.

[0109] 4. The physical layer signal processing module decodes the PBCH (Physical Broadcast Channel): (1) OFDM (Orthogonal Frequency Division Multiplexing) demodulation: FFT (Fast Fourier Transform) is performed on the SSB (synchronization signal block) symbols carrying PSS / SSS / PBCH to transfer them to the frequency domain.

[0110] (2) Channel estimation and equalization: Channel estimation is performed using the DMRS (Demodulation Reference Signal) embedded in the PBCH to compensate for channel effects.

[0111] (3) De-resource mapping: Extract the modulation symbols of PBCH from the resource grid of SSB.

[0112] (4) Demodulation: Demodulate the symbols into a bit stream (QPSK (Quadrature Phase Shift Keying)).

[0113] (5) Deinterleaving, channel decoding (Polar code), descrambling code.

[0114] (6) CRC (Cyclic Redundancy Check) verification: If successful, the main information block is obtained.

[0115] 5. Information Reporting: The physical layer signal processing module delivers the decoded MIB (containing the most important system information, such as SFN (System Frame Number), subcarrier spacing, initial downlink bandwidth, etc.) to the physical layer control module.

[0116] Phase 3: Receiving system information (acquiring SIB1 and other SIBs). Here, SIB stands for System Information Block. 1. Higher Layer Commands: The physical layer control module of the terminal simulation model configures the physical layer signal processing module to listen to the PDCCH (Physical Downlink Control Channel) based on the information in the MIB. The PDCCH is scrambled with SI-RNTI (System Information RNTI) and used to schedule the PDSCH (Physical Downlink Shared Channel) carrying SIB1.

[0117] 2. Monitoring PDCCH and decoding PDSCH (physical layer core processing): (1) PDCCH blind detection: The physical layer control module schedules the physical layer signal processing module within the configured search space to attempt to descramble and decode the PDCCH using SI-RNTI and obtain the DCI (Downlink Control Information) of the scheduling SIB1.

[0118] (2) Receiving PDSCH: The physical layer signal processing module receives the PDSCH signal according to the time and frequency resources indicated by DCI. The processing flow is the same as above (demapping -> equalization -> demodulation -> deinterleaving -> decoding (LDPC (Low-Density Parity-Check Code)).

[0119] 3. Information delivery and parsing: The terminal physical layer signal processing module delivers the decoded SIB1 data to the physical layer control module.

[0120] 4. Higher Layer Processing: The physical layer control module parses SIB1. SIB1 is crucial, as it contains: a list of operator PLMNs (Public Land Mobile Networks), tracking area codes, and scheduling information for other system information (such as SIB2, SIB3, etc.).

[0121] 5. Cell Selection: The physical layer control module selects an available PLMN and a suitable cell based on the SIB1 information and decides where to camp. Simultaneously, the camping result is reported to the protocol stack module.

[0122] Phase 4: Initiating Random Access (RACH (Random Access Channel)) – Msg1 and Msg3 1. Higher layer trigger: In order to initiate registration, the protocol stack module of the terminal emulation model initiates a random access process and notifies the physical layer control module.

[0123] 2. Send Msg1 (random access preamble): (1) The protocol stack selects preamble and PRACH (Physical Random Access Channel) resources.

[0124] (2) The physical layer signal processing module generates the corresponding ZC sequence, performs DFT-s-OFDM (Discrete Fourier Transform Extended Orthogonal Frequency Division Multiplexing) modulation, adds CP (Cyclic Prefix), and sends it to the adapter FIFO at a specified time.

[0125] 3. Receive Msg2 (Random Access Response, RAR): (1) Physical layer signal processing module: Listen to PDCCH (Blind detection RA-RNTI (Random Access RNTI)) -> Decode DCI -> Receive and decode PDSCH -> Obtain RAR.

[0126] (2) Reporting to higher layers: The physical layer signal processing module delivers the RAR data to the protocol stack module. The protocol stack module parses the RAR and obtains: Uplink Resource Grant (UL Grant, used to send Msg3) and Temporary Cell Radio Network Identifier.

[0127] 4. Send Msg3 (first scheduled uplink transmission): (1) High-level assembly: The protocol stack module generates the first RRC message - RRCSetupRequest (RRC connection establishment request, which includes the initial identity of the registration) and assembles it into a transport block.

[0128] (2) Physical layer transmission processing: Perform a complete transmission chain processing on this TB (Transport Block): CRC attachment -> LDPC channel coding -> Scrambling with TC-RNTI (Temporary C-RNTI, Temporary Cell Radio Network Temporary Identifier) ​​-> Modulation -> Resource mapping (using UL Grant in RAR) -> OFDM modulation -> Send to the adapter's FIFO.

[0129] Phase 5: Race condition resolution and RRC connection establishment (Msg4 and registration request) 1. Process Msg4: (1) Physical layer reception: The physical layer signal processing module reads data from the adapter FIFO, decodes PDCCH / PDSCH, obtains data, and sends it to the protocol stack module.

[0130] (2) High-level parsing: The protocol stack module completes the contention resolution and parses the RRCSetup message.

[0131] (3) Establish SRB1 (SRB stands for Signaling Radio Bearer): Establish Signaling Radio Bearer 1 according to the message configuration.

[0132] 2. Send registration request: (1) Higher layer generation: The protocol stack module generates an RRCSetupComplete message (RRC connection established). This message embeds a Registration Request from the NAS (Non-Access Stratum) layer.

[0133] (2) Physical layer transmission: The message is sent to the adapter FIFO via the newly established SRB1, through uplink scheduling, processed by the terminal physical layer signal processing module.

[0134] Phase Six: Registration Completed 1. Terminal Confirmation: The physical layer signal processing module receives data from the adapter FIFO, processes it, and sends it to the protocol stack for assembly into an RRCReconfiguration message. The protocol stack module assembles the RRCReconfigurationComplete message, which is then processed by the physical layer signal processing module and sent to the adapter FIFO.

[0135] 2. Registration Complete: At this point, the terminal has successfully registered and entered the RRC_CONNECTED state (RRC connected state), and can begin transmitting business data.

[0136] Phase Seven: Data Transmission All subsequent air interface signaling and data transmission rely on the coordinated operation of the aforementioned adapter and physical signal processing module transceiver processing chain, as well as the protocol stack module.

[0137] This concludes the description of the operation of the system described in the embodiments of this disclosure.

[0138] In some embodiments, this disclosure also provides a computer-readable storage medium (e.g., a non-transitory computer-readable storage medium) having stored thereon computer program instructions that are implemented when executed by a processor. Figure 1 and / or Figure 2 The steps of the method in the corresponding embodiments are described. Those skilled in the art will understand that embodiments of this disclosure can be provided as methods, apparatus, or computer program products. Therefore, this disclosure can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, this disclosure can take the form of a computer program product embodied on one or more computer-usable non-transitory storage media (including, but not limited to, disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0139] This disclosure is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of this disclosure. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create a machine for implementing the flowchart illustrations and / or block diagrams. Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0140] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0141] These computer program instructions may also be loaded onto a computer or other programmable data processing equipment to cause a series of operational steps to be performed on the computer or other programmable equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0142] In some embodiments of this disclosure, a computer program product is also provided, which includes a computer program or instructions that, when executed by a processor, implement the base station chip prototype verification method as described above.

[0143] In some embodiments of this disclosure, a computer program is also provided, comprising: instructions that, when executed by a processor, cause the processor to perform the base station chip prototype verification method as described above.

[0144] This concludes the detailed description of the present disclosure. To avoid obscuring the concept of the disclosure, some details known in the art have not been described. Those skilled in the art will fully understand how to implement the technical solutions disclosed herein based on the above description.

[0145] While specific embodiments of this disclosure have been described in detail by way of example, those skilled in the art should understand that the examples are for illustrative purposes only and not intended to limit the scope of this disclosure. Those skilled in the art should understand that modifications can be made to the above embodiments without departing from the scope and spirit of this disclosure. The scope of this disclosure is defined by the appended claims.

Claims

1. A method for prototype verification of a base station chip, comprising: Receive a first data stream from a terminal simulation model, wherein the terminal simulation model is obtained by loading a bitstream file on a chip prototype verification platform, and the first data stream includes one or more first timestamps; Based on the one or more first timestamps, the first data stream is converted into one or more first data packets; and The one or more first data packets are transmitted to the base station chip prototype.

2. The base station chip prototype verification method according to claim 1, wherein: Receiving a first data stream from a terminal simulation model includes: receiving the first data stream from the terminal simulation model through a first FIFO module; Transmitting the one or more first data packets to the base station chip prototype includes: transmitting the one or more first data packets to the base station chip prototype via a second FIFO module.

3. The base station chip prototype verification method according to claim 2, wherein, Based on the one or more first timestamps, the first data stream is converted into one or more first data packets, including: The processing module receives the first data stream from the first FIFO module, and the data format of the first data stream is the first data format. Convert the first data stream from the first data format to the second data format; Obtain one or more first timestamps from the first data stream having the second data format; One or more first data headers are determined based on the one or more first timestamps; and Based on the one or more first data headers, the first data stream is converted into one or more first data packets.

4. The base station chip prototype verification method according to claim 1 further includes: Receive one or more second data packets from the base station chip prototype; Based on one or more second timestamps, the one or more second data packets are converted into a second data stream; and The second data stream is transmitted to the terminal simulation model.

5. The base station chip prototype verification method according to claim 4, wherein: Receiving one or more second data packets from the base station chip prototype includes: receiving one or more second data packets from the base station chip prototype via a second FIFO module; Transmitting the second data stream to the terminal simulation model includes: transmitting the second data stream to the terminal simulation model through a first FIFO module.

6. The base station chip prototype verification method according to claim 1, wherein, The chip prototype verification platform is a field-programmable gate array (FPGA).

7. An adapter, comprising: The first FIFO module is used to receive a first data stream from a terminal simulation model, wherein the terminal simulation model is obtained by loading a bitstream file on a chip prototype verification platform, and the first data stream includes one or more first timestamps. The processing module is configured to convert the first data stream into one or more first data packets based on the one or more first timestamps; and The second FIFO module is used to transmit the one or more first data packets to the base station chip prototype.

8. The adapter according to claim 7, wherein, The processing module is configured to receive the first data stream from the first FIFO module, wherein the data format of the first data stream is a first data format, convert the first data stream from the first data format to a second data format, obtain one or more first timestamps from the first data stream having the second data format, determine one or more first data headers based on the one or more first timestamps, and convert the first data stream into one or more first data packets based on the one or more first data headers.

9. The adapter according to claim 7, wherein: The second FIFO module is also used to receive one or more second data packets from the base station chip prototype; The processing module is further configured to convert the one or more second data packets into a second data stream based on one or more second timestamps; The first FIFO module is also used to transmit the second data stream to the terminal simulation model.

10. An adapter, comprising: Memory; as well as A processor coupled to the memory, the processor being configured to execute the base station chip prototype verification method as described in any one of claims 1 to 6 based on instructions stored in the memory.

11. A base station chip prototype verification system, comprising: The adapter as described in any one of claims 7 to 10; and The terminal simulation model is obtained by loading a bitstream file on a chip prototype verification platform.

12. The base station chip prototype verification system according to claim 11, wherein, The terminal simulation model includes: A physical layer signal processing module is used to perform physical layer signal processing through the hardware of the chip prototype verification platform; The physical layer control module is used for physical layer scheduling on the chip prototype verification platform; and The protocol stack module is used to implement protocol stack processing on the chip prototype verification platform.

13. A computer-readable storage medium having stored thereon computer instructions that, when executed by a processor, implement the base station chip prototype verification method as described in any one of claims 1 to 6.

14. A computer program product comprising a computer program or instructions that, when executed by a processor, implement the base station chip prototype verification method as described in any one of claims 1 to 6.

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