Focal plane array circuit, data readout method thereof, and photodetector
By introducing first and second switching circuits into the focal plane array circuit, the counters are cascaded, which solves the problem of analog signal crosstalk caused by increasing the integrating capacitor, realizes the increase of full-well charge and the improvement of detector performance, and supports miniaturization design.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- WUXI SHENGWEI TECH DEV CO LTD
- Filing Date
- 2026-02-24
- Publication Date
- 2026-06-23
AI Technical Summary
Existing focal plane array circuits, when increasing the integrating capacitor, have a problem that goes against the trend of pixel miniaturization. Furthermore, the inability of the CMOS transmission gate switch to be completely closed causes crosstalk between analog signals during the integration process of adjacent pixels, affecting image quality.
By introducing first and second switching circuits into the focal plane array circuit, the counters are cascaded to increase the full-well charge in the digital domain while avoiding analog signal crosstalk. By cascading the counters in pixel merging mode, the full-well charge is increased without increasing the pixel unit size.
This technology enables the addition of full-well charge in the digital domain, improving the detector's response sensitivity and dynamic range while avoiding analog signal crosstalk and supporting miniaturized design.
Smart Images
Figure CN122269166A_ABST
Abstract
Description
Technical Field
[0001] This disclosure relates to the field of photoelectric detection technology, and in particular to a focal plane array circuit, its data readout method, and a photoelectric detector. Background Technology
[0002] The full-well charge of a pixel is a crucial performance indicator for focal plane array circuits (also known as focal plane readout circuits), directly affecting the detector's response sensitivity and dynamic range to light radiation. In related technologies, considering that the full-well charge of a pixel is positively correlated with the size of its integrating capacitance (a larger charge storage capacity means the pixel can hold more charge generated by photoelectric conversion, thus making the detector more sensitive to infrared radiation), increasing the pixel's integrating capacitance is generally used to improve the full-well charge.
[0003] In related technologies, there are two ways to increase the integrating capacitance: First, increase the overall area of the integrating capacitance to increase the integrating capacitance. However, this method contradicts the trend of pixel miniaturization. Second, set a CMOS transmission gate switch between the integrating capacitances of adjacent pixels. When operating in pixel binning mode, the CMOS transmission gate switch is turned on so that the integrating capacitances of adjacent pixels are connected in parallel to increase the integrating capacitance, that is, increase the integrating capacitance through pixel binning. However, when pixel binning mode is turned off, because the CMOS transmission gate switch cannot be completely turned off (leakage current and other issues), the analog signals generated by the integration process of adjacent pixels will interfere with each other, affecting the image quality. Summary of the Invention
[0004] This disclosure aims to at least solve one of the technical problems existing in the prior art, and proposes a focal plane array circuit, its data readout method, and a photodetector.
[0005] In a first aspect, embodiments of this disclosure provide a focal plane array circuit, comprising: at least one pixel unit group, the pixel unit group comprising at least two pixel units, the pixel unit comprising: a sensing pulse output circuit and a counter, the counter being connected to the output terminal of the sensing pulse output circuit, the sensing pulse output circuit being configured to output a corresponding number of pulse signals according to the sensed light signal during the sensing phase, and the counter being configured to count the pulse signals output by the sensing pulse output circuit;
[0006] Each pixel unit in the pixel unit group, except for the first pixel unit, is respectively configured with a corresponding first switch circuit and a second switch circuit.
[0007] The first terminal of the first switching circuit is connected to the sensing pulse output circuit in the corresponding pixel unit, and the second terminal of the first switching circuit is connected to the counter in the corresponding pixel unit.
[0008] The first terminal of the second switching circuit is connected to the counter in the corresponding pixel unit, and the second terminal of the second switching circuit is connected to the counter in the previous pixel unit of the corresponding pixel unit. When the second switching circuit is in the on state, the two counters connected to the second switching circuit are cascaded.
[0009] In some embodiments, the counter is an N-bit counter, which includes N cascaded flip-flops. The clock signal input of any of the N-1 flip-flops other than the first-stage flip-flop is connected to the cascade carry output of the flip-flop preceding it.
[0010] The second terminal of the first switching circuit is connected to the clock signal input terminal of the first stage flip-flop in the counter corresponding to the pixel unit;
[0011] The first terminal of the second switching circuit is connected to the clock signal input terminal of the first stage flip-flop in the counter within the corresponding pixel unit, and the second terminal of the second switching circuit is connected to the cascade carry output terminal of the last stage flip-flop in the counter within the preceding pixel unit.
[0012] In some embodiments, the first switching circuit includes: a first transistor, the control electrode of the first transistor being connected to a first control signal terminal, the first electrode of the first transistor being connected to the sensing pulse output circuit corresponding to the pixel unit, and the second electrode of the first transistor being connected to the counter corresponding to the pixel unit;
[0013] and / or;
[0014] The second switching circuit includes: a second transistor, the control electrode of the second transistor being connected to a second control signal terminal, the first electrode of the second transistor being connected to the counter in the corresponding pixel unit, and the second electrode of the second transistor being connected to the counter in the previous pixel unit corresponding to the pixel unit.
[0015] In some embodiments, the counter connected to the first terminal of the second switching circuit and the counter connected to the second terminal of the second switching circuit are two counters within adjacent pixel units.
[0016] In some embodiments, the pixel unit group includes a plurality of pixel units arranged in an array M×M, where M≥2 and is an integer.
[0017] In some embodiments, the pixel unit further includes:
[0018] A memory, connected to the counter, is configured to store the counting results of the counter.
[0019] In some embodiments, the sensing pulse output circuit includes: a photodiode, an input transistor, an integrating capacitor, an integrating reset transistor, a charge compensation transistor, a comparator, and a logic control generation circuit;
[0020] The first end of the photodiode is connected to the first voltage supply terminal, and the second end of the photodiode is connected to the first terminal of the input transistor;
[0021] The control terminal of the input transistor is connected to the input control signal terminal, and the second terminal of the input transistor is connected to the first terminal of the integrating capacitor.
[0022] The control terminal of the integral reset transistor is connected to the integral reset control signal terminal, the first terminal of the integral reset transistor is connected to the reset voltage supply terminal, and the second terminal of the integral reset transistor is connected to the first terminal of the integral capacitor.
[0023] The control electrode of the charge compensation transistor is connected to the logic control generation circuit, the first electrode of the charge compensation transistor is connected to the reset voltage supply terminal, and the second electrode of the charge compensation transistor is connected to the first terminal of the integrating capacitor.
[0024] The first terminal of the integrating capacitor is connected to the first phase input terminal of the comparator, and the second terminal of the integrating capacitor is connected to the second voltage supply terminal.
[0025] The second phase input terminal of the comparator is connected to the reference voltage supply terminal, the output terminal of the comparator is connected to the logic control generation circuit, and the output terminal of the comparator serves as the output terminal of the sensing pulse output circuit.
[0026] The logic control generation circuit is configured to provide a corresponding effective level control signal to the charge compensation transistor when the signal output by the output terminal of the comparator changes from a first preset level to a second preset level, so as to control the charge compensation transistor to turn on.
[0027] In a second aspect, embodiments of this disclosure provide a photodetector, including: the focal plane array circuit as provided in the first aspect.
[0028] Thirdly, embodiments of this disclosure provide a data readout method for a focal plane array circuit, characterized in that the focal plane array circuit is the focal plane array circuit provided in the first aspect, and the data readout method includes:
[0029] During the sensing phase, when in pixel merging mode, the first switching circuit is in an open state and the second switching circuit is in an open state. The sensing pulse output circuit in the first pixel unit in the pixel unit group outputs a corresponding number of pulse signals according to the sensed light signal. The counters in all the pixel units in the pixel unit group are cascaded and perform cascade counting on the pulse signals output by the sensing pulse output circuit in the first pixel unit.
[0030] In some embodiments, the data reading method further includes:
[0031] During the sensing phase, when in full-frame mode, the first switching circuit is in the on state and the second switching circuit is in the off state. The sensing pulse output circuit in each pixel unit of the pixel unit group outputs a corresponding number of pulse signals according to the sensed light signal. The counter in each pixel unit counts the pulse signals output by the sensing pulse output circuit in the same pixel unit.
[0032] This disclosed technical solution adds a first switching circuit and a second switching circuit within the pixel unit group, enabling cascaded counting of counters within the pixel unit group when the planar array circuit operates in pixel merging mode, thereby increasing the full-well charge in the digital domain. This technical solution also avoids increasing the size of the pixel units, facilitating product miniaturization. Furthermore, since the second switching circuit is positioned between the two counters, it effectively avoids the problem of crosstalk between analog signals generated during the integration process of adjacent pixels in related technologies. Simultaneously, when the planar array circuit operates in full-frame mode, the pulse signals output by the sensing pulse output circuits in the two pixel units connected through the second switching circuit are digital signals, and no crosstalk occurs when the second switching circuit is open. Attached Figure Description
[0033] Figure 1 A schematic diagram of the circuit structure of a focal plane array circuit provided in an embodiment of this disclosure;
[0034] Figure 2 This is a schematic diagram of a circuit structure for a pixel unit group in an embodiment of this disclosure;
[0035] Figure 3 This is a schematic diagram of the equivalent circuit structure of a pixel unit group in pixel merging mode in this disclosure;
[0036] Figure 4 This is a schematic diagram of the equivalent circuit structure of a pixel unit group in the full-frame mode merging mode of this disclosure;
[0037] Figure 5 This is a schematic diagram of the circuit structure of the counter section within a pixel unit group in an embodiment of this disclosure;
[0038] Figure 6 This is a schematic diagram of a circuit structure for a sensing pulse output circuit within a pixel unit in an embodiment of this disclosure;
[0039] Figure 7 for Figure 6 The diagram shows a timing diagram of a sensing pulse output circuit.
[0040] Figure 8 A flowchart illustrating a data readout method for a focal plane array circuit provided in an embodiment of this disclosure. Detailed Implementation
[0041] To enable those skilled in the art to better understand the technical solutions of this disclosure, the disclosure will be further described in detail below with reference to the accompanying drawings and specific embodiments.
[0042] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Similarly, the terms “an,” “a,” or “the,” and similar terms do not indicate a quantity limitation, but rather indicate the presence of at least one. The terms “including,” “comprising,” or “containing,” and similar terms mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. The terms “connected,” “linked,” or similar terms are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. The terms “upper,” “lower,” “left,” and “right,” etc., are used only to indicate relative positional relationships, and these relative positional relationships may change accordingly when the absolute position of the described object changes.
[0043] In the various figures, the same elements are represented by similar reference numerals. For clarity, not all parts in the figures are drawn to scale. Furthermore, some well-known parts may not be shown in the figures.
[0044] Many specific details of this disclosure, such as the structure, materials, dimensions, processing methods, and techniques of the components, are described below to provide a clearer understanding of the disclosure. However, as those skilled in the art will understand, this disclosure may be implemented without following these specific details.
[0045] The transistors used in the embodiments of this disclosure can be thin-film transistors, field-effect transistors, or other devices with the same or similar characteristics. Since the source and drain of the transistors are symmetrical, there is no distinction between them. In this disclosure, one of the two terminals of the transistor, excluding the control terminal (i.e., the gate), is referred to as the first terminal and the other as the second terminal. The transistors used in the embodiments of this disclosure can be N-type transistors or P-type transistors. In the embodiments of this disclosure, when an N-type thin-film transistor is used, its first terminal can be the source and its second terminal can be the drain. In this disclosure, "effective level" refers to the level that controls the corresponding transistor to conduct, and "ineffective level" refers to the level that controls the corresponding transistor to be off. For N-type transistors, the effective level is high and the ineffective level is low; for P-type transistors, the effective level is low and the ineffective level is high. In the following embodiments, when the described transistor type changes, the timing of the drive signal needs to be adjusted accordingly. Specific details are not elaborated here, but should still be within the scope of protection of this disclosure.
[0046] Figure 1 This is a schematic diagram of the circuit structure of a focal plane array circuit provided in an embodiment of the present disclosure. Figure 2 This is a schematic diagram of a circuit structure for a pixel unit group in an embodiment of this disclosure. Figure 1 and Figure 2 As shown, it includes: at least one pixel unit group PG, the pixel unit group PG includes at least two pixel units PIX, the pixel unit PIX includes: a sensing pulse output circuit 1 and a counter 2, the counter 2 is connected to the output terminal of the sensing pulse output circuit 1, the sensing pulse output circuit 1 is configured to output a corresponding number of pulse signals according to the sensed light signal during the sensing phase, and the counter 2 is configured to count the pulse signals output by the sensing pulse output circuit 1.
[0047] In this disclosure, each pixel unit PIX in the pixel unit group PG, except for the first pixel unit PIX, is respectively equipped with a corresponding first switching circuit SW1 and a second switching circuit SW2. The first terminal of the first switching circuit SW1 is connected to the sensing pulse output circuit 1 in the corresponding pixel unit PIX, and the second terminal of the first switching circuit SW1 is connected to the counter 2 in the corresponding pixel unit PIX. The first terminal of the second switching circuit SW2 is connected to the counter 2 in the corresponding pixel unit PIX, and the second terminal of the second switching circuit SW2 is connected to the counter 2 in the previous pixel unit PIX of the corresponding pixel unit PIX. When the second switching circuit SW2 is in the on state, the two counters 2 connected to the second switching circuit SW2 are cascaded.
[0048] In this disclosure, cascading of counters 2 refers to cascading two or more counters 2 in sequence (e.g., ...).Figure 2 The sequences ① to ④ shown are connected and, based on the carry principle, form a counter 2 with a larger number of bits (increasing the counting range). As an example, cascading two N-bit binary counters 2 results in a 2N-bit binary counter 2 with a counting range of [0, 2^N]. N -1]; Similarly, by cascading K N-bit binary counters 2, we can obtain one K*N-bit binary counter 2, with a counting range of [0, 2]. K*N -1].
[0049] The pixel unit in this disclosure is a digital pixel unit employing digital integration. The sensing pulse output circuit includes a photodiode and an integration processing circuit. The photodiode provides a corresponding electrical signal to the integration processing circuit based on the sensed light signal. The integration processing circuit performs digital domain integration processing based on the electrical signal output by the photodiode and outputs a corresponding number of pulse signals. Generally, within a fixed-duration sensing phase, the higher the intensity of the light signal sensed by the photodiode, the more pulse signals the sensing pulse output circuit outputs. Based on this, the intensity of the light signal can be obtained by counting the number of pulse signals output by the sensing pulse output circuit during the sensing phase using a counter.
[0050] The technical solution disclosed herein does not limit the specific circuit structure of the sensing pulse output circuit 1. The specific circuit structure of the sensing pulse output circuit 1 described below is only an optional implementation scheme in this disclosure and will not limit the technical solution of this disclosure.
[0051] Furthermore, the focal plane array circuit shown in the embodiment, which includes multiple pixel unit groups PG, with each pixel unit PIX group comprising 2×2 pixel units PIX, and four pixel units PIX arranged in the order of ① to ④ in the figure, is merely an optional implementation scheme of this disclosure and does not limit the technical solution of this disclosure. In this disclosure, the number of pixel unit groups PG included in the focal plane array circuit can be one, two, or even more, and the number of pixel units PIX included in each pixel unit group PG can be the same or different, as long as the number of pixel units PIX in each pixel unit group PG is greater than or equal to two.
[0052] Figure 3 This is a schematic diagram of the equivalent circuit structure of a pixel unit group in the pixel merging mode of this disclosure. Figure 4 This is a schematic diagram of the equivalent circuit structure of a pixel unit group in the full-frame mode merging mode of this disclosure. For example... Figure 3 and Figure 4As shown, the focal plane array circuit in this disclosure has two operating modes: pixel binning mode and full-frame mode, and can switch between these two modes as needed. Generally, when high-sensitivity detection or high-brightness environment detection is required, the focal plane array circuit can operate in pixel binning mode; while when high-resolution detection is required, the focal plane array circuit can operate in full-frame mode (also known as the conventional operating mode). The operating principle of the focal plane array circuit provided in this disclosure will be described in detail below with reference to the accompanying drawings.
[0053] For ease of description, Figure 2 to Figure 4 In the pixel unit group PG shown in the figure, the pixel unit PIX in the upper left corner is called the first pixel unit PIX, the pixel unit PIX in the upper right corner is called the second pixel unit PIX, the pixel unit PIX in the lower right corner is called the third pixel unit PIX, and the pixel unit PIX in the lower left corner is called the fourth pixel unit PIX.
[0054] See Figure 3 As shown, when the planar array circuit operates in pixel merging mode, a pixel unit group PG can be considered as a merged pixel. At this time, the first switching circuit SW1 is in an open-circuit state, and the second switching circuit SW2 is in a closed-circuit state. Since the first switching circuit SW1 is in an open-circuit state, the sensing pulse output circuits 1 in the second to fourth pixel units are all disconnected from the counters 2 in their respective pixel units. The second to fourth pixel units are equivalent to blind cells, and only the sensing pulse output circuit 1 in the first pixel unit forms a closed circuit with the counter 2. Because the second switching circuit SW2 is in a closed-circuit state, the counters 2 in the second and third pixel units are cascaded, the counters 2 in the third and fourth pixel units are cascaded, forming a large-digit counter 2. This large-digit counter 2 can count the number of pulse signals output by the sensing pulse output circuit 1 in the first pixel unit.
[0055] Taking an example where each counter 2 is an N-bit binary counter 2, the four counters 2 within the pixel unit group PG constitute a 4*N-bit binary counter 2. In this case, the count result of counter 2 in the first pixel unit PIX represents bits 1 to N of the final quantization result; the count result in the second pixel unit PIX represents bits N+1 to 2N of the final quantization result; the count result in the third pixel unit PIX represents bits 2N+1 to 3N of the final quantization result; and the count result in the fourth pixel unit PIX represents bits 3N+1 to 4N of the final quantization result. Therefore, it can be seen that the number of quantization bits in the merged pixel after digitization pixel merging is four times the number of quantization bits in the original single pixel.
[0056] The full well charge of the merged pixel It can be obtained based on the following formula:
[0057]
[0058] in, Let C be the capacitance of the integrating capacitor in the first pixel unit PIX. This is the preset integral pressure difference.
[0059] The dynamic range (DR) of the merged pixels can be obtained based on the following formula:
[0060]
[0061] in, To merge the dynamic range of pixels, This indicates the standard form for converting voltage ratios to decibels (dB). This indicates the maximum signal amplitude that the circuit system can handle (related to the number of bits 4*N and the integral voltage difference). DR represents the pixel noise power during one integration process. DR reflects the ratio of the maximum signal that the circuit system can process to the minimum detectable signal (noise floor). The larger the DR value, the better the performance of the circuit system, as it can capture weaker signals without distorting strong signals.
[0062] See Figure 3As shown, when the planar array circuit operates in full-frame mode, each pixel unit (PIX) within the pixel unit group PG operates independently. At this time, the first switching circuit SW1 is in the on state, and the second switching circuit SW2 is in the off state. Because the first switching circuit SW1 is in the on state, the sensing pulse output circuits 1 in the first to fourth pixel units (PIX) are all connected to the counters 2 within their respective pixel units (PIX). Simultaneously, because the second switching circuit SW2 is in the off state, the counters 2 in the second pixel unit (PIX) are not cascaded with the counters 2 in the first pixel unit (PIX), the counters 2 in the third pixel unit (PIX) are not cascaded with the counters 2 in the second pixel unit (PIX), and the counters 2 in the fourth pixel unit (PIX) are not cascaded with the counters 2 in the third pixel unit (PIX). At this time, the counters 2 in each pixel unit (PIX) within the pixel unit group PG count the pulses output by the sensing pulse output circuit 1 within their respective pixel unit (PIX).
[0063] At this point, for any pixel unit PIX, the full-well charge of a single pixel is... and dynamic range We can obtain them based on the following formulas:
[0064]
[0065]
[0066] Comparison revealed that the full-well charge of the planar array circuit operating in pixel-binning mode is equal to its full-well charge operating in full-frame mode. times, that is The dynamic range of a planar array circuit operating in pixel binning mode is greater than its dynamic range operating in full-frame mode. ,Right now .
[0067] As can be seen from the above, the technical solution of this disclosure, by adding a first switching circuit SW1 and a second switching circuit SW2 within the pixel unit group PG, enables the planar array circuit to operate in pixel merging mode, thereby increasing the full-well charge in the digital domain. This design also avoids increasing the size of the pixel unit PIX, which is beneficial for product miniaturization. Furthermore, since the second switching circuit SW2 is located between the two counters 2, it effectively avoids the problem of crosstalk between analog signals generated during the integration process of adjacent pixels in related technologies. Simultaneously, when the planar array circuit operates in full-frame mode, the pulse signals output by the sensing pulse output circuit 1 in the two pixel units PIX connected through the second switching circuit SW2 are digital signals, and no crosstalk occurs when the second switching circuit SW2 is open.
[0068] Figure 5 This is a schematic diagram of the circuit structure of counter 2 within a pixel unit group PG in an embodiment of this disclosure. Figure 5 As shown, in some embodiments, counter 2 is an N-bit counter 2, which includes N cascaded flip-flops trg. The clock signal input terminal C of any of the N-1 flip-flops trg other than the first-stage flip-flop trg is connected to the cascade carry output terminal K of its predecessor flip-flop trg. The second terminal of the first switching circuit SW1 is connected to the clock signal input terminal C of the first-stage flip-flop trg in the counter 2 within the corresponding pixel unit PIX. The first terminal of the second switching circuit SW2 is connected to the clock signal input terminal C of the first-stage flip-flop trg in the counter 2 within the corresponding pixel unit PIX, and the second terminal of the second switching circuit SW2 is connected to the cascade carry output terminal K of the last-stage flip-flop trg in the counter 2 within the pixel unit PIX preceding the corresponding pixel unit PIX.
[0069] When the first switching circuit SW1 in the pixel unit group PG is in the open circuit state and the second switching circuit SW2 is in the closed circuit state, a total of 4N flip-flops trg in the four N-bit counters 2 are cascaded to form a 4N-bit counter 2.
[0070] In some embodiments, the first switching circuit SW1 includes: a first transistor, the control electrode of the first transistor is connected to a first control signal terminal, the first electrode of the first transistor is connected to a sensing pulse output circuit 1 in the corresponding pixel unit PIX, and the second electrode of the first transistor is connected to a counter 2 in the corresponding pixel unit PIX.
[0071] The second switching circuit SW2 includes: a second transistor, the control electrode of the second transistor is connected to the second control signal terminal, the first electrode of the second transistor is connected to the counter 2 in the corresponding pixel unit PIX, and the second electrode of the second transistor is connected to the counter 2 in the previous pixel unit PIX of the corresponding pixel unit PIX.
[0072] Taking an example where both the first and second transistors are N-type transistors (e.g., NMOS off); when the focal plane array circuit is in pixel binning mode, the first control signal terminal provides a low-level control signal to control the first transistor to turn off, and the second control signal terminal provides a high-level control signal to control the second transistor to turn on; when the focal plane array circuit is in full-frame mode, the first control signal terminal provides a high-level control signal to control the first transistor to turn on, and the second control signal terminal provides a low-level control signal to control the second transistor to turn off.
[0073] In some embodiments, the counter 2 connected to the first terminal of the second switching circuit SW2 and the counter 2 connected to the second terminal of the second switching circuit SW2 are two counters 2 within adjacent pixel units PIX. That is, two pixel units PIX that are sequentially adjacent within pixel unit group PG are also two pixel units PIX that are physically adjacent. This design can effectively reduce wiring length.
[0074] In some embodiments, the pixel unit group PG includes a plurality of pixel units PIX arranged in an array M×M, where M≥2 and is an integer. Taking an N-bit binary counter 2 within a pixel unit PIX as an example, the full-well charge of the planar array circuit when operating in pixel binning mode is equal to its full-well charge when operating in full-frame mode. The dynamic range of a planar array circuit operating in pixel binning mode is twice that of its operating mode in full-frame mode. .
[0075] In some embodiments, the pixel unit PIX further includes a memory 3; the memory 3 is connected to the counter 2, and the memory 3 is configured to store the counting result of the counter 2. Taking an N-bit counter 2 in the pixel unit PIX as an example, the memory 3 in the pixel unit PIX can also be an N-bit memory 3.
[0076] It should be noted that the accompanying drawings only exemplify the case where the flip-flop trg is a D flip-flop trg. A D flip-flop trg generally has a data sampling terminal D, an output terminal Q, a reset terminal R (reset via a RESET signal), a clock signal input terminal C, and a cascade carry output terminal. The data sampling terminal D and the output terminal Q are both connected to the memory 3 to send the current result of the flip-flop trg to the memory 3 for storage. In this disclosure, the flip-flop trg is not limited to a D flip-flop trg; any flip-flop trg with cascade carry output functionality is applicable to the technical solutions of this disclosure.
[0077] Figure 6 This is a schematic diagram of a circuit structure for a sensing pulse output circuit within a pixel unit in an embodiment of this disclosure. Figure 7 for Figure 6 The diagram shows a timing diagram of a sensing pulse output circuit. Figure 6 and Figure 7 As shown, the sensing pulse output circuit 1 includes: a photodiode PIN, an input transistor T1, an integrating capacitor C, an integrating reset transistor T2, a charge compensation transistor T3, a comparator COMP, and a logic control generation circuit.
[0078] In this circuit, the first terminal of the photodiode PIN is connected to the first voltage supply terminal (providing the first voltage V1), and the second terminal of the photodiode PIN is connected to the first terminal of the input transistor T1. The control terminal of the input transistor T1 is connected to the input control signal terminal GPOL, and the second terminal of the input transistor T1 is connected to the first terminal of the integrating capacitor C. The control terminal of the integrating reset transistor T2 is connected to the integrating reset control signal terminal RST, the first terminal of the integrating reset transistor T2 is connected to the reset voltage supply terminal (providing the reset voltage Vrst), and the second terminal of the integrating reset transistor T2 is connected to the first terminal of the integrating capacitor C. The control terminal of the charge compensation transistor T3 is connected to the logic control generation circuit, the first terminal of the charge compensation transistor T3 is connected to the reset voltage supply terminal, and the second terminal of the charge compensation transistor T3 is connected to the first terminal of the integrating capacitor C. The first terminal of the integrating capacitor C is connected to the first phase input terminal of the comparator COMP, and the second terminal of the integrating capacitor C is connected to the second voltage supply terminal (providing the second voltage V2, for example, ground voltage VGND). The second phase input of comparator COMP is connected to the reference voltage supply terminal (providing the reference voltage Vref), and the output of comparator COMP is connected to the logic control generation circuit. The output of comparator COMP serves as the output of the sensing pulse output circuit 1. The logic control generation circuit is configured to provide a corresponding effective level control signal to the charge compensation transistor T3 when the signal output from the output of comparator COMP changes from a first preset level to a second preset level, thereby controlling the charge compensation transistor T3 to turn on.
[0079] It should be noted that one of the first and second phase inputs of comparator COMP is a non-inverting input (+), and the other is an inverting input (-). This disclosure only provides an example of the case where the non-inverting input (+) of comparator COMP is connected to the reference voltage supply terminal, and the inverting input (-) of comparator COMP is connected to node G.
[0080] Taking an input transistor T1 as an N-type transistor, and an integrating reset transistor T2 and a charge compensation transistor T3 as P-type transistors as an example.
[0081] Before entering the sensing phase, the integral reset control signal terminal RST provides a low-level signal to control the integral reset transistor T2 to turn on, thereby resetting the integral capacitor C, i.e., the voltage at node G is Vrst. After the reset is completed, the sensing phase begins.
[0082] During the sensing phase, the input control signal terminal GPOL provides a high-level signal to control the input transistor T1 to conduct. The electrical signal output by the photodiode PIN (also known as photocurrent) is injected into the integrating capacitor C through the input transistor T1 for integration. When the integrated voltage at node G reaches the reference voltage Vref (slightly less than the reference voltage Vref), the comparator COMP flips to output a high level. The logic control generation circuit detects that the output level of the comparator COMP has flipped from low to high and outputs a high-level pulse to the charge compensation transistor T3. The charge compensation transistor T3 is turned on in response to the high-level pulse, thereby writing the reset voltage Vrst to node G. The comparator COMP outputs a low level again. At this time, the comparator COMP outputs a complete pulse signal for counter 2 to count. The above process is regarded as an integration period T. The above integration period T is repeated until the sensing phase ends. In this case, the aforementioned preset integrated voltage difference... .
[0083] It should be noted that the higher the intensity of the light signal sensed by the photodiode PIN, the greater its output photocurrent, the shorter the time it takes for the voltage at node G to drop from Vrst to Vref, and the smaller the corresponding integration period T. With a fixed sensing phase duration, a smaller integration period T results in a greater number of integration periods, meaning a greater number of pulse signals output by the sensing pulse output circuit 1.
[0084] It should be noted that the above integration process being a voltage drop process at node G is only one optional implementation scheme in this disclosure. In this disclosure, the integration process being a voltage rise process at node G can also be achieved through circuit design, which will not be described in detail in this disclosure.
[0085] Based on the same inventive structure, this disclosure also provides a photodetector, which includes a focal plane array circuit. The focal plane array circuit adopts the focal plane array circuit provided in the previous embodiment. For details, please refer to the previous content, which will not be repeated here.
[0086] Other necessary structures in a photodetector besides the focal plane array circuit, such as drivers and signal processing chips, are not described in this disclosure.
[0087] In some embodiments, the photodetector in this embodiment is an infrared detector.
[0088] Figure 8 A flowchart illustrating a data readout method for a focal plane array circuit provided in this disclosure. Figure 8 As shown, the focal plane array circuit adopts the focal plane array circuit provided in the previous embodiment, and the data reading method of the focal plane array circuit includes:
[0089] Step Sa: During the sensing phase, when in pixel merging mode, the first switching circuit is in the open circuit state and the second switching circuit is in the closed circuit state. The sensing pulse output circuit in the first pixel unit in the pixel unit group outputs a corresponding number of pulse signals according to the sensed light signal. The counters in all pixel units in the pixel unit group are cascaded and perform cascade counting on the pulse signals output by the sensing pulse output circuit in the first pixel unit.
[0090] In some embodiments, the data reading method further includes:
[0091] Step Sb: During the sensing phase, when in full-frame mode, the first switching circuit is in the on state and the second switching circuit is in the off state. The sensing pulse output circuit in each pixel unit in the pixel unit group outputs a corresponding number of pulse signals according to the sensed light signal. The counter in each pixel unit counts the pulse signals output by the sensing pulse output circuit in the same pixel unit.
[0092] The technical solution disclosed herein does not impose any restrictions on the execution order or number of executions of steps Sa and Sb. For a detailed description of steps Sa and Sb, please refer to the preceding section... Figure 3 and Figure 4 The relevant descriptions will not be repeated here.
[0093] It is understood that the above embodiments are merely exemplary embodiments used to illustrate the principles of this disclosure, and this disclosure is not limited thereto. For those skilled in the art, various modifications and improvements can be made without departing from the spirit and substance of this disclosure, and these modifications and improvements are also considered to be within the scope of protection of this disclosure.
Claims
1. A focal plane array circuit, characterized in that, include: At least one pixel unit group, the pixel unit group including at least two pixel units, the pixel unit including: a sensing pulse output circuit and a counter, the counter being connected to the output terminal of the sensing pulse output circuit, the sensing pulse output circuit being configured to output a corresponding number of pulse signals according to the sensed light signal during the sensing phase, and the counter being configured to count the pulse signals output by the sensing pulse output circuit; Each pixel unit in the pixel unit group, except for the first pixel unit, is respectively configured with a corresponding first switch circuit and a second switch circuit. The first terminal of the first switching circuit is connected to the sensing pulse output circuit in the corresponding pixel unit, and the second terminal of the first switching circuit is connected to the counter in the corresponding pixel unit. The first terminal of the second switching circuit is connected to the counter in the corresponding pixel unit, and the second terminal of the second switching circuit is connected to the counter in the previous pixel unit of the corresponding pixel unit. When the second switching circuit is in the on state, the two counters connected to the second switching circuit are cascaded.
2. The focal plane array circuit according to claim 1, characterized in that, The counter is an N-bit counter, which includes N cascaded flip-flops. The clock signal input terminal of any of the N-1 flip-flops other than the first stage flip-flop is connected to the cascade carry output terminal of the flip-flop of the previous stage. The second terminal of the first switching circuit is connected to the clock signal input terminal of the first stage flip-flop in the counter corresponding to the pixel unit; The first terminal of the second switching circuit is connected to the clock signal input terminal of the first stage flip-flop in the counter within the corresponding pixel unit, and the second terminal of the second switching circuit is connected to the cascade carry output terminal of the last stage flip-flop in the counter within the preceding pixel unit.
3. The focal plane array circuit according to claim 1, characterized in that, The first switching circuit includes: a first transistor, the control electrode of the first transistor is connected to a first control signal terminal, the first electrode of the first transistor is connected to the sensing pulse output circuit in the corresponding pixel unit, and the second electrode of the first transistor is connected to the counter in the corresponding pixel unit; and / or; The second switching circuit includes: a second transistor, the control electrode of the second transistor being connected to a second control signal terminal, the first electrode of the second transistor being connected to the counter in the corresponding pixel unit, and the second electrode of the second transistor being connected to the counter in the previous pixel unit corresponding to the pixel unit.
4. The focal plane array circuit according to claim 1, characterized in that, The counter connected to the first terminal of the second switching circuit and the counter connected to the second terminal of the second switching circuit are two counters within adjacent pixel units.
5. The focal plane array circuit according to claim 1, characterized in that, The pixel unit group includes multiple pixel units arranged in an array M×M, where M≥2 and is an integer.
6. The focal plane array circuit according to claim 1, characterized in that, The pixel unit further includes: A memory, connected to the counter, is configured to store the counting results of the counter.
7. The focal plane array circuit according to any one of claims 1 to 6, characterized in that, The sensing pulse output circuit includes: a photodiode, an input transistor, an integrating capacitor, an integrating reset transistor, a charge compensation transistor, a comparator, and a logic control generation circuit; The first end of the photodiode is connected to the first voltage supply terminal, and the second end of the photodiode is connected to the first terminal of the input transistor; The control terminal of the input transistor is connected to the input control signal terminal, and the second terminal of the input transistor is connected to the first terminal of the integrating capacitor. The control terminal of the integral reset transistor is connected to the integral reset control signal terminal, the first terminal of the integral reset transistor is connected to the reset voltage supply terminal, and the second terminal of the integral reset transistor is connected to the first terminal of the integral capacitor. The control electrode of the charge compensation transistor is connected to the logic control generation circuit, the first electrode of the charge compensation transistor is connected to the reset voltage supply terminal, and the second electrode of the charge compensation transistor is connected to the first terminal of the integrating capacitor. The first terminal of the integrating capacitor is connected to the first phase input terminal of the comparator, and the second terminal of the integrating capacitor is connected to the second voltage supply terminal. The second phase input terminal of the comparator is connected to the reference voltage supply terminal, the output terminal of the comparator is connected to the logic control generation circuit, and the output terminal of the comparator serves as the output terminal of the sensing pulse output circuit. The logic control generation circuit is configured to provide a corresponding effective level control signal to the charge compensation transistor when the signal output by the output terminal of the comparator changes from a first preset level to a second preset level, so as to control the charge compensation transistor to turn on.
8. A photodetector, characterized in that, include: The focal plane array circuit as described in any one of claims 1 to 7.
9. A data readout method for a focal plane array circuit, characterized in that, The focal plane array circuit is any one of the focal plane array circuits described in claims 1 to 7, and the data reading method includes: During the sensing phase, when in pixel merging mode, the first switching circuit is in an open state and the second switching circuit is in an open state. The sensing pulse output circuit in the first pixel unit in the pixel unit group outputs a corresponding number of pulse signals according to the sensed light signal. The counters in all the pixel units in the pixel unit group are cascaded and perform cascade counting on the pulse signals output by the sensing pulse output circuit in the first pixel unit.
10. The data reading method according to claim 9, characterized in that, Also includes: During the sensing phase, when in full-frame mode, the first switching circuit is in the on state and the second switching circuit is in the off state. The sensing pulse output circuit in each pixel unit of the pixel unit group outputs a corresponding number of pulse signals according to the sensed light signal. The counter in each pixel unit counts the pulse signals output by the sensing pulse output circuit in the same pixel unit.