Diode ferroelectric tunnel junction memory and method of fabrication
By inserting a barrier control layer into the ferroelectric tunnel junction memory, adjusting the barrier height and forming a PN junction, the problems of small storage window and circuit crosstalk are solved, thereby improving the performance and computing power of the memory.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- XIDIAN UNIV
- Filing Date
- 2023-05-23
- Publication Date
- 2026-07-14
AI Technical Summary
Existing ferroelectric tunnel junction memories have small storage windows, which limits the computing power of neuromorphic chips, affects their ability to perform parallel computing and storage, and also causes circuit crosstalk problems.
In the traditional ferroelectric tunnel junction memory structure, a barrier control layer is inserted. Using intrinsic semiconductor materials or doped semiconductor materials with the opposite doping type to the substrate, the barrier height is adjusted to form a PN junction, thereby increasing the storage window and reducing circuit crosstalk.
It achieves a larger storage window and switching current ratio, reduces off-state current density, obtains significant rectification characteristics, reduces circuit crosstalk, and improves the performance of ferroelectric tunnel junction memory.
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Figure CN116963504B_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the field of microelectronic device technology, and specifically relates to a diode-type ferroelectric tunnel junction memory and its fabrication method, which can be used to manufacture memory. Background Technology
[0002] In recent years, neuromorphic computing has been proposed to address the severe limitations of traditional computing systems based on the von Neumann architecture in terms of energy consumption, deep learning capabilities, and scalability of large networks. Neuromorphic computing aims to realize electronic systems that simulate the computational efficiency and fault tolerance of the biological brain in a compact space. Compared to traditional computing systems, the human brain can perform more intelligent functions while consuming less energy and occupying less space. To bridge this gap, research on constructing electronic systems that simulate neuronal organization and nervous system functions is ongoing. Currently, devices with programmable conductance, such as phase-change memories and resistance-changing memories, while explored as potential synaptic devices, suffer from problems such as insufficient response speed, which restricts the further development of non-von Neumann neuromorphic computing.
[0003] Ferroelectric synaptic devices possess unique advantages, including high symmetry in enhancement / inhibition operations and fast response. Among them, ferroelectric tunneling junction memory (FTM), as the most promising in-memory computing structure in the field of high-efficiency neuromorphic computing, has a series of advantages such as simple structure, high reliability, fewer voltage control ports, and non-destructive information retrieval. Its structure is as follows: Figure 1 As shown, the key technological bottleneck currently hindering the development of non-von Neumann ferroelectric tunneling junction (FJT) neuromorphic chip technology is the small memory window of FJTs. This significantly weakens the computing power of neuromorphic chips, affecting both parallel processing and storage capabilities. Therefore, there is an urgent need to develop novel FJTs with large memory windows. Furthermore, good rectification characteristics can effectively reduce circuit crosstalk, which is of great significance for high-energy-efficiency neural network computing applications. Summary of the Invention
[0004] In order to overcome the shortcomings of the prior art, the present invention aims to provide a diode-type ferroelectric tunneling junction memory and its fabrication method, so as to solve the problem that the difference in shielding length between the electrodes on both sides of the existing ferroelectric tunneling junction is small, which makes it impossible to generate a high barrier change under the limited ferroelectric polarization characteristics, and ultimately limits the storage window of the ferroelectric tunneling junction memory.
[0005] To achieve the above objectives, the technical solution adopted by the present invention is as follows:
[0006] A diode-type ferroelectric tunnel junction memory includes a substrate, a barrier control layer, an insulating dielectric layer, a ferroelectric material layer, and a top electrode layer arranged sequentially. The barrier control layer uses an intrinsic semiconductor material or a doped semiconductor material with a doping type opposite to that of the substrate to achieve adjustment of the barrier height.
[0007] Traditional FTJs utilize the difference in shielding length between the upper and lower electrodes under different ferroelectric polarization directions to form different average barrier heights and tunneling widths, thereby achieving on / off states and storing information. The diode-type ferroelectric tunneling junction memory (i-FTJ) of this invention, due to the insertion of an additional barrier control layer, exhibits a lower electron concentration in the barrier control layer during the off-state, enhancing the control effect of ferroelectric polarization on the semiconductor side, further increasing the tunneling width on the semiconductor side, and reducing the off-state current density. In the on-state, the i-FTJ can still attract sufficient electrons, and the on-state current density remains almost unchanged. The i-FTJ thus achieves a significantly increased barrier width ratio, resulting in a larger switching current ratio. Furthermore, the inserted barrier control layer forms a PN junction with the heavily doped semiconductor electrode, enabling the device to acquire significant rectification characteristics.
[0008] In one embodiment, the substrate uses a doping concentration in the range of 1×10⁻⁶. 17 -1×10 19 cm -3 Heavily doped semiconductor materials.
[0009] In one embodiment, the substrate and the barrier control layer are made of the same material, namely any one of Si, Ge, SiC, SiGe, GaN, GaAs, SOI, GOI, sapphire, and diamond.
[0010] In one embodiment, the insulating dielectric layer is any one of SiO2, Si3N4, Al2O3, and La2O3; the ferroelectric material layer is Hf x Zr 1-x O2, Al2O3, HfO2, ZrO2, BaTiO3, Cd2Nb2O7, BiFeO3, Sr x Ba 1-x The top electrode layer is any one of O3, ZnSnO3 and PVDF; the top electrode layer is any one of W, Ti, Cu, Al, Pt, Ir, Ru, W2N, TiN, TaN, IrO2, RuO2, WC, TiC, WSi2 and Si3Ta5.
[0011] In one embodiment, the thickness of the barrier modulation layer is 1-20 nm, the thickness of the insulating dielectric layer is 0.1-2 nm, and the thickness of the ferroelectric material layer is 3-5 nm.
[0012] In one embodiment, as the thickness of the barrier control layer increases, the tunneling width increases accordingly, and the off-state current density decreases.
[0013] The present invention also provides a method for fabricating the diode-type ferroelectric tunnel junction memory, comprising the following steps:
[0014] Step 1), prepare the substrate;
[0015] Step 2): Using an intrinsic semiconductor material or a doped semiconductor material with the opposite doping type to the substrate, a barrier control layer is prepared on one side of the substrate using a low-pressure chemical vapor deposition process.
[0016] Step 3) Prepare an insulating dielectric layer on the side of the barrier modulation layer away from the substrate;
[0017] Step 4): Prepare a ferroelectric material layer on the side of the insulating dielectric layer away from the barrier modulation layer;
[0018] Step 5) Prepare a top electrode layer on the side of the ferroelectric material layer away from the insulating dielectric layer.
[0019] In one embodiment, step 1) involves using an ion implantation process to form a heavily doped semiconductor layer on the substrate;
[0020] In step 3), an insulating dielectric layer is grown on the surface of the barrier control layer using a dry oxygen oxidation process.
[0021] In step 5), a top electrode layer is grown on the side of the ferroelectric material layer away from the insulating dielectric layer using a magnetron sputtering process.
[0022] In one embodiment, step 4) involves depositing a ferroelectric material layer on the side of the insulating dielectric layer away from the barrier control layer using atomic layer deposition technology. Specifically, ferroelectric elements are used as the precursor source, H2O or O3 is used as the precursor oxygen source, and N2 is used as the purge gas. The ferroelectric material layer is formed by reaction deposition at a temperature of 250-400°C.
[0023] In one embodiment, the precursor source is tetrakis(dimethylamino)zirconium, HfCl4, TEMAHf, or TEMAZr.
[0024] Compared with the prior art, the beneficial effects of the present invention are:
[0025] This invention inserts a barrier control layer into the traditional ferroelectric tunneling junction memory (FTM) structure. By utilizing this barrier control layer to increase the shielding length on the semiconductor side in the off-state, a diode-type FTM is obtained. Compared to existing technologies, the on-state current density of the diode-type FTM remains relatively unchanged. However, due to the insertion of the barrier control layer, the shielding length on the semiconductor side in the off-state increases, further increasing the electron tunneling width and significantly reducing the off-state current density. This results in a device with a larger storage window, further improving the performance of the FTM. Simultaneously, thanks to the PN junction formed by the inserted barrier control layer and the heavily doped semiconductor electrode, the device exhibits significant rectification characteristics, effectively preventing circuit crosstalk. Attached Figure Description
[0026] Figure 1 This is a schematic diagram of the existing device structure.
[0027] Figure 2 The figures show the current-voltage curves for traditional ferroelectric tunneling junction memory (FTJ) and diode-type ferroelectric tunneling junction memory (i-FTJ).
[0028] Figure 3 This is a schematic diagram of the device structure of the present invention.
[0029] Figure 4 This is a schematic diagram illustrating the implementation process of the present invention. Detailed Implementation
[0030] To make the objectives and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are for illustrative purposes only and are not intended to limit the invention.
[0031] refer to Figure 2 In traditional ferroelectric tunnel junction memory (FTJ), the difference in shielding length between the two electrodes is small. Under the limited ferroelectric polarization characteristics, it is difficult to generate a high potential barrier change, which limits the memory storage window.
[0032] To address this issue, the difference in shielding length between the electrodes on both sides of the memory is increased, thereby achieving an increased tunneling barrier width ratio and memory window in the switching state, and further improving the memory window of the ferroelectric tunneling junction memory. (Refer to...) Figure 3 The present invention provides a diode-type ferroelectric tunnel junction memory, comprising a substrate 1, a barrier control layer 2, an insulating dielectric layer 3, a ferroelectric material layer 4 and a top electrode layer 5 arranged sequentially. The barrier control layer 2 is made of intrinsic semiconductor material or doped semiconductor material with the opposite doping type to the substrate, so as to achieve adjustment of the barrier height.
[0033] This invention increases the difference in shielding length between the electrodes on both sides of the memory by inserting a barrier modulation layer on the basis of a traditional ferroelectric tunnel junction, thereby obtaining an increased tunnel barrier width ratio and memory window in the switching state, which can be used in non-Von der Leyen neuromorphic chip technology.
[0034] More specifically, see reference Figure 2 Compared to traditional FTJs, the diode-type ferroelectric tunneling junction memory (i-FTJ) of this invention exhibits enhanced ferroelectric polarization control over the semiconductor side (i.e., the barrier control layer 2 and substrate 1) due to the lower electron concentration of the inserted barrier control layer 2. In the on-state, sufficient electrons remain on the semiconductor side to respond to polarization, resulting in an almost constant on-state current density. In the off-state, the shielding length on the semiconductor side significantly increases due to the insertion of the barrier control layer 2. Compared to FTJs, i-FTJs can achieve a greater difference in shielding length. This increased shielding length difference, i.e., a wider tunneling barrier in the off-state of i-FTJ, leads to a significantly reduced off-state current density. Since the tunneling barrier remains almost constant in the on-state, the tunneling barrier width ratio increases in the on-off state of i-FTJs, resulting in a larger storage window.
[0035] In an embodiment of the present invention:
[0036] Substrate 1 uses a doping concentration range of 1×10 17 -1×10 19 cm -3 The substrate 1 is a heavily doped semiconductor material. The substrate material can be any one of Si, Ge, SiC, SiGe, GaN, GaAs, SOI, GOI, sapphire, and diamond.
[0037] The barrier control layer 2 is located on the substrate 1. Its material is the same as that of the substrate 1, and its thickness is 1-20nm. When the thickness of the barrier control layer 2 increases, the tunneling width increases accordingly, and the off-state current density decreases.
[0038] The insulating dielectric layer 3 is located on the barrier control layer 2 and is made of materials such as SiO2, Si3N4, Al2O3 and La2O3, with a thickness ranging from 0.1 to 2 nm.
[0039] The ferroelectric material layer 4 is located on the insulating dielectric layer 3 and is made of a ferroelectric material with polarization properties to provide polarization charge. This ferroelectric material includes Hf... x Zr 1-x O2, Al2O3, HfO2, ZrO2, BaTiO3, Cd2Nb2O7, BiFeO3, Sr x Ba 1-x Materials include O3, ZnSnO3, and PVDF, with a thickness range of 3-5 nm.
[0040] The top electrode layer 5 is located on the ferroelectric material layer 4 and can be any one of W, Ti, Cu, Al, Pt, Ir, Ru, W2N, TiN, TaN, IrO2, RuO2, WC, TiC, WSi2 and Si3Ta5.
[0041] Under the action of an external electric field, the asymmetric electric dipoles contained in the ferroelectric material layer 4 can undergo directional flipping of the cell, and can maintain the directional flipping characteristic after the electric field is removed. This characteristic can generate a certain amount of polarization charge on the material surface, thereby inducing corresponding electrons and holes in the intrinsic semiconductor material. By applying pulse excitation of different polarities to the top electrode layer 5, different polarities of doping of the barrier control layer 2 can be achieved.
[0042] Reference Figure 4 The present invention fabricates an intrinsic semiconductor-insulated ferroelectric tunnel junction and provides the following three embodiments.
[0043] Example 1: Fabrication of a ferroelectric tunnel junction based on intrinsic semiconductor insertion of ZrO2 material.
[0044] Step 1: Select a substrate and deposit the bottom silicon layer.
[0045] An undoped silicon wafer was selected as substrate 1;
[0046] Using a low-pressure chemical vapor deposition (LPCVD) process, a substrate is placed in a low-pressure reaction chamber at 600°C to deposit polycrystalline silicon on the surface of the silicon substrate, forming a 50nm thick bottom silicon layer. Figure 4 (a)
[0047] Step 2: Prepare the bottom heavy doping layer.
[0048] Ion implantation was used to implant the substrate at an energy of 20 keV and a dose of 10. 19 cm -3 The addition of phosphorus (P) element resulted in a substrate with a doping concentration of approximately 1e19 cm⁻¹. -3 The heavily doped semiconductor layer 1, such as Figure 4 (b)
[0049] Step 3: Deposit the intrinsic semiconductor layer.
[0050] Using low-pressure chemical vapor deposition (LPCVD), a sample with an N-type heavily doped semiconductor layer 1 was placed in a low-pressure reaction chamber at 600°C. Polycrystalline silicon was deposited on the surface of the heavily doped semiconductor layer 1 to form a 10nm thick intrinsic semiconductor. Figure 4 (c)
[0051] Step 4: Deposit the insulating dielectric layer.
[0052] The sample with the intrinsic semiconductor layer 2 deposited is placed in the reaction chamber. Using chemical vapor deposition, the reaction chamber is first evacuated for 5-15 minutes, then Si3H4 and N2O are simultaneously introduced as silicon and oxygen sources, respectively. The reaction temperature is 75°C. A 0.4 nm thick SiO2 layer is inductively coupled to grow on the surface of the intrinsic semiconductor layer as a control insulating dielectric layer 3. Figure 4 (d)
[0053] Step 5: Deposit the ferroelectric layer.
[0054] The sample with the deposited insulating dielectric layer 3 was placed in the reaction chamber. Using atomic layer deposition (ALD), tetrakis(dimethylamino)zirconium was deposited as the zirconium precursor, H2O or O3 as the oxygen precursor, N2 as the purge gas, and 250°C as the reaction temperature, a 5 nm thick ZrO2 ferroelectric layer 4 was formed on the surface of the bottom channel layer 2. Figure 4 Middle (e).
[0055] Step 6: Deposit the top electrode layer.
[0056] The top electrode layer TiN5 was deposited using atomic layer deposition (ALD) and physical vapor deposition (PVD). Device fabrication was then completed, as shown below. Figure 4 (f).
[0057] Example 2: Fabrication of a ferroelectric tunnel junction based on intrinsic semiconductor insertion of HfO2 material.
[0058] Step 1: Select a substrate and deposit the bottom silicon layer.
[0059] An undoped silicon wafer was selected as substrate 1;
[0060] Using a low-pressure chemical vapor deposition (LPCVD) process, a substrate is placed in a low-pressure reaction chamber at 600°C to deposit polycrystalline silicon on the surface of the silicon substrate, forming a 50nm thick bottom silicon layer. Figure 4 (a)
[0061] Step 2: Prepare the bottom heavy doping layer.
[0062] Ion implantation was used to implant the substrate at an energy of 20 keV and a dose of 10. 19 cm -3 The addition of phosphorus (P) element resulted in a substrate with a doping concentration of approximately 1e19 cm⁻¹. -3 The heavily doped semiconductor layer 1, such as Figure 4 (b)
[0063] Step 3: Deposit the intrinsic semiconductor layer.
[0064] Using low-pressure chemical vapor deposition (LPCVD), a sample with an N-type heavily doped semiconductor layer 1 was placed in a low-pressure reaction chamber at 600°C. Polycrystalline silicon was deposited on the surface of the heavily doped semiconductor layer 1 to form a 10 nm thick intrinsic semiconductor. Ion implantation was then performed in the intrinsic semiconductor at an energy of 20 keV and a dose of 5 × 10⁻⁶ ions. 18 cm -3 The addition of element B resulted in a substrate with a doping concentration of approximately 5 × 10⁻⁶. 18 cm -3 The reverse-doped semiconductor layer 2, such as Figure 4 (c)
[0065] Step 4: Deposit the insulating dielectric layer.
[0066] The sample with the intrinsic semiconductor layer 2 deposited is placed in the reaction chamber. Using chemical vapor deposition, the reaction chamber is first evacuated for 5-15 minutes, then Si3H4 and N2O are simultaneously introduced as silicon and oxygen sources, respectively. The reaction temperature is 75°C. A 0.4 nm thick SiO2 layer is inductively coupled to grow on the surface of the intrinsic semiconductor layer as an insulating dielectric layer 3. Figure 4 (d)
[0067] Step 5: Deposit the ferroelectric layer.
[0068] The sample with the deposited insulating dielectric layer 3 was placed in the reaction chamber. Using atomic layer deposition (ALD) technology, with HfCl4 as the hafnium precursor source, H2O or O3 as the oxygen precursor source, N2 as the purge gas, and 260°C as the reaction temperature, a 6 nm thick HfO2 ferroelectric layer 4 was deposited on the surface of the insulating dielectric layer 3. Figure 4 Middle (e).
[0069] Step 6: Deposit the top electrode layer.
[0070] Device fabrication is completed by depositing a TaN thin film on the ferroelectric layer as the top electrode layer, such as... Figure 4 (f).
[0071] Example 3: Fabrication of a ferroelectric tunnel junction based on intrinsic semiconductor insertion of HZO material.
[0072] Step A: Select a substrate and deposit the bottom silicon layer.
[0073] An undoped silicon wafer was selected as substrate 1;
[0074] Using a low-pressure chemical vapor deposition (LPCVD) process, a substrate is placed in a low-pressure reaction chamber at 600°C to deposit polycrystalline silicon on the surface of the silicon substrate, forming a 50nm thick bottom silicon layer. Figure 4 (a)
[0075] Step B: Prepare the bottom heavy doping layer.
[0076] Ion implantation was used to implant the substrate at an energy of 20 keV and a dose of 10. 19 cm -3 The addition of element B resulted in a substrate with a doping concentration of approximately 1 × 10⁻⁶. 19 cm -3 The heavily doped semiconductor layer 1, such as Figure 4 (b)
[0077] Step C: Deposit the intrinsic semiconductor layer.
[0078] Using low-pressure chemical vapor deposition (LPCVD), a sample with a heavily p-doped semiconductor layer 1 was placed in a low-pressure reaction chamber at 600°C. Polycrystalline silicon was deposited on the surface of the heavily doped semiconductor layer 1 to form a 10 nm thick intrinsic semiconductor. Figure 4 (c)
[0079] Step D: Deposit the insulating dielectric layer.
[0080] The sample with the intrinsic semiconductor layer 2 deposited is placed in the reaction chamber. Using chemical vapor deposition, the reaction chamber is first evacuated for 5-15 minutes, then Si3H4 and N2O are simultaneously introduced as silicon and oxygen sources, respectively. The reaction temperature is 75°C. A 0.4 nm thick SiO2 layer is inductively coupled to grow on the surface of the intrinsic semiconductor layer as a control insulating dielectric layer 3. Figure 4 (d)
[0081] Step E: Deposit a ferroelectric layer.
[0082] The sample with the deposited insulating dielectric layer 3 was placed in the reaction chamber. Using atomic layer deposition (ALD), with HfCl4 as the hafnium source precursor, tetrakis(dimethylamino)zirconium as the zirconium source precursor, H2O or O3 as the oxygen source precursor, N2 as the purge gas, and a reaction temperature of 260°C, a 7 nm thick HZO ferroelectric layer 4 was deposited on the surface of the insulating dielectric layer 3. The Hf to Zr composition ratio was 1:1. Figure 4 Middle (e).
[0083] Step F: Deposit the top electrode W.
[0084] Using atomic layer deposition (ALD) and physical vapor deposition (PVD), the top electrode 5 is deposited on the surface of the ferroelectric layer 4 to complete the device fabrication, such as... Figure 4 (f).
Claims
1. A diode-type ferroelectric tunnel junction memory, comprising a substrate (1), a barrier modulation layer (2), an insulating dielectric layer (3), a ferroelectric material layer (4), and a top electrode layer (5) arranged sequentially, characterized in that, The barrier control layer (2) uses an intrinsic semiconductor material or a doped semiconductor material with the opposite doping type to the substrate to adjust the barrier height. The substrate (1) uses a doping concentration range of 1×10⁻⁶. 17 -1×10 19 cm -3 The electron concentration of the heavily doped semiconductor material in the barrier control layer (2) is lower than that of the substrate (1).
2. The diode-type ferroelectric tunnel junction memory according to claim 1, characterized in that, The substrate (1) and the barrier control layer (2) are made of the same material, namely any one of Si, Ge, SiC, SiGe, GaN, GaAs, SOI, GOI, sapphire and diamond.
3. The diode-type ferroelectric tunnel junction memory according to claim 1, characterized in that, The insulating dielectric layer (3) is made of any one of SiO2, Si3N4, Al2O3 and La2O3; the ferroelectric material layer (4) is made of Hf x Zr 1-x O2, Al2O3, HfO2, ZrO2, BaTiO3, Cd2Nb2O7, BiFeO3, Sr x Ba 1-x The top electrode layer (5) is any one of O3, ZnSnO3 and PVDF; the top electrode layer (5) is any one of W, Ti, Cu, Al, Pt, Ir, Ru, W2N, TiN, TaN, IrO2, RuO2, WC, TiC, WSi2 and Si3Ta5.
4. The diode-type ferroelectric tunnel junction memory according to claim 1, 2, or 3, characterized in that, The thickness of the barrier control layer (2) is 1-20 nm, the thickness of the insulating dielectric layer (3) is 0.1-2 nm, and the thickness of the ferroelectric material layer (4) is 3-5 nm.
5. The diode-type ferroelectric tunnel junction memory according to claim 1, characterized in that, When the thickness of the barrier control layer (2) increases, the tunneling width increases accordingly, and the off-state current density decreases.
6. The method for fabricating the diode-type ferroelectric tunnel junction memory according to claim 1, characterized in that, Includes the following steps: Step 1), prepare the substrate (1); Step 2), using intrinsic semiconductor material or doped semiconductor material with the opposite doping type to the substrate, a barrier control layer (2) is prepared on one side of the substrate (1) by low-pressure chemical vapor deposition. Step 3), an insulating dielectric layer (3) is prepared on the side of the barrier control layer (2) away from the substrate (1). Step 4), a ferroelectric material layer (4) is prepared on the side of the insulating dielectric layer (3) away from the barrier control layer (2). Step 5), a top electrode layer (5) is prepared on the side of the ferroelectric material layer (4) away from the insulating dielectric layer (3).
7. The method for fabricating a diode-type ferroelectric tunnel junction memory according to claim 6, characterized in that, In step 1), an ion implantation process is used to form a heavily doped semiconductor layer on the substrate (1); In step 3), an insulating dielectric layer (3) is grown on the surface of the barrier control layer (2) using a dry oxygen oxidation process. In step 5), a top electrode layer (5) is grown on the side of the ferroelectric material layer (4) away from the insulating dielectric layer (3) using a magnetron sputtering process.
8. The method for fabricating a diode-type ferroelectric tunnel junction memory according to claim 6 or 7, characterized in that, In step 4), an atomic layer deposition process is used to deposit a ferroelectric material layer (4) on the side of the insulating dielectric layer (3) away from the barrier control layer (2). That is, ferroelectric elements are used as precursor sources, H2O or O3 is used as precursor oxygen sources, and N2 is used as purge gas. The ferroelectric material layer (4) is formed by reaction deposition at a temperature of 250-400℃.
9. The method for fabricating a diode-type ferroelectric tunnel junction memory according to claim 8, characterized in that, The precursor source is tetrakis(dimethylamino)zirconium or HfCl4 or TEMAHf or TEMAZr.