A semiconductor device, a manufacturing method thereof, a chip, and an electronic device

Abstract

The embodiment of the application provides a kind of semiconductor device and its preparation method, chip, electronic equipment, applied in semiconductor technical field, the semiconductor device includes substrate, source and drain located inside substrate and gate located on substrate, wherein, source and drain are spaced apart;Gate is provided with side wall on both sides, each side wall is in contact with substrate respectively;Gate includes polycrystalline silicon layer and gate oxide dielectric layer of stacked arrangement, gate oxide dielectric layer is located between polycrystalline silicon layer and substrate, and the projection of polycrystalline silicon layer on substrate is located between source and drain;Polycrystalline silicon layer includes first doped region and second doped region, first doped region is arranged in polycrystalline silicon layer side close to drain, second doped region is arranged in the side of first doped region away from drain, and the doping concentration of first doped region is lower than the doping concentration of second doped region. Implement the embodiment of the application, can improve the reliability of MOSFET while maintaining its better conduction performance.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to a semiconductor device and its fabrication method, chip, and electronic device. Background Technology

[0002] With the development of technology, the size of metal-oxide-semiconductor field-effect transistors (MOSFETs) currently used in high-voltage devices is being miniaturized. Due to the high operating voltage, the transverse electric field strength in the channel is continuously enhanced, resulting in faster transport velocity of charge carriers in the on state. However, this also greatly increases the probability of collisional ionization, generating a large number of electron-hole pairs. Therefore, as the size decreases, the hot carrier injection (HCI) phenomenon in high-voltage devices increases significantly. That is, hot carriers are injected into the oxide layer under the vertical electric field applied to the gate, causing the threshold voltage of the device to rise and the saturation current to fall, affecting the reliability of the device.

[0003] Currently, the HCI phenomenon in devices can be improved by optimizing the lightly doped drain (LDD) process and channel doping, but these methods all have certain limitations. For example, the optimized LDD process is complex and increases the overlap region, enhancing gate-induced drain leakage (GIDL) and affecting device performance; channel doping leads to a significant decrease in channel carrier mobility, which is detrimental to device conductivity.

[0004] Therefore, how to provide a MOSFET with good performance and high reliability is a technical problem that urgently needs to be solved. Summary of the Invention

[0005] This application provides a semiconductor device, its fabrication method, chip, and electronic device, which can improve the reliability of MOSFETs while maintaining their good conduction performance.

[0006] In a first aspect, embodiments of this application provide a semiconductor device, including a substrate, a source and a drain located inside the substrate, and a gate located on the substrate, wherein the source and the drain are spaced apart, and the gate is further provided with sidewalls on both sides along a first direction, each sidewall contacting the substrate, the first direction being parallel to the substrate direction; the gate includes a polysilicon layer and a gate oxide dielectric layer stacked thereon, the gate oxide dielectric layer being located between the polysilicon layer and the substrate, and the projection of the polysilicon layer on the substrate being located between the source and the drain; the polysilicon layer includes a first doped region and a second doped region, the first doped region being located on the side of the polysilicon layer closer to the drain, the second doped region being located on the side of the first doped region away from the drain, and the doping concentration of the first doped region being lower than the doping concentration of the second doped region.

[0007] In existing technologies, hot carrier injection can negatively impact device performance and reliability. To mitigate this issue and improve device reliability without affecting performance, this application provides a semiconductor device, which can be a MOSFET and applied in various scenarios such as logic devices, input / output devices, and memory. The polysilicon layer of the gate in this device includes multiple doped regions with varying doping concentrations, such as a first doped region and a second doped region. The doping concentration of the first doped region near the drain is significantly lower than that of the second doped region; that is, the doping concentration on the drain side of the polysilicon layer of the gate is lower than that on the side further from the drain. This results in a thicker local depletion layer near the drain, increasing the local resistance near the drain. This helps reduce the peak electric field intensity near the drain, thereby mitigating the HCI effect. Compared to the optimized LDD process, this method only requires controlling the doping concentration in different regions during polysilicon predoping, without the need for complex process flows. Furthermore, the embodiments of this application do not lead to GIDL enhancement, thus affecting device performance. Moreover, the embodiments of this application do not dop the channel, so they do not significantly affect the channel carrier mobility, and the device can still maintain good conductivity.

[0008] In one possible implementation, the length of the first doped region is less than the length of the second doped region in a first direction, the first direction being parallel to the substrate direction.

[0009] In this embodiment, the length of the low-doped region (i.e., the first doped region) in the polysilicon layer of the gate is shorter than the length of the high-doped region (i.e., the second doped region). For example, the length of the high-doped region can be more than twice the length of the low-doped region. In this case, the overall doping concentration in the polysilicon layer of the gate remains high, and the overall device performance is not affected by reducing the doping concentration near the drain. Having a low doping concentration only in a small region near the drain helps increase the local resistance near the drain, reduces the peak electric field intensity near the drain, and thus improves the HCI effect.

[0010] In one possible implementation, the first doped region and the second doped region have the same doping type.

[0011] In the embodiments of this application, to ensure device performance, different doped regions in the polysilicon layer differ only in doping concentration, while their corresponding doping types are the same. For example, the polysilicon layer can be set to N-type doping or P-type doping based on the doping types of the source and drain.

[0012] In one possible implementation, the doping concentration of the second doped region is greater than or equal to twice the doping concentration of the first doped region.

[0013] In this embodiment, to ensure a significant reduction in the doping concentration of the polysilicon layer near the drain, thereby significantly increasing the local resistance near the drain and reducing the peak electric field intensity near the drain, thus improving the HCI effect, the doping concentration of the second doped region can be at least greater than or equal to twice the doping concentration of the first doped region. For example, the doping concentration of the first doped region is 1 × 10⁻⁶. 19 cm -3 In this case, the doping concentration of the second doped region needs to be greater than or equal to 2 × 10⁻⁶. 19 cm -3 .

[0014] In one possible implementation, the second doped region includes a plurality of third doped regions, wherein in any two adjacent third doped regions, the doping concentration of the third doped region closer to the drain is lower than the doping concentration of the third doped region farther from the drain.

[0015] In this embodiment, the polysilicon layer can further have multiple third doped regions within the second doped region. The closer these third doped regions are to the drain, the lower their corresponding doping concentration. This stepped arrangement, even with the continuously increasing lateral electric field in the channel, does not significantly affect the channel carrier mobility, thus improving hot carrier injection and enhancing device reliability.

[0016] In one possible implementation, the doping concentration of any doped region in the polysilicon layer is greater than or equal to 1 × 10⁻⁶. 18 cm -3 .

[0017] In this embodiment, to ensure that the polysilicon layer as a whole is within a high doping concentration range and can maintain good performance, the doping concentration of any doped region in the polysilicon layer needs to be greater than or equal to 1×10⁻⁶. 18 cm -3 To achieve heavy doping. For example, the doping concentration of the first doped region can be up to 1 × 10⁻⁶. 18 cm -3 The doping concentration of the second doped region can be 1×10⁻⁶. 20 cm -3 .

[0018] In one possible implementation, each of the sidewalls is made of an insulating material.

[0019] In this embodiment, sidewalls are provided on both sides of the gate. These sidewalls of the insulating material can prevent charge carriers from entering the channel during the fabrication of the source or drain, thereby improving the structural strength and stability of the semiconductor device, reducing leakage current, and ultimately enhancing the performance of the semiconductor device. The insulating material can be silicon dioxide (SiO2), silicon nitride (SiNx), silicon oxynitride (SiON), etc.

[0020] Secondly, embodiments of this application provide a method for fabricating a semiconductor device, the method comprising:

[0021] A substrate is provided; a gate electrode and sidewalls located on both sides of the gate electrode along a first direction are formed on the surface of the substrate, and a source electrode and a drain electrode are formed by doping inside the substrate; wherein the source electrode and the drain electrode are spaced apart, each sidewall is in contact with the substrate, and the first direction is parallel to the substrate direction; the gate electrode includes a polysilicon layer and a gate oxide dielectric layer stacked together, the gate oxide dielectric layer is located between the polysilicon layer and the substrate, and the projection of the polysilicon layer on the substrate is located between the source electrode and the drain electrode; the polysilicon layer includes a first doped region and a second doped region, the first doped region is located on the side of the polysilicon layer closer to the drain electrode, the second doped region is located on the side of the first doped region away from the drain electrode, and the doping concentration of the first doped region is lower than the doping concentration of the second doped region.

[0022] In one possible implementation, the step of forming a gate and sidewalls located on both sides of the gate along a first direction on the surface of the substrate, and forming a source and drain by doping inside the substrate, includes: forming a gate oxide dielectric layer on the surface of the substrate; depositing polysilicon on the surface of the gate oxide dielectric layer to form a first semiconductor layer, and doping the first semiconductor layer to form a second semiconductor layer; etching both sides of the second semiconductor layer to form a first opening and a second opening, the bottom of the first opening and the second opening exposing the gate oxide dielectric layer; forming the sidewalls at the first opening and the second opening respectively, and then doping the substrate. A source electrode is formed in a first region, and a drain electrode is formed in a second region of the substrate. The projection of the first region onto the substrate overlaps with the projection of the first opening, and the projection of the second region onto the substrate overlaps with the projection of the second opening. Photoresist is spin-coated onto the first opening, the surface of the second semiconductor layer, and the second opening to form a mask layer. The surface of the mask layer is etched to form a third opening, the bottom of which exposes the second semiconductor layer. The projection of the third opening onto the substrate overlaps with the projection of the second semiconductor layer near the source electrode. The second semiconductor layer is doped again at the third opening, and the remaining mask layer is removed to form the polysilicon layer.

[0023] In one possible implementation, the step of fabricating a gate electrode and sidewalls located on opposite sides of the gate electrode along a first direction on the surface of the substrate, and doping to form a source and drain electrode inside the substrate, includes: fabricating a gate oxide dielectric layer on the surface of the substrate; depositing polysilicon on the surface of the gate oxide dielectric layer to form a first semiconductor layer, and doping the first semiconductor layer to form a second semiconductor layer; spin-coating photoresist on the surface of the second semiconductor layer to form a mask layer; etching the surface of the mask layer to form a third opening, the bottom of the third opening exposing the second semiconductor layer, and the projection of the third opening on the substrate overlapping the projection of one side of the second semiconductor layer; and etching the second semiconductor layer at the third opening. The conductor layer is doped again and the remaining mask layer is removed to form a third semiconductor layer. The two sides of the third semiconductor layer are etched to form a first opening and a second opening. The gate oxide dielectric layer is exposed at the bottom of the first opening and the second opening. The doping concentration of the second opening near the first opening is less than the doping concentration of the first opening near the second opening. After forming the sidewalls at the first opening and the second opening, the substrate is doped. A source electrode is formed in a first region of the substrate, and a drain electrode is formed in a second region of the substrate. The projection of the first region and the first opening on the substrate overlaps, and the projection of the second region and the second opening on the substrate overlaps.

[0024] Thirdly, embodiments of this application provide a chip, characterized in that it includes a circuit and a semiconductor device as provided in the first aspect applied to the circuit.

[0025] Fourthly, embodiments of this application provide an electronic device, characterized in that it includes a circuit board and a chip as provided in the first aspect, wherein the circuit board is electrically connected to the chip.

[0026] It should be understood that the semiconductor device fabrication method provided in the second aspect of this application, the chip provided in the third aspect, and the electronic device provided in the fourth aspect are consistent with the technical solutions of the first aspect of this application. Their specific contents and beneficial effects can be referred to the semiconductor device provided in the first aspect above, and will not be repeated here. Attached Figure Description

[0027] To more clearly illustrate the technical solutions in the embodiments of this application or the background art, the accompanying drawings used in the embodiments of this application or the background art will be described below.

[0028] Figure 1 This is a schematic diagram of the structure of a MOSFET provided in an embodiment of this application.

[0029] Figure 2This is a schematic diagram of the structure of a semiconductor device provided in an embodiment of this application.

[0030] Figure 3 This is a schematic diagram of another semiconductor device provided in the embodiments of this application.

[0031] Figure 4 This is a schematic diagram of the structure of another semiconductor device provided in the embodiments of this application.

[0032] Figure 5 This is a schematic diagram of a process for fabricating a semiconductor device provided in an embodiment of this application.

[0033] Figure 6 This is a schematic diagram of another process for fabricating a semiconductor device provided in an embodiment of this application.

[0034] Figures 7-13 This is a set of cross-sectional schematic diagrams of the fabrication of semiconductor devices provided in the embodiments of this application.

[0035] Figure 14 This is a schematic diagram of another process for fabricating a semiconductor device provided in the embodiments of this application.

[0036] Figures 15-17 This is a set of cross-sectional schematic diagrams of the fabrication of semiconductor devices provided in the embodiments of this application.

[0037] Figure label:

[0038] 10 substrates;

[0039] 101 Source, 102 Drain, 103 Gate, 104 Sidewall;

[0040] 201 Polysilicon layer, 202 Gate oxide dielectric layer;

[0041] 2011 First doped region, 2012 Second doped region;

[0042] Third doping region 2013, third doping region 2023. Detailed Implementation

[0043] The embodiments of this application will now be described with reference to the accompanying drawings.

[0044] The terms "first" and "second," etc., in the specification, claims, and accompanying drawings of this application are used to distinguish different objects, not to describe a specific order. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or apparatus that includes a series of steps or units is not limited to the listed steps or units, but may optionally include steps or units not listed, or may optionally include other steps or units inherent to such processes, methods, products, or apparatus.

[0045] It should be understood that in this application, "at least one (item)" means one or more, and "more than" means two or more. "And / or" is used to describe the relationship between related objects, indicating that three relationships can exist. For example, "A and / or B" can represent three cases: only A exists, only B exists, and both A and B exist simultaneously, where A and B can be singular or plural. The character " / " generally indicates that the preceding and following related objects are in an "or" relationship. "At least one (item) of the following" or similar expressions refer to any combination of these items, including any combination of single or plural items. For example, at least one (item) of a, b, or c can represent: a, b, c, "a and b", "a and c", "b and c", or "a and b and c", where a, b, and c can be single or multiple.

[0046] For ease of description, embodiments of this application may use spatial relation terms such as "below," "below," "lower than," "below," "above," "upper," etc., to describe the relationship between an element or feature shown in the accompanying drawings and other elements or features. It will be understood that these spatial relation terms are intended to include orientations of the device in use or operation other than those depicted in the drawings. For example, if the device in the drawings is flipped, the orientation of an element described as "below," "below," or "below" other elements or features will change to "above" said other elements or features. Thus, the exemplary terms "below" and "below" can encompass both up and down directions. The device may also have other orientations (rotated 90 degrees or in other orientations), and therefore the spatial relation descriptors used herein should be interpreted accordingly. Furthermore, it will be understood that when a layer is referred to as being "between" two layers, it can be the only layer between the two layers, or there may be one or more layers in between.

[0047] In this document, the term "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0048] First, to facilitate understanding of the embodiments of this application, the following detailed analysis addresses the technical problems to be solved and the applicable application scenarios of the embodiments of this application.

[0049] With the development of technology, the size of metal-oxide-semiconductor field-effect transistors (MOSFETs) currently used in high-voltage devices is being miniaturized. Due to the high operating voltage, the transverse electric field strength in the channel is continuously enhanced, resulting in faster transport velocity of charge carriers in the on state. However, this also greatly increases the probability of collisional ionization, generating a large number of electron-hole pairs. Therefore, as the size decreases, the hot carrier injection (HCI) phenomenon in high-voltage devices increases significantly. That is, hot carriers are injected into the oxide layer under the vertical electric field applied to the gate, causing the threshold voltage of the device to rise and the saturation current to fall, affecting the reliability of the device.

[0050] Reference Appendix Figure 1 , Figure 1 This is a schematic diagram of the structure of a MOSFET provided in an embodiment of this application.

[0051] like Figure 1 As shown, current MOSFETs typically include a substrate, source, drain, and gate. The gate, which covers the space between the source and drain, comprises a polysilicon layer and a gate oxide dielectric layer. The region between the source and drain forms the channel. With decreasing size, hot carriers in the MOSFET channel at high operating voltages are injected into the oxide layer under the vertical electric field applied to the gate. This causes the threshold voltage of the MOSFET device to rise, the saturation current to decrease, and ultimately, the device's reliability to suffer.

[0052] Currently, the HCI phenomenon in devices can be improved by optimizing the lightly doped drain (LDD) process, channel doping, and optimizing the Gox process, but all of these methods have certain limitations.

[0053] For example, the lightly doped drain (LDD) process can be optimized by reducing the LDD dose while increasing the LDD implantation energy, or by gradually increasing the LDD implantation angle and performing multiple ion implantations to reduce the LDD concentration gradient and form a stepped drain, thereby improving HCI. However, the optimized LDD process is more complex and increases the overlap region, enhancing gate-induced drain leakage (GIDL) and affecting device performance.

[0054] For example, Halo implantation (IMP) at the channel location can increase the local channel resistance and reduce the peak drain electric field, thereby improving HCI. However, channel doping leads to a significant decrease in channel carrier mobility, which is detrimental to device conductivity.

[0055] For example, the Gox process can be optimized by using a double-liner process. At high temperatures (e.g., 1100 degrees Celsius), the segregation effect of boron doping at the silicon oxide interface is significantly increased, reducing the carrier concentration near the drain end of the channel and thus improving HCI. However, this method greatly increases the thermal budget of the device and raises the difficulty of fabrication.

[0056] To address this issue and improve device reliability without affecting device performance or increasing manufacturing complexity, this application provides a semiconductor device, which can be a MOSFET and can be applied to various scenarios such as logic devices, input / output devices, and memory. The polysilicon layer of the gate of this device includes multiple doped regions with different doping concentrations, such as a first doped region and a second doped region. The doping concentration of the first doped region near the drain is significantly lower than that of the second doped region; that is, the doping concentration on the drain side of the polysilicon layer of the gate is lower than that on the side farther from the drain. This results in a thicker polydepletion layer near the drain, increasing the local resistance near the drain, which helps reduce the peak electric field intensity near the drain and thus improves the HCI effect. Compared to the optimized LDD process, this method only requires controlling the doping concentration in different regions during polysilicon predoping, without the need for complex process flows. Furthermore, the embodiments of this application do not lead to GIDL enhancement, thus affecting device performance. Moreover, the embodiments of this application do not dop the channel, so they do not significantly affect the channel carrier mobility, and the device can still maintain good conductivity.

[0057] Secondly, based on the technical problems mentioned above, and in order to facilitate understanding of the embodiments of this application, the semiconductor devices on which the embodiments of this application are based will be described below.

[0058] This application provides a semiconductor device, which includes a substrate, a source and a drain located inside the substrate, and a gate located on the substrate, wherein the gate includes a polysilicon layer and a gate oxide dielectric layer stacked thereon.

[0059] Please refer to the attached document. Figure 2 , Figure 2 This is a schematic diagram of the structure of a semiconductor device provided in an embodiment of this application.

[0060] like Figure 2 As shown, the semiconductor device includes a substrate 10, with a source 101 and a drain 102 located inside the substrate 10 and spaced apart, and the source 101 and drain 102 are both located on the same side inside the substrate 10. A gate 103 is also located on the substrate.

[0061] The gate 103 is further provided with sidewalls 104 on both sides in the first direction, and each sidewall 104 is in contact with the substrate 10. The sidewalls 104 can prevent charge carriers from entering the channel when fabricating the source or drain, thereby improving the structural strength and stability of the semiconductor device, reducing leakage current, and improving the performance of the semiconductor device.

[0062] The gate 103 includes a polysilicon layer 201 and a gate oxide dielectric layer 202 stacked together.

[0063] The gate oxide dielectric layer 202 is located between the polysilicon layer 201 and the substrate 10, and the projection of the polysilicon layer 201 onto the substrate 10 lies between the source 101 and the drain 102. It is understood that the projection of the gate oxide dielectric layer 202 onto the substrate 10 also lies between the source 101 and the drain 102. Both sides of the polysilicon layer 201 and the gate oxide dielectric layer 202 in the first direction are covered by sidewalls 104.

[0064] The polysilicon layer 201 includes a first doped region 2011 and a second doped region 2012. The first doped region 2011 is located on the side of the polysilicon layer 201 closer to the drain 102, and the second doped region 2012 is located on the side of the first doped region 2011 away from the drain 102. The doping concentration of the first doped region 2011 is lower than the doping concentration of the second doped region 2012.

[0065] It should be noted that in the embodiments of this application and the following related embodiments, the X-axis direction is defined as the direction parallel to the surface of the substrate 10 and parallel to the direction between the source and drain electrodes in the semiconductor device. That is, parallel to the direction between the source and drain electrodes in the semiconductor device. Figure 2The left-right direction of the substrate 10 surface is the X-axis direction. Furthermore, this X-axis direction is the first direction mentioned in the embodiments of this application and the related embodiments described below. The Y-axis direction (not shown) is a direction parallel to the substrate 10 surface and perpendicular to the X-axis direction; that is, parallel to... Figure 2 The front-to-back direction of the surface of substrate 10 is shown. Perpendicular to... Figure 2 The direction of the substrate 10 surface shown, which is the thickness direction of the semiconductor device, is the Z-axis direction, i.e., as shown... Figure 2 The vertical direction of the substrate 10 surface is shown. The X-axis, Y-axis, and Z-axis are all perpendicular to each other.

[0066] Furthermore, the polysilicon layer 201 of the gate 103 of this semiconductor device includes multiple doped regions with different doping concentrations, such as a first doped region 2011 and a second doped region 2012. By controlling the doping concentration of the first doped region 2011 near the drain 102 to be lower than that of the second doped region 2012 far from the drain 102, the local polydepletion near the drain can be thickened, increasing the local resistance near the drain. This helps to reduce the peak electric field intensity near the drain, thereby reducing the injection of hot carriers and improving the HCI effect.

[0067] It is understandable that the doping concentration in the polysilicon layer 201 is lower only on the side near the drain 102, while other areas maintain a higher doping concentration, in order to avoid affecting device performance due to the overall reduction in the doping concentration of the polysilicon layer 201.

[0068] It is also understood that the substrate 10 of the semiconductor device is a highly doped semiconductor material layer. Depending on the type of semiconductor device, the semiconductor device substrate 10 can be adapted to be a P-type substrate. Specifically, when the semiconductor device is an N-type MOSFET, P-type doping can be performed during well implantation, and when the semiconductor device is a P-type MOSFET, N-type doping can be performed during well implantation.

[0069] The substrate 10 may be one or more of the following materials, including but not limited to: silicon (Si), glass, quartz, diamond, germanium (Ge), silicon-germanium (SiGe), silicon carbide (SiC), silicon-germanium (SiGeC), etc. This application does not impose specific limitations on these materials.

[0070] Furthermore, the source 101 and drain 102 of this semiconductor device are fabricated inside the substrate 10 by ion implantation. The doping type of the source 101 and drain 102 varies depending on the type of well implantation. For example, when the well implantation type is P-type, the source 101 and drain 102 are N-type doped; when the well implantation type is N-type, the source 101 and drain 102 are P-type doped.

[0071] Correspondingly, the polysilicon layer 201 in the gate 103 also has the same type of doping as the source 101 and drain 102. Depending on the type of field-effect transistor, when the semiconductor device is a P-type MOSFET, a forward voltage can be applied to the gate 103, and the gate electric field causes a conductive channel (channel) to be formed in the substrate region from the drain to the source. When the semiconductor device is an N-type MOSFET, a reverse voltage can be applied to the gate 103, and the gate electric field causes a conductive channel (channel) to be formed in the substrate region from the drain to the source. Charge carriers can flow freely through the conductive channel, thereby realizing current transmission, and the MOSFET is in the on state.

[0072] In some embodiments, the first doped region 2011 and the second doped region 2012 have the same doping type. Different doped regions in the polysilicon layer 201 differ only in doping concentration, but their corresponding doping types are the same. For example, the polysilicon layer can be configured as N-type doped or P-type doped depending on the doping types of the source and drain.

[0073] Correspondingly, the doping materials corresponding to the source 101, drain 102 and polysilicon layer 201 can be one or more of the following, including but not limited to boron, phosphorus, etc., and this application embodiment does not make specific limitations on this.

[0074] It should also be noted that the embodiments of this application do not specifically limit the arrangement and structure of the source 101 and drain 102. For example, the source 101 and drain 102 may include a stepped doped structure. Figure 2 As shown, the source 101 and drain 102 may include regions such as heavily doped N+, and adjacent to them are regions of lightly doped N-.

[0075] It should also be noted that the relative positions of the source 108 and the drain 109 can be interchanged, but the corresponding first doped region 2011 and second doped region 2012 will also be interchanged. That is, the doped region closer to the drain 102 is the first doped region 2011 with a low doping concentration, and the doped region farther away from the drain 102 is the second doped region 2012 with a high doping concentration. This application embodiment does not make specific limitations on this.

[0076] In other embodiments, the source 101 and drain 102 may also include more heavily doped regions, which are not specifically limited in this application. For example, the drain 102 is provided with multiple doped regions along a first direction, wherein the doping concentration of the doped regions closer to the gate 103 is less than the doping concentration of the doped regions farther from the gate 103.

[0077] As mentioned above Figure 2As shown, the gate oxide dielectric layer 202 of the gate 103 can cover a portion of the surface of the substrate 10 and may or may not be in contact with a portion of the source 101 and drain 102. A polysilicon layer is disposed on the side of the gate oxide dielectric layer 202 away from the substrate. In this case, the length of the gate oxide dielectric layer 202 in the first direction (i.e., the X-axis direction) can be equal to the length of the polysilicon layer 201 in the first direction.

[0078] In addition, the material forming the gate oxide dielectric layer 202 may be one or more of the following materials, including but not limited to: silicon dioxide (SiO2), silicon nitride (SiNx), etc. This application embodiment does not make specific limitations on this.

[0079] In some embodiments, each of the sidewalls is made of an insulating material.

[0080] The material forming the sidewall 104 may be one or more of the following materials, including but not limited to: silicon dioxide (SiO2), silicon nitride (SiNx), silicon oxynitride (SiON), etc. This application embodiment does not make specific limitations on this.

[0081] In addition, the length of each sidewall 104 in the first direction can be set according to the needs of the semiconductor device, and this application embodiment does not impose specific limitations on this.

[0082] In other embodiments, the semiconductor device may also include a plurality of contact electrodes, through which the semiconductor device can be connected to a circuit.

[0083] Understandably, please refer to the appendix. Figure 3 , Figure 3 This is a schematic diagram of another semiconductor device provided in an embodiment of this application. For example... Figure 3 As shown, the source 101, drain 102 and gate 103 in the semiconductor device can be connected to a contact electrode respectively. The contact electrode corresponding to the gate 103 can be connected to a power supply so as to apply a gate voltage to control the semiconductor device to turn on or off.

[0084] In addition, to avoid short circuits, the multiple contact electrodes are insulated from each other, and the material forming the contact electrodes can be a metallic conductive material or other conductive material. This application does not specifically limit this aspect.

[0085] Based on the above embodiments, the following related descriptions can also be referred to for the first doped region 2011 and the second doped region 2012 in the polysilicon layer 201.

[0086] In some embodiments, in a first direction, the length of the first doped region is less than the length of the second doped region, and the first direction is parallel to the substrate direction.

[0087] As mentioned above Figure 2 As shown, in the first direction (i.e., the X-axis direction), the length of the first doped region 2011 is less than the length of the second doped region 2012, and the first direction is parallel to the substrate direction.

[0088] Understandably, the length of the low-doped region (i.e., the first doped region 2011) in the polysilicon layer 201 is shorter than the length of the high-doped region (i.e., the second doped region 2012). In this case, the overall doping concentration in the polysilicon layer of the gate remains high, and the overall device performance is not affected by reducing the doping concentration near the drain. Having a lower doping concentration only in a small region near the drain helps increase the local resistance near the drain and reduce the peak electric field intensity near the drain, thereby improving the HCI effect. For example, the length of the high-doped region can be greater than twice the length of the low-doped region.

[0089] Furthermore, it is understandable that, to avoid the low-doping concentration region being too short, resulting in a low increase in local resistance near the drain and no significant improvement in the peak electric field intensity near the drain, the length of the high-doping concentration region is generally less than 10 times the length of the low-doping concentration region. That is, the length of the second doped region 2012 in the first direction can generally be between 2 and 10 times the length of the first doped region 2011 in the first direction, or it can be outside this range. The embodiments of this application do not impose specific limitations on this.

[0090] It should be noted that, in the direction perpendicular to the substrate (i.e., the Z-axis direction), the thickness of the first doped region 2011 and the thickness of the second doped region 2012 can be the same. For example, the thickness of the first doped region 2011 and the second doped region 2012 can be greater than or equal to 50 nm and less than or equal to 200 nm, or can be outside this range. This application does not impose specific limitations on this aspect.

[0091] In some embodiments, the doping concentration of the second doped region is greater than or equal to twice the doping concentration of the first doped region.

[0092] Understandably, to ensure a significant reduction in doping concentration near the drain side of the polysilicon layer, thereby increasing the local resistance near the drain and reducing the peak electric field strength near the drain, thus improving the HCI effect, the doping concentration of the second doped region can be at least greater than or equal to twice the doping concentration of the first doped region. For example, if the doping concentration of the first doped region is 1 × 10⁻⁶... 19 cm -3 In this case, the doping concentration of the second doped region needs to be at least greater than or equal to 2 × 10⁻⁶. 19 cm -3For example, the doping concentration of the second doped region can be 1 × 10⁻⁶. 19 cm -3 Or 1×10 20 cm -3 Since a higher doping concentration in the second doped region results in better performance of the semiconductor device, in some other embodiments it can be 1×10⁻⁶. 21 cm -3 The embodiments of this application do not specifically limit the scope of these embodiments.

[0093] It should be noted that, although the above descriptions of the length and doping concentration difference of the first doped region 2011 and the second doped region 2012 are exemplified by the example of 2-10 times, considering the influence of factors such as differences in preparation processes and tolerance errors, the length and doping concentration difference of the first doped region 2011 and the second doped region 2012 can also fluctuate adaptively outside this range. The embodiments of this application do not make specific limitations in this regard.

[0094] In other embodiments, the second doped region includes a plurality of third doped regions, wherein, in any two adjacent third doped regions, the doping concentration of the third doped region closer to the drain is lower than the doping concentration of the third doped region farther from the drain.

[0095] Please refer to the attached document. Figure 4 , Figure 4 This is a schematic diagram of the structure of another semiconductor device provided in the embodiments of this application. For example... Figure 4 As shown, the polysilicon layer can further incorporate multiple third doped regions within the second doped region, such as third doped region 2013 and third doped region 2023. The closer these multiple third doped regions are to the drain, the lower their corresponding doping concentration. That is, the doping concentration of third doped region 2013 is less than or equal to the doping concentration of third doped region 2023, and the doping concentration of third doped region 2013 is greater than the doping concentration of first doped region 2011. This stepped arrangement, even with the continuously increasing lateral electric field strength in the channel, does not significantly affect the channel carrier mobility, thus improving hot carrier injection and enhancing device reliability.

[0096] Furthermore, as can be seen from the above description regarding the doping concentration of the second doped region being greater than or equal to twice the doping concentration of the first doped region, the third doped region (e.g., the third doped region 2013) with the lowest doping concentration in the second doped region is greater than or equal to twice the doping concentration of the first doped region.

[0097] In some embodiments, the doping concentration of any doped region in the polysilicon layer is greater than or equal to 1 × 10⁻⁶. 18 cm-3 .

[0098] To ensure that the polysilicon layer remains within a high doping concentration range and maintains good performance, the doping concentration of any doped region within the polysilicon layer needs to be greater than or equal to 1 × 10⁻⁶. 18 cm -3 This means it is in a heavily doped state. For example, the doping concentration of both the first doped region 2011 and the second doped region 2012 is at least greater than or equal to 1 × 10⁻⁶. 18 cm -3 .

[0099] In addition, the doping concentration of the second doped region 2012 can be less than or equal to 1×10⁻⁶. 21 cm -3 This application does not impose specific limitations on the embodiments thereof.

[0100] In summary, the polysilicon layer of this semiconductor device includes multiple doped regions with different doping concentrations, such as a first doped region and a second doped region. The doping concentration of the first doped region near the drain is significantly lower than that of the second doped region; that is, the doping concentration on the drain side of the polysilicon layer of the gate is lower than that on the side farther from the drain. This results in a thicker polydepletion layer near the drain, increasing the local resistance near the drain. This helps reduce the peak electric field intensity near the drain, thereby mitigating the HCI effect.

[0101] Secondly, the semiconductor devices mentioned in the above embodiments can be applied to common MOSFET application scenarios such as logic devices with planar transistors as the core, input / output I / O devices, static random-access memory (SRAM), and gate transistors of dynamic random-access memory (DRAM).

[0102] In this regard, the present application provides a method for fabricating a semiconductor device, which can be used to manufacture the semiconductor device mentioned in the above embodiments.

[0103] Please refer to the attached document. Figure 5 , Figure 5 This is a schematic diagram of a process for fabricating a semiconductor device according to an embodiment of this application. Figure 5 As shown, the method includes:

[0104] Step 1: Provide a substrate.

[0105] Step 2: Form a gate and sidewalls on both sides of the gate along the first direction on the surface of the substrate, and form a source and drain by doping inside the substrate.

[0106] The source and drain are spaced apart, and each sidewall is in contact with the substrate. The first direction is parallel to the substrate direction. The gate includes a polysilicon layer and a gate oxide dielectric layer stacked together. The gate oxide dielectric layer is located between the polysilicon layer and the substrate, and the projection of the polysilicon layer on the substrate is located between the source and drain. The polysilicon layer includes a first doped region and a second doped region. The first doped region is located on the side of the polysilicon layer closer to the drain, and the second doped region is located on the side of the first doped region away from the drain. The doping concentration of the first doped region is lower than that of the second doped region.

[0107] Specifically, a gate oxide dielectric layer can be prepared first, and a polysilicon layer can be formed on the surface of the gate oxide dielectric layer. Then, the polysilicon layer is etched to form a gate structure. After sidewalls are formed on both sides of the gate structure along a first direction, the substrate is doped to form the source and drain. The etching process for forming the gate structure is not described in the embodiments of this application and the following related embodiments. The final polysilicon layer includes a first doped region and a second doped region. The first doped region is located on the side of the polysilicon layer closest to the drain, and the second doped region is located on the side of the first doped region furthest from the drain. The doping concentration of the first doped region is lower than that of the second doped region.

[0108] In the preparation of polycrystalline silicon layers, in order to ensure that the doping concentrations of the first doped region and the second doped region are different, they can be doped by multiple predoping processes. In order to achieve doped regions with different doping concentrations, the number of predoping processes or the dosage of predoping for each doped region are different. For example, the first predoping process is performed on the entire region of the polycrystalline silicon layer, and the second predoping process is performed only on the second doped region in the polycrystalline silicon layer.

[0109] The doping dose for each of the multiple pre-doping processes can be the same or different. For example, the doping dose for the first pre-doping process could be 1 × 10⁻⁶. 15 cm -2 The doping dose corresponding to the second predoping can be 2×10⁻⁶. 15 cm -2 The total doping dose for the two pre-doping operations is 3 × 10⁻⁶. 15 cm -2 .

[0110] It should be noted that the doping dose for each pre-doping step can be determined based on the implantation energy and depth, as long as the doping concentration of the polycrystalline silicon layer after preparation is greater than or equal to 1×10⁻⁶. 18 cm-3 This application does not specify the doping dose for each instance.

[0111] Furthermore, this application does not impose specific limitations on the order of fabricating the first and second doped regions in the polycrystalline silicon layer, or on the order of doping the substrate on both sides of the polycrystalline silicon layer to form the source and drain electrodes. For example, the first doped region can be fabricated first, followed by the source and drain electrodes, and finally the second doped region; alternatively, the first and second doped regions can be fabricated first, followed by the source and drain electrodes.

[0112] For step two above, we will take the preparation of the first doped region, the source and drain as examples, and the preparation of the second doped region as examples.

[0113] Please refer to Figures 6-13 , Figure 6 This is a schematic diagram of another process for fabricating a semiconductor device provided in an embodiment of this application. Figures 7-13 This is a set of cross-sectional schematic diagrams of the fabrication of semiconductor devices provided in the embodiments of this application.

[0114] like Figure 6 As shown, step S11: a gate oxide dielectric layer is formed on the surface of the substrate.

[0115] like Figure 7 As shown, a gate oxide material can be grown on the surface of the substrate 10 by thermal oxidation to prepare a gate oxide dielectric layer 202.

[0116] Step S12: Deposit polysilicon on the surface of the gate oxide dielectric layer to form a first semiconductor layer, and dope the first semiconductor layer to form a second semiconductor layer.

[0117] like Figure 8 As shown, a first semiconductor layer is formed by depositing polysilicon on the surface of the gate oxide dielectric layer 202 using methods such as chemical vapor deposition (CVD), physical vapor deposition (PVD), or atomic layer deposition (ALD). The first semiconductor layer is then doped to form a second semiconductor layer. That is, in this embodiment, the poly pre-doping, which would normally be performed only once, is performed twice with different doping doses. For example, the doping dose of the first pre-doping can be 1 × 10⁻⁶. 15 cm -2 .

[0118] Step S13: Etch both sides of the second semiconductor layer to form a first opening and a second opening.

[0119] like Figure 9 As shown, etching is performed on the surface of the second semiconductor layer to form a first opening and a second opening, the bottom of which exposes the substrate. The first and second openings, with their exposed substrate bottoms, can also be used to define the relative positions of the source and drain electrodes.

[0120] like Figure 10 As shown, after etching the first opening and the second opening, sidewalls 104 can be formed on both sides of the second semiconductor layer. For example, a dielectric layer (such as silicon dioxide, silicon nitride, etc.) can be deposited on both sides and the surface of the second semiconductor layer, and then the excess dielectric layer can be removed by etching back, leaving only the dielectric layers on both sides of the second semiconductor layer to form the sidewalls 104.

[0121] Step S14: After forming sidewalls at the first opening and the second opening respectively, the substrate is doped to form a source electrode in the first region of the substrate and a drain electrode in the second region of the substrate.

[0122] Based on the above Figure 10 Taking the semiconductor device structure shown as an example, as Figure 11 As shown, in this embodiment of the application, the substrate can be doped after sidewalls are formed at the first opening and the second opening, respectively, to form a source electrode 101 in the first region of the substrate and a drain electrode 102 in the second region of the substrate.

[0123] It is understandable that the projections of the first region and the first opening onto the substrate overlap, and the projections of the second region and the second opening onto the substrate overlap. Accordingly, the first region can be the region inside the substrate located below the first opening, and a portion of the region below the gate; the second region can be the region inside the substrate located below the second opening, and a portion of the region below the gate.

[0124] It is also understandable that before fabricating the drain 102, a lightly doped LDD ion implantation technique can be used first, followed by subsequent process flows, and finally the source 101 and drain 102, as well as other front-end process flows, can be fabricated.

[0125] Step S15: Spin-coat photoresist on the surface of the first opening, the second semiconductor layer, and the second opening to form a mask layer.

[0126] like Figure 12As shown, after the source electrode 101 and drain electrode 102 are fabricated, photoresist is spin-coated onto the first opening, the surface of the second semiconductor layer, and the second opening to form a mask layer. This mask layer can protect the remaining area from ion implantation during the second pre-doping treatment of a portion of the second semiconductor layer, thereby maintaining a low doping concentration in the current region. For example, the doping dose for the second pre-doping can be 2 × 10⁻⁶. 15 cm -2 .

[0127] Step S16: Etch the surface of the mask layer to form a third opening.

[0128] like Figure 13 As shown, a third opening is formed by etching the surface of the mask layer. The bottom of this third opening exposes the second semiconductor layer, and the projection of the third opening onto the substrate overlaps with the projection of the second semiconductor layer near the source. This third opening defines the size of the second doped region.

[0129] Step S17: The second semiconductor layer is doped again at the third opening and the remaining mask layer is removed to form a polycrystalline silicon layer.

[0130] As mentioned above Figure 13 As shown, after the second semiconductor layer is doped again at the third opening, the remaining mask layer can be removed to form a polycrystalline silicon layer, thereby preparing the above-mentioned structure. Figure 2 The semiconductor device shown.

[0131] In this embodiment of the application, since the second pre-doping treatment of the polysilicon layer (i.e. the second semiconductor layer mentioned above) is performed after the source and drain are prepared, it can be avoided that the carriers in the heavily doped region (second doped region) diffuse into the low doped region (i.e. the first doped region) under the high temperature environment when preparing the source and drain, thus avoiding the effect of the device's HCI improvement.

[0132] Regarding step two above, the above embodiments provided an exemplary description by first preparing the first doped region, then preparing the source and drain, and finally preparing the second doped region. The embodiments of this application provide an exemplary description by first preparing the first doped region and the second doped region, and then preparing the source and drain.

[0133] Please refer to Figures 14-17 , Figure 14 This is a schematic diagram of another process for fabricating a semiconductor device provided in an embodiment of this application. Figures 15-17 This is a set of cross-sectional schematic diagrams of the fabrication of semiconductor devices provided in the embodiments of this application.

[0134] like Figure 14 As shown, the preparation method in step two above specifically includes:

[0135] Step S21: A gate oxide dielectric layer is formed on the surface of the substrate; polysilicon is deposited on the surface of the gate oxide dielectric layer to form a first semiconductor layer, and the first semiconductor layer is doped to form a second semiconductor layer.

[0136] Among them, as mentioned above Figures 7-8 As shown, a gate oxide dielectric layer 202 is formed on the surface of the substrate, and a first semiconductor layer is formed by depositing polysilicon on the surface of the gate oxide dielectric layer. The first semiconductor layer is then subjected to a first pre-doping treatment to form a second semiconductor layer. The corresponding descriptions of steps S11-S12 above can also be found, and will not be repeated here in this embodiment.

[0137] Step S22: Spin-coat photoresist on the surface of the second semiconductor layer to form a mask layer.

[0138] like Figure 15 As shown, photoresist is spin-coated onto the surface of the second semiconductor layer to form a mask layer.

[0139] Step S23: Etch the surface of the mask layer to form a third opening.

[0140] like Figure 16 As shown, a third opening is formed by etching the surface of the mask layer. It is understood that the bottom of the third opening exposes the second semiconductor layer, and the projection of the third opening onto the substrate overlaps with the projection of the second semiconductor layer on one side. This third opening defines the size of the second doped region in the polysilicon layer.

[0141] Step S24: The second semiconductor layer is doped again at the third opening and the remaining mask layer is removed to form the third semiconductor layer.

[0142] As mentioned above Figure 16 As shown, the second semiconductor layer is doped again at the third opening, i.e., the second pre-doping process. After the second pre-doping, the remaining mask layer is removed to form the third semiconductor layer (not shown).

[0143] Step S25: Etch both sides of the third semiconductor layer to form the first opening and the second opening.

[0144] like Figure 17 As shown, after removing the remaining mask layer, the two sides of the third semiconductor layer can be etched to form the first opening and the second opening. It can be understood that at this point, the first doped region and the second doped region in the polysilicon layer can be considered to have been fabricated.

[0145] In addition, the bottom of the first opening and the second opening are exposed with gate oxide dielectric layers, and the doping concentration in the polysilicon layer on the side of the second opening closer to the first opening is lower than the doping concentration in the polysilicon layer on the side of the first opening closer to the second opening.

[0146] Step S26: After forming sidewalls at the first opening and the second opening respectively, the substrate is doped to form a source electrode in the first region of the substrate and a drain electrode in the second region of the substrate.

[0147] Next, as mentioned above Figure 11 As shown, after forming sidewalls at the first opening and the second opening respectively, the substrate can be doped. A source electrode is formed in a first region of the substrate, and a drain electrode is formed in a second region of the substrate. The projections of the first region and the first opening onto the substrate overlap, and the projections of the second region and the second opening onto the substrate overlap. Finally, the substrate can be formed as described above. Figure 2 The semiconductor device structure shown.

[0148] After the source and drain electrodes are fabricated, other structural processes (such as sidewalls, contact electrodes, etc.) can be adapted, which will not be described in the embodiments of this application. Moreover, the relevant descriptions of the source and drain electrodes can be referred to the above embodiments, and will not be repeated here.

[0149] It is understood that due to different fabrication processes, the shapes or arrangements of the source and drain may differ. The embodiments in this application are merely illustrative examples and do not impose specific limitations on the specific fabrication processes. The fabrication process of this semiconductor device can also be adapted or modified by referring to the fabrication processes of other planar MOSFETs.

[0150] In this embodiment of the application, since the second pre-doping treatment of the polycrystalline silicon layer (i.e., the second semiconductor layer mentioned above) is prepared together with the first pre-doping treatment, the process fabrication flow can be simplified, and the device manufacturing cost can be reduced while improving the HCI phenomenon of the device.

[0151] This application also provides a chip, which includes a circuit and the semiconductor device involved in the above embodiments, wherein the circuit and the semiconductor device are described above. Alternatively, this chip may also be referred to as an integrated circuit, and this application does not specifically limit it to that term.

[0152] This application also provides an electronic device, which includes a circuit board and the chip involved in the above embodiments, wherein the circuit board and the chip are electrically connected.

[0153] It should be understood that the semiconductor device fabrication method, chip, and electronic device provided in this application can be consistent with the semiconductor device technical solution provided in this application, and their specific content and beneficial effects can be referred to the above. Figures 2-5 The semiconductor devices mentioned in the illustrated embodiments will not be described in detail here.

[0154] It should be noted that, for the sake of simplicity, the foregoing method embodiments are all described as a series of actions. However, those skilled in the art should understand that this application is not limited to the described order of actions, as some steps may be performed in other orders or simultaneously according to this application. Furthermore, those skilled in the art should also understand that the embodiments described in the specification are preferred embodiments, and the actions and modules involved are not necessarily essential to this application.

[0155] In the several embodiments provided in this application, it should be understood that the disclosed apparatus can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of the units described above is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between devices or units may be electrical or other forms.

[0156] The units described above as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0157] Furthermore, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.

[0158] The above-described embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application.

Claims

1. A semiconductor device, characterized in that, The device includes a substrate, a source and a drain located inside the substrate, and a gate located on the substrate. The source and the drain are spaced apart, and the gate is provided with sidewalls on both sides along a first direction. Each sidewall contacts the substrate. The first direction is parallel to the substrate. The gate includes a polysilicon layer and a gate oxide dielectric layer stacked together, the gate oxide dielectric layer being located between the polysilicon layer and the substrate, and the projection of the polysilicon layer onto the substrate being located between the source and the drain. The polysilicon layer includes a first doped region and a second doped region. The first doped region is located on the side of the polysilicon layer closer to the drain, and the second doped region is located on the side of the first doped region away from the drain. The doping concentration of the first doped region is lower than that of the second doped region.

2. The device according to claim 1, characterized in that, In the first direction, the length of the first doped region is less than the length of the second doped region.

3. The device according to claim 1, characterized in that, The first doped region and the second doped region have the same doping type.

4. The device according to claim 1, characterized in that, The doping concentration of the second doped region is greater than or equal to twice the doping concentration of the first doped region.

5. The device according to claim 2, characterized in that, The second doped region includes a plurality of third doped regions, wherein, in any two adjacent third doped regions, the doping concentration of the third doped region closer to the drain is lower than the doping concentration of the third doped region farther from the drain.

6. The device according to claim 1, characterized in that, The doping concentration of any doped region in the polycrystalline silicon layer is greater than or equal to 1 × 10⁻⁶. 18 cm -3 .

7. The device according to claim 1, characterized in that, Each of the sidewalls is made of an insulating material.

8. A method for fabricating a semiconductor device, characterized in that, The method includes: Provide substrate; A gate electrode and sidewalls located on both sides of the gate electrode along a first direction are formed on the surface of the substrate, and a source electrode and a drain electrode are formed by doping inside the substrate; The source and drain are spaced apart, and each sidewall is in contact with the substrate. The first direction is parallel to the substrate direction. The gate includes a polysilicon layer and a gate oxide dielectric layer stacked together. The gate oxide dielectric layer is located between the polysilicon layer and the substrate, and the projection of the polysilicon layer on the substrate is located between the source and the drain. The polysilicon layer includes a first doped region and a second doped region. The first doped region is located on the side of the polysilicon layer closer to the drain, and the second doped region is located on the side of the first doped region away from the drain. The doping concentration of the first doped region is lower than that of the second doped region.

9. The method according to claim 8, characterized in that, The process of forming a gate electrode and sidewalls located on both sides of the gate electrode along a first direction on the surface of the substrate, and forming a source electrode and a drain electrode by doping inside the substrate, includes: The gate oxide dielectric layer is formed on the surface of the substrate; A first semiconductor layer is formed by depositing polysilicon on the surface of the gate oxide dielectric layer, and the first semiconductor layer is doped to form a second semiconductor layer. The two sides of the second semiconductor layer are etched to form a first opening and a second opening, and the substrate is exposed at the bottom of the first opening and the second opening. After forming the sidewalls at the first opening and the second opening respectively, the substrate is doped, a source electrode is formed in a first region of the substrate, and a drain electrode is formed in a second region of the substrate. The projection of the first region and the first opening on the substrate overlaps, and the projection of the second region and the second opening on the substrate overlaps. Photoresist is spin-coated onto the surface of the first opening, the second semiconductor layer, and the second opening to form a mask layer; The surface of the mask layer is etched to form a third opening, the bottom of the third opening exposes the second semiconductor layer, and the projection of the third opening on the substrate overlaps with the projection of the second semiconductor layer near the source electrode. The second semiconductor layer is doped again at the third opening and the remaining mask layer is removed to form the polycrystalline silicon layer.

10. The method according to claim 8, characterized in that, The process of forming a gate electrode and sidewalls located on both sides of the gate electrode along a first direction on the surface of the substrate, and forming a source electrode and a drain electrode by doping inside the substrate, includes: The gate oxide dielectric layer is formed on the surface of the substrate; A first semiconductor layer is formed by depositing polysilicon on the surface of the gate oxide dielectric layer, and the first semiconductor layer is doped to form a second semiconductor layer. Photoresist is spin-coated onto the surface of the second semiconductor layer to form a mask layer; The surface of the mask layer is etched to form a third opening, the bottom of which exposes the second semiconductor layer, and the projection of the third opening on the substrate overlaps with the projection of the second semiconductor layer on one side. The second semiconductor layer is doped again at the third opening and the remaining mask layer is removed to form the third semiconductor layer. The two sides of the third semiconductor layer are etched to form a first opening and a second opening. The substrate is exposed at the bottom of the first opening and the second opening. The doping concentration of the second opening near the first opening is less than the doping concentration of the first opening near the second opening. After forming the sidewalls at the first opening and the second opening respectively, the substrate is doped, a source electrode is formed in a first region of the substrate, and a drain electrode is formed in a second region of the substrate. The projection of the first region and the first opening on the substrate overlaps, and the projection of the second region and the second opening on the substrate overlaps.

11. A chip, characterized in that, Includes the semiconductor device as described in any one of claims 1-7.

12. An electronic device, characterized in that, It includes a circuit board and a chip as described in claim 11 above, wherein the circuit board is electrically connected to the integrated circuit.

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