A semiconductor structure and a method of forming the same

Abstract

The application provides a semiconductor structure and a forming method thereof. The semiconductor structure comprises: a silicon carbide substrate, a silicon carbide epitaxial layer is formed on the surface of the silicon carbide substrate; a first doped region is located in the silicon carbide epitaxial layer; a trench gate structure is located in the first doped region; a third doped region is located in the first doped region and covers the end corner of the trench gate structure; and a gate metal layer is located on the silicon carbide epitaxial layer and electrically connected with the trench gate structure and the third doped region.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to a semiconductor structure and a method for forming the same. Background Technology

[0002] As the performance requirements of power semiconductor devices increase, trench devices, which have higher channel density than planar devices, are becoming more common. While further increasing the channel density and reducing the cell size, it is inevitable to narrow the trench width. However, narrowing the trench width will inevitably lead to a sharp increase in the electric field at the bottom and end of the trench, which will bring great reliability risks and reduced lifespan to the gate dielectric layer in the channel.

[0003] Therefore, it is necessary to propose a protection scheme for the electric field problem at the end of the trench when the trench width is reduced. Summary of the Invention

[0004] The purpose of this invention is to provide a technical solution to protect the end electric field problem of trench gate structures.

[0005] One aspect of this application provides a semiconductor structure comprising: a silicon carbide substrate having a silicon carbide epitaxial layer formed on its surface; a first doped region located in the silicon carbide epitaxial layer; a trench gate structure located in the first doped region; a third doped region located in the first doped region and covering the end corner of the trench gate structure; and a gate metal layer located on the silicon carbide epitaxial layer and electrically connecting the trench gate structure and the third doped region.

[0006] In some embodiments of this application, the semiconductor structure further includes: a second doped region located in the first doped region and covering the bottom and sidewalls of the third doped region, wherein the doping types of the first doped region and the second doped region are opposite, and the doping types of the first doped region and the third doped region are the same.

[0007] In some embodiments of this application, the gate metal layer is electrically connected to the third doped region through a fourth doped region, the fourth doped region extending vertically from the surface of the third doped region into the third doped region.

[0008] In some embodiments of this application, the fourth doped region extends along the outer edge of the end of the trench gate structure in a direction perpendicular to the extension direction of the trench gate structure.

[0009] In some embodiments of this application, the fourth doped region is located between adjacent trench gate structures.

[0010] In some embodiments of this application, the gate dielectric layer of the trench gate structure extends to the surface of the silicon carbide epitaxial layer.

[0011] In some embodiments of this application, the semiconductor structure further includes: an interlayer dielectric layer covering the gate dielectric layer and the trench gate structure, wherein the gate metal layer is located on the surface of the interlayer dielectric layer.

[0012] Another aspect of this application provides a method for forming a semiconductor structure, comprising: providing a silicon carbide substrate, wherein a silicon carbide epitaxial layer is formed on the surface of the silicon carbide substrate; forming a first doped region in the silicon carbide epitaxial layer; forming a trench gate structure in the first doped region; forming a third doped region in the first doped region covering the end corner of the trench gate structure; and forming a gate metal layer on the silicon carbide epitaxial layer electrically connecting the trench gate structure and the third doped region.

[0013] In some embodiments of this application, the method for forming the semiconductor structure further includes: forming a second doped region in the first doped region that covers the bottom and sidewalls of the third doped region, wherein the doping types of the first doped region and the second doped region are opposite, and the doping types of the first doped region and the third doped region are the same.

[0014] In some embodiments of this application, the gate metal layer is electrically connected to the third doped region through a fourth doped region, the fourth doped region extending vertically from the surface of the third doped region into the third doped region.

[0015] In some embodiments of this application, the fourth doped region extends along the outer edge of the end of the trench gate structure in a direction perpendicular to the extension direction of the trench gate structure.

[0016] In some embodiments of this application, the fourth doped region is located between adjacent trench gate structures.

[0017] In some embodiments of this application, the gate dielectric layer of the trench gate structure extends to the surface of the silicon carbide epitaxial layer.

[0018] In some embodiments of this application, the method for forming the semiconductor structure further includes: forming an interlayer dielectric layer covering the gate dielectric layer and the trench gate structure, wherein the gate metal layer is located on the surface of the interlayer dielectric layer.

[0019] This application provides a semiconductor structure and a method for forming the same, and provides a technical solution to protect the electric field problem at the end of a trench gate structure by forming a third dielectric layer at the end corner of the trench gate structure to provide protection. Attached Figure Description

[0020] The following accompanying drawings describe in detail the exemplary embodiments disclosed in this application. The same reference numerals denote similar structures in several views of the drawings. Those skilled in the art will understand that these embodiments are non-limiting and exemplary, and the drawings are for illustrative purposes only and are not intended to limit the scope of this application. Other embodiments may similarly fulfill the inventive intent of this application. It should be understood that the drawings are not drawn to scale. Wherein: Figures 1 to 4 This is a schematic diagram of the semiconductor structure described in some embodiments of this application; Figures 5 to 8 This is a schematic diagram of the semiconductor structure described in other embodiments of this application. Detailed Implementation

[0021] The following description provides specific application scenarios and requirements for this application, intended to enable those skilled in the art to make and use the content of this application. Various partial modifications to the disclosed embodiments will be apparent to those skilled in the art, and the general principles defined herein can be applied to other embodiments and applications without departing from the spirit and scope of this application. Therefore, this application is not limited to the embodiments shown, but rather to the widest scope consistent with the claims.

[0022] The technical solution of the present invention will be described in detail below with reference to the embodiments and accompanying drawings.

[0023] Figures 1 to 4 This is a schematic diagram of the semiconductor structure described in some embodiments of this application. Wherein, Figure 1 and Figure 2 A three-dimensional view of the semiconductor structure after removing a portion. Figure 3 For along Figure 1 XZ section view of the middle A axis, Figure 4 For along Figure 1 The XZ section view along the B-axis. A three-dimensional XYZ coordinate system is established in the attached figure for easy observation.

[0024] refer to Figure 1 and Figure 2 As shown, the B-axis is located in the direction of the trench gate structure, and the A-axis and C-axis are located between adjacent trench gate structures. The cell of the semiconductor structure 100 is the region between the A-axis and C-axis on the YZ plane, and the semiconductor structure 100 can be an arbitrary number of repeating arrangements of the cells. (Reference) Figures 1 to 4 The coordinate system icon shows that the positive X direction is the direction of the active region of the device, and the negative X direction is the direction of the terminal region of the device.

[0025] refer to Figures 1 to 4As shown, some embodiments of this application provide a semiconductor structure 100, including: a silicon carbide substrate 102, on which a silicon carbide epitaxial layer 103 is formed; a first doped region 104 located in the silicon carbide epitaxial layer 103; a trench gate structure located in the first doped region 104; a third doped region 106 located in the first doped region 104 and covering the end corner 101b of the trench gate structure; and a gate metal layer 131 located on the silicon carbide epitaxial layer 103 and electrically connecting the trench gate structure and the third doped region 106.

[0026] Continue to refer to Figures 1 to 4 As shown, in some embodiments of this application, the semiconductor structure 100 further includes: a second doped region 105, located within the first doped region 104 and covering the bottom and sidewalls of the third doped region 106; the first doped region 104 and the second doped region 105 have opposite doping types, for example, P-type; the first doped region 104 and the third doped region 106 have the same doping type. The first doped region 104, the second doped region 105, and the third doped region 106 constitute a PNP structure.

[0027] When reducing cell size in trench power devices, it is inevitable to narrow the trench width. However, this narrowing inevitably leads to electric field concentration at the bottom and ends of the trench, causing a sharp increase in the electric field at these locations. Generally, the bottom and ends of the trench are covered by a shielding region with a doping type opposite to the drift region, such as a P-type doped shielding region, to resist the source-drain voltage when the device is turned off. The implementation method at the end of the trench is generally called junction termination extension. Therefore, the electric field concentration effect at the bottom and ends of the trench is the gate-source electric field concentration effect. Since the gate-source voltage is much lower than the source-drain voltage, a high gate-source electric field may not cause immediate gate dielectric layer damage. However, the gate dielectric layer degradation effect caused by the high gate-source electric field, such as hot carrier injection, will lead to long-term device performance deterioration, such as threshold drift and increased gate leakage current, and may even eventually lead to device failure. Therefore, in terms of device lifetime and reliability, the concentrated effect of the gate-source electric field at the bottom and end of the trench is a problem that must be solved first when miniaturizing trench power devices.

[0028] In the technical solution of this application, the first doped region 104 is connected to the source 142 through the first doped region metal contact 104x and the source metal layer 132, and is at the source potential; the second doped region 105 is at a floating potential; the third doped region 106 is connected to the gate metal layer 131 and the gate 141, and is at the gate potential. In this design, the second doped region 105 and the third doped region 106 are provided to cover the end corner 101b of the trench gate structure, wherein the third doped region 106 directly covers the end corner 101b of the trench gate structure. Since both the gate 141 and the third doped region 106 covering the end corner 101b of the trench gate structure are at the gate potential, the electric field in the gate dielectric layer 111 at the end corner 101b of the trench gate structure is zero, eliminating the degradation problem of the gate dielectric layer 111 caused by the electric field concentration effect at the end corner 101b of the trench gate structure. Furthermore, the first doped region 104, the second doped region 105, and the third doped region 106 are doped in a forward-reverse-forward stack, such as a PNP stack, with two reverse-connected PN junctions. Under any gate-source voltage, one of the two PN junctions will be reverse-biased. Therefore, if the gate-source voltage is below the breakdown voltage of the two PN junctions, the first doped region 104 and the third doped region 106 will not conduct. The electric field at the end corner 101b of the trench gate structure, which was originally borne by the gate dielectric layer 111 at that location, is instead borne by the depletion layer provided by the PN junction formed by the second doped region 105 and the third doped region 106 in this design. The corner radius of the depletion layer is larger than the corner radius of the end corner 101b of the trench gate structure, and the thickness of the depletion layer is thicker than the gate dielectric layer 111. Therefore, the electric field borne by the depletion layer is smaller than the corner electric field at the end corner 101b of the trench gate structure without the stacked structure, and the electric field being borne by the PN junction depletion layer does not result in a reliability degradation effect.

[0029] The second advantage of this application's design is that, generally, when avalanche breakdown occurs in the junction termination extension region, i.e., the first doped region 104 in this application's design, most of the avalanche current will flow to the nearest source metal contact 104x. However, if the breakdown location is far from the source metal contact 104x, the large avalanche current and the parasitic resistance within the first doped region 104 will cause a large potential difference between the surface of the first doped region 104 and the gate dielectric layer 111, which may break down the weak point of the gate dielectric layer 111, causing gate-source failure. The same situation will also occur when the device is turned off at an extremely high gate voltage drop rate. The large positive via current and the parasitic resistance within the first doped region 104 will cause a large potential difference between the surface of the first doped region 104 and the gate dielectric layer 111, which may cause the gate dielectric layer 111 to break down. In the design of this application, the potential difference is borne by the depletion layer provided by the PN junction in the aforementioned stack. Similarly, since the thickness of the second doped region 105 and the third doped region 106 is thicker than that of the gate dielectric layer 111, the electric field borne by the depletion layer is smaller, effectively protecting the gate dielectric layer 111 from damage caused by the high potential difference brought by avalanche current or positive hole current at high turn-off speed.

[0030] The third advantage of this design is that, generally, the gate electrode of the gate interconnect 121b is placed on a thicker insulating layer, such as a field oxide layer with a thickness of more than 1 micrometer. This is to reduce gate-source failure caused by defects that may be present in the gate dielectric layer 111 in the non-cell region, and also to reduce the electric field concentration effect at the bottom corner of the gate interconnect structure 121b. In this design, the area under the gate interconnect structure 101b is covered by the third doped region 106, so the electric field in the gate dielectric layer 111 under the gate interconnect structure 121b is zero. Therefore, the aforementioned thicker insulating layer, such as the field oxide layer, placed at this location can be omitted. This eliminates the need for spacing between the insulating layer and the metal layer stack for pattern alignment deviation and stress management, which helps to reduce the device chip area.

[0031] In some embodiments of this application, the silicon carbide substrate 102 is made of silicon carbide, and the silicon carbide epitaxial layer 103 is also made of silicon carbide. In some embodiments of this application, the silicon carbide substrate 102 and the silicon carbide epitaxial layer 103 may contain doped ions, such as N-type doped nitrogen or phosphorus ions. The doping concentration of the silicon carbide substrate 102 is 1 x 10⁻⁶. 14 Up to 5x10 16 Atoms per cubic centimeter. The doping concentration of the silicon carbide epitaxial layer 103 is 1 x 103. 17 Up to 1x10 21 Atoms per cubic centimeter.

[0032] Continue to refer to Figures 1 to 4As shown, in some embodiments of this application, a drain metal layer 133 is further formed on the back side of the silicon carbide substrate 102. The thickness of the drain metal layer 133 is 0.1 to 10 micrometers. The material of the drain metal layer 133 includes any one or more of aluminum, copper, silver, gold, nickel, titanium, platinum, and palladium. The drain metal layer 133 is connected to the drain 143.

[0033] In some embodiments of this application, the first doped region 104 is a termination extension region located in the termination region of the semiconductor structure 100. The doping type of the first doped region 104 is, for example, P-type. The depth of the first doped region 104 is, for example, 0.5 to 5 micrometers. The doping concentration of the first doped region 104 is, for example, 1 x 10⁻⁶. 17 Up to 5x10 18 Atoms per cubic centimeter.

[0034] Continue to refer to Figures 1 to 4 As shown, in some embodiments of this application, the trench gate structure includes: a gate electrode 121a and a gate dielectric layer 111 covering the bottom and sidewalls of the gate electrode 121a, the gate dielectric layer 111 further extending to the surface of the silicon carbide epitaxial layer 103. The gate electrode 121a is connected to the gate metal layer 131 through the gate electrode contact region 121x of the gate electrode interconnect structure 121b. The trench gate structure is formed in the gate trench 101a. The gate electrode interconnect structure 121b is directly electrically connected to the gate electrode 121a. The gate electrode interconnect structure 121b intersects the gate electrode 121b perpendicularly. The gate electrode interconnect structure 121b is isolated from the third doped region 106 only through the gate dielectric layer 111. The material of the gate electrode interconnect structure 121b can be the same as that of the gate electrode 121a, and it is fabricated simultaneously with the gate electrode 121a (depositing polysilicon material followed by etching; the polysilicon material located in the trench serves as the gate electrode 121a, and the remaining polysilicon outside the trench serves as the gate electrode interconnect structure 121b). The trench gate structure is a conventional structure in silicon carbide power devices, and its detailed structure will not be described in detail here. The thickness of the gate dielectric layer 111 is, for example, 0.02 to 0.1 micrometers.

[0035] Continue to refer to Figures 1 to 4As shown, the third doped region 106 is located within the first doped region 104 and covers the end corner 101b of the trench gate structure. The trench gate structure is elongated, i.e., a cuboid, or an elongated shape with semicircular ends, i.e., a capsule shape; the end corner 101b of the trench gate structure refers to the corner of the three-dimensional elongated shape located at the bottom of the trench 101a, i.e., the bottom corner of the cuboid, or the rounded corner of the capsule shape. Specifically, the third doped region 106 covers part of the bottom surface, all of the end surface, and portions of the two sides of the end 101b of the trench gate structure. The third doped region 106 also covers the bottom corner of the gate electrode interconnect structure 121b. The third doped region 106 also extends to the surface of the first doped region 104. The doping type of the third doped region 106 is, for example, P-type. The thickness of the third doped region 106 is, for example, 0.1 to 1 micrometer. The doping concentration of the third doped region 106 is, for example, 1 x 10⁻⁶. 18 Up to 5x10 21 Atoms per cubic centimeter.

[0036] Continue to refer to Figures 1 to 4 As shown, the doping type of the second doped region 105 is, for example, N-type. The thickness of the second doped region 105 is, for example, 0.1 to 0.5 micrometers. The doping concentration of the second doped region 105 is, for example, 1 x 10⁻⁶. 14 Up to 5x10 18 Atoms per cubic centimeter. The second doped region 105 covers the third doped region 106, separating the first doped region 104 and the third doped region 106. The first doped region 104 and the third doped region 106 are not connected at any location. The boundary of the second doped region 105 is as close as possible to the metal contact 104x of the first doped region, for example, within 2 micrometers, preferably within 1 micrometer.

[0037] Continue to refer to Figures 1 to 4 As shown, in some embodiments of this application, the gate metal layer 131 is electrically connected to the third doped region 106 via a fourth doped region 107, which extends vertically from the surface of the third doped region 106 into the third doped region 106. The doping type of the fourth doped region 107 is, for example, N-type. The thickness of the fourth doped region 107 is, for example, 0.1 to 0.5 micrometers. The doping concentration of the fourth doped region 107 is, for example, 1 x 10⁻⁶. 19 Up to 5x10 21 Atoms per cubic centimeter. The fourth doped region 107 is located on the upper surface of the silicon carbide epitaxial layer 103 and does not exist within the trench area. The fourth doped region 107 is connected to the third doped region 106.

[0038] The third doped region 106 may or may not cover the fourth doped region 107. The fourth doped region 107 may or may not contact the second doped region 105. The third doped region 106 is connected to the gate metal layer 131 and the gate 141 through the fourth doped region 107 and the fourth doped region metal contact 107x. The function of the fourth doped region 107 is to provide a higher doping concentration at the junction of the third doped region 106 and the gate metal layer 131 than the third doped region 106 itself, thereby obtaining a lower contact resistance.

[0039] refer to Figure 2 As shown, in some embodiments of this application, the fourth doped region 107 extends in a direction perpendicular to the extension direction of the trench gate structure along the outer edge of the end of the trench gate structure.

[0040] Continue to refer to Figures 1 to 4 As shown, in some embodiments of this application, the semiconductor structure 100 further includes: an interlayer dielectric layer 112 covering the gate dielectric layer 111 and the trench gate structure, wherein the gate metal layer 131 and the source metal layer 132 are located on the surface of the interlayer dielectric layer 112. The thickness of the interlayer dielectric layer 112 is 0.1 to 1 micrometer.

[0041] Figures 5 to 8 This is a schematic diagram of the semiconductor structure described in other embodiments of this application.

[0042] refer to Figures 5 to 8 As shown, in some other embodiments of this application, the fourth doped region 207 and the fourth doped region metal contact 207x are located between the gate electrode interconnect structure 121b and the active region of the device 200 in the x direction, and between adjacent trenches 201a in the y direction.

[0043] It should be noted that, Figures 5 to 8 Other embodiments shown are similar to Figures 1 to 4 Apart from the differences mentioned above, the embodiments are identical in all other structures, and therefore will not be described in detail again. Figures 5 to 8 and Figures 1 to 4 The numbering in the code is the same except that the first digit is changed from 1 to 2.

[0044] This application also provides a method for forming the semiconductor structure 100, see reference. Figures 1 to 4As shown, the method includes: providing a silicon carbide substrate 102, on the surface of which a silicon carbide epitaxial layer 103 is formed; forming a first doped region 104 in the silicon carbide epitaxial layer 103; forming a trench gate structure in the first doped region 104; forming a third doped region 106 in the first doped region 104 covering the end corner of the trench gate structure; and forming a gate metal layer 131 on the silicon carbide epitaxial layer 103 electrically connecting the trench gate structure and the third doped region 106.

[0045] Since the structure of the semiconductor structure 100 has been described in detail above, the structure will not be described again in the method section. Only the formation process of the semiconductor structure 100 will be briefly described.

[0046] refer to Figures 1 to 4 As shown, a silicon carbide substrate 102 is provided, and a silicon carbide epitaxial layer 103 is formed on the surface of the silicon carbide substrate 102; a first doped region 104, a second doped region 105, a third doped region 106, and a fourth doped region 107 are formed by ion implantation; a trench 101a is formed; a gate dielectric layer 111 is formed; a gate electrode 121a and a gate electrode interconnect structure 121b are formed; an interlayer dielectric layer 112 is formed; a source metal layer 131 and a gate metal layer 132 are formed; and a drain metal layer 133 is formed.

[0047] This application provides a semiconductor structure and a method for forming the same, and provides a technical solution to protect the electric field problem at the end of a trench gate structure by forming a third dielectric layer at the end corner of the trench gate structure to provide protection.

[0048] In summary, after reading this application, those skilled in the art will understand that the foregoing application content is presented by way of example only and is not restrictive. Although not explicitly stated herein, those skilled in the art will understand that this application is intended to encompass various reasonable changes, improvements, and modifications to the embodiments. These changes, improvements, and modifications are all within the spirit and scope of the exemplary embodiments of this application.

[0049] It should be understood that the term "and / or" as used in this embodiment includes any or all combinations of one or more of the associated listed items. Similarly, it should be understood that when an element such as a layer, region, or substrate is referred to as being "on" another element, it may be directly on the other element, or there may be intermediate elements present. Conversely, the term "directly" means without intermediate elements. It should also be understood that the terms "comprising," "including," "comprise," or "including" as used in this application specify the presence of the described features, integrals, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or groups thereof.

[0050] It should also be understood that although the terms first, second, third, etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. Therefore, without departing from the teachings of this application, a first element in some embodiments may be referred to as a second element in other embodiments. The same reference numerals or the same reference signs denote the same elements throughout the specification.

[0051] Furthermore, this application specification describes exemplary embodiments by referring to idealized exemplary cross-sectional views and / or plan views and / or perspective views. Therefore, differences from the illustrated shapes are foreseeable due to factors such as manufacturing techniques and / or tolerances. Thus, exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but should include deviations in shape caused, for example, by manufacturing processes. For instance, etched areas shown as rectangular typically have circular or curved features. Therefore, the regions shown in the figures are substantially schematic, and their shapes are not intended to illustrate the actual shape of the regions of the device, nor are they intended to limit the scope of the exemplary embodiments.

Claims

1. A semiconductor structure, characterized in that, include: A silicon carbide substrate, wherein a silicon carbide epitaxial layer is formed on the surface of the silicon carbide substrate; The first doped region is located in the silicon carbide epitaxial layer; A trench gate structure is located in the first doped region; The third doped region is located in the first doped region and covers the end corner of the trench gate structure; A gate metal layer is located on the silicon carbide epitaxial layer and electrically connects the trench gate structure and the third doped region.

2. The semiconductor structure as described in claim 1, characterized in that, Also includes: The second doped region is located within the first doped region and covers the bottom and sidewalls of the third doped region. The doping types of the first and second doped regions are opposite, while the doping types of the first and third doped regions are the same.

3. The semiconductor structure as described in claim 1, characterized in that, The gate metal layer is electrically connected to the third doped region through a fourth doped region, which extends vertically from the surface of the third doped region into the third doped region.

4. The semiconductor structure as described in claim 3, characterized in that, The fourth doped region is located at the outer edge of the end of the trench gate structure and extends in a direction perpendicular to the extension direction of the trench gate structure.

5. The semiconductor structure as described in claim 3, characterized in that, The fourth doped region is located between adjacent trench gate structures.

6. The semiconductor structure as described in claim 1, characterized in that, The gate dielectric layer of the trench gate structure extends to the surface of the silicon carbide epitaxial layer.

7. The semiconductor structure as described in claim 6, characterized in that, Also includes: An interlayer dielectric layer covers the gate dielectric layer and the trench gate structure, and the gate metal layer is located on the surface of the interlayer dielectric layer.

8. A method for forming a semiconductor structure, characterized in that, include: A silicon carbide substrate is provided, wherein a silicon carbide epitaxial layer is formed on the surface of the silicon carbide substrate; A first doped region is formed in the silicon carbide epitaxial layer; A trench gate structure is formed in the first doped region; A third doped region is formed in the first doped region to cover the end corner of the trench gate structure; A gate metal layer electrically connecting the trench gate structure and the third doped region is formed on the silicon carbide epitaxial layer.

9. The method for forming a semiconductor structure as described in claim 8, characterized in that, Also includes: A second doped region is formed in the first doped region to cover the bottom and sidewalls of the third doped region. The doping types of the first doped region and the second doped region are opposite, while the doping types of the first doped region and the third doped region are the same.

10. The method for forming a semiconductor structure as described in claim 8, characterized in that, The gate metal layer is electrically connected to the third doped region through a fourth doped region, which extends vertically from the surface of the third doped region into the third doped region.

11. The method for forming a semiconductor structure as described in claim 10, characterized in that, The fourth doped region is located at the outer edge of the end of the trench gate structure and extends in a direction perpendicular to the extension direction of the trench gate structure.

12. The method for forming a semiconductor structure as described in claim 10, characterized in that, The fourth doped region is located between adjacent trench gate structures.

13. The method for forming a semiconductor structure as described in claim 8, characterized in that, The gate dielectric layer of the trench gate structure extends to the surface of the silicon carbide epitaxial layer.

14. The method for forming a semiconductor structure as described in claim 8, characterized in that, Also includes: An interlayer dielectric layer is formed covering the gate dielectric layer and the trench gate structure, wherein the gate metal layer is located on the surface of the interlayer dielectric layer.

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