Microelectronic assembly having decomposition features

Abstract

In one example, a microelectronic assembly having a decomposition component includes a substrate, a die, a redistribution layer (RDL) disposed on the die, and a conductive interconnect (e.g., one or more of a conductive pillar, a solder cap, and a solder ball) between and coupled with the substrate and the RDL. The die can be coupled with a top side of the RDL. Another die can be coupled with a package side of the RDL. For example, the other die can be in a bump field between the RDL and the substrate. In some examples, the other die can be embedded in the substrate. In some examples, the other die can be TSV-less and lack a conductive interconnect in direct contact with a conductive contact of the substrate. In some examples, the other die can be embedded within a redistribution layer (RDL) of the substrate and coplanar with a conductive pillar between the RDL and the substrate.

Description

Background Technology

[0001] Electronic circuits are typically fabricated on wafers made of semiconductor materials such as silicon; these circuits are then called integrated circuits (ICs). Wafers containing such ICs are usually diced into many individual dies. These dies can be packaged into IC packages that contain one or more dies along with other electronic components such as resistors, capacitors, and inductors. IC packages can be integrated into electronic systems such as consumer electronics systems, which also include servers such as mainframes. Attached Figure Description

[0002] The embodiments will be readily understood from the following detailed description taken in conjunction with the accompanying drawings. For ease of description, the same reference numerals denote the same structural elements. The embodiments are illustrated in the accompanying drawings by way of example rather than limitation.

[0003] Figure 1A-Figure 1B , Figures 2-7 , Figures 8A-8B and Figures 9-13 Different cross-sectional views of examples of microelectronic components with disassembled parts according to some embodiments of the present disclosure are shown.

[0004] Figures 14A-14B A cross-sectional side view is shown of an example of a die that may be included in a microelectronic assembly having disassembled components, according to some embodiments of the present disclosure.

[0005] Figures 15A-15C A cross-sectional side view is shown of an example of a substrate that may be included in a microelectronic assembly having disassembled components, according to some embodiments of the present disclosure.

[0006] Figure 16 A plan view is shown of an example of a system that can be implemented as a microelectronic component having disassembled parts according to an embodiment of the present disclosure.

[0007] Figure 17 This is a top view of a wafer and die that may be included in any microelectronic component disclosed herein, according to any embodiment disclosed herein.

[0008] Figure 18 It is a side cross-sectional view of an IC package that may be included in or incorporated into any microelectronic component disclosed herein, according to various embodiments.

[0009] Figure 19 This is a side cross-sectional view of an IC device assembly that may include or be an example of a microelectronic component disclosed herein, according to any embodiment disclosed herein.

[0010] Figure 20It is a block diagram of an exemplary electrical device that may be included in or incorporated into any microelectronic component disclosed herein, according to any embodiment disclosed herein. Detailed Implementation

[0011] This document discloses microelectronic components with disassembled parts. The systems, methods, and apparatuses of this disclosure each have multiple aspects of innovation, and no single aspect can alone assume all the desired properties disclosed herein. Details of one or more implementations of the subject matter described herein are set forth in the following description and accompanying drawings.

[0012] Semiconductor chip manufacturing involves a series of complex processes used to create the structure of integrated circuits (ICs). These processes include photolithography, ion implantation, etching, and deposition. Wafers typically undergo multiple rounds of these processes to form devices and interconnects on the wafer. Once wafer processing is complete, the wafer can be diced into individual chips (also known as dies). After dicing (slicing), individual dies are packaged to provide interconnection and protection with other components.

[0013] Encapsulating a die can involve attaching the die to a substrate (such as a motherboard, interposer, or other circuit board or structure with conductive interconnects) to connect the die's conductive contacts to the package's conductive contacts (e.g., using flip-chip bonding, ball grid array (BGA), etc.). For attachment to a circuit board, the die can be soldered directly to the board or inserted into a socket (e.g., in the case of a packaged die). In some cases, multiple dies can be combined (e.g., stacked) into a single component or package before being mounted on a circuit board.

[0014] In some instances, components can be embedded within the interposer. For example, bridging dies can be embedded within the interposer, and other IC dies attached to the interposer can be interconnected through such embedded bridging dies. In some instances, active dies can be embedded within the interposer. However, embedding active dies within the mold of the interposer can lead to poor heat dissipation and other thermodynamic challenges. Furthermore, embedded dies significantly increase assembly cost and complexity. For instance, embedded bridging dies may require thinning to expose through-silicon vias (TSVs) or substrate through-vias (TSVs) on the surface of the bridging die, attaching it to the interposer, and securing it with underfill material and / or molding material around the bridging die, which increases assembly cost and complexity. Additionally, using embedded bridging dies with TSVs extending through the bridging die typically involves forming conductive pads on the back side of the bridging die, which increases the height of the embedded bridging die and the complexity of the bridging die or assembly.

[0015] In contrast, microelectronic assemblies with decomposed components and "TSV-free" components, according to the examples described herein, can achieve a lower-cost decomposed architecture. In one example, a die (e.g., a bridging die or other passive or active die) can be attached to the back side of an interposer (e.g., between the interposer and the substrate coupled to the interposer). The die can be TSV-free in the sense that it may lack vias extending through the die (e.g., from one side of the die to the opposite side of the die, and / or through the body of the semiconductor substrate of the die). However, as used herein, a TSV-free die may include vias that interconnect layers within the die and / or interconnect the layer containing the die with contacts on one side of the die. Thus, in one example, the conductive contacts on the die (e.g., on one side of the die) are confined to the side of the die facing the interposer.

[0016] In one example, the die may be located in a bump field, for example, in the same layer or plane as conductive bumps or other interconnects that couple the interposer to the package substrate. In one example, the die may be embedded in the substrate. In one example, the assembly may include multiple dies coupled to the back side of the interposer via conductive bumps or other interconnects coplanar between the dies. In such an example, a bridging die or other die may be “split” across two or more dies, allowing space for conductive bumps or other interconnects to pass between adjacent split dies. In some examples, the die may have at least one side exposed to air (e.g., air gaps or voids may exist between the die and the substrate, between the die and the interposer, and / or on the side of the die). Exposure of the back side of the die in the bump field allows for flexible thermodynamic solutions for such dies. In some examples, an underfill material may exist between the die and the interposer and / or between the die and the substrate.

[0017] In another example, the disassembled TSV-free component can be embedded in the interposer. In one such example, the microelectronic component may include dies between redistribution layers (RDLs) of the interposer, and conductive vias may exist between the dies and be coplanar with the dies. Using the space between and / or around the dies embedded or attached to the back side of the interposer for conductive bumps and / or vias can reduce assembly complexity and cost.

[0018] An IC assembly having the components described herein can be implemented in one or more components associated with the IC and / or among various such components. In various embodiments, components associated with the IC include, for example, transistors, diodes, power supplies, resistors, capacitors, inductors, sensors, transceivers, receivers, antennas, etc. Components associated with the IC can include components mounted on the IC or components connected to the IC. Depending on the components associated with the IC, the IC can be analog or digital and can be used in many applications, such as microprocessors, optoelectronics, logic blocks, audio amplifiers, etc. In some embodiments, the IC structure described herein can be included in a radio frequency IC (RFIC), which can be included, for example, in any component associated with an IC of an RF receiver, RF transmitter, or RF transceiver, as used in telecommunications components within a base station (BS) or user equipment (UE). Such components can include, but are not limited to, power amplifiers, low-noise amplifiers, RF filters (including RF filter arrays or RF filter banks), switches, upconverters, downconverters, and duplexers. In some embodiments, the IC structure described herein can be included in a memory device or circuitry. In some embodiments, the IC structure described herein may be part of a chipset for performing one or more related functions in a computer.

[0019] For illustrative purposes, specific quantities, materials, and configurations are set forth to provide a thorough understanding of exemplary embodiments. However, it will be apparent to those skilled in the art that this disclosure may be practiced without specific details, or / and may be practiced using only some of the described aspects. In other instances, well-known features have been omitted or simplified to avoid obscuring exemplary embodiments. Based on the context of the specific values ​​described herein or common knowledge known in the art, the terms “substantially,” “close to,” “approximately,” “about,” and “approximately” generally refer to within + / -10% of the target value, for example, within + / -5% of the target value. Similarly, based on the context of the specific values ​​described herein or common knowledge known in the art, terms indicating the orientation of various elements or any other angle between elements, such as “coplanar,” “perpendicular,” “orthogonal,” “parallel,” etc., generally refer to within + / -10% of the target value, for example, within + / -5% of the target value.

[0020] In the following description, reference is made to the accompanying drawings, which form a part of this document, and embodiments that may be implemented are illustrated by way of example in the drawings. It should be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope of this disclosure. Therefore, the following detailed description is not restrictive.

[0021] In the accompanying drawings, while some schematic diagrams of exemplary structures of the various devices and components described herein may be shown with precise right angles and straight lines, this is merely for illustrative purposes, and embodiments of these components may be curved, circular, or otherwise irregularly shaped as prescribed by the manufacturing processes used to manufacture semiconductor device components, and sometimes unavoidably due to the manufacturing processes used to manufacture semiconductor device components. Therefore, it should be understood that such schematic diagrams may not reflect real-world process limitations, which could result in features appearing less “ideal” when examined using, for example, scanning electron microscopy (SEM) or transmission electron microscopy (TEM) images. In such images of real structures, possible manufacturing defects would also be visible, such as imperfectly straight edges of the material, tapered vias or other openings, unintentional rounding of corners or variations in the thickness of different material layers, accidental spiral dislocations within crystalline regions, edge dislocations or combinations of dislocations, and / or accidental dislocation defects of individual atoms or clusters of atoms. Other defects not listed herein but common in the field of device manufacturing may also be present. Using methods such as optical microscopy, TEM, or SEM to examine layout and mask data, and to reverse engineer parts of the device to reconstruct the circuit, and / or using methods such as physical failure analysis (PFA) to examine cross-sections of the device to detect the shape and location of the various device elements described herein, allows the determination of the presence of microelectronic components with disassembled parts as described herein.

[0022] Various operations can be described sequentially as a plurality of discrete actions or operations in a manner most conducive to understanding the claimed subject matter. However, the order of description should not be construed as implying that these operations must depend on the order. These operations may not be performed in the presented order. The described operations may be performed in an order different from that described in the embodiments. In additional embodiments, various additional operations may be performed and / or the described operations may be omitted.

[0023] For the purposes of this disclosure, the phrase "A and / or B" refers to (A), (B), or (A and B). For the purposes of this disclosure, the phrase "A, B, and / or C" refers to (A), (B), (C), (A and B), (A and C), (B and C), or (A, B, and C). When used with reference to a measurement range, the term "between" includes the endpoints of the measurement range.

[0024] The phrases “in one embodiment” or “in multiple embodiments” used in the description may each refer to one or more of the same or different embodiments. The terms “comprising,” “including,” “having,” etc., used with respect to embodiments of this disclosure are synonymous. This disclosure may use perspective-based descriptions such as “above,” “below,” “top,” “bottom,” and “side”; such descriptions are for ease of discussion and are not intended to limit the application of the disclosed embodiments. The drawings are not necessarily drawn to scale. Unless otherwise stated, ordinal adjectives such as “first,” “second,” and “third” are used to describe common objects only to indicate different instances of similar objects being referenced and are not intended to imply that objects so described must be in a given sequence in time, space, rating, or any other way. Although some materials may be described in the singular, such materials may include multiple materials; for example, semiconductor materials may include two or more different semiconductor materials.

[0025] exist Figure 1A-Figure 1B , Figures 2-7 , Figures 8A-8B , Figures 9-13 , Figures 14A-14B and Figures 15A-15C The description refers to several elements marked with reference numerals, which are shown in different patterns in these figures, wherein the elements include Figure 1A-Figure 1B , Figures 2-7 , Figures 8A-8B , Figures 9-13 , Figures 14A-14B and Figures 15A-15C At the bottom of each page of figures is a legend illustrating the correspondence between the reference numerals and the figures. For example, the legend explains... Figure 1A-Figure 1B Different patterns are used to represent conductive pads 226 and conductive bumps 228, etc.

[0026] Figure 1A-Figure 1B Different cross-sectional views of examples of microelectronic components 100 having disassembled parts according to some embodiments of the present disclosure are shown. Figure 1A It shows Figure 1A-Figure 1B In the xz plane of the exemplary coordinate system shown, along Figure 1B The cross-section shown is the cross section cut by plane AA. Figure 1B It shows Figure 1A-Figure 1B In the exemplary coordinate system shown, along the xy plane Figure 1A The cross-section shown is the cross section cut by plane BB.

[0027] Figure 1AA cross-sectional side view of a microelectronic component 100 is shown. The microelectronic component 100 includes a substrate 201 having a first side or first surface 111-1 (e.g., a top side or front side) and a second side or second surface 111-2 opposite to the first surface 111-1 (e.g., a bottom side or back side). The substrate 201 may be, for example, a package substrate. The substrate 201 may include an insulating material (e.g., a dielectric material formed in multiple layers, as known in the art) and one or more conductive paths (e.g., including conductive traces and / or conductive vias) to route power, ground, and signals through the dielectric material. In some instances, the substrate 201 may include a substrate core having multiple layers located above and below the substrate core. In other instances, the substrate 201 may be coreless (e.g., lacking a core of a different material). The following discusses… Figures 15A-15C An example of a substrate is illustrated. In some embodiments, the insulating material of substrate 201 may be a dielectric material, such as an organic dielectric material, a flame retardant grade 4 material (FR-4), a bismaleimide triazine (BT) resin, a polyimide material, a glass-reinforced epoxy material, an organic dielectric material with inorganic fillers, or a low-k and ultra-low-k dielectric (e.g., a carbon-doped dielectric, a fluorine-doped dielectric, a porous dielectric, and an organic polymer dielectric). In particular, when substrate 201 is formed using standard printed circuit board (PCB) processes, substrate 201 may include FR-4, and conductive paths in substrate 201 may be formed by patterned copper sheets separated by stacked layers of FR-4. In some embodiments, substrate 201 may be formed using a photolithographically defined through-hole packaging process. In some embodiments, substrate 201 may be manufactured using standard organic packaging manufacturing processes, and therefore substrate 201 may take the form of an organic substrate. In some embodiments, substrate 201 may be a set of redistribution layers formed on a panel carrier by laminating or spinning on a dielectric material and creating conductive vias and lines by laser drilling and electroplating. In some embodiments, the substrate 201 may be formed on the removable carrier using any suitable technique (e.g., redistribution layer technique). Any method known in the art for manufacturing the substrate 201 may be used, and for the sake of brevity, such methods will not be discussed in further detail herein.

[0028] Conductive contacts 226-1 on surface 111-1 of substrate 201 may be coupled to conductive bumps 228-1, which may be coupled to a circuit board (e.g., a motherboard or other circuit board or interconnect structure). As used herein, “conductive contact” may refer to a portion of a conductive material (e.g., a metal) that serves as an electrical interface between different components (e.g., a portion of a conductive interconnect); conductive contacts may be recessed into the surface of a component, flush with the surface of a component, or extend from the surface of a component (e.g., having a columnar shape), and may take any suitable form (e.g., a conductive pad or socket, or a portion of a conductive line or through-hole). In a general sense, “interconnect” refers to any element that provides a physical connection between two other elements. For example, an electrical interconnect provides an electrical connection between two electrical components, thereby facilitating the communication of electrical signals between the electrical components. Therefore, when used with reference to an electronic device, for example, an IC that operates using electrical signals, the term “interconnect” describes any element formed of conductive material for providing an electrical connection to one or more components associated with the IC and / or between various such components. In this context, the term "interconnect" can refer to both electrical traces (sometimes also called "metallic traces," "lines," "metallic wires," "conductors," "metallic wires," "grooves," or "metallic trenches") and conductive vias (sometimes also called "vias" or "metallic vias"). Sometimes, conductive traces and vias can be referred to as "metallic traces" and "metallic vias," respectively, to highlight the fact that these components comprise conductive materials such as metals.

[0029] An interface with conductive bumps 228 may include multiple coplanar bumps between two bonded IC structures (e.g., between two dies, between a die and an interposer, between an interposer and a package substrate, etc.). Conductive bumps 228 are typically coupled to conductive elements, such as conductive pads 226. In some instances, taller conductive bumps 228 (e.g., conductive bumps with a height greater than their width) and / or conductive bumps 228 exhibiting a generally cylindrical cross-sectional shape with relatively flat sides (as opposed to rounded protruding sides) may be referred to as conductive pillars. In some instances, bumps may be arranged in an array, such as in a ball grid array (BGA) assembly. Conductive bumps can be formed in various shapes (e.g., spherical / circular, cylindrical, etc.) and these conductive bumps can be deformed after bonding. Conductive bumps include conductive materials (e.g., one or more metals), such as solder, copper, gold, or other suitable conductive materials. Conductive bumps including solder can include any suitable solder material, such as lead / tin, tin / bismuth, eutectic tin / silver, ternary tin / silver / copper, eutectic tin / copper, tin / nickel / copper, tin / bismuth / copper, tin / indium / copper, tin / zinc / indium / bismuth, or other alloys. In some instances, conductive bumps such as conductive pillars can include metals such as copper and can be covered by solder caps. Therefore, in some instances, the interconnect can include a first conductive portion (e.g., a metal bump or metal pillar) and a second conductive portion (e.g., a solder cap). In some instances, conductive bump 228 is surrounded by an insulating material (sometimes referred to as filler or underfill material) that is in the same plane as the conductive bump; however, in Figure 1A The underfill material surrounding the conductive bump 228-1 is not shown. The underfill material can be provided by any suitable method (e.g., deposited before or after bump formation), and this underfill material can provide mechanical support to the interface layer having the conductive bump 228. The underfill material can be any suitable insulating material, such as silicon oxide, silicon carbide, silicon oxynitride, carbon-doped silicon oxide, spin-coated glass, boron-doped silicon oxide, organic polymers, carbon, carbon polymers, or any other suitable insulating material.

[0030] Component 100 further includes an interposer layer 202 having a first surface 112-1 (e.g., bottom or back side) and a second surface 112-2 (e.g., top or front side) opposite to the first surface 112-1. Surface 112-1 of the interposer layer 202 may also be referred to as the encapsulation side. Figure 1A In the example shown, the interposer 202 is coupled to the substrate 201 via a plurality of conductive bumps 228-2, which are located between conductive contacts 226-2 on surface 111-2 of the substrate 201 and conductive contacts 226-3 on surface 112-1 of the interposer 202. Interposers are typically intermediate structures in microelectronic components that allow IC structures to be electrically coupled to each other. For example, as can be... Figure 1A As seen in the cross-sectional side view, the interposer 202 facilitates coupling IC dies 204-1, 204-2, and 204-3 to each other and / or to the substrate 201. The interposer 202 may include one or more layers of dielectric material 220 and conductive interconnects 231 (e.g., conductive lines and vias) within the dielectric material. Such a layer (e.g., a layer of dielectric material 220 with conductive interconnects 231) may be referred to as RDL 221. Although... Figure 1A Interposer 202 is shown as having three RDLs 221; however, the interposer may have fewer (e.g., one or two RDLs) or more (e.g., four, five, six, or more than six RDLs). The dielectric material 220 of interposer 202 may include silicon (e.g., in the case of a silicon-based interposer), an organic dielectric material (e.g., in the case of an organic interposer), or both a silicon-based dielectric material and an organic dielectric material. Examples of silicon-based dielectric materials that may be included in one or more layers of interposer 202 include silicon and one or more of oxygen and nitrogen (e.g., silicon oxide, silicon nitride, or silicon oxynitride). Examples of organic dielectric materials that may be included in one or more layers of interposer 202 include flame retardant grade 4 materials (FR-4), BT resins, polyimide materials, glass-reinforced epoxy materials, organic dielectrics with inorganic fillers, or low-k and ultra-low-k dielectrics (e.g., carbon-doped dielectrics, fluorine-doped dielectrics, porous dielectrics, and organic polymer dielectrics).

[0031] exist Figure 1AIn the example shown, dies 204-1, 204-2, and 204-3 are coupled to facet 112-2 of interposer 202 via conductive bumps 228-3, which are located between conductive contacts 226-4 on facet 112-2 of interposer 202 and conductive contacts 226-5 on the bottom side of dies 204-1, 204-2, and 204-3. Dies 204-1, 204-2, and 204-3 can be, for example, discrete IC structures, which may be referred to as chiplets, and these chiplets can be packaged together. Typically, different chiplets in an IC device or IC system may include logic for providing specific functions (e.g., computing, memory, and I / O) in the IC device or IC system. For example, an IC device may include one or more computing chiplets, memory chiplets, cache chiplets, accelerator chiplets, etc. The terms IC die, die, chiplet, chip, and microelectronic component are used interchangeably. For example, a computing chiplet can also be referred to as a computing die. In one instance, a computing chiplet may include one or more processor cores and / or other computing logic. In one instance, a computing chiplet including one or more processor cores may be referred to as a processor chiplet or a processor die. A memory chiplet may include one or more memory arrays (e.g., dynamic random access memory (DRAM) and / or static random access memory (SRAM) arrays). A cache chiplet may include one or more memory arrays (e.g., SRAM arrays or other low-latency memories). A chiplet may have more than one type of device; for example, a computing chiplet may also include one or more memory arrays, and a memory chiplet may include computing logic. Dies 204-1, 204-2, and 204-3 may be dies that include power-consuming electrical load circuitry. The underfill material 229 may at least partially surround the conductive bumps 228-3. Figure 1A As shown, molding material 222 may at least partially surround dies 204-1, 204-2, and 204-3, and may be disposed on the underfill material 229. Molding material 222 may be any material known to be suitable for overlaying molded IC packages, such as epoxy, silicone, compounds thereof, or any other suitable molding compound. In other instances, molding material 222 may not be present above or around dies 204-1, 204-2, and 204-3.

[0032] The microelectronic assembly 100 also includes dies on the back side (e.g., face 112-1) of the interposer 202. For example, dies 206-1 and 206-2 are coupled to face 112-1 of the interposer 202 via conductive bumps 228-4, which are located between conductive contacts 226-6 on dies 206-1 and 206-2 and conductive contacts 226-7 on face 112-1 of the interposer 202. Dies 206-1 and 206-2 can be active or passive dies. For example, one or both of dies 206-1 and 206-2 can be passive interconnect or bridging dies, which include interconnects between dies 204-1, 204-2 and / or 204-3 coupled to the front side of the interposer 202. In some instances, active interconnect or bridging dies may include one or more transistors (e.g., transistors configured as switches) to enable signal routing configuration on the die. In some instances, one or both of dies 206-1 and 206-2 include one or more capacitors (e.g., capacitors for voltage regulation circuitry, high-frequency noise suppression, and / or power supply voltage stabilization). In some instances, one or both of dies 206-1 and 206-2 contain memory (e.g., SRAM or DRAM). In some instances, dies 206-1 and 206-2 may be two “split” dies (e.g., a split bridging die or a split die with capacitors), wherein the functionality of the bridging die or the die with capacitors is split across both dies 206-1 and 206-2. In one such example, the split dies allow interconnects to be placed between the split dies to couple one of dies 204-1, 204-2, and 204-3 to substrate 201 without relying on TSVs through dies 206-1 and 206-2. Thus, in some examples, dies 206-1 and 206-2 lack TSVs extending throughout the entire die, and the conductive contacts on dies 206-1 and 206-2 are confined to the side of the die facing the bottom of interposer 202 (e.g., face 112-1 of interposer 202). Although both dies 206-1 and 206-2 are shown attached to the back side of interposer 202, other components may include a single die coupled to the back side of interposer 202 in a bump field, or more than two dies coupled to the back side of interposer 202 in a bump field.

[0033] Conductive bumps and contacts between different components of the microelectronic assembly 100 may have different spacing and / or width. The width of a conductive bump or contact is its dimension in a plane substantially parallel to the substrate 201 or the interposer 202. The spacing of conductive contacts is a measure of the distance between the approximate center of one contact and the approximate center of an adjacent contact. Similarly, the spacing of conductive bumps is a measure of the distance between the approximate center of one bump and the approximate center of an adjacent bump. Figure 1AIn the illustrated example, the conductive bumps 228-1 and corresponding conductive contacts 226-1 at the bottom of substrate 201 have maximum width and spacing (relative to the conductive bumps and contacts between substrate 201 and interposer 202, and between interposer 202 and dies 206-1, 206-2, 204-1, 204-2, and 204-3). In one example, the width of the conductive bumps 228-1 can range from approximately 200 micrometers to 600 micrometers. In other examples, the conductive bumps may not be present at the bottom of substrate 201 (e.g., when component 100 is inserted into a socket instead of being bonded to the underlying substrate or circuit board with solder balls).

[0034] The width and spacing of the conductive bumps 228-2 and conductive contacts 226-2 and 226-3 between the substrate 201 and the interposer 202 can be smaller than the width and spacing of the conductive bumps 228-1 and conductive contacts 226-1 at the bottom of the substrate 201. However, in some embodiments, the conductive contacts 226-3 disposed on the interposer 202 and coupled to the substrate have a larger width and spacing than the conductive contacts 226-7 and 226-4 coupled to the dies 206-1 and 206-2 and the dies 204-1, 204-2 and 204-3. In one embodiment, the conductive bumps 228-2 have a width in the range of about 40 micrometers to 120 micrometers, about 50 micrometers to 75 micrometers, or about 50 micrometers to 60 micrometers. In one embodiment, the width of the conductive bumps 228-4 between the back side of the interposer 202 and the dies 206-1 and 206-2 can be in the range of about 20 micrometers to 50 micrometers. In one such example, the spacing of the conductive bumps can range from approximately 40 micrometers to 110 micrometers. Therefore, in some examples, the bottom side of the interposer 202 can have relatively wide conductive contacts 226-3 for coupling with larger conductive bumps 228-2 between the dies 206-1 and 206-2 and the interposer 202, and relatively narrow conductive contacts 226-7 for coupling with smaller conductive bumps 228-4. In one such example, the spacing of the conductive bumps 228-2 is greater than the spacing of the conductive bumps 228-4 and 228-3.

[0035] As in Figure 1AAs can be seen, dies 206-1 and 206-2 are situated within a “bump field” comprising conductive bumps 228-2 between the interposer 202 and the substrate 201. As used herein, the term bump field can refer to a region in the same layer as conductive bumps and / or conductive pillars (e.g., an array of conductive bumps). For example, dies 206-1 and 206-2 are coupled to the interposer 202 via conductive contacts 226-7 and 226-6 and conductive bump 228-4, and are situated in the same layer and / or plane as conductive bump 228-2. Therefore, conductive dies 206-1 and 206-2 can be considered to be situated within a bump field of conductive bump 228-2. In some instances, one or both of dies 206-1 and 206-2 may be defined by conductive bumps between conductive bumps (e.g., between two adjacent bumps 228-2) or on two or more sides. For example, Figure 1B It shows along Figure 1A The cross-section of plane BB in the xy plane is shown.

[0036] Figure 1B A bump array 238 is depicted, wherein dies 206-1 and 206-2 are in the same layer as the bump array 238. Figure 1B In the example shown, dies 206-1 and 206-2 are surrounded by conductive bumps in plane BB. For example, die 206-1 has four sides, with a first conductive bump 228-21 adjacent to the first side, a second conductive bump 228-22 adjacent to the second side, a third conductive bump 228-23 adjacent to the third side, and a fourth conductive bump 228-24 adjacent to the fourth side. Thus, die 206-1 is along an axis (e.g., as shown in the figure). Figure 1B The y-axis shown is located between conductive bumps 228-1 and 228-2, and along another axis (e.g., as shown) Figure 1B The x-axis shown is located between conductive bumps 228-23 and 228-24. In some instances, such as... Figure 1B As shown, multiple dies can exist in a conductive bump field. Figure 1B In the example shown, the microelectronic component 100 includes two dies 206-1 and 206-2 (e.g., two coplanar dies) in the same layer as the conductive bump array 238. In one such example, one or more of the conductive bumps 228-2 are located between die 206-1 and the second die 206-2.

[0037] Refer again Figure 1AThe dies 206-1 and 206-2 of the microelectronic component 100 are exposed (e.g., exposed to air) on all sides of dies 206-1 and 206-2. For example, there is no underfill material between the face 112-1 of the interposer 202 in the plane having conductive bumps 228-4 and the die 206-1, between the die 206-1 and the substrate 201, and between the side of the die 206-1 and the adjacent conductive bumps 228-2. In one such example, due to the lack of underfill material, the component 100 includes air gaps located between the die 206-1 and the face 112-1 of the interposer 202, between the die 206-1 and the substrate 201 (e.g., as shown by air gap 235), and between the die 206-1 and the adjacent conductive bumps 228-2. In one example, the air gap may be a region that is substantially free of solid material. The air gap may include minimal material or no material at all, or it may be filled with a gaseous substance, such as air, nitrogen, and / or different gases. The air gap may also be referred to as a void. In other instances, insulating material (e.g., underfill material and / or molding compound) may be present on one or more sides of the dies 206-1 and 206-2.

[0038] For example, Figure 2 An exemplary microelectronic assembly 200 is illustrated, comprising an underfill material 240 located between the bottom side (e.g., face 112-1) of an interposer 202 and dies 206-1 and 206-2. In one such example, the underfill material 240 may be confined to the region between face 112-1 of the interposer 202 and dies 206-1 and 206-2 in a plane having conductive bumps 228-4, and may not be present around and between adjacent conductive contacts 226-2 and 226-3, nor around and between adjacent conductive bumps 228-2. In one such example, the underfill material 240 may provide structural support for solder joints formed by the conductive bumps 228-4 (e.g., during downstream processes that may involve heating the assembly 200). The underfill material 240 may be the same as or different from underfill material 229.

[0039] Dies attached to the bottom side of the interposer can be arranged to achieve desired interconnect placements (e.g., the location of conductive bump 228-2, the location of an interconnect between a die attached to the back side of the interposer and a die attached to the front side of the interposer, or other interconnect locations). In some instances, the die attached to the back side of the interposer can be below and aligned (e.g., substantially aligned) with one of the dies attached to the front side of the interposer. For example, Figure 3An example is shown where a die 207 of a microelectronic component 300 attached to face 112-1 of interposer 202 is aligned with a die 204-1 attached to face 112-2 of interposer 202. In one such example, the die 207, attached to the back side of interposer 202 and aligned with the die 204-1 attached to the front side of interposer 202, may be a die having circuitry directly supporting the die 204-1 attached to the front side of interposer 202. For example, die 204-1 may include computational logic (e.g., a processor core, graphics processor, and / or other computational logic), and die 207 may include one or more capacitors (e.g., decoupling capacitors), voltage regulator circuitry, power integrity circuitry, or other circuitry for die 204-1. Figure 3 As shown, in some instances where die 207 includes a capacitor, the height or thickness 330 of die 207 can be larger (e.g., greater than the thickness of a die without a capacitor) and can occupy a large portion of the height of the bump field. In one instance, the height or thickness 330 of die 207 can range from about 15 to 80 micrometers or from about 40 to 60 micrometers, wherein the thickness 330 is the height of the die in a plane substantially orthogonal to the substrate 201 (e.g., along such a plane). Figure 3 The dimensions are shown on the z-axis. In an example where die 207 includes a capacitor, any suitable capacitor may be included in die 207 (e.g., metal-insulator-metal (MIM) capacitors, film capacitors, and / or any other type of capacitor). In an example where die 204-1 is or includes a processor (e.g., a central processing unit (CPU), graphics processing unit (GPU), neural processing unit (NPU), or other processor), die 207 may include memory coupled to die 204-1. For example, die 207 may include a memory array such as SRAM or DRAM to provide cache and / or system memory to die 204-1.

[0040] In some instances, dies with different heights can be located in a bump field between the interposer 202 and the substrate 201. For example, Figure 4 An example of a microelectronic assembly 400 is shown, comprising a die 207 having a first thickness 330 mm and a die 206-2 having a second thickness 440 mm, wherein the thickness 440 mm of die 206-2 is less than the thickness 330 mm of die 207 (i.e., the thickness 330 mm is greater than the thickness 440 mm). In one such example, die 207 may include a capacitor, and dies 206-1 and 206-2 may be, for example, bridge dies, memory dies, or other dies. Thus, in some examples, dies 207, 206-1, and / or 206-2 may be different types of dies (e.g., dies including different circuits). In other examples, dies 207, 206-1, and 206-2 may have approximately the same thickness.

[0041] Figure 5 Another example of a microelectronic component 500 with a die located in a bump field between an interposer and a substrate is shown. The microelectronic component 500 is similar to... Figure 4 The microelectronic component 400 shown differs in that the bottom filler material 229 surrounds both the dies 206-1, 206-2, and 207, and the conductive bumps 228-2. (As shown in...) Figure 5 As can be seen in the example shown, the same underfill material 229 is located between the dies 206-1, 206-2, and 207 and the interposer 202, and between the dies 206-1, 206-2, and 207 and the substrate 201. In one example, the thermally conductive underfill material can be used to facilitate heat transfer from the dies 206-1, 206-2, and 207. Figure 5 Examples are shown where the same underfill material 229 is disposed between the interposer and the substrate and between the interposer and the dies 204-1, 204-2 and 204-3; however, in other examples, different underfill materials may be used in the bump fields around conductive bump 228-2 and around conductive bump 228-3.

[0042] therefore, Figure 1A-Figure 1B and Figures 2-5 An example is shown where dies 206-1, 206-2, and 207 are coplanar with conductive bump 228-2. One challenge in assembling dies in the field of bumps is that large conductive bumps may be required to accommodate die thickness. For example, if dies 206-1 and 206-2 or 207 have a thickness of approximately 50 micrometers, conductive bumps of approximately 150 micrometers may be used to ensure sufficient space for the die. Large conductive bumps can limit the number of interconnects that can be formed between the interposer 202 and the substrate 201. In one example, to address the challenges associated with large conductive bumps between the interposer 202 and the substrate 201, the assembly may include conductive pillars coplanar with dies 206-1, 206-2, and 207, having a width narrower than conductive bump 228-2.

[0043] For example, Figure 6 An exemplary microelectronic component 600 is shown, which includes conductive vias or conductive pillars 630 extending between an interposer 202 and a substrate 201 and coplanar with dies 206-1, 206-2, and 207. Figure 6 In the example shown, the conductive post 630 is coupled to the conductive contact 226-9 on the back side of the interposer 202. In such an example, for example... Figure 6As shown, conductive contacts 226-9 may be in the dielectric material (e.g., recessed in the interposer 202). In one such example, smaller conductive bumps 228-8 may be disposed between the conductive post 630 and the conductive contacts 226-8 on the substrate 201. In one example, the conductive post 630 may comprise any suitable conductive material, such as copper (Cu), aluminum (Al), tungsten (W), or cobalt (Co), and / or any other suitable conductive material. The conductive bumps may be, for example, solder balls. Figure 6 In the example shown, molding material 222 surrounds dies 206-1, 206-2, and 207, as well as conductive posts 630. Therefore, in Figure 6 In the illustrated example, there is a dielectric material (e.g., molding material 222) at least partially surrounding dies 206-1, 206-2, and 207, and conductive posts 630 extend through the dielectric material and are coupled to one of the conductive bumps 228-8 on one side and to conductive interconnects of the interposer 202 (e.g., conductive contacts 226-9 or other conductive interconnects in RDL 221), wherein dies 206-1, 206-2, and 207 are in the same plane as the conductive posts 630. In one such example, molding material may not be present on the face or side of one or more of dies 206-1, 206-2, and 207 facing the substrate 201 (e.g., in...). Figure 6 An air gap may exist between the die 207 and the substrate 201 shown.

[0044] Figure 7 Another example of a microelectronic assembly 700 is shown, comprising conductive pillars extending between an interposer 202 and a substrate 201 and coplanar with dies 206-1, 206-2 and 207. Figure 7 The microelectronic component 700 shown is similar to Figure 6 The microelectronic component 600 shown differs in that an underfill material 229 is present between adjacent bumps 228-8 and between the molding material 222 and the substrate 201 (e.g., between dies 206-1, 206-2, and 207 and the substrate 201, and between a portion of the molding material 222 and the substrate 201). In one such example, the molding material 222 is a first dielectric material, and the underfill material 229 is a second dielectric material having a different material composition than the first dielectric material. In other examples, the molding material 222 and the underfill material 229 may have similar or identical material compositions.

[0045] therefore, Figure 1A-Figure 1B and Figures 2-7An example of a microelectronic assembly with a split die is shown, which is coupled to the back side of an interposer located above and coupled to a substrate. In one such example, conductive interconnects (e.g., bumps and / or pillars) are interposed between and coupled to the substrate and the interposer. One or more first dies are located above and coupled to a first side (e.g., the front side) of the interposer, and one or more second dies are located below and coupled to a second side (e.g., the back side) of the interposer opposite to the first side. In one such example, the second dies are located between the substrate and the interposer and are coplanar with the conductive interconnects. In one example, the second die is TSV-free, for example, the conductive contacts on the second die are confined to the side of the second die facing the second side (e.g., the back side) of the interposer (e.g., one or more of the second dies may lack vias extending from the first side of the die to the second side of the die).

[0046] Figures 8A-8B A different cross-sectional view is shown of another example of a microelectronic assembly with disassembled components according to some embodiments of the present disclosure. Figure 8A It shows along Figure 8B The plane AA shown is in Figures 8A-8B The cross section in the xy plane of the exemplary coordinate system shown. Figure 8B It shows along Figure 8A The plane BB shown is in Figures 8A-8B The cross section in the xz plane of the exemplary coordinate system shown.

[0047] First go to Figure 8A The microelectronic component 800 includes dies 807 and 806 embedded in an interposer. In one example, the die may be embedded in the interposer if it is located between a first dielectric material layer (e.g., a first RDL) and a second dielectric material layer (e.g., a second RDL). For example, as discussed below... Figure 8B An interposer layer 802 with RDLs 821 and 822 is shown. In one such example, a different insulating material, such as a molding compound, may at least partially surround the embedded die between the RDLs of the interposer layer. For example, in Figure 8A In the perspective view shown, dies 806 and 807, located between dielectric material layers of the interposer (e.g., between RDLs), are at least partially surrounded by molding material 222. IC dies may be attached to the interposer (e.g., above the top or front side of the interposer). For example, IC dies 804-1 and 804-2 (located in...) Figure 8A (Shown in dashed box) It is positioned above and coupled to the interposer. Dies 804-1 and 804-2 can be instances of dies 204-1, 204-2 and 204-3 discussed above.

[0048] exist Figures 8A-8B In the examples shown, some of the embedded dies are split components distributed across multiple embedded dies. For example, dies 806-1 and 806-2 could be two separate dies used to implement bridging dies. Similarly, dies 807-1 and 807-2 could be two separate dies including capacitors. Distributing the circuit across multiple smaller embedded dies allows for additional areas for setting conductive vias through the interposer. Figure 8A In the illustrated example, conductive vias or conductive posts 630 are located between and coplanar with adjacent dies 806-1 and 806-2, and between and coplanar with adjacent dies 807-1 and 807-2. In some examples, dies 806-1, 806-2, 807-1, and 807-2 may have conductive posts 630 adjacent to two or more sides of the die. For example, die 807-2 has conductive posts 630 adjacent to all four sides of die 807-2. In contrast, die 807-3 represents a die having a capacitor that is not split across multiple dies.

[0049] Figure 8B A cross-sectional side view of a microelectronic component 800 including an interposer 802 is shown. The interposer 802 has a first side or first surface 812-1 (e.g., a bottom side or a back side) and a second side or second surface 812-2 opposite to surface 812-1 (e.g., a top side or a front side). In one example, the interposer 802 may include conductive contacts 826-1 disposed on surface 812-1, wherein the conductive contacts 826-1 are coupled to conductive bumps 828-1. The conductive bumps 828-1 may be coupled to conductive contacts on another substrate or circuit board (e.g., substrate 201 as described above). In another example, the interposer 802 may be coupled to another substrate or circuit board via a socket. Figure 8B As can be seen, dies 804-1 and 804-2 are disposed on the interposer layer 802 and coupled to the interposer layer 802 via conductive bumps 228-9 between conductive pads 226. Underfill material 229 at least partially surrounds the conductive bumps 228-9, and molding material 222 at least partially surrounds dies 804-1 and 804-2 and is disposed on the underfill material 229.

[0050] exist Figure 8BIn the example shown, dies 807-1, 807-2, and 806-2 are located between RDLs of interposer 802 (e.g., between one of RDLs 821 and RDL 822). Dies 807-1, 807-2, and 806-2 are coupled to interconnects in RDL 821 located on / above dies 807-1, 807-2, and 806-2 via conductive bumps 228-10 between conductive pads 226. Molding material 222 at least partially surrounds dies 807-1, 807-2, and 806-2 and is located between dies 807-1, 807-2, and 806-2. In some instances, dies 807-1, 807-2, and 806-2 are TSV-free in the sense that they lack a through-hole extending completely through the die from one side to the opposite side. For example, the electrical interconnect / signal paths between dies 807-1, 807-2, and 806-2 and the interposer 802 are confined to the region between dies 807-1, 807-2, and 806-2 and the RDL 821 of the interposer 802 (e.g., there is no electrical / signal interconnect between the bottom of dies 807-1, 807-2, and 806-2 and the bottom RDL 822 of the interposer). Figure 8B In the examples shown, adhesive material 811 (e.g., die attachment film) or other materials may be present between dies 807-1, 807-2, and 806-2 and RDL 822. Although Figure 8B The example shown illustrates that the molding material is not present between dies 807-1, 807-2, and 806-2 and RDL 822; however, in other examples, the region between dies 807-1, 807-2, and 806-2 and RDL 822 may include a continuous portion of the molding material 811. In one such example, there is no conductive interconnect (e.g., conductive via) between dies 807-1, 807-2, and 806-2 and RDL 822.

[0051] therefore, Figures 8A-8B Another example of a microelectronic component 800 is shown, which may include dies located beneath an interposer, wherein the dies lack conductive vias that extend fully through the die. In some instances, the component may include multiple dies (e.g., multiple interconnect / bridging dies, multiple dies with capacitors, etc.) embedded between RDLs, wherein conductive interconnects (e.g., bumps and / or pillars) are coplanar with adjacent embedded dies and between adjacent embedded dies.

[0052] Figure 9 A cross-sectional side view of another example of a microelectronic assembly 900 with disassembled components is shown. Figure 6 The microelectronic component 600 shown and Figure 7 Similar to the microelectronic component 700 shown, in Figure 9 In the microelectronic component 900 shown, die 906 is attached to the back side of interposer 902 in the bump field of conductive pillars 630 between interposer 902 and substrate 201. As described above, die 906 can be an example of die 206-1, 206-2, 207, and interposer 902 can be an example of interposer 202. Figure 6 The microelectronic component 600 shown and Figure 7 The microelectronic component 700 shown is... Figure 9 One difference between the microelectronic components 900 shown is that, Figure 9 The die 906 is coupled to the face 112-1 of the interposer 902 having conductive pillars 630-1, which results in a greater height of the die 906 relative to the interposer 902 (e.g., a greater distance between the side or face 919-1 of the die 906 and the face 112-1 of the interposer). For example, as... Figure 9 As shown, the microelectronic component 900 includes a conductive post 630-1 between conductive contacts 226-12 located in the interposer 902 and conductive contacts 226-11 on the surface 919-2 of the die 906. Figure 9 In the example shown, when an interposer 902 is used (e.g., the conductive contact 226-12 is coplanar with the dielectric material of the RDL 921 of the interposer 902), the conductive contact 226-12 that contacts the conductive post 630-1 is recessed in the RDL 921. Figure 9 In the example shown, the welding cap 928-1 is located between the conductive contact 226-11 on the face 919-2 of the post 630-1 and the die 906.

[0053] like Figure 9 As shown, compared to the case where the die 906 is coupled to the face 112-1 of the interposer 902 using solder balls of the same width, the height of the die 906 relative to the face 112-1 of the interposer 902 can be greater. For example, the die 906 has a face 919-2 facing the interposer and a face 919-1 opposite to the face 919-2, and the face 919-1 is separated from the interposer 902 by a distance 943. In such an example, a high pillar 630-2 can be used to allow space for the height of the die 906, wherein the height 945 of the pillar 630-2 is greater than the distance 943. For example, the conductive pillar 630-2 has a first end coupled to a conductive contact 226-10 in the interposer 902 and a second end opposite to the first end coupled to a conductive contact 226-13 on the substrate 201. In one such example, the second end of the pillar 630-2 coupled to the substrate is at a greater distance from the interposer 902 than the distance 943 from the face 919-1 of the die 906 to the interposer 902.

[0054] Another difference between microelectronic component 900 and microelectronic components 600 and 700 is that microelectronic component 900 lacks solder balls between conductive pillars 630-2 and conductive contacts 226-13 on substrate 201; instead, conductive pillars 630-2 are covered by solder caps 928-2, which couple to conductive contacts 226-13 on substrate 201. Similar to conductive contacts 226-12, conductive contacts 226-10 that contact conductive pillars 630-2 can be recessed in the RDL 921 of interposer 902. Solder caps 928-2 contact conductive contacts on surface 111-2 of substrate 201. Microelectronic component 900 includes solder mask 910, in which conductive contacts 226-13 are located in openings within solder mask 910. The solder resist layer 910 may include any suitable solder resist material, such as epoxy-based materials, dry films, UV-curable solder resist materials, or any other suitable solder resist material.

[0055] Similar to solder balls, solder caps are portions of solder material that lie between and couple to two conductive elements. Solder caps typically differ from solder balls in shape and height or thickness. Before being heated in the reflow process to form a solder joint, solder balls typically have a rounded (e.g., circular or elliptical) cross-sectional shape. After reflow, solder balls in a solder joint may still have a relatively rounded shape (e.g., the cross-sectional shape of solder balls in a solder joint may have rounded or curved, convex sides). In other instances, the cross-sectional shape of solder balls in a solder joint may have generally flat sides. In some instances, solder caps may have a semi-circular or rectangular cross-sectional shape. The height or thickness of a solder ball is typically greater than that of a solder cap, both relative to the total height or thickness of the solder joint and relative to the thickness of the conductive contacts (e.g., pads) coupled to the solder portion. Additionally, the percentage of the cross-sectional area of ​​the solder joint as solder in a solder joint with solder balls is typically larger than in a solder joint with solder caps. For example, a solder joint including solder balls typically comprises solder balls between two conductive pads. In one such example, the solder ball can be thicker than the conductive pad, and the majority of the cross-sectional area of ​​the solder joint can be occupied by solder material. Conversely, a solder cap can be applied to the end of another conductive bump (such as a copper pillar or other conductive bump). In one such example, the height or thickness of the solder cap can be less than the height or thickness of the conductive bump. In other examples, the height or thickness of the solder cap can be approximately the same as or greater than the height of the conductive bump.

[0056] exist Figure 9In the example shown, solder caps 928-1 and 928-2 have a semi-circular cross-sectional shape and a thickness significantly smaller than the height of the corresponding conductive posts 630-1 and 630-2. For example, the thickness of conductive cap 928-2 is less than about 10% of the height of conductive post 630-2, where the thickness or height of the conductive cap is a dimension of those components in a plane substantially orthogonal to substrate 201, for example, along the z-axis. Figure 9 In the example shown, underfill material is present around conductive pillar 630-2 and conductive pillar 630-1. For example, microelectronic component 900 includes underfill material 240 between die 906 and interposer 902 and at least partially surrounding conductive pillar 630-1, and underfill material 229 between interposer 902 and substrate 201 and at least partially surrounding conductive pillar 630-2. Underfill material 240 and underfill material 229 may have the same material composition or different material compositions. For example, underfill material 240 may include a material with a higher viscosity than underfill material 229.

[0057] therefore, Figure 9 An exemplary microelectronic component 900 is shown, having conductive pillars located between and coupled to both a die 906 and an interposer 902, and highly conductive pillars 630-2 located between and coupled to both the interposer 902 and a substrate 201. In one such example, the die (e.g., face 919-1 of die 906) may be spaced from the substrate 201 by approximately 5 to 20 micrometers. Although Figure 9 An example is shown in which conductive post 630-1 has a narrower width and spacing than conductive post 630-2 (this allows for a higher number of interconnections between die 906 and dies 904-1 and / or 904-2), however, in other instances, conductive posts 630-1 and 630-2 may have approximately the same width and / or spacing.

[0058] Figure 10 A cross-sectional side view of another example of a microelectronic assembly 1000 with disassembled components is shown. Similar to... Figure 9 The microelectronic component 900 shown, and microelectronic component 1000 include a die 906 back-coupled to an interposer 902 having conductive pillars 630-1. One difference between microelectronic component 900 and microelectronic component 1000 is that microelectronic component 1000 includes shorter solder-covered conductive pillars 630-3 and solder balls 228-11 between the interposer 902 and the substrate 201, instead of... Figure 9 The highly conductive pillar 630-2 shown is illustrated.

[0059] As in Figure 10As can be seen in the example shown, the height of die 906 relative to the back side of interposer 902 is greater than the height 1045 of conductive post 630-3. In other words, the distance between the face 919-1 of die 906 facing away from interposer 902 and face 112-2 of interposer 902 is 1043, and the height 1045 of one of the conductive posts 630-3 is less than the distance 1043. For example, the post in conductive post 630-3 has a first end coupled to one of the conductive contacts 226-10 and a second end opposite to the first end (e.g., the second end of conductive post 630-3 is covered by solder cap 928-3), wherein the second end of conductive post 630-3 is a certain distance (e.g., height 1045) from the surface 112-1 of interposer 902, and wherein the distance of the second end of conductive post 630-3 is less than the distance 1043 (e.g., the height of post 630-3 relative to the back side of interposer 902 is less than the height of die 906 relative to the back side of interposer 902).

[0060] exist Figure 10 In the example shown, the microelectronic component 1000 also includes solder balls 228-11 between conductive pillars 630-3 and conductive contacts 226-13 on the substrate 201, wherein the solder balls 228-11 are not present in the region of the die 906. Therefore, cavities can be formed between adjacent solder balls 228-11 to accommodate the die 906. Figure 10 In the example shown, die 906 and solder ball 228-11 are in the same plane. Solder ball 228-11 contacts solder cap 928-3. Solder ball 228-11 and solder cap 928-3 may have substantially the same material composition or may have different material compositions. Regardless of whether the material compositions of solder ball 228-11 and solder cap 928-3 are the same or different, an interface can be seen between solder ball 228-11 and solder cap 928-3. Therefore, in the microelectronic assembly 900 after reflow, the solder joint formed by solder cap 928-3 and solder ball 228-11 between conductive post 630-3 and conductive contact 226-13 may include a first solder portion (e.g., a portion of solder from solder cap 928-3) and a second solder portion (e.g., a portion of solder forming solder ball 228-11), wherein the first solder portion has a smaller thickness than the second solder portion.

[0061] The microelectronic component 1000 also includes a solder mask 910, wherein a portion of the conductive contacts 226-13 and solder balls 228-11 are located in openings within the solder mask 910. Figure 10 In the example shown, the solder mask 910 has an opening 1047 substantially aligned with the die 906, wherein at least a portion of the die 906 is within the opening 1047. (As in...) Figure 10As can be seen, opening 1047 includes a portion of bottom filler material 229, which is coplanar with the solder resist layer 910 and with other openings in the solder resist layer 910 where conductive contacts 226-13 are provided. The bottom filler material 229 can be disposed below and around the side of the die 906, such that the bottom filler material is located between the die 906 and the sidewall of opening 1047. Figure 10 In the example shown, the underfill material 229 is not present in the opening 1047; therefore, the underfill material 229 is located between the substrate 201 and the die 906 and is in contact with both the substrate 201 and the die 906. Figure 10 In the example shown, the width 1049 of the opening 1047 is greater than or approximately equal to the width of the die 906 (where the width 1049 of the opening 1047 is approximately parallel to the substrate 201, for example along...). Figure 10 The dimensions of the x-axis or y-axis are shown, where the y-axis enters and leaves the page. In one such example, face 919-1 of die 906 may be coplanar with solder mask 910. In other examples, solder mask 910 may still be present between die 906 and substrate 201.

[0062] Figure 11 A cross-sectional side view of another example of a microelectronic assembly 1100 with disassembled components is shown. The microelectronic assembly 1100 includes a die 906 back-coupled to an interposer 902, the interposer 902 having a similar... Figure 10 The microelectronic component 1000 includes conductive posts 630-1, solder-capped conductive posts 630-3, and solder balls. One difference between microelectronic component 1000 and microelectronic component 1100 is that microelectronic component 1100 includes an additional layer of insulating material 1110 on top of the solder resist layer 910. Therefore, in Figure 10 In the example shown, a layer of insulating material 1110 is located between and in contact with the solder mask layer 910 and the underfill material 229. In some examples, the insulating material 1110 may be a dry film, such as a dry resist film. In some examples, the combined thickness of the solder mask 910 and the insulating material 1110 may be in the range of about 30 micrometers to 55 micrometers or about 35 micrometers to 50 micrometers. In one such example, the solder mask layer 910 may have a thickness 1142 of about 20 micrometers (or in the range of about 15 to 30 micrometers), and the layer of insulating material 1110 may have a thickness 1141 of about 15 to 30 micrometers. Therefore, in some examples, the thickness 1141 of the insulating material 1110 may be approximately equal to, less than, or greater than the thickness 1142 of the solder mask layer 910. In one example, the combined thicknesses 1141 and 1142 may be about 60-75% of the height of the solder ball 228-11.

[0063] As in Figure 11As can be seen, the microelectronic component 1100 includes openings 1147 in the solder mask layer 910 and in the insulating material 1110, wherein the openings 1147 are generally aligned with the die 906, and wherein at least a portion of the die 906 is within the openings 1147. Figure 11 As shown, opening 1047 includes a portion of bottom filler material 229, which is coplanar with solder resist 910, coplanar with insulating material 1110, and coplanar with other openings in solder resist 910 where conductive contacts 226-13 are provided. The bottom filler material 229 may be disposed below and around the side of die 906, such that the bottom filler material is between die 906 and the sidewall of opening 1147 (e.g., between die 906 and solder resist 910 at the sidewalls of insulating material 1110 and opening 1147). Figure 11 In the example shown, neither the underfill material 229 nor the insulating material 1110 is present in the opening 1147; therefore, the underfill material 229 is located between the substrate 201 and the die 906 and is in contact with both the substrate 201 and the die 906. Similar to... Figure 10 ,exist Figure 11 In the example shown, the width 1049 of the opening 1147 is greater than or approximately equal to the width of the die 906 (where the width 1049 of the opening 1147 is approximately parallel to the substrate 201, for example along...). Figure 11 The dimensions of the x-axis or y-axis are shown, where the y-axis enters and exits the page. In one such example, face 919-1 of die 906 may be coplanar with solder mask 910 or with insulating material 1110. In some examples, die 906 is coplanar with both solder mask 910 and insulating material 1110. In other examples, solder mask 910 may still be present between die 906 and substrate 201.

[0064] although Figure 11 Two distinct material layers (solder resist 910 and insulating material 1110, such as a dry resist film) are shown, but in other instances, insulating material 1110 may comprise a thicker layer of solder resist 910. For example, the thickness of solder resist 910 may be... Figure 11 The combined thicknesses 1141 and 1142 are shown. In one such example, the solder mask 910 may have a thickness ranging from about 30 micrometers to 55 micrometers or from about 35 micrometers to 50 micrometers. In one example, the thickness of the solder mask 910 may be about 60% to 75% of the height of the solder ball 228-11.

[0065] Figure 12 and Figure 13Examples of microelectronic assemblies 1200 and 1300 with disassembled components are shown, in which a die 906 is embedded in a substrate 201. Microelectronic assemblies 1200 and 1300 include a substrate 1201, an interposer 902 above the substrate 1201, and conductive bumps (e.g., bumps or pillars) located between and coupled to the substrate 1201 and the interposer 902. The substrate 1201 includes a recessed region or opening 1230 and a die 906 within the opening 1230. The die 906 has a first surface 919-1 facing and attached to the substrate 1201 and a second surface 919-2 opposite to the first surface 919-1, wherein the second surface 919-2 faces and is coupled to the interposer 902. Figure 11 and Figure 12 In the example shown, the face 919-1 of the die 906 is substantially flush with or coplanar with the non-recessed area of ​​the substrate 1201. Therefore, the die 906 is coplanar with the substrate 1201 (e.g., coplanar with the insulating material of the substrate 1201), and the face 919-2 may not protrude from the opening 1230.

[0066] In one example, microelectronic components 1200 and 1300 may include an adhesive material 1210 between a die 906 and a substrate 1201. The adhesive material 1210 may include, for example, a die attachment film or other materials for bonding the die 906 to the substrate 1201 in the opening 1230. Microelectronic components 1200 and 1300 may also include an insulating material 1212, such as an underfill material, a molding material, or other insulating materials that can provide structural support to the die 906 (e.g., prior to attaching the interposer and providing the underfill material 229, for example, during shipment of the substrate 1201 with the die 906 embedded). In the illustrated example, the insulating material 1212 may surround the die 906 along its edges. For example, the insulating material 1212 may be present between the substrate 1201 (e.g., the sidewall of the opening 1230) and the edge of the die 906.

[0067] One difference between microelectronic components 1200 and 1300 is the type of interconnect between the interposer 902 and the substrate 1201. Figure 12 The microelectronic component 1200 shown includes conductive pillars 630-4 located between and coupled to the substrate 1201 and the interposer 902. Figure 12 In the example shown, the conductive post is covered by a solder cap 928-4 coupled to the conductive contact 226-14. Therefore, the conductive post 630-4 is located between the conductive contact 226-15 and the solder cap 928-4. Due to the position of the die 906 within the cavity or opening 1230 on the top surface of the substrate 1201, the conductive post 630-4 can be shorter than the conductive posts in some of the aforementioned examples. Figure 13An exemplary microelectronic component 1300 is shown, which includes conductive bumps comprising solder balls / bumps 228-12 between conductive contacts 226-17 on face 112-1 of interposer 902 and conductive contacts 226-16 on substrate 1201.

[0068] Microelectronic components 1200 and 1300 include one or more conductive contacts 226-18 on face 919-2 of die 906. Figure 12 and Figure 13 In the example shown, since the die 906 is disposed in the recessed area of ​​the substrate, the conductive contact 226-18 can be coplanar with the solder mask layer 910 and with other conductive contacts 226-14 ( Figure 12 ) and conductive contacts 226-16 ( Figure 13 Coplanar. Although a single conductive bump (e.g., a single conductive post 630-4 and a single solder ball / conductive bump 228-12) is shown coupled to a contact 226-18 on die 906, multiple conductive bumps may be coupled to face 919-2 of die 906. Furthermore, although Figure 12 and Figure 13 The conductive pillars 630-4 coupled to the substrate 1201 and coupled to the die 906 are shown to have approximately the same width and spacing. However, in other instances, the conductive bumps coupled to the die 906 may be narrower and / or have a narrower spacing than the conductive bumps between the substrate 1201 and the interposer 902 and coupled to both the substrate 1201 and the interposer 902.

[0069] exist Figure 12 and Figure 13 In the example shown, the bottom filler material 229 at least partially surrounds the conductive bumps between the interposer layer 902 and the substrate 1201. For example, see reference... Figure 12 The bottom filler material 229 surrounds the conductive pillars 630-4 between the interposer layer 902 and the substrate 1201. Similarly, in Figure 13 In this configuration, underfill material 229 surrounds the conductive bumps 228-12 between the interposer 902 and the substrate. Underfill material 229 may be located above the die 906 and a portion above the insulating material 1212. Underfill material 229 may also surround one or more conductive contacts between the top side (e.g., face 919-2) of the die 906 and corresponding conductive bumps or posts that couple the die 906 to the interposer 902.

[0070] Figures 14A-14B A cross-sectional side view of an example die is shown, which may be included on the back side of the interposer and coplanar with conductive bumps and / or vias (e.g. Figure 1A-Figure 1B and Figures 2-7The 206-1, 206-2 and 207 or 106-2 dies Figures 9-13 The die 906), or it can be embedded in the interposer (e.g., the die 906). Figures 8A-8B The shown are the dies 807-1, 807-2, and 806-2.

[0071] Figure 14A and Figure 14B Examples of dies 1400A and 1400B including multiple interconnect layers 1430 disposed on a substrate 1401 are shown. The substrate can be a semiconductor substrate composed of a semiconductor material system including, for example, an N-type or P-type material system. In one embodiment, the semiconductor substrate can be a crystalline substrate formed using bulk silicon (bulk silicon) or silicon-on-insulator (SOI) substructures. In other embodiments, alternative materials can be used to form the semiconductor substrate, which may or may not be combined with silicon. These alternative materials include, but are not limited to, germanium, germanium silicon, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, aluminum gallium arsenide, aluminum indium arsenide, indium gallium arsenide, indium gallium nitride, aluminum indium nitride, or gallium antimonide, or group III-V materials (i.e., materials from groups II and IV of the periodic system), or other combinations of group IV materials (i.e., materials from group IV of the periodic system). In some embodiments, the substrate can be amorphous. In some instances, the substrate 1401 can be thinned (e.g., polished, etched, or otherwise removed).

[0072] In one example, the conductive interconnects 1417 of dies 1400A and 1400B are in an interconnect layer 1430 above substrate 1401. Interconnect layer 1430 may also be referred to as a back-end process (BEOL) layer. In one example, each of interconnect layers 1430 includes multiple interconnects electrically coupled (e.g., conductive contacts) to one or more conductive contacts on the top surface of the die. Various interconnect layers 1430 may be / comprise one or more metal layers of a metallized stack. The various metal layers of interconnect layers 1430 can be used to interconnect the conductive contacts to each other, and thus to couple the IC die (e.g., ...) to the interposer layer. Figure 1A-Figure 1B The dies 206-1, 206-2, and 206-3 are interconnected. In some instances (e.g., in...) Figure 14AIn one or more interconnect layers 1430, various inputs and outputs of devices 1410 (e.g., logic devices) in device region 1451 can be interconnected with each other or with conductive contacts on the top surface of a die. In one example, each of the interconnect layers 1430 may include vias and wires / trenches. For example, the metal layer of interconnect layer 1430 includes via portions 1428b and wires or trenches / interconnect portions 1428a. The trench portion 1428a of the metal layer is configured to transmit signals and power along conductive (e.g., metal) lines (sometimes also referred to as “trenches”) extending in the xy plane (e.g., in the x or y direction), while the via portion 1428b of the metal layer is configured to transmit signals and power to, for example, any adjacent metal layer above or below through conductive vias extending in the z direction. Although dies 1400A and 1400B include conductive via / via portion 1428b, they can be considered TSV-free because dies 1400A and 1400B lack a via extending through substrate 1401 and between the top and bottom surfaces of the die.

[0073] Therefore, in one example, a via connects a metal structure (e.g., a metal wire or via) from one layer to a metal structure in an adjacent layer. Although referred to as a "metal" layer, the various layers of interconnect layer 1430 may simply include patterns of conductive metals such as copper (Cu), aluminum (Al), tungsten (W), or cobalt (C) or metal alloys formed in an insulating medium such as interlayer dielectric (ILD) 1416, or more generally, patterns of conductive materials. The insulating medium may include any suitable ILD material, such as silicon oxide, carbon-doped silicon oxide, silicon carbide, silicon nitride, aluminum oxide, and / or silicon oxynitride. In some embodiments, the ILD 1416 disposed between interconnect structures in several different layers of the interconnect layer may have different compositions; in other embodiments, the composition of the ILD 1416 between different interconnect layers may be the same. The die may include... Figures 14A-14B The diagram shows more or fewer interconnect layers, as indicated by the ellipse in the top interconnect layer 1430.

[0074] Figure 14A and Figure 14B The difference is that, Figure 14A An example of a die 1400A that may include device 1410 and / or a capacitor is shown, while Figure 14B An example of a die 1400B consisting only of a passive interconnect layer is shown. For example, Figure 14AThe die 1400A includes a device region 1451 disposed above a substrate 1401. In one example, the device region 1451 may include a front-end device 1410 (e.g., a front-end transistor such as a FinFET, a nanowire transistor, a nanoribbon transistor, a front-end memory cell, or other front-end device). The device region 1451 and the substrate 1401 may also be referred to as a front-end process (FEOL) layer 1422. The die 1400A also includes a back-end device or back-end component 1412. In one example, the back-end device or back-end component 1412 may include a transistor, a memory cell, a capacitor, or other device or component.

[0075] In comparison, Figure 14B An example of a passive die 1400B (e.g., a die without transistors) is shown. Figure 14B In the example shown, interconnect layer 1430 is directly on substrate 1401 without any intermediate device layers (e.g., one of interconnect layers 1430 is in direct contact with substrate 1401). In such an example, transistors are not present in the layer directly on substrate 1401, nor in the BEOL layer. Therefore, interconnect die 1400B can be referred to as a passive interconnect die or a passive bridge die.

[0076] Figures 15A-15C It can be a cross-sectional side view of a substrate that may be included in a microelectronic assembly having the components described herein. Figure 15A and Figure 15B Substrates 1501A and 1501B are shown, comprising a core material having multiple layers on either side of the core. Figure 15C An example of a coreless substrate is shown. Figure 15B It shows a device for accommodating, for example, such as Figures 14A-14B An example of a substrate 1501B with an embedded die cavity is shown.

[0077] First go to Figure 15AThe substrate 1501A includes a dielectric material 1512 and a conductive material 1508 disposed in one or more layers of the dielectric material 1512 to provide conductive paths through the substrate 1501A (e.g., conductive traces 1508A and conductive vias 1508B), and to provide conductive pads and contacts. The substrate 1501A may include a first surface 1520-1 and an opposite second surface 1520-2. The dielectric material 1512 of the substrate 1501A may be formed in the respective layers. In some embodiments, the dielectric material 1512 may include an organic material, such as an organic accumulation film. In some embodiments, the dielectric material 1512 may include, for example, ceramics, epoxy films having filler particles, glass, inorganic materials, or combinations of organic and inorganic materials. In some embodiments, the conductive material 1508 may include a metal (e.g., copper). In some embodiments, substrate 1501A may include layers of dielectric material 1512 / conductive material 1508, wherein lines / traces / pads / contacts (e.g., conductive trace 1508A) of conductive material 1508 in one layer are electrically coupled to lines / traces / pads / contacts (e.g., conductive trace 1508A) of conductive material 1508 in adjacent layers via vias (e.g., 1508B) extending through dielectric material 1512. Conductive trace 1508A may be referred to herein as a “conductive line,” “conductive element,” “conductive pad,” or “conductive contact.” For example, PCB manufacturing techniques can be used to form substrate 1501A including such layers. Although specific numbers and arrangements of dielectric material 112 / conductive material 1508 layers are shown in the various figures in the accompanying drawings, these specific numbers and arrangements are merely illustrative, and any desired number and arrangement of dielectric material 112 / conductive material 1508 can be used.

[0078] like Figure 15AAs shown, substrate 1501A may further include a glass core 1510. Glass core 1510 may also be referred to as a glass layer or glass substrate. A layer of dielectric material 1512 having conductive material 1508 may be present above and below glass core 1510. In some instances, the layer above the glass core may be coupled to, for example, interposers 202, 802, and 902 discussed above. In some instances, the layer below the glass core may be coupled to, for example, another packaging substrate or circuit board. As used herein, the term "glass core" refers to a layer (e.g., a glass layer) or structure (e.g., a portion of a glass layer) of any glass material, such as quartz, silica, fused silica, silicate glass (e.g., borosilicate, aluminosilicate, aluminoborosilicate), soda-lime glass, soda-lime silica, borosilicate float glass, lead borate glass, photosensitive glass, non-photosensitive glass, or ceramic glass. Specifically, unlike materials that may include glass particles (e.g., glass fiber reinforced polymers, such as substrates / plates constructed from glass fibers and epoxy binders), the glass core 1510 may be a bulk glass or a solid volume / glass layer. Such glass materials are typically amorphous, generally transparent, and amorphous solids. In some embodiments, the glass core 1510 may be an amorphous solid glass layer. In some embodiments, the glass core 1510 may include materials comprising silicon and oxygen, and any one or more of aluminum, boron, magnesium, calcium, barium, tin, sodium, potassium, strontium, phosphorus, zirconium, lithium, titanium, and zinc. In some embodiments, the glass core 1510 may include any of the materials described above, wherein the weight percentage of silicon is at least about 0.5%, for example between about 0.5% and 50%, between about 1% and 48%, or at least about 23%. For example, if the glass core 1510 is molten silicon dioxide, the weight percentage of silicon may be about 47%. In some embodiments, the glass core 1510 may comprise a material having at least 23% by weight silicon and / or at least 26% by weight oxygen, and in some other embodiments, the glass core 1510 may also comprise at least 5% by weight aluminum. In some embodiments, the glass core 1510 may comprise any of the above-described materials, and may also comprise one or more additives, such as Al2O3, B2O3, MgO, CaO, SrO, BaO, SnO2, Na2O, K2O, SrO, P2O3, ZrO2, Li2O, Ti, and Zn. In some embodiments, the glass core 1510 may be a glass layer that does not include organic binders or organic materials. The glass core 1510 can be distinguished from, for example, a “prepreg” or “FR4” core of a PCB substrate, which typically comprises glass fibers embedded in a resinous organic material such as epoxy resin. In such conventional cores / substrates comprising glass fibers and epoxy resin, the diameter of the glass fibers is typically in the range of 5 micrometers to 200 micrometers.In contrast, the glass core 1510 can be a glass layer with a side length ranging from about 10 mm to about 250 mm (e.g., from 10 mm × 10 mm to 250 mm × 250 mm).

[0079] In some embodiments, the glass core 1510 is Figure 15A The cross-sections in the xz, yz, and / or xy planes of the exemplary coordinate system shown may be generally rectangular (the axes shown in the following figures refer to...). Figure 15A The axes of the coordinate system shown are shown in the figure. However, in some other embodiments, the glass core 1510 may have rounded or beveled edges / sides / sidewalls. In some embodiments, in a top view of the glass core 1510 (e.g., Figure 15A In the coordinate system shown in the xy plane, the glass core 1510 may have a first length in the range of 10 mm to 250 mm and a second length in the range of 10 mm to 250 mm, the first length being perpendicular to the second length. The thickness of the glass core 1510 (e.g., along the xy plane of the coordinate system shown) Figure 15A The dimensions (measured along the z-axis of a coordinate system) can range from approximately 50 micrometers to 1.4 millimeters. In some embodiments, the glass core 1510 can be a glass core substrate having a thickness ranging from approximately 50 micrometers to 1.4 millimeters. In some embodiments, the glass core 1510 can be a glass layer comprising a rectangular prism having edges / sides / sidewalls that may have rounded or beveled edges. In some such embodiments, the rectangular prism may have a first side and a second side perpendicular to the first side, the length of the first side ranging from 10 millimeters to 250 millimeters, and the length of the second side ranging from 10 millimeters to 250 millimeters. In some embodiments, the glass core 1510 can be a rectangular prism having portions (e.g., through-holes) with other materials (e.g., metal) removed and filled, such as TGV 1515. In some embodiments, the glass core 1510 can be a glass layer having a thickness ranging from 50 micrometers to 1.4 millimeters, a first length ranging from 10 millimeters to 250 millimeters, and a second length ranging from 10 millimeters to 250 millimeters, the first length being perpendicular to the second length. In some embodiments, the dielectric material 1512 and the glass core 1510 may be referred to together as a "multilayer glass substrate". In some such embodiments, the glass core 1510 may be a glass layer with a thickness in the range of about 25 micrometers to 50 micrometers.

[0080] exist Figure 15AIn the examples shown, glass core 1510 includes through-glass vias (TGVs) 1515. In the illustrated examples, some of the TGVs may be or include conductive vias that include a conductive material to form a conductive interconnect. For example, TGV 1515 is a conductive via that may include any suitable conductive material, such as copper, silver, nickel, gold, aluminum, or other metals or alloys. TGV 1515 may be a via extending between a first and a second side of glass core 1510 (e.g., between the bottom and top surfaces of glass core 1510). The opening for TGV 1515 can be formed using any suitable process, including, for example, direct laser drilling or laser-induced etching processes (which may also be referred to as laser patterning or selective laser activation). In some embodiments, the TGV 1515 disclosed herein may have a spacing, for example, between 50 micrometers and 500 micrometers measured from the center of one TGV 1515 to the center of an adjacent TGV 1515. TGV 1515 may have any suitable size and shape. In some embodiments, the TGV 1515 may have a rounded (e.g., circular or elliptical), rectangular, or other shaped cross-section. In some embodiments, at least some of the TGV 1515 may have an hourglass shape (e.g., the TGV 1515 may taper gradually from both sides, such that the TGV has a narrower width between two larger widths). In some embodiments, at least some of the TGV 1515 may taper gradually from one face of the glass core 1510 to another, for example, from the top face of the glass core 1510 to the bottom face of the glass core 1510.

[0081] Figure 15B Another exemplary substrate 1501B with a glass core 1510 is shown. Substrate 1501B is similar to substrate 1501A; however, substrate 1501B includes a cavity 1570 in substrate 1501B, in which a die 1506 can be embedded and attached. The die can be an example of dies 206-1, 206-2, 207, 806-1, 806-2, 807-1, 807-2, and 906 discussed above. Figure 15BIn the illustrated example, die 1506 can be attached to substrate 1501B at the bottom of cavity 1570 using an adhesive material 1580, such as die attachment film. The cavity can be filled with another insulating material 1582 to secure die 1506 within cavity 1570. Die 1506 may be a TSV-free die without conductive contacts at its bottom. In one example, die 1506 lacks conductive contacts that directly contact the contacts of substrate 1501B. Instead, as described above, die 1506 can be coupled to an interlayer that can be disposed above and coupled to substrate 1501B. In such an example, die 1506 is surrounded by an insulating material on its side surface 1581 and on the side of die 1506 facing substrate 1501B (e.g., the side of die 1506 attached to the substrate with adhesive material 1580).

[0082] Figure 15C A coreless substrate 1501C lacking a glass core is shown. The substrate 1501C includes a dielectric material 1512 and a conductive material 1508 disposed in one or more layers of the dielectric material 1512 to provide conductive paths (e.g., conductive traces 1508A and conductive vias 1508B) through the substrate 1501C, and to provide conductive pads and contacts. Although not shown, coreless substrates such as substrate 1501C may also include features for accommodating, for example, Figure 15B The cavity shown is without a TSV die.

[0083] Figure 16 A plan view of an example of a system 1550 according to an embodiment of the present disclosure is shown. The system 1550 may be implemented as or include a microelectronic component with disassembled parts. Figure 16 In the example shown, system 1550 includes a plurality of dies 1575, which may be attached to an interposer 1571 (e.g., the top or front side of the interposer). Dies 1575 may be examples of dies 204-1, 204-2, and 204-3 discussed above. Interposer 1571 may be, for example... Figure 1A Interposer 202 is shown. In one such example, the interposer is an organic interposer. System 1550 includes one or more layers located in interposer 1571 and a substrate beneath the interposer. Figure 16 Components / dies 1567, 1567, and 1573 (not shown in the diagram) are located between substrates. According to the examples described herein, dies 1567, 1567, and 1573 may be attached to the back side of an interposer, embedded in an interposer, and / or embedded in a substrate. Dies 1567, 1567, and 1573 may be coplanar with conductive bump 1577, which may include one or more of solder balls / bumps, metal pillars, and solder caps. Figure 16In the example shown, die 1567 can represent a capacitor die, die 1569 can represent a memory die, and die 1573 can represent a voltage regulator die. In such an example, memory die 1569-1 can provide non-volatile memory to a specific die in system 1550 and / or die 1575; memory die 1569-2 can provide a cache (e.g., an extended system cache for die 1575 aligned with memory die 1569-2); and memory die 1569-3 can provide a cache (e.g., a modular graphics cache) to die 1575 aligned with die 1569-3. However, alternatives or other... Figure 16 In addition to the exemplary dies 1567, 1567 and 1573 shown, other types of dies may be attached to the back side of the interposer, embedded in the interposer, and / or embedded in the substrate.

[0084] Therefore, microelectronic components with disassembled components as described herein can achieve low-cost and highly flexible disassembled components. In one example, the component includes an interposer on a substrate and conductive interconnects (e.g., one or more of conductive pillars, solder caps, and solder balls) coupled between and to the substrate and the interposer. One or more dies (e.g., processor dies, etc.) may be coupled to the top side of the interposer. Another die may be coupled to the package side (e.g., the bottom side) of the interposer. Another die may be, for example, in a bump field between the interposer and the substrate (e.g., coplanar with conductive pillars or solder balls). In some examples, an additional die may be embedded in the substrate. In some examples, the other die may be TSV-free and therefore lack conductive interconnects that directly contact the conductive contacts of the substrate. In other examples, the other die may be embedded within an RDL of the interposer. In one such example, the other die may be coplanar with conductive pillars coupled between and to the upper and lower RDLs located between the RDL above and below the other die. In some instances, another die can provide capacitors, routing, and / or memory to one or more dies on top of the interposer layer.

[0085] The features of the above-mentioned microelectronic components can be combined. For example, Figure 2 The bottom filler material 240 shown can exist in the interlayer 202 and Figure 3-7 The dies shown are between 206-1, 206-2, and 207. In another example, although... Figure 1A and Figure 2-7 Examples of dies 206-1, 206-2, and 207 coupled to an interposer 202 with solder balls are shown; however, in other examples, dies 206-1, 206-2, and 207 may be coupled to an interposer 202 with conductive pillars, instead of solder balls or in addition to solder balls. Similarly, instead of solder balls or in addition to solder balls, Figure 8B The dies 806 and 807 shown can be coupled to the RDL 821 with conductive posts, and can replace solder balls or other materials besides solder balls. Figure 9-13 The die 906 shown can be coupled to an interposer 902 with solder balls. Although the specific example shows the die attached to the back side of the interposer or embedded in the interposer or substrate, microelectronic assemblies may include one or more dies attached to the back side of the interposer, embedded in the interposer, and / or embedded in the substrate. It should be noted that although specific examples of the spacing and width of the conductive bumps are provided, other spacings and widths are also possible. Furthermore, the bump distribution in a given interface may be non-uniform (e.g., in the same bump field, some bumps may have a larger width than others).

[0086] An IC assembly that includes the disassembled components according to the examples described herein may be included or incorporated in any suitable electronic component or electronic device. Figure 16-19 Various examples of devices that may include or be included in an IC assembly comprising disassembled components as disclosed herein are shown.

[0087] Figure 17 This is a top view of wafer 1500 and die 1502 according to any embodiment disclosed herein. Wafer 1500 and die 1502 may include or be included in one or more IC structures or components. Wafer 1500 may be made of semiconductor material and may include one or more dies 1502 having IC structures formed on the surface of wafer 1500. Each of the dies 1502 may be a repeating unit of a semiconductor product including any suitable IC. After the semiconductor product is manufactured, wafer 1500 may undergo a singlet process in which dies 1502 are separated from each other to provide discrete “chips” of the semiconductor product. In some embodiments, wafer 1500 or die 1502 may include memory devices (e.g., random access memory (RAM) devices such as static RAM (SRAM) devices, magnetic RAM (MRAM) devices, resistive RAM (RRAM) devices, conductive bridged RAM (CBRAM) devices, etc.), logic devices (e.g., AND, OR, NAND, or NOR gates), or any other suitable circuit elements. Multiple of these devices may be combined on a single die 1502. For example, a memory array formed by multiple memory devices can be formed in conjunction with a processing device (e.g., Figure 20 On the processing device 1802 shown or other die 1502 with the same logic, other logic is configured to store information in a memory device or execute instructions stored in a memory array.

[0088] Figure 18This is a side sectional view of an exemplary IC package 1650 that may be included in or incorporated into a microelectronic component according to any embodiment disclosed herein. In some embodiments, the IC package 1650 may be a system-in-package (SiP).

[0089] The encapsulation substrate 1652 may be formed of a dielectric material (e.g., ceramic, deposited film, epoxy film having filler particles therein, glass, organic material, inorganic material, combination of organic and inorganic materials, embedded portion formed of different materials, etc.) and may have conductive paths extending through the dielectric material between surfaces 1672 and 1674, or between different locations on surface 1672, and / or between different locations on surface 1674.

[0090] The package substrate 1652 may include conductive contacts 1663, which are coupled to conductive paths (not shown) through the package substrate 1652, thereby allowing circuitry within the die 1656 and / or the interposer 1657 to be electrically coupled to various conductive contacts in the conductive contacts 1664 (or to devices (not shown) included in the package substrate 1652).

[0091] IC package 1650 may include an interposer 1657 coupled to package substrate 1652 via conductive contacts 1661 of interposer 1657, first-level interconnects 1665 and conductive contacts 1663 of package substrate 1652. Figure 18 The first-level interconnect 1665 shown is a solder bump, but any suitable first-level interconnect 1665 can be used. In some embodiments, the interposer 1657 may not be included in the IC package 1650; instead, the die 1656 can be directly coupled to the conductive contact 1663 at face 1672 via the first-level interconnect 1665. More generally, one or more dies 1656 can be coupled to the package substrate 1652 via any suitable structure (e.g., silicon bridge, organic bridge, one or more waveguides, one or more interposers, wire bonding, etc.).

[0092] IC package 1650 may include one or more dies 1656 coupled to the interposer 1657 via conductive contacts 1654 of die 1656, first-level interconnect 1658, and conductive contacts 1660 of interposer 1657. Conductive contacts 1660 may be coupled to conductive paths (not shown) via the interposer 1657, thereby allowing circuitry within die 1656 to be electrically coupled to various conductive contacts in conductive contacts 1661 (or electrically coupled to other devices included in the interposer 1657, not shown). Figure 18The first-level interconnect 1658 shown is a solder bump, but any suitable first-level interconnect 1658 can be used. As used herein, "conductive contact" can refer to a portion of a conductive material (e.g., metal) that serves as an interface between different components; conductive contacts can be recessed in the surface of a component, flush with the surface of a component, or extend away from the surface of a component, and can take any suitable form (e.g., conductive pad or socket).

[0093] In some embodiments, an underfill material 1666 may be disposed around a first-level interconnect 1665 between a package substrate 1652 and an interposer 1657, and a molding compound 1668 may be disposed around a die 1656 and an interposer 1657 and contact the package substrate 1652. In some embodiments, the underfill material 1666 may be the same as the molding compound 1668. Exemplary materials that may be used for the underfill material 1666 and the molding compound 1668 are epoxy molding materials (as applicable). A second-level interconnect 1670 may be coupled to a conductive contact 1664. Figure 18 The second-level interconnect 1670 shown is a solder ball (e.g., for a BGA arrangement), but any suitable second-level interconnect 1670 can be used (e.g., pins in a pin grid array arrangement or pads in a pad grid array arrangement). As known in the art and referenced below... Figure 19 The second-level interconnect 1670 discussed can be used to couple IC package 1650 to another component, such as a circuit board (e.g., motherboard), an interposer, or another IC package.

[0094] Die 1656 may take the form of any embodiment of die 1502 discussed herein. In embodiments where IC package 1650 includes multiple dies 1656, IC package 1650 may be referred to as a multi-chip package (MCP). Die 1656 may include circuitry for performing any desired function. For example, one or more of dies 1656 may be logic dies (e.g., silicon-based dies), and one or more of dies 1656 may be memory dies (e.g., high-bandwidth memory).

[0095] although Figure 18 The IC package 1650 shown is a flip-chip package, but other package architectures can be used. For example, IC package 1650 can be a BGA package, such as an embedded chip-level ball grid array (eWLB) package. In another example, IC package 1650 can be a wafer-level chip-scale package (WLCSP) or a panel fan-out (FO) package. Although in Figure 18Two dies 1656 are shown in the IC package 1650, but the IC package 1650 may include any desired number of dies 1656. The IC package 1650 may include additional passive components, such as surface-mount resistors, capacitors, and inductors disposed on either side of the first side 1672 or the second side 1674 of the package substrate 1652 or on either side of the interposer 1657. More generally, the IC package 1650 may include any other active or passive components known in the art.

[0096] Figure 19 This is a side sectional view of an IC device assembly 1700 according to any embodiment disclosed herein. The IC device assembly 1700 may include one or more IC packages or other electronic components (e.g., dies), the other electronic components including an organic interposer layer having fan-out wiring dies. The IC device assembly 1700 includes a plurality of components disposed on a circuit board 1702 (which may be, for example, a motherboard). The IC device assembly 1700 includes components disposed on a first surface 1740 of the circuit board 1702 and an opposite second surface 1742 of the circuit board 1702; typically, components may be disposed on one or both of surfaces 1740 and 1742. Any IC package discussed below with reference to the IC device assembly 1700 may take the form of the above reference. Figure 18 The IC package 1650 discussed may take any form (e.g., it may include one or more IC structures according to the embodiments described herein).

[0097] In some embodiments, circuit board 1702 may be a PCB comprising multiple metal layers separated from each other by dielectric material layers and interconnected by conductive vias. Any one or more of the metal layers may be formed in a desired circuit pattern to route electrical signals between components coupled to circuit board 1702 (optionally combined with other metal layers). In other embodiments, circuit board 1702 may be a non-PCB substrate.

[0098] Figure 19 The illustrated IC device assembly 1700 includes an interposer-on-a-package (IPA) structure 1736 coupled to a first surface 1740 of a circuit board 1702 via a coupling member 1716. The coupling member 1716 can electrically and mechanically couple the IPA structure 1736 to the circuit board 1702 and may include solder balls (e.g., ...). Figure 19 (as shown), the convex and concave portions of the socket, adhesive, bottom filler material and / or any other suitable electrical coupling structure and / or mechanical coupling structure.

[0099] The on-intermediate package structure 1736 may include an IC package 1720 coupled to the package intermediary 1704 via a coupling member 1718. The coupling member 1718 may take any form suitable for the application, such as the form discussed above with reference to coupling member 1716. Although in Figure 19 A single IC package 1720 is shown, but multiple IC packages can be coupled to a package interposer 1704; in fact, additional interposers can be coupled to the package interposer 1704. The package interposer 1704 can provide an intermediate substrate for bridging the circuit board 1702 and the IC package 1720. The IC package 1720 can be, as or include, for example, a die ( Figure 17 This refers to a die 1502, an IC device, or any other suitable component. Typically, the package interposer 1704 can extend connections to wider spacing or reroute connections to different connections. For example, the package interposer 1704 can couple an IC package 1720 (e.g., a die) to a set of BGA conductive contacts of a coupling component 1716 for coupling to a circuit board 1702. Figure 19 In the illustrated embodiment, IC package 1720 and circuit board 1702 are attached to opposite sides of package interposer 1704; in other embodiments, IC package 1720 and circuit board 1702 may be attached to the same side of package interposer 1704. In some embodiments, three or more components may be interconnected via package interposer 1704.

[0100] In some embodiments, the encapsulation interposer 1704 may be formed as a PCB comprising multiple metal layers separated from each other by dielectric material layers and interconnected by conductive vias. In some embodiments, the encapsulation interposer 1704 may be formed of epoxy resin, glass fiber reinforced epoxy resin, epoxy resin with inorganic fillers, ceramic materials, or polymeric materials such as polyimide. In some embodiments, the encapsulation interposer 1704 may be formed of a rigid or flexible material, which may include, for example, silicon, germanium, and other III-V and IV group materials used in semiconductor substrates. The encapsulation interposer 1704 may include metal lines 1710 and vias 1708 including, but not limited to, TSV 1706. The encapsulation interposer 1704 may also include embedded devices 1714, which may include both passive and active devices. Such devices may include, but are not limited to, capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, electrostatic discharge (ESD) devices, and memory devices. More complex devices, such as RF devices, power amplifiers, power management devices, antennas, arrays, sensors, and microelectromechanical systems (MEMS) devices, can also be formed on the package interposer 1704. The package structure 1736 can take any form of package structure on interposer known in the art.

[0101] IC device assembly 1700 may include IC package 1724, which is coupled to a first side 1740 of circuit board 1702 via coupling member 1722. Coupling member 1722 may take the form of any embodiment discussed above with reference to coupling member 1716, and IC package 1724 may take the form of any embodiment discussed above with reference to IC package 1720.

[0102] Figure 19 The illustrated IC device assembly 1700 includes a package-on-package structure 1734 coupled to a second side 1742 of a circuit board 1702 via a coupling member 1728. The package-on-package structure 1734 may include IC packages 1726 and 1732 coupled together via a coupling member 1730, such that IC package 1726 is disposed between the circuit board 1702 and IC package 1732. Coupling members 1728 and 1730 may take the form of any embodiment of the coupling member 1716 described above, and IC packages 1726 and 1732 may take the form of any embodiment of the IC package 1720 described above. The package-on-package structure 1734 can be configured according to any package-on-package structure known in the art.

[0103] Figure 20 This is a block diagram of an exemplary electrical device 1800 according to any embodiment disclosed herein. The exemplary electrical device 1800 may include or be included in a microelectronic assembly having an organic interposer layer having fan-out wiring dies. For example, any suitable component of the electrical device 1800 may include one or more of the IC device assembly 1700, IC package 1650, or die 1502 disclosed herein. Figure 20 The diagram illustrates several components included in electrical device 1800, but any one or more of these components may be omitted or copied, depending on the application. In some embodiments, some or all of the components included in electrical device 1800 may be attached to one or more motherboards. In some embodiments, some or all of these components are manufactured onto a single system-on-a-chip (SoC) die.

[0104] Additionally, in various embodiments, electrical equipment 1800 may not include... Figure 20The electrical device 1800 may include one or more of the components shown, but may include interface circuitry for coupling to one or more components. For example, the electrical device 1800 may not include display device 1806, but may include display device interface circuitry (e.g., connectors and driver circuitry) to which display device 1806 may be coupled. In another set of examples, the electrical device 1800 may not include audio input device 1824 or audio output device 1808, but may include audio input or output device interface circuitry (e.g., connectors and support circuitry) to which audio input device 1824 or audio output device 1808 may be coupled.

[0105] Electrical device 1800 may include processing device 1802 (e.g., one or more processing devices). As used herein, the term "processing device" or "processor" may refer to any device or part of a device that processes electronic data from registers and / or memory to convert that electronic data into other electronic data that can be stored in registers and / or memory. Processing device 1802 may include one or more digital signal processors (DSPs), application-specific integrated circuits (ASICs), central processing units (CPUs), graphics processing units (GPUs), cryptographic processors (dedicated processors that execute cryptographic algorithms within hardware), server processors, or any other suitable processing device. Electrical device 1800 may include memory 1804, which itself may include one or more memory devices, such as volatile memory (e.g., dynamic random access memory (DRAM)), non-volatile memory (e.g., read-only memory (ROM)), flash memory, solid-state memory, and / or hard disk drives. In some embodiments, memory 1804 may include memory that shares a die with processing device 1802. This memory may be used as cache memory and may include embedded DRAM (eDRAM) or spin-transfer torque magnetic random access memory (STT-MRAM).

[0106] In some embodiments, electrical device 1800 may include communication chip 1812 (e.g., one or more communication chips). For example, communication chip 1812 may be configured to manage wireless communication for transmitting data to and from electrical device 1800. The term "wireless" and its derivatives can be used to describe circuits, devices, systems, methods, techniques, communication channels, etc., that can transmit data through a non-solid medium using modulated electromagnetic radiation. This term does not imply that the associated device does not contain any wires, although in some embodiments the associated device may not contain any wires.

[0107] The 1812 communication chip can implement any of a variety of wireless standards or protocols, including but not limited to Institute of Electrical and Electronics Engineers (IEEE) standards, such as Wi-Fi (IEEE 802.11 family), IEEE 802.16 standards (e.g., IEEE 802.16-2005 revision), Long Term Evolution (LTE) projects, and any modifications, updates, and / or revisions (e.g., Advanced LTE project, Ultra Mobile Broadband (UMB) project (also known as “3GPP2”), etc.). IEEE 802.16 compliant Broadband Wireless Access (BWA) networks are commonly referred to as WiMAX networks. WiMAX is an acronym for Global Interoperability for Microwave Access and is a certification mark for products that have passed conformance and interoperability testing of the IEEE 802.16 standard. The 1812 communication chip can operate according to Global System for Mobile Communications (GSM), General Packet Radio Service (GPRS), Universal Mobile Telecommunications System (UMTS), High Speed ​​Packet Access (HSPA), Evolved HSPA (E-HSPA), or LTE networks. The communication chip 1812 can operate according to enhanced data for GSM Evolution (EDGE), GSM Edge Radio Access Network (GERAN), Universal Terrestrial Radio Access Network (UTRAN), or Evolved UTRAN (E-UTRAN). The communication chip 1812 can operate according to Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Digital Enhanced Cordless Telecommunications (DECT), Evolved Data Optimization (EV-DO) and its derivatives, as well as any other wireless protocol designated as 3G, 4G, 5G, and higher. In other embodiments, the communication chip 1812 can operate according to other wireless protocols. The electrical device 1800 may include an antenna 1822 to facilitate wireless communication and / or receive other wireless communications (e.g., AM or FM radio transmissions).

[0108] In some embodiments, the communication chip 1812 can manage wired communication, such as electrical, optical, or any other suitable communication protocol (e.g., Ethernet). As described above, the communication chip 1812 may include multiple communication chips. For example, a first communication chip 1812 may be dedicated to short-range wireless communication such as Wi-Fi or Bluetooth, and a second communication chip 1812 may be dedicated to longer-range wireless communication such as Global Positioning System (GPS), EDGE, GPRS, CDMA, WiMAX, LTE, EV-DO, or others. In some embodiments, the first communication chip 1812 may be dedicated to wireless communication, and the second communication chip 1812 may be dedicated to wired communication.

[0109] Electrical device 1800 may include battery / power circuit 1814. Battery / power circuit 1814 may include one or more energy storage devices (e.g., batteries or capacitors) and / or circuitry for coupling components of electrical device 1800 to an energy source (e.g., AC line power) separate from electrical device 1800.

[0110] Electrical device 1800 may include display device 1806 (or corresponding interface circuitry, as described above). Display device 1806 may include any visual indicator, such as a head-up display, computer monitor, projector, touch screen display, liquid crystal display (LCD), light-emitting diode display, or flat panel display.

[0111] Electrical device 1800 may include audio output device 1808 (or corresponding interface circuitry, as described above). Audio output device 1808 may include any device that generates audible indicators, such as a speaker, headphones, or earphones.

[0112] Electrical device 1800 may include audio input device 1824 (or a corresponding interface circuit, as described above). Audio input device 1824 may include any device that generates a signal representing sound, such as a microphone, microphone array, or digital musical instrument (e.g., a musical instrument with a Musical Instrument Digital Interface (MIDI) output).

[0113] Electrical device 1800 may include GPS device 1818 (or a corresponding interface circuit, as described above). As is known in the art, GPS device 1818 can communicate with satellite-based systems and can receive the location of electrical device 1800.

[0114] Electrical device 1800 may include another output device 1810 (or a corresponding interface circuit, as described above). Examples of other output devices 1810 may include audio codecs, video codecs, printers, wired or wireless transmitters for providing information to other devices, or additional storage devices.

[0115] Electrical device 1800 may include another input device 1820 (or a corresponding interface circuit, as described above). Examples of other input devices 1820 may include accelerometers, gyroscopes, compasses, image capture devices, keyboards, cursor control devices such as mice, styluses, and touchpads, barcode readers, quick-response (QR) code readers, any sensors, or radio frequency identification (RFID) readers.

[0116] Electrical device 1800 may have any desired form factor, such as handheld or mobile electrical devices (e.g., cellular phones, smartphones, mobile internet devices, music players, tablet computers, laptop computers, netbook computers, ultrabook computers, personal digital assistants (PDAs), ultra-mobile personal computers, etc.), desktop electrical devices, server equipment or other networked computing components, printers, scanners, monitors, set-top boxes, entertainment control units, vehicle control units, digital cameras, digital video recorders, or wearable electrical devices. In some embodiments, electrical device 1800 may be any other electronic device that processes data.

[0117] The following paragraphs provide various examples of the embodiments disclosed herein.

[0118] Example 1 provides a microelectronic component comprising: an interposer including two or more interconnect layers, wherein the interposer has a first side and a second side opposite to the first side, wherein: the first side (e.g., the bottom / back side of the interposer) includes a first conductive contact (e.g., having a first spacing) and a second conductive contact (e.g., having a second spacing, wherein a wider contact is used for coupling with a larger bump / substrate and a narrower contact is used for coupling with a smaller bump / die); the second side (e.g., the top / front side of the interposer) includes a third conductive contact (e.g., having a third spacing, wherein the third conductive contact is used for coupling with a chiplet, processor die, etc., which is coupled to the top of the interposer); conductive bumps coupled to the first conductive contacts; and dies (e.g., bridge die, die with capacitor, etc.) in the same layer as the conductive bumps (e.g., in a bump field) and coupled to the second conductive contacts.

[0119] Example 2 provides a microelectronic component according to Example 1, wherein the conductive bumps include a first conductive bump and a second conductive bump coplanar with the first conductive bump, and the die is located between the first conductive bump and the second conductive bump.

[0120] Example 3 provides a microelectronic component according to Example 2, wherein the die includes four sides, including a first side, a second side opposite to the first side, a third side, and a fourth side opposite to the third side, a first conductive bump adjacent to the first side, a second conductive bump adjacent to the second side, the conductive bump further including a third conductive bump and a fourth conductive bump, wherein the third conductive bump is adjacent to the third side, and the fourth conductive bump is adjacent to the fourth side.

[0121] Example 4 provides a microelectronic component according to any one of Examples 1-3, further comprising: a second conductive bump (e.g., a bump between the die and the bottom side of the interposer) located between the die and the second conductive contact and coupled to the second conductive contact; and a gap that is coplanar with the second conductive bump and located between the first surface and the die, wherein the plane is substantially parallel to the interposer (e.g., there may be no underfill between the die and the bottom side of the interposer).

[0122] Example 5 provides a microelectronic component according to any one of Examples 1-3, further comprising: a second conductive bump located between and coupled to the die and the second conductive contact; and a dielectric material (e.g., an underfill material) in the same plane as the second conductive bump and located between the first surface and the die, wherein the plane is substantially parallel to the interposer.

[0123] Example 6 provides a microelectronic component according to Example 5, wherein the dielectric material is not present between adjacent bumps of the conductive bumps (e.g., the underfill material may be limited to the region between the die and the bottom side of the interposer).

[0124] Example 7 provides a microelectronic component according to any one of Examples 1-6, further comprising: a substrate including a third conductive contact coupled to the conductive bumps; and an air gap located between the die and the substrate.

[0125] Example 8 provides a microelectronic component according to any one of Examples 1-6, further comprising: a substrate including a third conductive contact coupled to the conductive bumps; and a continuous portion of dielectric material located between the die and the substrate, wherein there are no conductive interconnects in the continuous portion of the dielectric material (e.g., an underfill material may be present between the die and the substrate).

[0126] Example 9 provides a microelectronic component according to any one of Examples 1-8, wherein the die is a passive die, the passive die including conductive interconnects coupled to a first and a second of the second conductive contacts.

[0127] Example 10 provides a microelectronic component according to any one of Examples 1-8, wherein the die includes one or more transistors.

[0128] Example 11 provides a microelectronic component according to any one of Examples 1-8, wherein the die includes a memory array.

[0129] Example 12 provides a microelectronic component according to any one of Examples 1-8, further comprising another die (e.g., a processor die) coupled to the third conductive contact, wherein the die is located below and substantially aligned with the other die, and the die includes a capacitor.

[0130] Example 13 provides a microelectronic assembly according to any one of Examples 1-12, wherein the die includes a first die face and a second die face opposite to the first die face, and the die lacks a through hole extending from the first die face to the second die face.

[0131] Example 14 provides a microelectronic assembly according to any one of Examples 1-12, wherein the die is a first die, and the microelectronic assembly further includes a second die coplanar with the first die, wherein one or more of the conductive bumps are located between the first die and the second die within the layer.

[0132] Example 15 provides a microelectronic assembly according to any one of Examples 1-14, wherein the die and the conductive bump are in the same plane, wherein the plane is substantially parallel to the interposer.

[0133] Example 16 provides a microelectronic component according to any one of Examples 1-14, further comprising: a dielectric material (e.g., a molding material) that at least partially surrounds the die; and a conductive post that passes through the dielectric material, wherein the conductive post is located between one of the conductive bumps and a conductive interconnect of the interposer and coupled to the conductive interconnect of the one of the conductive bumps and the interposer, wherein the die and the conductive post are in the same plane, and the plane is substantially parallel to the interposer.

[0134] Example 17 provides a microelectronic component according to Example 16, wherein the dielectric material is a first dielectric material, and wherein the microelectronic component further includes a second dielectric material that at least partially surrounds the conductive bump (e.g., around the bump and an underfill material may be present between the substrate and the molding material).

[0135] Example 18 provides a microelectronic component according to Example 1, wherein the die is coupled to a second conductive contact via a first conductive post, the conductive bump including a second conductive post (e.g., wherein the first conductive contact is recessed in the dielectric material of the RDL of the interposer), a side of the die opposite to the interposer is at a predetermined distance from the first surface, and one of the second conductive posts has a height greater than the distance.

[0136] Example 19 provides a microelectronic component according to Example 18, further comprising: a substrate located below the interposer and the die; a fourth conductive contact disposed on the substrate, wherein the conductive post is located between and coupled to the first conductive contact and the fourth conductive contact; and a solder cap located between the conductive post and the fourth conductive contact.

[0137] Example 20 provides a microelectronic component according to Example 19, further comprising an underfill material that at least partially surrounds the conductive pillar, wherein a portion of the underfill material located between the die and the substrate is in the same plane as the conductive pillar.

[0138] Example 21 provides a microelectronic component according to Example 20, wherein the underfill material is a first underfill material, and wherein the microelectronic component further includes a second underfill material located between the die and the interposer.

[0139] Example 22 provides a microelectronic component according to Example 1, wherein the die is coupled to a second conductive contact via a first conductive post, the conductive bump including a second conductive post (e.g., wherein the first conductive contact is recessed in the dielectric material of the RDL of the interposer), a side of the die opposite to the interposer is at a predetermined distance from the first surface, and one of the second conductive posts has a height less than the distance.

[0140] Example 23 provides a microelectronic component according to Example 22, further comprising: a substrate located below the interposer and the die; a fourth conductive contact disposed on the substrate; and a solder bump located between the fourth conductive contact and the second conductive post and coupled to the fourth conductive post.

[0141] Example 24 provides a microelectronic assembly according to any one of Examples 22-23, wherein the die and the solder bump are in the same plane.

[0142] Example 25 provides a microelectronic component according to any one of Examples 22-24, further comprising a solder cap located between and coupled to the posts and the solder bumps in the conductive posts and the solder bumps.

[0143] Example 26 provides a microelectronic component according to Example 25, further comprising an interface located between the solder cap and the solder bump.

[0144] Example 27 provides a microelectronic component according to any one of Examples 19-26, further comprising a solder resist layer disposed on the substrate, wherein the fourth conductive contact is located in an opening in the solder resist layer.

[0145] Example 28 provides a microelectronic component according to Example 27, further comprising an underfill material located between the die and the substrate, wherein a portion of the underfill material is located between the solder resist and the die and is in contact with the solder resist and the die.

[0146] Example 29 provides a microelectronic component according to Example 27, further comprising an underfill material located between the die and the substrate, wherein a portion of the underfill material is coplanar with the solder resist layer and contacts the substrate and the die.

[0147] Example 30 provides a microelectronic component according to Example 29, wherein the face of the die is coplanar with the solder resist layer.

[0148] Example 31 provides a microelectronic component according to any one of Examples 27-30, wherein the solder resist layer has a thickness in the range of 35 micrometers to 50 micrometers.

[0149] Example 32 provides a microelectronic component according to any one of Examples 27-30, further comprising: an underfill material located between the interposer and the solder resist layer; and an insulating material layer (e.g., a dry resist film) located between the solder resist layer and the underfill material.

[0150] Example 33 provides a microelectronic component according to Example 32, wherein the die is coplanar with one or both of the insulating material layer and the solder resist layer.

[0151] Example 34 provides a microelectronic component according to any one of Examples 32-33, wherein the insulating material layer (e.g., a dry resist film) has a first thickness in the range of 15 micrometers to 30 micrometers, and the solder resist layer has a second thickness in the range of 15 micrometers to 30 micrometers.

[0152] Example 35 provides a microelectronic component comprising: an interposer including a first dielectric material layer (e.g., a first RDL) and a second dielectric material layer (e.g., a second RDL) on the first layer; a first die located between the first layer and the second layer; a second die located between the first layer and the second layer and coplanar with the first die; an insulating material (e.g., a molding material) at least partially surrounding the first die and the second die and located between the first die and the second die; and a conductive post passing through the dielectric material between the first layer and the second layer (e.g., extending between the first layer and the second layer), wherein the conductive post is located between the first die and the second die and is coplanar with the first die and the second die.

[0153] Example 36 provides a microelectronic component according to Example 35, further comprising conductive interconnects (e.g., conductive bumps, pillars, etc.) located between the first die and the second layer of the interposer, wherein the insulating material at least partially surrounds the conductive interconnects.

[0154] Example 37 provides a microelectronic component according to any one of Examples 35-36, wherein the conductive interconnect between the first die and the interposer is confined to the region between the first die and the second layer of the interposer (e.g., there may be no electrical / signal interconnect between the bottom of the die and the bottom layer of the interposer).

[0155] Example 38 provides a microelectronic assembly according to any one of Examples 35-37, wherein the region between the first die and the first layer of the interposer includes a continuous portion of the insulating material (e.g., a molding material exists between the die and the bottom layer of the interposer).

[0156] Example 39 provides a microelectronic component according to any one of Examples 35-38, wherein the conductive pillar is a first conductive pillar, and wherein the microelectronic component further includes a second conductive pillar passing through the insulating material between the first layer and the second layer, wherein the first die is located between the first conductive pillar and the second conductive pillar.

[0157] Example 40 provides a microelectronic assembly according to Example 39, wherein the first die includes four sides, the four sides including a first side, a second side opposite to the first side, a third side and a fourth side opposite to the third side, a first conductive post adjacent to the first side, a second conductive post adjacent to the second side, a third conductive post adjacent to the third side and a fourth conductive post adjacent to the fourth side.

[0158] Example 41 provides a microelectronic component according to any one of Examples 35-40, further comprising an adhesive film (e.g., a die attachment film) located between the first layer of the interposer and the first die.

[0159] Example 42 provides a microelectronic component according to any one of Examples 35-41, wherein the first die includes a first interconnect die and the second die includes a second interconnect die.

[0160] Example 43 provides a microelectronic component according to any one of Examples 35-41, wherein the first die includes a first capacitor and the second die includes a second capacitor.

[0161] Example 44 provides a microelectronic component comprising: a substrate; an interposer disposed on the substrate; conductive interconnects (e.g., bumps, pillars, etc.) located between and coupled to the substrate and the interposer; one or more first dies disposed on and coupled to the first side (e.g., the front side) of the interposer; and a second die located below and coupled to a second side of the interposer opposite to the first side, wherein the second die is located between the substrate and the interposer, and conductive contacts on the second die are confined to the side of the second die facing the second side of the interposer.

[0162] Example 45 provides a microelectronic assembly according to Example 44, wherein the conductive interconnect includes one or both of conductive bumps and conductive pillars, and the second die is coplanar with the conductive interconnect.

[0163] Example 46 provides a microelectronic component according to any one of Examples 44-45, further comprising a third die located below and bonded to the second side of the interposer, wherein one or more of the conductive interconnects are located between the second die and the third die.

[0164] Example 47 provides a microelectronic component according to any one of Examples 44-46, wherein the conductive interconnects are arranged around two or more edges of the second die.

[0165] Example 48 provides a microelectronic component according to any one of Examples 44-47, wherein the conductive interconnect is a first conductive interconnect, and wherein the microelectronic component further includes a second conductive interconnect located between and coupled to the second side of the second die and the second side of the interposer.

[0166] Example 49 provides a microelectronic component according to Example 48, further comprising an air gap that is coplanar with the second conductive interconnect and located between the second die and the second side of the interposer.

[0167] Example 50 provides a microelectronic component according to Example 48, further comprising an underfill material that is coplanar with the second conductive interconnect and located between the second die and the second side of the interposer.

[0168] Example 51 provides a microelectronic component according to any one of Examples 44-50, further comprising an air gap located between the second die and the substrate.

[0169] Example 52 provides a microelectronic component according to any one of Examples 44-50, further comprising an underfill material located between the second die and the substrate.

[0170] Example 53 provides a microelectronic component according to any one of Examples 44-52, further comprising a molding material that at least partially surrounds the second die, wherein the conductive interconnects include conductive pillars extending through the molding material.

[0171] Example 54 provides a microelectronic component according to Example 53, further comprising a conductive bump that is substantially aligned with and located between the conductive post and the substrate.

[0172] Example 55 provides a microelectronic component according to Example 54, further comprising an underfill material that at least partially surrounds the conductive bump and is located between the substrate and the molding material.

[0173] Example 56 provides a microelectronic component according to Example 44, wherein the substrate includes a recessed region and the second die is in the recessed region.

[0174] Example 57 provides a microelectronic component according to Example 56, further comprising an adhesive material between the second die and the substrate.

[0175] Example 58 provides a microelectronic assembly according to any one of Examples 56-57, wherein the substrate has a first substrate side facing the interposer, and the second side of the second die facing the interposer lies in a plane substantially the same as the first substrate side (e.g., the top of the die may be substantially flush with the top of the substrate).

[0176] Example 59 provides a microelectronic component according to any one of Examples 56-58, further comprising an underfill material that at least partially surrounds the conductive interconnect and is located between the second side of the interposer and the substrate.

[0177] Example 60 provides a microelectronic assembly according to Example 59, wherein the recessed region includes a portion of the underfill material located between the insulating material of the second die and the substrate (e.g., underfill material is present around the die in the recessed region).

[0178] Example 61 provides a microelectronic component according to any one of Examples 59-60, further comprising a solder resist material disposed on the first substrate side, wherein the conductive contacts on the second die are coplanar with the solder resist material.

[0179] Example 62 provides a microelectronic component according to any one of Examples 1-61, wherein the microelectronic component includes a central processing unit or a portion thereof.

[0180] Example 63 provides a microelectronic component according to any one of Examples 1-62, wherein the microelectronic component includes or is part of a memory device.

[0181] Example 64 provides a microelectronic component according to any one of Examples 1-63, wherein the microelectronic component includes or is part of a logic circuit.

[0182] Example 65 provides a microelectronic component according to any one of Examples 1-64, wherein the microelectronic component includes or is part of an input / output circuit.

[0183] Example 66 provides a microelectronic component according to any one of Examples 1-65, wherein the microelectronic component includes or is part of a field-programmable gate array transceiver.

[0184] Example 67 provides a microelectronic component according to any one of Examples 1-66, wherein the microelectronic component includes or is part of a field-programmable gate array (FPGA) logic.

[0185] Example 68 provides a microelectronic component according to any one of Examples 1-67, wherein the microelectronic component includes or is part of a power delivery circuit.

[0186] Example 69 provides an IC package comprising a microelectronic component according to any one of Examples 1-68.

[0187] Example 70 provides an IC package according to Example 69, which also includes another IC component coupled to the microelectronic component.

[0188] Example 71 provides an IC package according to Example 70, wherein another IC component includes a package substrate.

[0189] Example 72 provides an IC package according to Example 70, wherein another IC component includes an interposer layer.

[0190] Example 73 provides an IC package according to Example 70, wherein the other IC component includes another component or another die.

[0191] Example 74 provides a computing device including a carrier substrate and a component coupled to the carrier substrate, wherein the component is a component according to any one of Examples 1-68, or the component is included in an IC package according to any one of Examples 69-73.

[0192] Example 75 provides a computing device according to Example 74, wherein the computing device is a wearable or handheld computing device.

[0193] Example 76 provides a computing device according to Example 74 or 75, wherein the computing device further includes one or more communication chips.

[0194] Example 77 provides a computing device according to any one of Examples 74-76, wherein the computing device further includes an antenna.

[0195] Example 78 provides a computing device according to any one of Examples 74-77, wherein the carrier substrate is a motherboard.

[0196] The above description of the embodiments shown in this disclosure, including the content described in the abstract, is not intended to be exhaustive or to limit this disclosure to the precise forms disclosed. While specific embodiments and examples of this disclosure have been described herein for illustrative purposes, those skilled in the art will recognize that various equivalent modifications are possible within the scope of this disclosure. These modifications can be made to this disclosure based on the above detailed description.

Claims

1. A microelectronic component, comprising: An intermediary layer comprising two or more interconnect layers, wherein the intermediary layer has a first side and a second side opposite to the first side, wherein: The first surface includes a first conductive contact and a second conductive contact, and The second surface includes a third conductive contact; Conductive bumps, which are coupled to the first conductive contact; and The die is located in the same layer as the conductive bump and is coupled to the second conductive contact.

2. The microelectronic component according to claim 1, wherein: The conductive bump includes a first conductive bump and a second conductive bump that is coplanar with the first conductive bump, and The die is located between the first conductive bump and the second conductive bump.

3. The microelectronic component according to claim 2, wherein: The die includes four sides: a first side, a second side opposite to the first side, a third side, and a fourth side opposite to the third side. The first conductive bump is adjacent to the first side, and the second conductive bump is adjacent to the second side. The conductive bumps also include a third conductive bump and a fourth conductive bump, and The third conductive bump is adjacent to the third side, and the fourth conductive bump is adjacent to the fourth side.

4. The microelectronic component according to claim 1, wherein the conductive bump is a first conductive bump, and wherein the microelectronic component further comprises: A second conductive bump is located between the die and the second conductive contact and is coupled to the die and the second conductive contact; as well as A gap, which is in the same plane as the second conductive bump and located between the first surface and the die, wherein the plane is substantially parallel to the interlayer.

5. The microelectronic component according to claim 1, wherein the conductive bump is a first conductive bump, and wherein the microelectronic component further comprises: A second conductive bump is located between the die and the second conductive contact and is coupled to the die and the second conductive contact; as well as A dielectric material, which is in the same plane as the second conductive bump and located between the first surface and the die, wherein the plane is substantially parallel to the interlayer.

6. The microelectronic component according to claim 1, further comprising: A substrate, comprising a fourth conductive contact coupled to the conductive bump; as well as An air gap is located between the die and the substrate.

7. The microelectronic component according to claim 1, further comprising: A substrate, comprising a fourth conductive contact coupled to the conductive bump; as well as A continuous portion of dielectric material located between the die and the substrate, wherein there are no conductive interconnects in the continuous portion of the dielectric material.

8. The microelectronic component according to any one of claims 1-7, wherein: The die includes a first die surface and a second die surface opposite to the first die surface, and The die lacks a through hole extending from the first die surface to the second die surface.

9. The microelectronic component according to any one of claims 1-7, wherein the die is a first die, and wherein the microelectronic component further comprises: The second die is coplanar with the first die, wherein: One or more of the conductive bumps are located between the first die and the second die in the layer.

10. The microelectronic component according to any one of claims 1-7, wherein: The die and the conductive bump are in the same plane, wherein the plane is substantially parallel to the interlayer.

11. The microelectronic component according to any one of claims 1-7, further comprising: A dielectric material, which at least partially surrounds the die; as well as A conductive post passes through the dielectric material, wherein the conductive post is located between a conductive bump of the conductive bumps and a conductive interconnect of the interposer layer and is coupled to the conductive bump of the conductive bumps and the conductive interconnect of the interposer layer, wherein: The die and the conductive post are in the same plane, and The plane is substantially parallel to the intermediate layer.

12. The microelectronic component according to any one of claims 1-7, wherein: The die is coupled to the second conductive contact via a first conductive post. The conductive bump includes a second conductive post. The side of the die facing away from the interlayer is at a predetermined distance from the first surface, and The height of one of the second conductive pillars is greater than the distance.

13. The microelectronic component according to claim 12, further comprising: A substrate located below the interposer and the die; A fourth conductive contact is disposed on the substrate, wherein the conductive post is located between and coupled to both the first and fourth conductive contacts; and A welding cap is located between the conductive post and the fourth conductive contact.

14. The microelectronic component according to claim 13, further comprising: A bottom filler material, which at least partially surrounds the conductive pillar, wherein: A portion of the bottom filler material located between the die and the substrate is in the same plane as the conductive post.

15. The microelectronic component of claim 14, wherein the underfill material is a first underfill material, and wherein the microelectronic component further comprises: A second bottom filler material is located between the core and the interlayer.

16. The microelectronic component according to any one of claims 1-7, wherein: The die is coupled to the second conductive contact via a first conductive post. The conductive bump includes a second conductive post. The side of the die facing away from the interlayer is at a predetermined distance from the first surface, and The height of one of the second conductive pillars is less than the distance.

17. The microelectronic component according to claim 16, further comprising: A substrate located below the interposer and the die; A fourth conductive contact is disposed on the substrate; as well as A solder bump is located between the fourth conductive contact and the second conductive post and is coupled to the fourth conductive contact and the second conductive post.

18. The microelectronic component according to any one of claims 17, wherein: The die and the solder bump are in the same plane.

19. The microelectronic component according to any one of claims 16, further comprising: A solder cap is located between the post in the conductive post and the solder bump in the solder bump and is coupled to the post and the solder bump; as well as The interface is located between the solder cap and the solder bump.

20. A microelectronic component, comprising: An interposer layer, the interposer layer comprising a first layer formed of a dielectric material and a second layer formed of the dielectric material on the first layer; The first die is located between the first layer and the second layer; The second die is located between the first layer and the second layer and is coplanar with the first die; An insulating material, said insulating material at least partially surrounding the first die and the second die and located between the first die and the second die; as well as A conductive post that passes through the dielectric material between the first layer and the second layer, wherein the conductive post is located between the first die and the second die and is coplanar with the first die and the second die.

21. The microelectronic component according to claim 20, wherein: The conductive interconnect between the first die and the interposer is confined to the region between the first die and the second layer of the interposer.

22. The microelectronic component according to claim 20, further comprising: An adhesive film, which is in the same plane as the conductive post and located between the first layer of the interlayer and the first die, wherein the plane is substantially parallel to the interlayer.

23. A microelectronic component, comprising: substrate; An intermediate layer is disposed on the substrate; A conductive interconnect is located between the substrate and the interposer and is coupled to the substrate and the interposer; One or more first dies are located above and bonded to the first side of the interposer layer; as well as The second die is located below and bonded to the second side of the interposer, opposite to the first side, wherein: The second die is located between the substrate and the interposer layer, and The conductive contacts on the second die are restricted to the second side of the second die facing the second side of the interlayer.

24. The microelectronic component of claim 23, wherein: The conductive interconnect includes one or both of conductive bumps and conductive pillars, and The second die is coplanar with the conductive interconnect.

25. The microelectronic component of claim 23, wherein: The substrate includes a recessed region, and The second die is located in the recessed region.

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