Stripping semiconductor processing

Abstract

This disclosure generally relates to a subtractive semiconductor process, for example, for a bipolar junction transistor (BJT). In an example, a semiconductor layer stack is formed over a semiconductor substrate (102). The semiconductor layer stack includes a first semiconductor layer (122) over the semiconductor substrate (102), a second semiconductor layer (124) over the first semiconductor layer (122), and a third semiconductor layer (126) over the second semiconductor layer (124). The first and third semiconductor layers (122, 126) have the same conductivity type, and the second semiconductor layer (124) has a conductivity type opposite to that of the first and third semiconductor layers (122, 126). The semiconductor layer stack is patterned into a first mesa (202). The first mesa (202) forms the emitter of the BJT. The semiconductor layer stack is patterned into a second mesa (402). The second mesa (402) extends laterally from the first mesa (202). The first mesa (202) is above the second mesa (402). The second mesa (402) forms the base of the BJT.

Description

Technical Field

[0001] This disclosure generally relates to reduction-layer semiconductor processing. Background Technology

[0002] Semiconductor processing for manufacturing integrated circuits (ICs) can involve numerous processing steps. ICs may contain diverse devices that may require unique processing for each type of device. Integrating the processing of these devices into a stream can result in implementing many processing steps. Performing these processing steps on a finished IC die can be costly. Summary of the Invention

[0003] This invention is provided to introduce a simplified series of disclosed concepts, which will be further described below in specific embodiments, including the provided drawings. Various disclosed apparatuses and methods can be advantageously applied in the context of semiconductor processing for manufacturing integrated circuits (ICs). Some examples described herein can be applied to the manufacture of ICs comprising one or more bipolar junction transistors (BJTs). While such examples are contemplated to achieve a reduced number of processing steps, reduced manufacturing time and cost, and / or improved isolation and leakage characteristics, specific results are not required unless expressly stated in the particular claims.

[0004] The example described herein is a method for manufacturing an IC. A semiconductor layer stack is formed over a semiconductor substrate. The semiconductor layer stack includes a first semiconductor layer over the semiconductor substrate, a second semiconductor layer over the first semiconductor layer, and a third semiconductor layer over the second semiconductor layer. The first and third semiconductor layers have the same conductivity type, and the second semiconductor layer has a conductivity type opposite to that of the first and third semiconductor layers. The semiconductor layer stack is patterned in a region to form a first mesa. The first mesa forms the emitter of a BJT. The semiconductor layer stack is patterned in the region to form a second mesa. The second mesa extends laterally from the first mesa. The first mesa is above the second mesa. The second mesa forms the base of the BJT.

[0005] Another example described herein is a method for manufacturing an IC. A first epitaxial layer is formed over a semiconductor substrate. The first epitaxial layer has a first conductivity type. A second epitaxial layer is formed over the first epitaxial layer. The second epitaxial layer has a second conductivity type opposite to the first conductivity type. A third epitaxial layer is formed over the second epitaxial layer. The third epitaxial layer has the first conductivity type. The third epitaxial layer is etched to form an emitter layer of a BJT in a region. The second epitaxial layer is etched to form a base layer of the BJT in the region. The emitter layer is over the base layer. The base layer extends laterally from the emitter layer.

[0006] Another example described herein is an integrated circuit (IC). The IC includes a semiconductor substrate, a base-joint device (BJT), and a conformal dielectric layer. The BJT comprises a semiconductor layer stack above the semiconductor substrate. The semiconductor layer stack includes a base semiconductor layer above the semiconductor substrate and an emitter semiconductor layer above the base semiconductor layer. The base semiconductor layer extends laterally from the emitter semiconductor layer. The conformal dielectric layer is on the semiconductor layer stack and is located in a recess in the semiconductor substrate.

[0007] Another example described herein is a method for manufacturing an IC. Forming a BJT (Browser Joint Transformer). Forming the BJT includes forming a semiconductor layer stack over a semiconductor substrate. Forming the semiconductor layer stack includes forming a base semiconductor layer over the semiconductor substrate and an emitter semiconductor layer over the base semiconductor layer. The base semiconductor layer extends laterally from the emitter semiconductor layer. A conformal dielectric layer is formed on the semiconductor layer stack and in a notch in the semiconductor substrate.

[0008] The foregoing summary provides a fairly broad overview of various features of the embodiments of this disclosure in order to better understand the following detailed description. Additional features and advantages of such embodiments will be described below. The described embodiments can be readily used as a basis for modifying or designing other embodiments within the scope of this disclosure. Attached Figure Description

[0009] To understand the above features in detail, please refer to the following detailed description in conjunction with the accompanying drawings.

[0010] Figures 1 to 8 These are cross-sectional views of integrated circuits (ICs) during the corresponding manufacturing stages, based on some examples.

[0011] The drawings and accompanying detailed description are provided for understanding the features of various examples and do not limit the scope of the appended claims. Examples illustrated in the drawings and described in the accompanying detailed description can be readily used as a basis for modifying or designing other examples within the scope of this disclosure. Where possible, the same reference numerals may be used to refer to the same elements common to each drawing. The drawings are drawn to clearly illustrate the relevant elements or features and are not necessarily drawn to scale. Detailed Implementation

[0012] Various features will be described below with reference to the diagrams. The illustrated examples may not possess all aspects or advantages shown. Aspects or advantages described in connection with a particular example are not necessarily limited to that example and can be practiced in any other example, even if not so stated or explicitly described. Furthermore, the methods described herein may be described with a specific order of operations, but other methods according to other examples may be implemented with various other orders of operations (e.g., different serial or parallel executions involving various operations). In the following discussion, doping levels may be described using quantitative and / or qualitative terms, where less than 1 x 10⁻⁶ is used. 16 cm -3 The doping level is lightly doped, at 1x10⁻⁶. 16 cm -3 With 1x10 18 cm -3 The doping level is moderate, at 1x10 18 cm -3 With 1x10 20 cm -3 The doping levels between them are heavily doped and higher than 1x10. 20 cm -3 The doping level is extremely heavy doping. The doping level at the boundaries of these ranges can be qualitatively referred to by either terminology indicating a higher or lower range.

[0013] This disclosure generally, but not exclusively, relates to subtractive semiconductor processing, for example, for bipolar junction transistors (BJTs). In some instances, a semiconductor layer stack comprising multiple semiconductor layers is formed over a semiconductor substrate. The semiconductor layer stack is patterned into a first mesa and a second mesa. The first mesa is above the second mesa, and the second mesa extends laterally from the first mesa. The first and second mesa form corresponding components of the BJT. The examples described herein avoid some processing steps and allow for process flows containing fewer processing steps than some baseline methods, which can reduce manufacturing time and cost. Additionally, improved isolation and leakage characteristics can be achieved in devices formed using the semiconductor processing described herein. Other benefits or advantages can be achieved through various examples.

[0014] Figures 1 to 8 These are cross-sectional views of integrated circuits (ICs) during the respective manufacturing stages, based on some examples. (Reference) Figure 1 A semiconductor substrate 102 is provided. The semiconductor substrate 102 may be or comprise a bulk wafer, a semiconductor-on-insulator (SOI) substrate, etc. The semiconductor substrate 102 may be or comprise any semiconductor material, such as silicon (Si), silicon germanium (SiGe), gallium arsenide (GaAs), etc., or combinations thereof, and may comprise bulk material (e.g., bulk silicon). In some examples, the semiconductor substrate 102 may have a concentration of about 1 × 10⁻⁶. 14 cm -3 Up to approximately 5×10 15 cm -3 The p-type dopant (e.g., boron (B)) within the range is p-doped, for example, lightly doped. The semiconductor substrate 102 includes a first device region 104, a second device region 106, a third device region 108, a fourth device region 110, and a fifth device region 112. Corresponding devices are formed in device regions 104 to 112, as shown subsequently.

[0015] A semiconductor layer stack is formed over (e.g., on) a semiconductor substrate 102. In the illustrated example, the semiconductor layer stack is a three-layer stack. The semiconductor layer stack includes a first semiconductor layer 122 over the semiconductor substrate 102, a second semiconductor layer 124 over the first semiconductor layer 122, and a third semiconductor layer 126 over the second semiconductor layer 124. In some examples, semiconductor layers 122 to 126 are corresponding epitaxial semiconductor layers. In some examples, each of semiconductor layers 122 to 126 is or contains the same semiconductor material as the semiconductor substrate 102 on which the semiconductor layer stack is formed. For example, each of semiconductor layers 122 to 126 may be primarily silicon and may contain dopants as described elsewhere. In other examples, semiconductor layers 122 to 126 may contain different semiconductor materials.

[0016] The first semiconductor layer 122 and the third semiconductor layer 126 may have the same conductivity type (e.g., doped with the same dopant type). The second semiconductor layer 124 has a conductivity type opposite to that of the first semiconductor layer 122 and the third semiconductor layer 126 (e.g., doped with the same dopant type). For example, the first semiconductor layer 122 and the third semiconductor layer 126 are doped with an n-type dopant (e.g., phosphorus (P) or arsenic (As)), and the second semiconductor layer 124 is doped with a p-type dopant (e.g., boron (B)). In some instances, the first semiconductor layer 122 is doped with a concentration of approximately 1 × 10⁻⁶. 15 cm -3 Up to approximately 5×10 18 cm -3The range of n-type dopants, from lightly to heavily doped, is considered; the second semiconductor layer 124 is doped with a concentration of approximately 1 × 10⁻⁶. 13 cm -3 Up to approximately 5×10 15 cm -3 p-type dopant within the range, such as light doping; and the third semiconductor layer 126 is doped with a concentration of approximately 1 × 10⁻⁶. 15 cm -3 Up to approximately 1×10 20 cm -3 The range of n-type dopants, from lightly to heavily doped, is acceptable. Other dopant concentrations may be implemented, and the conductivity types of semiconductor layers 122 to 126 may differ (e.g., opposite to the conductivity types described in a particular example).

[0017] In some instances, the thickness of the first semiconductor layer 122 may be greater than the thickness of the second semiconductor layer 124 and the thickness of the third semiconductor layer 126, and the thickness of the third semiconductor layer 126 may be greater than the thickness of the second semiconductor layer 124. The thickness of the layers is typically in a direction orthogonal to the surface on which the layers are formed. In some instances, the thickness of the first semiconductor layer 122 is in the range of 8 μm to 10 μm (e.g., 9 μm); the thickness of the second semiconductor layer 124 is in the range of 0.5 μm to 2 μm (e.g., 1 μm); and the thickness of the third semiconductor layer 126 is in the range of 1 μm to 3 μm (e.g., 2 μm). Other thicknesses of the semiconductor layers 122 to 126 may be implemented.

[0018] Semiconductor layers 122 to 126 can be formed using epitaxial growth processes, such as low-pressure chemical vapor deposition (LPCVD), reduced-pressure chemical vapor deposition (RPCVD), and metal-organic chemical vapor deposition (MOCVD). Semiconductor layers 122 to 126 can be doped in situ during epitaxial growth using dopant types and concentrations as described above.

[0019] refer to Figure 2 The semiconductor layers are stacked and patterned to form the first device mesa 202 in the first device region 104 and the fifth device mesa 204 in the fifth device region 112. For example... Figure 2As shown, a third semiconductor layer 126 is patterned and removed (e.g., etched through) from the exterior of the first mesa 202 and the fifth mesa 204 of the first device, and may further remove an upper portion of the second semiconductor layer 124 in the region where the third semiconductor layer 126 has been removed. In the illustrated example, the first mesa 202 of the first device includes a first patterned third semiconductor layer 126a patterned from the third semiconductor layer 126, and the fifth mesa 204 includes a second patterned third semiconductor layer 126b patterned from the third semiconductor layer 126. The first mesa 202 and the fifth mesa 204 of the first device may further include upper portions of the second semiconductor layer 124 below the patterned third semiconductor layers 126a and 126b, respectively. The semiconductor layer stack can be patterned using appropriate photolithography and etching (e.g., reactive ion etching (RIE)) processes.

[0020] refer to Figure 3 A base contact region 302 in a first device region 104, an emitter region 304 in a second device region 106, and a collector region 306 and an emitter region 308 in a third device region 108 are formed in the semiconductor layer stack. The base contact region 302 is located on the opposite side of the first mesa 202 of the first device (e.g., the first patterned third semiconductor layer 126a) in the second semiconductor layer 124. Similarly, the emitter region 304, collector region 306, and emitter region 308 are located in the second semiconductor layer 124. Regions 302 to 308 have the same conductivity type as the second semiconductor layer 124 and the opposite conductivity type to the first semiconductor layer 122. In some instances, regions 302 to 308 are doped with a p-type dopant at a concentration greater than that of the p-type dopant in the second semiconductor layer 124. For example, the base contact region 302 is doped with a concentration of approximately 1 × 10⁻⁶ p-type dopant. 18 cm -3 Up to approximately 1×10 20 cm -3 Doping with p-type dopant within the range, such as heavy doping; the emitter region 304 uses a concentration of approximately 1 × 10⁻⁶. 18 cm -3 Up to approximately 1×10 20 cm -3 Doping with p-type dopant within the range, for example, heavy doping; collector region 306 is doped with a concentration of approximately 1 × 10⁻⁶. 16 cm -3 Up to approximately 1×10 18 cm -3 Doping with p-type dopant within the range, for example, moderate doping; and the emitter region 308 is doped with a concentration of approximately 1 × 10⁻⁶. 18 cm -3 Up to approximately 1×10 20 cm -3The region is doped with p-type dopant within the specified range, for example, heavily doped. Regions 302 to 308 can be formed using photolithography and implantation processes. In some instances, the same implantation process can be used to form regions 302 to 308, or a different implantation process can be used to form the base contact region 302. A diffusion process can be performed after implantation to diffuse the dopant in the semiconductor layer stack. The diffusion process can be a thermal process, such as annealing (e.g., rapid thermal annealing (RTA)).

[0021] refer to Figure 4 The semiconductor layer stack is patterned to form a first device second mesa 402 in the first device region 104, a second device mesa 404 in the second device region 106, and a third device mesa 406 in the third device region 108, and a fifth device mesa 204 is extended into the semiconductor layer stack. Figure 4 As shown, a second semiconductor layer 124 is patterned and removed (e.g., etched through) from the exterior of the second mesa 402, second mesa 404, third mesa 406, and fifth mesa 204 of the first device, and may further remove the upper portion of the first semiconductor layer 122 in the region where the second semiconductor layer 124 is removed. In the illustrated example, the second mesa 402 of the first device includes a first patterned second semiconductor layer 124a patterned from the second semiconductor layer 124; the second mesa 404 includes a second patterned second semiconductor layer 124b patterned from the second semiconductor layer 124; the third mesa 406 includes a third patterned second semiconductor layer 124c patterned from the second semiconductor layer 124; and the fifth mesa 204 further includes a fourth patterned second semiconductor layer 124d patterned from the second semiconductor layer 124. The first device second mesa 402, the second device mesa 404, the third device mesa 406 and the fifth device mesa 204 may further include the upper portion of the first semiconductor layer 122 below the patterned second semiconductor layers 124a, 124b, 124c, 124d, respectively.

[0022] The second mesa 402 of the first device is below and extends laterally from the first mesa 202 of the first device. The second mesa 402 includes a base contact region 302 on a laterally opposite side of the first mesa 202 (e.g., a first patterned third semiconductor layer 126a). The second mesa 404 includes an emitter region 304. The second mesa 404 may have a smaller than... Figure 3 The lateral dimension of the emitter region 304 formed in the middle allows the patterning of the second device stage 404 to be removed. Figure 3Some emitter regions 304 are formed in the middle. The third device mesa 406 includes a collector region 306 and an emitter region 308. In some instances, further extending the fifth device mesa 204 through the second semiconductor layer 124 can form another mesa, such that a fourth patterned second semiconductor layer 124d extends laterally from the fifth device mesa 204 (e.g., a second patterned third semiconductor layer 126b), for example, through misalignment of a photomask. The semiconductor layer stack can be patterned using appropriate photolithography and etching (e.g., RIE) processes.

[0023] refer to Figure 5 The collector contact region 502 in the first device region 104, the base contact region 504 in the second device region 106, the base contact region 506 and the base region 508 in the third device region 108, and the Zener region 510 in the fourth device region 110 are formed in a semiconductor layer stack. The collector contact region 502 extends into the semiconductor substrate 102 in the first semiconductor layer 122 and on the opposite side of the first device second mesa 402 (e.g., the first patterned second semiconductor layer 124a). The collector contact region 502 may further include a corresponding portion of itself in the first semiconductor layer 122 at a corresponding sidewall of the first semiconductor layer 122, the corresponding portion forming part of the first device second mesa 402. The base contact region 504 extends into the semiconductor substrate 102 in the first semiconductor layer 122 and on the opposite side of the second device mesa 404 (e.g., the second patterned second semiconductor layer 124b). The base contact region 506 is in the first semiconductor layer 122 and extends laterally into the first semiconductor layer 122 adjacent to the third device mesa 406 (e.g., the third patterned second semiconductor layer 124c). The base region 508 is in the third patterned second semiconductor layer 124c and extends laterally into the first semiconductor layer 122 between the collector region 306 and the emitter region 308. In some embodiments, the base region 508 may be omitted. The Zener region 510 is in the first semiconductor layer 122 and extends into the semiconductor substrate 102.

[0024] Regions 502 to 510 have the same conductivity type as the first semiconductor layer 122 and the opposite conductivity type to that of the second semiconductor layer 124 and the semiconductor substrate 102. In some instances, regions 502 to 510 are doped with an n-type dopant at a concentration greater than that of the n-type dopant in the first semiconductor layer 122. For example, collector contact region 502 is doped with an n-type dopant at a concentration of approximately 1 × 10⁻⁶. 18 cm -3 Up to approximately 5×10 20 cm -3 Doping with n-type dopant within a range, such as heavy doping to very heavy doping; the base contact region 504 uses a concentration of approximately 1 × 10⁻⁶. 18 cm -3Up to approximately 5×10 20 cm -3 Doping with n-type dopant within a range, such as heavy doping to very heavy doping; the base contact region 506 uses an concentration of approximately 1 × 10⁻⁶. 18 cm -3 Up to approximately 5×10 20 cm -3 Doping with n-type dopant within a range, such as heavy to very heavy doping; the base region of 508 uses a concentration of approximately 1 × 10⁻⁶. 16 cm -3 Up to approximately 1×10 18 cm -3 The range of n-type dopants is used, for example, moderate doping; and the Zener region 510 is doped with a concentration of approximately 1 × 10⁻⁶. 18 cm -3 Up to approximately 5×10 20 cm -3 The range of n-type dopants is considered, from heavily doped to extremely heavily doped. Regions 502 to 510 can be formed using photolithography and implantation processes, which may include tilted implantation. A diffusion process can be performed after implantation to diffuse the dopants in the semiconductor layer stack and / or semiconductor substrate 102. The diffusion process can be a thermal process, such as annealing (e.g., RTA).

[0025] refer to Figure 6A notch 602 is formed in the semiconductor substrate 102. As shown, the notch 602 is also formed through any remaining layers of the semiconductor layer stack (e.g., the first semiconductor layer 122), where the notch 602 is formed. In the illustrated example, the notch 602 is formed in a first patterned first semiconductor layer 122a (which may form a mesa) formed in a first device region 104 patterned from the first semiconductor layer 122, a second patterned first semiconductor layer 122b (which may form a mesa) formed in a second device region 106 patterned from the first semiconductor layer 122, a third patterned first semiconductor layer 122c (which may form a mesa) formed in a third device region 108 patterned from the first semiconductor layer 122, a fourth patterned first semiconductor layer 122d (which may form a mesa) formed in a fourth device region 110 patterned from the first semiconductor layer 122, and a fifth patterned first semiconductor layer 122e (which may extend the fifth device mesa 204) formed in a fifth device region 112 patterned from the first semiconductor layer 122. The first patterned first semiconductor layer 122a includes at least a corresponding portion of the collector contact region 502. The second patterned first semiconductor layer 122b includes at least a corresponding portion of the base contact region 504. The third patterned first semiconductor layer 122c includes at least a portion of the base contact region 506. The fourth patterned first semiconductor layer 122d includes at least a portion of the Zener region 510. A notch 602 is formed at the periphery of device regions 104 to 112 and laterally between the formed devices. The notch 602 can be formed using suitable photolithography and etching (e.g., RIE) processes.

[0026] refer to Figure 7 A first dielectric layer 702 is formed over a patterned semiconductor layer stack (e.g., on) and in a recess 602 in the semiconductor substrate 102, and a second dielectric layer 704 is formed over the first dielectric layer 702. The first dielectric layer 702 is conformally formed over the patterned semiconductor layer stack and may be referred to as a component conformal dielectric layer or a device conformal dielectric layer. In some instances, the first dielectric layer 702 is formed by an oxidation process (e.g., in-situ vapor generation (ISSG) oxidation, etc.), and in other instances, the first dielectric layer 702 is formed by a deposition process (e.g., chemical vapor deposition (CVD), atomic layer deposition (ALD), etc.). In some instances, when the semiconductor layer stack is or includes silicon and the first dielectric layer 702 is formed by oxidation, the first dielectric layer 702 may be or include an oxide, such as silicon oxide. In some instances, the first dielectric layer 702 may be or include a nitride or other dielectric material.

[0027] The second dielectric layer 704 may be a pre-metal dielectric (PMD), an interlayer dielectric (ILD), an inter-metal dielectric (IMD), or the like. The second dielectric layer 704 may be or contain silicon oxide (e.g., phosphosilicate glass (PSG) or tetraethyl orthosilicate (TEOS) oxide), or combinations thereof. In some instances, the second dielectric layer 704 may be deposited by CVD, such as plasma-enhanced CVD (PECVD). The second dielectric layer 704 may be planarized, for example, by chemical mechanical polishing (CMP).

[0028] refer to Figure 8 Metal contacts 802, 804, 806, 808, 810, 812, 814, 816, 818, 820, 822, and 824 are formed through dielectric layers 702 and 704, and metal lines 832, 834, 836, 838, 840, 842, 844, 846, 848, 850, 852, and 854 and a metal plate 856 are formed above (e.g., on) the second dielectric layer 704. Metal contact 802 contacts the collector contact region 502. Metal contact 804 contacts the base contact region 302. Metal contact 806 contacts the first patterned third semiconductor layer 126a. Therefore, metal contacts 802 to 806 are metal contacts in the first device region 104 for a semiconductor device (e.g., a BJT) and electrically connected to said semiconductor device. Metal contact 808 contacts the base contact region 504. Metal contact 810 contacts emitter region 304. Metal contact 812 contacts semiconductor substrate 102. Therefore, metal contacts 808 to 812 are metal contacts in the second device region 106 for a semiconductor device (e.g., BJT) and electrically connected to said semiconductor device. Metal contact 814 contacts base contact region 506. Metal contact 816 contacts collector region 306. Metal contact 818 contacts emitter region 308. Therefore, metal contacts 814 to 818 are metal contacts in the third device region 108 for a semiconductor device (e.g., BJT) and electrically connected to said semiconductor device. Metal contact 820 contacts semiconductor substrate 102. Metal contact 822 contacts Zener region 510. Therefore, metal contacts 820 and 822 are metal contacts in the fourth device region 110 for a semiconductor device (e.g., diode) and electrically connected to said semiconductor device. Metal contact 824 contacts the second patterned third semiconductor layer 126b. Therefore, metal contact 824 is a metal contact in the fifth device region 112 for a semiconductor device (e.g., a capacitor) and electrically connected to said semiconductor device. Metal lines 832 to 854 are respectively above and in contact with metal contacts 802 to 824. Metal plate 856 is above the second patterned third semiconductor layer 126b, wherein the first dielectric layer 702 and the second dielectric layer 704 are disposed between metal plate 856 and the second patterned third semiconductor layer 126b.

[0029] Metal contacts 802 to 824 may each comprise one or more barrier and / or adhesion layers (e.g., titanium nitride (TiN), tantalum nitride (TaN), etc., or combinations thereof) conformally disposed in corresponding openings through dielectric layers 702, 704, and filler metal (e.g., tungsten (W), copper (Cu), aluminum (Al), etc., or combinations thereof) above and / or on the barrier and / or adhesion layers. Similarly, metal lines 832 to 854 and metal plate 856 may each comprise one or more barrier and / or adhesion layers (e.g., titanium nitride (TiN), tantalum nitride (TaN), etc., or combinations thereof) above the second dielectric layer 704, and filler metal (e.g., tungsten (W), copper (Cu), aluminum (Al), etc., or combinations thereof) above and / or on the barrier and / or adhesion layers. The contact openings may be formed using appropriate photolithography and etching (e.g., RIE) processes. The metals used for the metal contacts 802 to 824, metal lines 832 to 854, and metal plate 856 can be deposited, for example, by CVD, physical vapor deposition (PVD), etc., in the contact openings and over the second dielectric layer 704. The metal over the second dielectric layer 704 can then be patterned into the metal lines 832 to 854 and the metal plate 856 using appropriate photolithography and etching (e.g., RIE) processes.

[0030] The first device region 104 includes a first bipolar junction transistor (BJT), which may be an NPN BJT. Furthermore, the NPN BJT may be a vertical NPN BJT. The first BJT in the first device region 104 includes a first patterned third semiconductor layer 126a as the emitter, a first patterned second semiconductor layer 124a (having a base contact region 302) as the base, and a first patterned first semiconductor layer 122a (having a collector contact region 502) as the collector. A first dielectric layer 702 is conformally fitted to the first patterned first semiconductor layer 122a, the first patterned second semiconductor layer 124a, and the first patterned third semiconductor layer 126a. For example, the first dielectric layer 702 is on the sidewalls and top surface of the first patterned first semiconductor layer 122a, the first patterned second semiconductor layer 124a, and the first patterned third semiconductor layer 126a. The first dielectric layer 702 is further defined on the sidewalls and bottom surface of a recess 602 in the semiconductor substrate 102, the recess being located at the periphery of the first BJT.

[0031] The second device region 106 includes a second BJT, which may be a PNP BJT. Furthermore, the PNP BJT may be a vertical PNP BJT. The second BJT in the second device region 106 includes a second patterned second semiconductor layer 124b having an emitter region 304 as an emitter, a second patterned first semiconductor layer 122b (having a base contact region 504) as a base, and a portion (e.g., a p-doped portion or region) of a semiconductor substrate 102 serving as a collector (e.g., electrically contacted via metal contacts 812). A first dielectric layer 702 is conformally fitted to the second patterned first semiconductor layer 122b and the second patterned second semiconductor layer 124b. For example, the first dielectric layer 702 is on the sidewalls and top surfaces of the second patterned first semiconductor layer 122b and the second patterned second semiconductor layer 124b. The first dielectric layer 702 further defines a notch 602 in the semiconductor substrate 102 on the sidewalls and bottom surfaces, the notch being located at the periphery of the second BJT.

[0032] The third device region 108 includes a third BJT, which may be a PNP BJT. Furthermore, the PNP BJT may be a lateral PNP BJT. The third BJT in the third device region 108 includes an emitter region 308 as an emitter, a base region 508 as a base, and a collector region 306 as a collector. The first dielectric layer 702 is conformally fitted to the third patterned first semiconductor layer 122c and the third patterned second semiconductor layer 124c. For example, the first dielectric layer 702 is on the sidewalls and top surfaces of the third patterned first semiconductor layer 122c and the third patterned second semiconductor layer 124c. The first dielectric layer 702 is further on the sidewalls and bottom surfaces of a recess 602 defined in the semiconductor substrate 102, the recess being located at the periphery of the third BJT.

[0033] The fourth device region 110 includes a diode, which may further be a Zener diode. The diode in the fourth device region 110 includes a fourth patterned first semiconductor layer 122d having a Zener region 510 as a cathode and a portion (e.g., a p-doped portion or region) of a semiconductor substrate 102 as an anode (e.g., electrically contacted via metal contacts 820). A first dielectric layer 702 is conformally fitted to the fourth patterned first semiconductor layer 122d. For example, the first dielectric layer 702 is on the sidewalls and upper surface of the fourth patterned first semiconductor layer 122d. The first dielectric layer 702 is further on the sidewalls and bottom surface defining a recess 602 in the semiconductor substrate 102, the recess being located at the periphery of the diode.

[0034] The fifth device region 112 includes a capacitor. The capacitor in the fifth device region 112 includes a second patterned third semiconductor layer 126b as a base and a metal plate 856 as a top plate. Any semiconductor layers 122e, 124d, 126b in the fifth device mesa 204 can form a base with any overlying semiconductor layers removed. The combined thickness of the dielectric layers 702, 704 between the base and top plates can be tuned using different semiconductor layers of the fifth device mesa 204 to achieve the target capacitance of the capacitor. The first dielectric layer 702 is conformal to the fifth patterned first semiconductor layer 122e, the fourth patterned second semiconductor layer 124d, and the second patterned third semiconductor layer 126b. For example, the first dielectric layer 702 is on the upper surface of the second patterned third semiconductor layer 126b and on the sidewalls of the fifth patterned first semiconductor layer 122e, the fourth patterned second semiconductor layer 124d, and the second patterned third semiconductor layer 126b. The first dielectric layer 702 is further defined on the sidewalls and bottom surface of a recess 602 in the semiconductor substrate 102, the recess being located at the periphery of the capacitor.

[0035] ICs may include, for example Figure 8 Any device shown in device areas 104 to 112. An IC may contain multiple devices and / or any device may be omitted. Devices are shown to illustrate how various devices can be formed by methods of manufacturing an IC. Any component or device may be repeated to form multiple devices, and any processing of any device may be omitted to omit such a device in the IC.

[0036] The semiconductor processing described above can reduce the number of photolithography processes used to form devices in an IC (e.g., which includes one or more BJTs). As mentioned above, in-situ doping of the semiconductor layer during epitaxial growth avoids the photolithography processes used to form photoresist masks for diffusion layer implantation. By avoiding those photolithography processes, bottlenecks in semiconductor processing caused by photolithography are avoided, and IC manufacturing time is reduced. Furthermore, avoiding these diffusion layer implantations also avoids the thermal diffusion process, which further reduces manufacturing time. Avoiding photolithography processes also reduces processing costs. In-situ doping of the semiconductor layer can provide improved dopant uniformity and improved junction control of the device pn junction.

[0037] Furthermore, forming a dielectric layer conformally on the device within a recess in the semiconductor substrate allows for a uniform isolation strategy for ICs. Oxide isolation (e.g., the opposite of junction isolation) can be implemented in the semiconductor substrate, which improves device isolation. The semiconductor layer implemented for a given device (e.g., a BJT) can be used almost entirely or completely for the device, resulting in reduced or no stray electron flow paths, which can lead to improved device leakage performance.

[0038] Although various examples have been described in detail, it should be understood that various changes, substitutions and alterations may be made therein without departing from the scope of this disclosure.

Claims

1. A method for manufacturing an integrated circuit (IC), the method comprising: A semiconductor layer stack is formed above a semiconductor substrate, the semiconductor layer stack comprising a first semiconductor layer above the semiconductor substrate, a second semiconductor layer above the first semiconductor layer, and a third semiconductor layer above the second semiconductor layer, the first semiconductor layer and the third semiconductor layer having the same conductivity type, and the second semiconductor layer having a conductivity type opposite to that of the first semiconductor layer and the third semiconductor layer; The semiconductor layer is stacked in a first region and patterned into a first mesa, the first mesa forming the first emitter of a first bipolar junction transistor (BJT); as well as The semiconductor layer is stacked in the first region and patterned into a second mesa, the second mesa extending laterally from the first mesa, the first mesa being above the second mesa, and the second mesa forming the first base of the first BJT.

2. The method according to claim 1, further comprising: A notch is formed that passes through the first semiconductor layer and enters the semiconductor substrate; as well as A conformal dielectric layer is formed on the first platform and the second platform, as well as in the recess.

3. The method of claim 1, wherein the semiconductor layer stack is patterned into the second mesa and the semiconductor layer is further patterned into a third mesa in the second region, the third mesa forming the second emitter of the second BJT.

4. The method of claim 3, further comprising forming a notch through the first semiconductor layer and into the semiconductor substrate, the notch being located between the first BJT and the second BJT.

5. The method according to claim 3, wherein: The first BJT includes: The first emitter includes the third semiconductor layer in the first mesa; The first base includes the second semiconductor layer in the second mesa; and The first collector electrode is contained in a first portion of the first semiconductor layer beneath the second mesa; and The second BJT includes: The second emitter includes the second semiconductor layer in the third mesa; The second base is contained in a second portion of the first semiconductor layer beneath the second mesa; as well as The second collector electrode is contained in a portion of the semiconductor substrate beneath the second portion of the first semiconductor layer.

6. The method of claim 1, wherein the conductivity type of the first semiconductor layer and the third semiconductor layer is n-type doped, and the conductivity type of the second semiconductor layer is p-type doped.

7. The method of claim 1, wherein the semiconductor layers are stacked in the first region and patterned into the first mesa and the second mesa, and the third semiconductor layer and the second semiconductor layer are removed from the second region, thereby forming an anode and a cathode of a diode in the second region, the anode comprising a portion of the first semiconductor layer and the cathode comprising a portion of the semiconductor substrate.

8. The method of claim 1, further comprising: In the second region of the semiconductor layer stack, a collector region and an emitter region are implanted, wherein the semiconductor layer stack is patterned in the first region to form a second mesa, and the semiconductor layer stack is further patterned in the second region to form a third mesa, the third mesa comprising the collector region and the emitter region; as well as A base region is injected laterally between the collector region and the emitter region in the third mesa, and the second BJT includes the collector region, the base region, and the emitter region.

9. A method for manufacturing an integrated circuit (IC), the method comprising: A first epitaxial layer is formed above a semiconductor substrate, the first epitaxial layer having a first conductivity type; A second epitaxial layer is formed above the first epitaxial layer, the second epitaxial layer having a second conductivity type opposite to the first conductivity type; A third epitaxial layer is formed above the second epitaxial layer, the third epitaxial layer having the first conductivity type; Etching the third epitaxial layer to form the first emitter layer of the first bipolar junction transistor (BJT) in the first region; and The second epitaxial layer is etched to form the first base layer of the first BJT in the first region, the first emitter layer being above the first base layer and extending laterally from the first emitter layer.

10. The method of claim 9, further comprising: A notch is formed that penetrates the first epitaxial layer and enters the semiconductor substrate; as well as A conformal dielectric layer is formed on the first emitter layer and the first base layer, as well as in the notch.

11. The method of claim 9, wherein etching the second epitaxial layer further forms a second emitter layer of the second BJT in the second region.

12. The method of claim 11, further comprising forming a notch through the first epitaxial layer and into the semiconductor substrate, the notch being located between the first BJT and the second BJT.

13. The method according to claim 11, wherein: The first BJT further includes a first collector layer formed by the first epitaxial layer in the first region; and The second BJT includes: A second base layer, which is formed in the second region by the first epitaxial layer; and The second collector layer is contained within a portion of the semiconductor substrate beneath the second base layer.

14. The method of claim 9, wherein the first conductivity type is n-type doped and the second conductivity type is p-type doped.

15. The method of claim 9, wherein etching the third epitaxial layer and the second epitaxial layer in the first region removes the third epitaxial layer and the second epitaxial layer from the second region, a diode is formed in the second region, the diode comprising an anode and a cathode, the anode comprising a portion of the first epitaxial layer, and the cathode comprising a portion of the semiconductor substrate.

16. The method of claim 9, further comprising: In the second region of the second epitaxial layer, a collector region and an emitter region are implanted, wherein the third epitaxial layer is etched to further remove the third epitaxial layer from the second region; and The second BJT includes the collector region, the base region, and the emitter region, and is implanted laterally between the collector region and the emitter region in the second epitaxial layer and the first epitaxial layer.

17. An integrated circuit IC, comprising: Semiconductor substrate; A bipolar junction transistor (BJT) comprising a semiconductor layer stack above the semiconductor substrate, the semiconductor layer stack comprising: The base semiconductor layer above the semiconductor substrate; as well as An emitter semiconductor layer is located above the base semiconductor layer, and the base semiconductor layer extends laterally from the emitter semiconductor layer. as well as A conformal dielectric layer is disposed on the semiconductor layer stack and in a notch in the semiconductor substrate.

18. The IC of claim 17, wherein the semiconductor layer stack further includes a collector semiconductor layer above the semiconductor substrate, and the base semiconductor layer is above the collector semiconductor layer, wherein: The emitter semiconductor layer is n-type doped; The base semiconductor layer is p-type doped; and The collector semiconductor layer is n-type doped.

19. The IC according to claim 17, wherein: The BJT is contained in a p-doped collector region in the semiconductor substrate beneath the semiconductor layer stack; The emitter semiconductor layer is p-type doped; and The base semiconductor layer is n-type doped.

20. A method for manufacturing an integrated circuit (IC), the method comprising: Forming a bipolar junction transistor (BJT) involves forming a semiconductor layer stack over a semiconductor substrate. A base semiconductor layer is formed above the semiconductor substrate; as well as An emitter semiconductor layer is formed above the base semiconductor layer, and the base semiconductor layer extends laterally from the emitter semiconductor layer. as well as A conformal dielectric layer is formed on the semiconductor layer stack and in the recess in the semiconductor substrate.

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