Semiconductor device including isolated pattern

Abstract

A semiconductor device includes: a lower channel pattern and a lower source / drain pattern alternately disposed on a substrate in a first direction; an upper channel pattern on the lower channel pattern and an upper source / drain pattern on the lower source / drain pattern; a gate pattern spaced apart in a second direction crossing the first direction and at least partially surrounding the lower channel pattern and the upper channel pattern; a separation pattern at least partially passing through the gate pattern in a third direction crossing the first and second directions; and a through-penetrating piece spaced apart in the first direction by the separation pattern, extending in the third direction, and coupled with at least one of the lower source / drain pattern or the upper source / drain pattern.

Description

Cross-references to related applications

[0001] This application claims priority to Korean Patent Application No. 10-2024-0192591, filed on December 20, 2024, with the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0002] This disclosure generally relates to semiconductor devices, and more specifically, to three-dimensional (3D) semiconductor devices comprising a separate pattern between a gate pattern and a through-hole. Background Technology

[0003] With the continued increase in demand for higher integration and / or high performance in semiconductor devices, three-dimensional (3D) semiconductor devices can be positioned at the heart of next-generation semiconductor technologies. By designing complex 3D structures in the vertical and / or horizontal directions, 3D semiconductor devices can attempt to provide improved electrical characteristics and / or integration of the device.

[0004] However, 3D semiconductor devices may require multilayer structures and / or relatively complex pattern designs, and as a result, the possible short circuits between metals can be at least one cause of reduced reliability and / or performance of the semiconductor device.

[0005] Short circuits between metals can be caused by (but are not limited to) residual metal material during the process, incomplete insulating layer formation, misalignment in metal deposition and patterning processes, etc. For example, the risk of electrical short circuits can increase as the space between metals in 3D structures decreases. Therefore, there is a need to develop technologies that can be effectively integrated into the manufacturing processes of 3D semiconductor devices while preventing and / or reducing the possibility of short circuits between metal layers. Summary of the Invention

[0006] When compared with related semiconductor devices, one or more examples of embodiments of this disclosure provide semiconductor devices with reduced distribution of through-passes when a through-pass is formed within a gate dicing pattern by forming a separate pattern prior to forming a gate dicing pattern.

[0007] According to one aspect of this disclosure, a semiconductor device includes: a lower channel pattern and a lower source / drain pattern alternately disposed on a substrate in a first direction; an upper channel pattern on the lower channel pattern and an upper source / drain pattern on the lower source / drain pattern; a gate pattern spaced apart in a second direction intersecting the first direction and at least partially surrounding the lower channel pattern and the upper channel pattern; a separation pattern that at least partially passes through the gate pattern in a third direction intersecting the first and second directions; and a through-pass that is spaced apart by the separation pattern in the first direction, extends in a third direction, and is coupled to at least one of the lower source / drain pattern or the upper source / drain pattern.

[0008] According to one aspect of this disclosure, a semiconductor device includes: an insulating substrate including a first side and a second side facing each other; a lower channel pattern and a lower source / drain pattern alternately disposed on the first side in a first direction; an upper channel pattern on the lower channel pattern and an upper source / drain pattern on the lower source / drain pattern; a gate pattern spaced apart in a second direction intersecting the first direction and at least partially surrounding the lower channel pattern and the upper channel pattern; a separation pattern that at least partially passes through the gate pattern in a third direction intersecting the first and second directions; a through-pass that is spaced apart by the separation pattern in the first direction, extends in a third direction, and is coupled to at least one of the lower source / drain pattern or the upper source / drain pattern; and a lower wiring structure on the second side and coupled to the through-pass.

[0009] According to one aspect of this disclosure, a semiconductor device includes: a lower channel pattern and a lower source / drain pattern alternately disposed on a substrate in a first direction; an upper channel pattern on the lower channel pattern and an upper source / drain pattern on the lower source / drain pattern; a gate pattern spaced apart in a second direction intersecting the first direction and at least partially surrounding the lower channel pattern and the upper channel pattern; a gate dicing pattern disposed in the second direction between one of the lower source / drain patterns and one of the upper source / drain patterns and the other of the lower source / drain patterns; a separation pattern that at least partially passes through the gate pattern in a third direction intersecting the first and second directions; and a through-through member disposed in the gate dicing pattern, extending in the third direction, and coupled to at least one of the lower source / drain pattern or the upper source / drain pattern. The separation pattern and the through-through member are alternately disposed along the first direction.

[0010] According to one aspect of this disclosure, a method of manufacturing a semiconductor device includes: preparing a substrate, the substrate including a lower channel pattern and a lower source / drain pattern alternately disposed in a first direction, an upper channel pattern disposed on the lower channel pattern, and an upper source / drain pattern disposed on the lower source / drain pattern; forming a gate pattern surrounding the lower channel pattern and the upper channel pattern and extending in a second direction intersecting the first direction; forming a separation pattern extending through the gate pattern in a third direction intersecting the first and second directions; and forming a through-pass, the through-pass being separated in the first direction by the separation pattern and connected to the lower source / drain pattern or the upper source / drain pattern by extending in a third direction.

[0011] In an embodiment, a method of manufacturing a semiconductor device may further include: after forming a separation pattern, forming a gate dicing pattern disposed in a second direction between a lower source / drain pattern and another lower source / drain pattern and disposed in a second direction between an upper source / drain pattern and another upper source / drain pattern.

[0012] In a method for manufacturing a semiconductor device, according to an embodiment, the through-hole may not be disposed between gate patterns separated by a separation pattern in a second direction.

[0013] In a method for manufacturing a semiconductor device, according to an embodiment, a separation pattern may be formed before the gate dicing pattern is formed.

[0014] In a method for manufacturing a semiconductor device, according to an embodiment, the formation of a gate dicing pattern may include: forming a recess in a second direction between one of the lower channel patterns and one of the upper channel patterns and another of the lower channel patterns and another of the upper channel patterns; conformally forming an insulating liner layer on the inner wall of the recess; and forming a gap-filling insulating layer on the insulating liner layer.

[0015] In a method for manufacturing a semiconductor device, according to an embodiment, the gap-filling insulating layer may comprise silicon oxide (SiO2) and the insulating liner may comprise silicon nitride.

[0016] In a method for manufacturing a semiconductor device, according to an embodiment, the formation of a through-hole may include: forming a recess by filling an insulating layer through an etch gap, and filling the recess with metal.

[0017] In an embodiment, the method of manufacturing a semiconductor device may further include: forming upper source / drain contacts that can be connected to an upper source / drain pattern; and forming an upper wiring structure that can be connected to the upper source / drain pattern via the upper source / drain contacts.

[0018] In an embodiment, the method of manufacturing a semiconductor device may further include: removing a substrate and filling the area where the substrate has been removed with an insulating material; forming a lower source / drain contact connected to a lower source / drain pattern; and forming a connection portion extending from below the lower source / drain contact to below the through-hole.

[0019] In an embodiment, the method of manufacturing a semiconductor device may further include: forming a lower wiring structure connected to the lower source / drain contacts and the connection portion.

[0020] According to an embodiment, when compared with a related semiconductor device, by forming a separate pattern before forming a gate dicing pattern, the distribution of through-throughs can be reduced when forming through-throughs within the gate dicing pattern.

[0021] Additional aspects may be set forth in part in the description below, and in part may become clear from the description and / or be learned through practice of the presented embodiments. Attached Figure Description

[0022] The above and other aspects, features, and advantages of specific embodiments of the present disclosure will become clearer from the following description taken in conjunction with the accompanying drawings, in which: Figure 1 This is a top view of a semiconductor device according to an example embodiment; Figure 2 According to the example embodiment Figure 1 A cross-sectional view taken along lines A-A' and D-D'; Figure 3 According to the example embodiment Figure 1 A cross-sectional view taken along line B-B'; Figure 4 According to the example embodiment Figure 1 A cross-sectional view taken along line C-C'; Figure 5 According to the example embodiment Figure 1 A cross-sectional view taken along line E-E'; Figure 6 According to the example embodiment Figure 1 A cross-sectional view taken along line A-A'; Figure 7 According to the example embodiment Figure 1 A cross-sectional view taken along line B-B'; Figure 8 This is a top view of a semiconductor device according to an example embodiment; and Figures 8 to 45 This is a cross-sectional view showing the process sequence of a semiconductor device manufacturing method according to an example embodiment. Detailed Implementation

[0023] Hereinafter, various examples of this disclosure are described with reference to the accompanying drawings, enabling those skilled in the art to implement this disclosure. This disclosure may be implemented in many different forms and is not limited to the examples described herein.

[0024] For the purpose of describing this disclosure, parts that may not be relevant to the description may be omitted, and the same reference numerals may be used in this disclosure for the same or similar components.

[0025] Furthermore, the size and thickness of the components shown in the figures may be arbitrarily depicted for better understanding and ease of description, and therefore this disclosure is not necessarily limited to the content shown in the figures. The thickness of layers, films, panels, areas, etc., may be exaggerated in the figures for clarity. Additionally, the thickness of some layers and areas may be exaggerated in the figures for better understanding and ease of description.

[0026] It should be understood that when an element such as a layer, film, region, or substrate is referred to as being "located" "on" another element, it may be located directly on that other element, or there may be intermediate elements present. Conversely, when an element is referred to as being "located directly" "on" another element, there are no intermediate elements present. Furthermore, in this disclosure, the term "located" "on" a target element should be understood as being located on or below that target element, and may not necessarily be understood as being arranged "on the upper side" in the opposite direction based on the direction of gravity.

[0027] Furthermore, unless explicitly stated otherwise, the word "includes" and its variations should be understood to include the listed elements while not excluding any other elements.

[0028] Furthermore, in this disclosure, the phrase "in a plane" may refer to the target portion viewed from above, and the phrase "in a cross section" may refer to the cross section formed by vertically cutting the target portion viewed from the side.

[0029] As used herein, each of the phrases such as “A or B,” “at least one of A and B,” “at least one of A or B,” “A, B or C,” “at least one of A, B and C,” and “at least one of A, B or C” may include any one or all possible combinations of the items listed together with the corresponding one of these phrases. As used herein, terms such as “first” and “second” may be used to simply distinguish components from each other without otherwise limiting the components (e.g., in terms of importance or order).

[0030] As used herein, when an element or layer is referred to as “covering” another element or layer, “overlapping” another element or layer, or “around” another element or layer, the element or layer may cover at least a portion of the other element or layer, wherein the portion may include a part of the other element or layer or may include the entire other element or layer. Similarly, when an element or layer is referred to as “through” another element or layer, the element or layer may pass through at least a portion of the other element or layer, wherein the portion may include a part of the other element or layer or may include the entire dimensions (e.g., length, width, depth) of the other element or layer.

[0031] The terms "an embodiment," "embodiment," "example embodiment," or similar language used in this disclosure may indicate that a specific feature, structure, or characteristic described in connection with the indicated embodiment is included in at least one embodiment of the present invention. Therefore, the phrases "in an embodiment," "in an embodiment," "in an example embodiment," and similar language in this disclosure may (but not necessarily) all refer to the same embodiment. The embodiments described herein are exemplary embodiments, and therefore, this disclosure is not limited thereto but may be implemented in various other forms.

[0032] Furthermore, in this disclosure, the two directions parallel to the upper surface of the substrate and intersecting each other can be referred to as the first direction D1 and the second direction D2, respectively, and the direction perpendicular to the upper surface of the substrate can be referred to as the third direction D3. For example, the first direction D1 and the second direction D2 can be orthogonal to each other.

[0033] In the accompanying drawings of the semiconductor device according to the example, a three-dimensionally stacked field-effect transistor (3D-SFET) structure may be shown as an example, but this disclosure is not limited thereto. According to the example, the semiconductor device may include (but is not limited to) gate all-around (GAA) including nanowires or nanosheets, multi-bridge channel field-effect transistors (MBCFET™), fin transistors (FinFET) including channel regions with fin patterned shapes, tunneling transistors (FETs), 3D-SFET structures, and complementary field-effect transistor (CFET) structures.

[0034] As used in this article, the terms "Al2O3", "BaSrTi2O6", "BaTiO3", "CoN", "HfO2", "HfSiO4", and "Hf" are used interchangeably. x Ta 1-x O yEach of the following terms, such as “HfZrO”, “La2O3”, “Li2O”, “NiN”, “PbScTaO3”, “PbZnNbO3”, “PtN”, “SiBN”, “SiN”, “SiO2”, “SiOBN”, “SiOC”, “SiOCN”, “SiON”, “SrTiO3”, “TaN”, “Ta2O5”, “TiN”, “TiO2”, “WN”, “ZrO2”, and “ZrSiO4”, may refer to a material made from the elements included in each of these terms, rather than a chemical formula representing a stoichiometric relationship.

[0035] Hereinafter, various embodiments of the present disclosure are described with reference to the accompanying drawings.

[0036] Figure 1 This is a top view of a semiconductor device according to an example embodiment. Figure 2 According to the example embodiment Figure 1 A cross-sectional view taken along lines A-A' and D-D'. Figure 3 According to the example embodiment Figure 1 A cross-sectional view taken along line B-B'. Figure 4 According to the example embodiment Figure 1 A cross-sectional view taken along line C-C'. Figure 5 According to the example embodiment Figure 1 A cross-sectional view taken along line E-E'.

[0037] Reference Figure 1 The diagram shows a top view of a semiconductor device including a gate pattern GE, an upper source / drain pattern USD, a split pattern 500, a gate cut pattern 600, and a through-hole 650.

[0038] Reference Figures 1 to 5 The semiconductor device can be a three-dimensional (3D) semiconductor device (e.g., a stacked transistor). That is, transistors can be stacked on a third direction D3 in a cell region. For example, a single-height cell (SHC) can be disposed between a first power line and a second power line, and the single-height cell can include a first active region AR1 as the bottom layer, and a second active region AR2 can be stacked on the first active region AR1 as the top layer.

[0039] For example, an N-type metal-oxide-semiconductor field-effect transistor (NMOSFET) of the first active region AR1 can be disposed on the bottom pattern BP, and a P-type metal-oxide-semiconductor field-effect transistor (PMOSFET) of the second active region AR2 can be disposed on the NMOSFET. The first active region AR1 and the second active region AR2 can be separated from each other on the third direction D3.

[0040] In other words, in a 3D semiconductor device, the first active region AR1 and the second active region AR2 can overlap on the third direction D3. Therefore, compared to conventional semiconductor devices, the element density of the semiconductor device can be increased by reducing the area of ​​the logic cells.

[0041] In some embodiments, the peripheral region of the transistor forming the processing core and / or input / output (I / O) terminals may be located around the cell region. That is, the peripheral region may be a core / peripheral region. For example, the peripheral region may include a long-gate transistor (or a long-channel transistor) having a relatively long gate length (e.g., channel length). Transistors in the peripheral region can operate with greater power compared to transistors in the cell region. For example, transistors in the cell region may be single-gate (SG) devices, while transistors in the peripheral region may be additional-gate (EG) devices.

[0042] like Figure 4 and Figure 5 As shown, the bottom pattern BP can be defined by a trench TR disposed in the cell region. That is, the bottom pattern BP can be a portion that vertically protrudes from the upper end of the substrate 100. In a plane, the bottom pattern BP can have stripes that can be spaced apart in the second direction D2 and can extend in the first direction D1. The first active region AR1 and the second active region AR2 can be stacked sequentially on the bottom pattern BP.

[0043] For example, the bottom pattern BP may include a semiconductor material such as (but not limited to) silicon (Si), germanium (Ge), or silicon-germanium (SiGe), and may include, for example, silicon (Si). In some examples, the bottom pattern BP may be replaced by an insulating material after the substrate 100 is removed to form the lower source / drain contact bCA, as shown in the reference. Figure 6 and Figure 7 For example, the bottom pattern BP can be replaced with silicon oxide (SiO2), and therefore, the bottom pattern BP may include silicon oxide (SiO2).

[0044] According to the example, the device isolation layer ST may fill the trench between the bottom patterns BP. For example, the device isolation layer ST may include silicon oxide (SiO2). The upper end of the device isolation layer ST may be coplanar with the upper end of the bottom pattern BP. Alternatively, on the third direction D3, the horizontal height of the upper end of the device isolation layer ST may be lower than the horizontal height of the upper end of the bottom pattern BP. The device isolation layer ST may not cover the lower channel pattern LCH.

[0045] According to the example, a first active region AR1, including a lower channel pattern LCH and a lower source / drain pattern LSD, can be disposed on a bottom pattern BP. The lower channel pattern LCH can be located between one lower source / drain pattern LSD spaced apart from another lower source / drain pattern LSD in a first direction D1. The lower channel pattern LCH can connect a pair of lower source / drain patterns LSD to each other. For example, the lower channel pattern LCH and the lower source / drain pattern LSD can be alternately disposed in the first direction D1.

[0046] According to the example, the lower channel pattern LCH may include a first semiconductor pattern SP1 and a second semiconductor pattern SP2 that may be stacked spaced apart from each other on a third-direction D3. However, embodiments of the present disclosure are not limited thereto, and the lower channel pattern LCH may include three (3) or more semiconductor patterns. Each of the first semiconductor pattern SP1 and the second semiconductor pattern SP2 may include silicon (Si), germanium (Ge), or silicon-germanium (SiGe). For example, each of the first semiconductor pattern SP1 and the second semiconductor pattern SP2 may include crystalline silicon.

[0047] According to the example, the lower source / drain pattern LSD can be positioned above the bottom pattern BP. The lower source / drain pattern LSD can be an epitaxial pattern formed by a selective epitaxial growth (SEG) process. For example, the upper end of the lower source / drain pattern LSD can be higher than the upper end of the second semiconductor pattern SP2 of the lower channel pattern LCH.

[0048] According to the example, the lower source / drain pattern LSD may be doped with impurities to become a first conductivity type. The first conductivity type may be N-type or P-type. For example, the first conductivity type may be N-type. The lower source / drain pattern LSD may include silicon (Si) or silicon germanium (SiGe).

[0049] According to the example, a dummy source / drain pattern 155 may be disposed below a lower source / drain pattern LSD. The dummy source / drain pattern 155 may extend through at least a portion of the bottom pattern BP. For example, the dummy source / drain pattern 155 may be embedded within the bottom pattern BP. The dummy source / drain pattern 155 may be disposed below at least one of a plurality of lower source / drain patterns LSD.

[0050] For example, the dummy source / drain pattern 155 may include a material substantially similar to and / or the same as the lower source / drain pattern LSD. For example, the dummy source / drain pattern 155 may include silicon (Si) or silicon germanium (SiGe), and may also include carbon (C), silicon (Si), germanium (Ge), or tin (Sn).

[0051] As an example, the first interlayer stop film ESL1 can be disposed on the lower source / drain pattern LSD. For instance, the first interlayer stop film ESL1 can cover the lower source / drain pattern LSD.

[0052] According to the example, a first interlayer insulating layer 110 may be disposed on a first interlayer stop film ESL1. The first interlayer insulating layer 110 may cover the lower source / drain pattern LSD.

[0053] For example, the first interlayer insulating layer 110 may include silicon oxide (SiO2), silicon nitride (SiN), silicon oxynitride (SiON), or a low dielectric constant material.

[0054] According to the example, the first interlayer stop film ESL1 may include a material that has etch selectivity relative to the first interlayer insulating layer 110. For example, the first interlayer stop film ESL1 may include silicon nitride (SiN), silicon oxynitride (SiON), silicon carbonitride (SiOCN), silicon boron nitride (SiBN), silicon boron oxynitride (SiOBN), or silicon carbide (SiOC).

[0055] According to the example, a second active region AR2 may be located on the first active region AR1. The second active region AR2 may include an upper channel pattern UCH and an upper source / drain pattern USD.

[0056] According to the example, the upper channel pattern UCH can be disposed on the lower channel pattern LCH. The upper source / drain pattern USD can be disposed on the lower source / drain pattern LSD. That is, the upper channel pattern UCH can overlap with the lower channel pattern LCH in the third direction D3. The upper source / drain pattern USD can overlap with the lower source / drain pattern LSD in the third direction D3. The upper channel pattern UCH can be disposed between one upper source / drain pattern USD and another upper source / drain pattern USD that is separate from it in the first direction D1. The upper channel pattern UCH can connect a pair of upper source / drain patterns USD. For example, the upper channel pattern UCH and the upper source / drain pattern USD can be disposed alternately in the first direction D1.

[0057] According to the example, the upper channel pattern UCH may include a third semiconductor pattern SP3 and a fourth semiconductor pattern SP4 that may be alternately stacked on a third-direction D3. However, embodiments of the present disclosure are not limited thereto, and the upper channel pattern UCH may include three (3) or more semiconductor patterns. The third semiconductor pattern SP3 and the fourth semiconductor pattern SP4 of the upper channel pattern UCH may include semiconductor materials that are substantially similar to and / or the same as the first semiconductor pattern SP1 and the second semiconductor pattern SP2 of the lower channel pattern LCH described above.

[0058] According to the example, at least one intermediate insulating structure DSP may be located between the lower channel pattern LCH and the upper channel pattern UCH disposed on the lower channel pattern LCH, and at least one dummy channel pattern SDL may be located between the first semiconductor pattern to the fourth semiconductor pattern (e.g., the first semiconductor pattern SP1, the second semiconductor pattern SP2, the third semiconductor pattern SP3 and the fourth semiconductor pattern SP4).

[0059] For example, the intermediate insulating structure DSP can be disposed between the lower channel pattern LCH and the upper channel pattern UCH, and the dummy channel pattern SDL can be disposed between the intermediate insulating structure DSP and the third semiconductor pattern SP3 of the upper channel pattern UCH.

[0060] In other words, the second semiconductor pattern SP2 of the lower channel pattern LCH, the third gate portion PO3 of the lower gate pattern LGE, the intermediate insulating structure DSP, the dummy channel pattern SDL, the fourth gate portion PO4 of the upper gate pattern UGE, and the third semiconductor pattern SP3 of the upper channel pattern UCH can be stacked sequentially on the third-direction D3.

[0061] The intermediate insulating structure DSP may include semiconductor materials such as (but not limited to) silicon (Si), germanium (Ge), or silicon-germanium (SiGe), or silicon-based insulating materials such as (but not limited to) silicon oxide (SiO2) or silicon nitride (SiN). For example, the intermediate insulating structure DSP may include silicon-based insulating materials.

[0062] The dummy channel pattern SDL may include semiconductor materials such as (but not limited to) silicon (Si), germanium (Ge), or silicon-germanium (SiGe) or silicon-based insulating materials such as (but not limited to) silicon oxide (SiO2) or silicon nitride (SiN).

[0063] According to the example, the upper source / drain pattern USD can be disposed on the upper surface of the first interlayer insulating layer 110. The upper source / drain pattern USD can be an epitaxial pattern formed by a SEG process. For example, the upper end of the upper source / drain pattern USD can be higher than the upper end of the fourth semiconductor pattern SP4 of the upper channel pattern UCH.

[0064] The upper source / drain pattern (USD) can be doped with impurities to have a second conductivity type. This second conductivity type may differ from the first conductivity type of the lower source / drain pattern (LSD). For example, when the first conductivity type is N-type, the second conductivity type may be P-type. The upper source / drain pattern (USD) may include silicon germanium (SiGe) or silicon (Si).

[0065] As an example, the second interlayer stop film ESL2 can be disposed on the upper source / drain pattern USD. For instance, the second interlayer stop film ESL2 can cover the upper source / drain pattern USD.

[0066] The second interlayer stop film ESL2 can cover both sides of the upper source / drain pattern USD in the second direction D2. The second interlayer stop film ESL2 may not be disposed between the upper source / drain pattern USD and the upper source / drain contact aCA.

[0067] The second interlayer insulating layer 120 can be disposed on the second interlayer stop film ESL2. The second interlayer insulating layer 120 can cover the upper source / drain pattern USD.

[0068] For example, the second interlayer insulating layer 120 may include silicon oxide (SiO2), silicon nitride (SiN), silicon oxynitride (SiON), or a low dielectric constant material.

[0069] The second interlayer stop film ESL2 may include a material that is etch-selective relative to the second interlayer insulating layer 120. The second interlayer stop film ESL2 may include, for example, silicon nitride (SiN), silicon oxynitride (SiON), silicon carbonitride (SiOCN), silicon boron nitride (SiBN), silicon boron oxynitride (SiOBN), silicon carbide (SiOC), or combinations thereof.

[0070] According to the example, the gate pattern GE can be disposed on the lower channel pattern LCH and the upper channel pattern UCH. For example, at least a portion of the gate pattern GE can be replaced by a separation pattern 500. That is, after removing at least a portion of the gate pattern GE, the separation pattern 500 can be formed at the location where the gate pattern GE can be removed.

[0071] Therefore, any gate pattern GE can be separated from another gate pattern GE in the second direction D2 by a separation pattern 500. That is, the separation pattern 500 can pass through the lower gate pattern LGE and the upper gate pattern UGE of the gate pattern GE. Therefore, the connection of the gate patterns GE can be cut by the separation pattern 500.

[0072] The separation distance of the gate pattern GE along the second direction D2 can be substantially similar to and / or the same as the width of the separation pattern 500 along the second direction D2. For example, the width of the separation pattern 500 in the second direction D2 can be less than or equal to the distance between a lower channel pattern LCH and an upper channel pattern UCH and another lower channel pattern LCH and another upper channel pattern UCH.

[0073] A portion of the gate pattern GE may overlap with the stacked lower channel pattern LCH and upper channel pattern UCH on the third direction D3. The gate pattern GE may extend on the third direction D3 from the top of the device isolation layer ST or the top of the bottom pattern BP to the gate cap pattern GP. The gate pattern GE may extend on the third direction D3 from the lower channel pattern LCH of the first active region AR1 to the upper channel pattern UCH of the second active region AR2. That is, the gate pattern GE may extend on the third direction D3 from the bottom first semiconductor pattern SP1 to the top fourth semiconductor pattern SP4.

[0074] The gate pattern GE can be disposed on the top end, bottom surface, and opposite side surface of each of the first semiconductor pattern SP1, the second semiconductor pattern SP2, the third semiconductor pattern SP3, and the fourth semiconductor pattern SP4. That is, in the logic cell, the gate pattern GE may include a 3D field-effect transistor (e.g., a multi-bridge channel field-effect transistor (MBCFET™) or a gate all-around field-effect transistor (GAAFET) that surrounds the channel in three dimensions).

[0075] According to the example, the gate pattern GE may include a lower gate pattern LGE and an upper gate pattern UGE that can be stacked sequentially. The lower gate pattern LGE and the upper gate pattern UGE may overlap each other on a third-direction D3. The lower gate pattern LGE and the upper gate pattern UGE may be connected to each other. That is, the gate pattern GE may be a lower gate pattern LGE on the lower channel pattern LCH and an upper gate pattern UGE on the upper channel pattern UCH that can be connected to their common gate electrode.

[0076] At least a portion of the gate pattern GE may be disposed above and below a structure in which the lower channel pattern LCH, the intermediate insulating structure DSP, the dummy channel pattern SDL, and the upper channel pattern UCH may be alternately stacked. Another portion of the gate pattern GE may be formed to cover the opposing side surfaces of the structure in which the lower channel pattern LCH, the intermediate insulating structure DSP, the dummy channel pattern SDL, and the upper channel pattern UCH may be alternately stacked. In this case, four (4) sides of each of the lower channel pattern LCH and the upper channel pattern UCH may be surrounded by the gate pattern GE.

[0077] According to the example, the lower gate pattern LGE may include a first gate portion PO1 disposed between the bottom pattern BP and the first semiconductor pattern SP1, a second gate portion PO2 disposed between the first semiconductor pattern SP1 and the second semiconductor pattern SP2, and a third gate portion PO3 disposed between the second semiconductor pattern SP2 and the intermediate insulating structure DSP.

[0078] The upper gate pattern UGE may include a fourth gate portion PO4 disposed between the dummy channel pattern SDL and the third semiconductor pattern SP3, a fifth gate portion PO5 disposed between the third semiconductor pattern SP3 and the fourth semiconductor pattern SP4, and a sixth gate portion PO6 disposed on the fourth semiconductor pattern SP4.

[0079] For example, the lower gate pattern LGE may include a first work function metal pattern disposed on a first semiconductor pattern SP1 and a second semiconductor pattern SP2. The upper gate pattern UGE may include a second work function metal pattern disposed on a third semiconductor pattern SP3 and a fourth semiconductor pattern SP4. The first and second work function metal patterns may each include a metal comprising titanium (Ti), tantalum (Ta), aluminum (Al), tungsten (W), molybdenum (Mo), or combinations thereof, and nitrogen (N). The first and second work function metal patterns may have different work functions. The gate pattern GE may include a low resistivity metal on the first and second work function metal patterns, such as (but not limited to) tungsten (W), ruthenium (Ru), aluminum (Al), titanium (Ti), tantalum (Ta), or combinations thereof.

[0080] A gate insulating layer GI may be disposed between the gate pattern GE and the first semiconductor patterns SP1 to the fourth semiconductor patterns SP4. The gate insulating layer GI may include silicon oxide (SiO2), a silicon oxynitride (SiON) layer, a high-dielectric layer, or a combination thereof. For example, the gate insulating layer GI may include silicon oxide (SiO2) directly covering the surfaces of the first semiconductor pattern SP1 to the fourth semiconductor pattern SP4, and a high-dielectric layer disposed on the silicon oxide (SiO2). In other words, the gate insulating layer GI may comprise a multilayer formed of silicon oxide (SiO2) and a high-dielectric layer.

[0081] The high-dielectric layer may include a high-dielectric-constant material having a higher dielectric constant than silicon oxide (SiO2). For example, high-dielectric-constant materials may include hafnium oxide (HfO2), hafnium silicon oxide (HfSiO4), hafnium zirconium oxide (HfZrO), and hafnium tantalum oxide (Hf... x Ta 1-x O y Lanthanum oxide (La2O3), zirconium oxide (ZrO2), zirconium silicon oxide (ZrSiO4), tantalum oxide (Ta2O5), titanium oxide (TiO2), barium strontium titanium oxide (BaSrTi2O6), barium titanium oxide (BaTiO3), strontium titanium oxide (SrTiO3), lithium oxide (Li2O), aluminum oxide (Al2O3), lead scandium tantalum oxide (PbScTaO3), lead zinc niobate (PbZnNbO3), or combinations thereof.

[0082] In some embodiments, an inner gate spacer may be disposed between the gate pattern GE and the lower source / drain pattern LSD. The inner gate spacer may also be disposed between the gate pattern GE and the upper source / drain pattern USD. For example, the inner gate spacer may be disposed between the first to third gate portions (e.g., the first gate portion PO1, the second gate portion PO2, and the third gate portion PO3) of the lower gate pattern LGE and the lower source / drain pattern LSD, and may be disposed between the fourth gate portion PO4 and the fifth gate portion PO5 of the upper gate pattern UGE and the upper source / drain pattern USD.

[0083] For example, in one cross section, the gate spacer may be disposed on the opposite side of each of the first gate portions PO1 to the fifth gate portions PO5 in a direction D1.

[0084] For example, the gate spacer may include a low dielectric constant material. The low dielectric constant material may include silicon oxide (SiO2), or a material having a lower dielectric constant than silicon oxide (SiO2). For example, the low dielectric constant material may include silicon oxide (SiO2), fluorine (F) or carbon (C) doped silicon oxide, porous silicon oxide, or an organic polymer dielectric.

[0085] A pair of gate spacers GS may be arranged on opposite side surfaces in the sixth gate portion PO6 of the gate pattern GE in the first direction D1.

[0086] The upper end of the gate spacer GS may be higher than the upper end of the gate pattern GE. The upper end of the gate spacer GS may be coplanar with the upper end of the second interlayer insulating layer 120.

[0087] The gate spacer GS may include silicon carbonitride (SiCN), silicon carbonitride oxynitride (SiOCN), silicon nitride (SiN), or combinations thereof. For example, the gate spacer GS may include a multilayer comprising silicon carbonitride (SiCN), silicon carbonitride oxynitride (SiOCN), silicon nitride (SiN), or combinations thereof.

[0088] The gate cap pattern GP may be disposed on the upper end of the gate pattern GE. For example, the gate cap pattern GP may include silicon oxynitride (SiON), silicon carbonitride (SiCN), silicon carbonitride (SiOCN), silicon nitride (SiN), or a combination thereof.

[0089] According to the example, before the gate dicing pattern 600 can be formed, and after at least a portion of the gate pattern GE can be removed, a separation pattern 500 can be formed at the location where the gate pattern GE can be removed. Therefore, the width of the separation pattern 500 in the first direction D1 can be approximately or substantially the same as the width of the gate pattern GE in the first direction D1.

[0090] According to the example, the separation pattern 500 may extend in the second direction D2. The separation pattern 500 may extend in the second direction D2 from one gate pattern GE to another gate pattern GE that is separated in the second direction D2. For example, as Figure 4 As shown, the separation pattern 500 may have stripes that can be separated in a first direction D1 and extend in a second direction D2. Alternatively, for example, as... Figure 5 As shown, the separation pattern 500 can be separated in the first direction D1 and also in the second direction D2, while the lower channel pattern LCH and the upper channel pattern UCH are in between.

[0091] According to the example, as the separation pattern 500 can be formed at the location where the gate pattern GE can be removed, the separation pattern 500 and the gate pattern GE can be disposed between a gate cut pattern 600 and another gate cut pattern 600 spaced apart from the one gate cut pattern 600 in the first direction D1.

[0092] According to the example, the separation pattern 500 can be set on the bottom pattern BP.

[0093] However, the upper end of the bottom pattern BP located below the separation pattern 500 may be at a lower level in the third direction D3 than the upper end of the bottom pattern BP located below the gate pattern GE. Therefore, the lower end of the separation pattern 500 may be at a lower level in the third direction D3 than the lower end of the gate pattern GE.

[0094] According to the example, the separation pattern 500 may extend along the third direction D3. For example, the separation pattern 500 may extend along the third direction D3 from the lower end of the gate pattern GE to a horizontal height higher than the upper end of the gate pattern GE. The separation pattern 500 may extend along the third direction D3 from a horizontal height lower than the lower end of the gate pattern GE to the upper end of the gate cap pattern GP. That is, the lower end of the separation pattern 500 may be configured to be closer to the lower end of the bottom pattern BP rather than the lower end of the gate pattern GE in the third direction D3.

[0095] For example, the lower end of the separation pattern 500 may be at a horizontal height lower than the upper end of the bottom pattern BP, lower than the lower end of the lower source / drain pattern LSD, higher than the lower end of the dummy source / drain pattern 155, higher than the lower end of the gate cut pattern 600, and lower than the lower end of the through-hole 650.

[0096] As used herein, the horizontal height of the lower end of the separation pattern 500 along the third direction D3 can be referred to as the shortest distance from the lower end of the separation pattern 500 along the third direction D3 with the lower end of the bottom pattern BP as a reference.

[0097] For example, the separation pattern 500 may include an insulating material. For example, the separation pattern 500 may include silicon oxide (SiO2), silicon nitride (SiN), silicon oxynitride (SiON), a high dielectric constant (high k) material having a higher dielectric constant than silicon oxide (SiO2), or a combination thereof, and may include silicon nitride (SiN).

[0098] According to the example, in a plane (e.g., Figure 1 The gate dicing pattern 600 may be spaced apart in the second direction D2. As described above, since at least a portion of the gate pattern GE may be replaced by the separation pattern 500, the gate dicing pattern 600 may also be separated by the separation pattern 500 in the first direction D1.

[0099] According to the example, the lower end of the gate diced pattern 600 may be at a horizontal height lower than the lower end of the split pattern 500, lower than the lower end of the through-hole 650, and higher than or equal to the lower end of the dummy source / drain pattern 155. The lower end of the gate diced pattern 600 may contact the upper end of the substrate 100.

[0100] As used herein, the horizontal height of the lower end of the gate diced pattern 600 along the third direction D3 can refer to the shortest distance from the lower end of the gate diced pattern 600 along the third direction D3 with reference to the upper end of the substrate 100.

[0101] According to the example, the gate cleavage pattern 600 can be disposed between a lower source / drain pattern LSD and another lower source / drain pattern LSD spaced apart in the second direction D2. The gate cleavage pattern 600 can be disposed between any upper source / drain pattern USD and upper source / drain pattern USD.

[0102] Additionally, the gate dicing pattern 600 may be disposed between the dummy source / drain pattern 155 and another dummy source / drain pattern 155 spaced apart in the second direction D2.

[0103] Since a gate dicing pattern 600 can be formed after a separation pattern 500 that passes through the gate pattern GE in the third direction D3 is formed, the gate dicing pattern 600 may not be disposed between the gate patterns GE in the second direction D2. For example, the gate dicing pattern 600 may not be disposed between one gate pattern GE and another gate pattern GE spaced apart in the second direction D2.

[0104] For example, the gate dicing pattern 600 may include a gap-filling insulating layer 620 and an insulating liner 610.

[0105] The gap-filling insulating layer 620 can be configured to fill the inner space of the gate dicing pattern 600. The gap-filling insulating layer 620 can be disposed approximately at the center of the gate dicing pattern 600 in the second direction D2.

[0106] As described below, since the separation pattern 500 can be formed before the gate dicing pattern 600 can be formed, the insulating liner 610 can be configured to fill the four (4) sides of the insulating layer 620 around the gap. In addition, the insulating liner 610 can be formed to fill the four (4) sides of the through-piece 650 described below.

[0107] In some examples, the boundary between the insulating liner 610 and the separation pattern 500 may be invisible. For example, the boundary between the insulating liner 610 and the separation pattern 500 may be invisible when the insulating liner 610 and the separation pattern 500 comprise the same and / or substantially similar materials.

[0108] In some examples, the insulating liner 610 may be disposed on the opposite side of the gap-filling insulating layer 620. For example, the insulating liner 610 may be detachably disposed on the opposite side of the gap-filling insulating layer 620 in the second direction D2.

[0109] The gate cleaving pattern 600 may include an insulating material. For example, the gate cleaving pattern 600 may include silicon oxide (SiO2), silicon nitride (SiN), silicon oxynitride (SiON), a high dielectric constant (high k) material having a higher dielectric constant than silicon oxide (SiO2), or a combination thereof, and may include silicon nitride (SiN).

[0110] For example, the gap-filling insulating layer 620 and insulating liner 610 forming the gate dicing pattern 600 may comprise different materials. For example, the gap-filling insulating layer 620 may comprise silicon oxide (SiO2), and the insulating liner 610 may comprise silicon nitride (SiN). However, this is only an example, and the materials of the gap-filling insulating layer 620 and insulating liner 610 may vary.

[0111] According to the example, a through-hole 650 may be disposed in the gate dicing pattern 600. The through-hole 650 may extend on the third direction D3, and therefore may be inserted into the entire gate dicing pattern 600 or at least a portion of the gate dicing pattern 600.

[0112] For example, the through-hole 650 may extend in the third direction D3 from a horizontal height above the lower end of the gate cut pattern 600 to a horizontal height below or substantially equal to the upper end of the gate cut pattern 600. That is, the lower end of the through-hole 650 may be positioned in the third direction D3 further away from the lower end of the bottom pattern BP than the lower end of the gate cut pattern 600.

[0113] In addition, the lower end of the through-hole 650 may be at a higher horizontal height than the upper end of the bottom pattern BP, higher than the lower end of the gate cut pattern 600, higher than the lower end of the split pattern 500, and higher than the lower end of the dummy source / drain pattern 155.

[0114] As used herein, the horizontal height of the lower end of the through piece 650 along the third direction D3 can refer to the shortest distance from the lower end of the through piece 650 along the third direction D3, with the lower end of the bottom pattern BP as the reference.

[0115] According to the example, the through-hole 650 may be spaced apart in the second direction D2. As described above, as at least a portion of the gate pattern GE can be replaced by the separation pattern 500, the through-hole 650 may be separated by the separation pattern 500 in the first direction D1. According to the example, since the through-hole 650 may be separated in the first direction D1 by the separation pattern 500 passing through the gate pattern GE in the third direction D3, the through-hole 650 may not pass through the gate pattern GE.

[0116] According to the example, the through-hole 650 may be disposed approximately at the center of the gate dicing pattern 600 in the second direction D2. The insulating liner 610 of the gate dicing pattern 600 may be configured to surround four (4) sides of the through-hole 650. That is, the insulating liner 610 may contact the through-hole 650 in the first direction D1 and the second direction D2. However, embodiments of the present disclosure are not limited thereto, and for example, the gap-filling insulating layer 620 of the gate dicing pattern 600 may be configured to fill the inner space between the through-hole 650 and the insulating liner 610.

[0117] In some examples, the through-hole 650 may include a conductive pattern and a blocking pattern that may surround the conductive pattern. For example, the conductive pattern may include a metal containing aluminum (Al), copper (Cu), tungsten (W), molybdenum (Mo), or a combination thereof. The blocking pattern may cover the sidewalls and bottom surface of the conductive pattern. The blocking pattern may include a metal layer or a metal nitride layer. The metal layer may include titanium (Ti), tantalum (Ta), tungsten (W), nickel (Ni), cobalt (Co), platinum (Pt), or a combination thereof. The metal nitride layer may include titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), nickel nitride (NiN), cobalt nitride (CoN), platinum nitride (PtN), or a combination thereof.

[0118] An insulating liner 610 may be disposed on both sides of the through-hole member 650 in the first direction D1 and the second direction D2, and a gap-filling insulating layer 620 may be disposed below the through-hole member 650. The through-hole member 650 may be disposed within the gate dicing pattern 600, and the gap-filling insulating layer 620 fills the interior of the gate dicing pattern 600, and thus the bottom surface of the through-hole member 650 may contact the gap-filling insulating layer 620.

[0119] When the gate dicing pattern 600 includes an oxide-containing gap-filling insulating layer 620 and a nitride-containing insulating liner 610, etching of the gate dicing pattern 600 for forming a through-hole 650 within the gate dicing pattern 600 can be performed smoothly.

[0120] As described above, the semiconductor device according to this disclosure may have a through-hole 650 that does not overlap with the gate pattern GE in the second direction D2. Therefore, a short circuit can be prevented between the through-hole 650 and the gate pattern GE.

[0121] Figure 6 According to the example embodiment Figure 1 A cross-sectional view taken along line A-A'. Figure 7 According to the example embodiment Figure 1 A cross-sectional view taken along line B-B'.

[0122] Figure 6 and Figure 7 The semiconductor device shown may include, as referenced Figures 1 to 5 The semiconductor device described has components similar to and / or identical to those in the current embodiment. However, the semiconductor device in the current embodiment is similar to... Figures 1 to 5 The semiconductor device shown may differ in that the substrate 100 may be removed and replaced with an insulating material to form the lower source / drain contacts bCA. Therefore, for simplicity, details repeated above may be simply described and / or omitted, and differences may be described.

[0123] Reference Figure 6and Figure 7 The semiconductor device according to the example may include an insulating substrate 101. Specifically, substrate 100 may be removed and replaced with insulating substrate 101 to form the lower source / drain contact bCA. For example, insulating substrate 101 may include silicon oxide (SiO2).

[0124] According to the example, when removing the substrate 100 to form the lower source / drain contact bCA, the substrate 100 can be removed until the dummy source / drain pattern 155 can be exposed. Therefore, the lower end of the dummy source / drain pattern 155 can have a flat shape and can contact the lower wiring structure M1b.

[0125] According to the example, the separation pattern 500 may be disposed between an upper source / drain contact aCA and another upper source / drain contact aCA spaced apart in the first direction D1. Alternatively, the separation pattern 500 may be disposed between a lower source / drain contact bCA and another lower source / drain contact bCA spaced apart in the first direction D1. Alternatively, the separation pattern 500 may be disposed between the lower source / drain contact bCA and a dummy source / drain pattern 155 spaced apart from the lower source / drain contact bCA in the first direction D1. Alternatively, the separation pattern 500 may be disposed between a dummy source / drain pattern 155 and another dummy source / drain pattern 155 spaced apart in the first direction D1.

[0126] According to the example, the separation pattern 500 can be separated from the lower wiring structure M1b on the third direction D3. That is, the lower end of the separation pattern 500 may not contact the upper end of the lower wiring structure M1b. An insulating substrate 101 may be disposed between the separation pattern 500 and the lower wiring structure M1b.

[0127] According to the example, the lower end of the gate dicing pattern 600 may contact the upper end of the lower wiring structure M1b. Alternatively, the gate dicing pattern 600 may be disposed between one lower source / drain contact bCA and another lower source / drain contact bCA spaced apart in the second direction D2. Alternatively, the gate dicing pattern 600 may be disposed between one lower source / drain contact bCA in the second direction D2 and a dummy source / drain pattern 155 spaced apart in the second direction D2. Alternatively, the gate dicing pattern 600 may be disposed between one dummy source / drain pattern 155 in the second direction D2 and another dummy source / drain pattern 155 spaced apart in the second direction D2.

[0128] According to the example, the upper part of the through-hole 650 can be connected to the upper source / drain contact aCA, and the lower part of the through-hole 650 can be connected to the lower source / drain contact bCA. Therefore, the through-hole 650 can be connected between the upper source / drain contact aCA and the lower source / drain contact bCA. In addition, the through-hole 650 can be connected to the lower wiring structure M1b.

[0129] The lower end of the through-hole member 650 may not contact the upper end of the lower wiring structure M1b. The gap-filling insulating layer 620 of the gate dicing pattern 600 may be disposed between the through-hole member 650 and the lower wiring structure M1b. The connecting portion CM may be disposed between the through-hole member 650 and the lower wiring structure M1b.

[0130] According to the example, the upper source / drain contact aCA may pass through the second interlayer insulating layer 120 and thus be electrically connected to the upper source / drain pattern USD. Additionally, in some embodiments, the upper gate contact may pass through the second interlayer insulating layer 120 and the gate cap pattern GP, ​​and thus be electrically connected to the gate pattern GE.

[0131] The upper source / drain contact aCA may extend in the second direction D2 and thus be connected to the through-hole 650. A portion of the upper source / drain contact aCA may be inserted into the gate dicing pattern 600. That is, a portion of the upper source / drain contact aCA may overlap with a portion of the gate dicing pattern 600 in the third direction D3. For example, a portion of the upper source / drain contact aCA may be located above the gap-filling insulating layer 620 via the insulating liner 610 of the gate dicing pattern 600. For example, the upper source / drain contact aCA may contact the through-hole 650. Therefore, the upper source / drain contact aCA may be connected to the lower source / drain contact bCA via the through-hole 650.

[0132] In some embodiments, the upper source / drain contact aCA may include a conductive pattern and a barrier pattern surrounding the conductive pattern. For example, the conductive pattern may include aluminum (Al), copper (Cu), tungsten (W), molybdenum (Mo), or combinations thereof. The barrier pattern may cover the side and bottom surfaces of the conductive pattern. The barrier pattern may include a metal layer or a metal nitride layer. The metal layer may include titanium (Ti), tantalum (Ta), tungsten (W), nickel (Ni), cobalt (Co), platinum (Pt), or combinations thereof. The metal nitride layer may include titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), nickel nitride (NiN), cobalt nitride (CoN), platinum nitride (PtN), or combinations thereof.

[0133] In some embodiments, an interlayer insulation layer may be disposed on the upper source / drain contact aCA and cover the upper source / drain contact aCA.

[0134] According to the example, the lower source / drain contact bCA may be disposed below the lower source / drain pattern LSD and may be electrically connected to the lower source / drain pattern LSD. For example, the lower source / drain contact bCA may pass through the insulating substrate 101 and may be electrically connected to the lower source / drain pattern LSD.

[0135] According to the example, the connecting portion CM can be disposed below the lower source / drain contact bCA and the through-hole 650. The connecting portion CM can extend in the second direction D2 to connect the lower source / drain contact bCA and the through-hole 650. Therefore, the lower source / drain contact bCA can be connected to the upper source / drain contact aCA through the connecting portion CM and the through-hole 650.

[0136] According to the example, the connection portion CM may be disposed on the third-direction D3 between the lower wiring structure M1b, the lower source / drain contact bCA, and the through-hole 650. A portion of the connection portion CM may be inserted into the gate dicing pattern 600. That is, a portion of the connection portion CM may overlap with a portion of the gate dicing pattern 600 on the third-direction D3. For example, a portion of the connection portion CM may pass through the insulating liner 610 of the gate dicing pattern 600 and may be connected to the through-hole 650.

[0137] Alternatively, the lower gate contact may be disposed below and electrically connected to the lower gate pattern LGE. For example, the lower gate contact may be electrically connected to the lower gate pattern LGE via the insulating substrate 101 or the device isolation layer ST.

[0138] In some embodiments, each of the lower source / drain contact bCA and the lower gate contact may include a conductive pattern and a blocking pattern surrounding the conductive pattern. For example, the conductive pattern may include aluminum (Al), copper (Cu), tungsten (W), molybdenum (Mo), or combinations thereof. The blocking pattern may cover the side and bottom surfaces of the conductive pattern. The blocking pattern may include a metal layer or a metal nitride layer. The metal layer may include titanium (Ti), tantalum (Ta), tungsten (W), nickel (Ni), cobalt (Co), platinum (Pt), or combinations thereof. The metal nitride layer may include titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), nickel nitride (NiN), cobalt nitride (CoN), platinum nitride (PtN), or combinations thereof.

[0139] According to the example, the lower wiring structure M1b can be located below the lower source / drain contact bCA and the lower gate contact.

[0140] The lower wiring structure M1b may include a lower interlayer insulation layer 410 and a lower metal layer 420 disposed in the lower interlayer insulation layer 410.

[0141] The lower interlayer insulating layer 410 can be disposed below the lower source / drain contact bCA and the lower gate contact, and can cover the lower end of the insulating substrate 101, the device isolation layer ST, the lower source / drain contact bCA, the lower gate contact, the dummy source / drain pattern 155, the connection portion CM and the separation pattern 500.

[0142] The lower interlayer insulating layer 410 may include an insulating material, and for example, may include silicon oxide (SiO2), silicon nitride (SiN), silicon oxynitride (SiON), a low dielectric material, or a combination thereof.

[0143] The lower metal layer 420 may be disposed within the lower interlayer insulating layer 410. The lower metal layer 420 may include a lower power line, a lower wiring, and a lower through-hole. The lower through-hole may be disposed on the lower power line and the lower wiring. The lower through-hole may be located between the lower source / drain contact bCA, the lower gate contact, and the connection portion CM and the lower power line and the lower wiring, respectively.

[0144] The lower power lines and lower wirings of the lower metal layer 420 may contain the same or different conductive materials. For example, the lower power lines and lower wirings may include aluminum (Al), copper (Cu), tungsten (W), molybdenum (Mo), cobalt (Co), or combinations thereof.

[0145] Reference Figures 8 to 45 The above describes a method for manufacturing a semiconductor device according to an example. Additionally, the above... Figures 1 to 7 Can also be used with Figures 8 to 45 Please refer to the descriptions together.

[0146] Figures 8 to 45 This is a cross-sectional view of the process sequence of a semiconductor device manufacturing method according to an example embodiment.

[0147] Figure 8 This is a top view of a semiconductor device according to an example embodiment. Figure 9 According to the example embodiment Figure 8 A cross-sectional view taken along lines A-A' and D-D'. Figure 10 According to the example embodiment Figure 8 A cross-sectional view taken along line B-B'. Figure 11 According to the example embodiment Figure 8 A cross-sectional view taken along line C-C'.

[0148] Reference Figures 8 to 11 It can provide a semiconductor device in which a first active region AR1 and a second active region AR2 can be stacked sequentially on a substrate 100.

[0149] A first sacrificial layer and a first active layer may be stacked alternately on the substrate 100. An intermediate insulating structure (DSP) and a dummy channel pattern (SDL) may be stacked on the first sacrificial layer and the first active layer. A second sacrificial layer and a second active layer may be stacked on the dummy channel pattern (SDL).

[0150] The substrate 100 may be a semiconductor substrate containing silicon (Si), germanium (Ge), silicon-germanium (SiGe), or a compound semiconductor substrate. For example, the substrate 100 may be a silicon (Si) substrate.

[0151] According to the example, the first sacrificial layer and the second sacrificial layer may contain materials that are different from the materials of the first active layer and the second active layer. The first sacrificial layer and the second sacrificial layer may contain silicon (Si), germanium (Ge), or silicon-germanium (SiGe), and the first active layer and the second active layer may contain silicon (Si), germanium (Ge), or silicon-germanium (SiGe). For example, the first sacrificial layer and the second sacrificial layer may contain silicon-germanium (SiGe), and the first active layer and the second active layer may contain silicon (Si).

[0152] The stacked first and second sacrificial layers, first and second active layers, intermediate insulating structure DSP, and dummy channel pattern SDL can be patterned to form a stacked pattern. For example, the stacked pattern can be formed by the following steps: forming a hard mask pattern on the uppermost second active layer; and etching the stacked layers on the substrate 100 using the hard mask pattern as an etch mask. Simultaneously with forming the stacked pattern, the upper portion of the substrate 100 can be patterned to form a trench TR defining a bottom pattern BP. The stacked pattern may have stripes extending in a first direction D1.

[0153] The stacking pattern may include a lower stacking pattern on the bottom pattern BP and an upper stacking pattern on the lower stacking pattern. The lower stacking pattern may include a first sacrificial layer and a first active layer that can be stacked alternately. The upper stacking pattern may include a second sacrificial layer and a second active layer that can be stacked alternately.

[0154] A device isolation layer ST with filled trenches can be formed on the substrate 100. For example, an insulating layer covering the bottom pattern BP and the stacked pattern can be formed over the entire surface of the substrate 100. The device isolation layer ST can be formed by recessing the insulating layer until the stacked pattern STP is exposed.

[0155] Multiple sacrificial patterns can be formed across a stacked pattern. Each sacrificial pattern can be formed as a line extending in a second direction D2. For example, a sacrificial pattern can be formed by the following steps: forming a sacrificial layer on a stacked pattern; forming a hard mask pattern on the sacrificial layer; and patterning the sacrificial layer using the hard mask pattern as an etch mask. The sacrificial layer may include amorphous silicon or polycrystalline silicon.

[0156] Additionally, an initial capping layer and a pair of gate spacers GS can be formed on the two side surfaces of the sacrificial pattern in the first direction D1, respectively.

[0157] By using the sacrificial pattern, the initial capping layer, and the gate spacer GS as an etching mask, at least a portion of the stacked pattern and the bottom pattern BP can be etched to form a recess, and a dummy source / drain pattern 155, a lower source / drain pattern LSD, a first interlayer stop film ESL1, a first interlayer insulating layer 110, an upper source / drain pattern USD, a second interlayer stop film ESL2, and a second interlayer insulating layer 120 can be sequentially formed in the recess.

[0158] The initial capping layer can be removed to expose the sacrificial pattern, and the exposed sacrificial pattern can be removed to form the first recess. For example, the sacrificial pattern can be removed by wet etching using an etch solution that selectively etches polysilicon. As the sacrificial pattern is removed, a first sacrificial layer and a second sacrificial layer can be exposed.

[0159] An etching process can be performed to selectively etch the exposed first and second sacrificial layers, thereby removing only the first and second sacrificial layers while retaining the first semiconductor pattern SP1 and the second semiconductor pattern SP2.

[0160] For example, the etching process for the first and second sacrificial layers can achieve a high etching rate for silicon-germanium (SiGe). For example, the etching process can achieve a high etching rate for silicon-germanium (SiGe) with a germanium (Ge) content greater than ten (10) atomic percentages (at%). However, embodiments of this disclosure are not limited thereto, and the germanium (Ge) content can vary depending on design constraints.

[0161] According to the example, the gate pattern GE can be formed in the region of the removable sacrificial pattern and the first sacrificial layer and the second sacrificial layer.

[0162] A gate insulating layer GI can be conventionally formed in the region where the sacrificial pattern can be removed and the first and second sacrificial layers are located.

[0163] A gate pattern GE can be formed on the gate insulating layer GI. The gate pattern GE can be formed by the following steps: forming a lower gate pattern LGE including a first gate portion PO1 to a third gate portion PO3 between the first semiconductor patterns SP1; and forming an upper gate pattern UGE including a fourth gate portion PO4 to a sixth gate portion PO6 between the second semiconductor patterns SP2.

[0164] The gate pattern GE can be recessed to reduce its height. A gate cap pattern GP can be formed on the recessed gate pattern GE. A planarization process can be performed on the gate cap pattern GP so that the upper surface of the gate cap pattern GP is coplanar with the upper surface of the second interlayer insulating layer 120.

[0165] Figure 12 This is a top view of a semiconductor device according to an example embodiment. Figure 13 According to the example embodiment Figure 12 A cross-sectional view taken along lines A-A' and D-D'. Figure 14 According to the example embodiment Figure 12 A cross-sectional view taken along line B-B'. Figure 15 According to the example embodiment Figure 12 A cross-sectional view taken along line C-C'.

[0166] Reference Figures 12 to 15 A first hard mask pattern 210 may be formed on the second interlayer insulating layer 120 and the gate cap pattern GP. For example, the first hard mask pattern 210 may be formed to cover the upper surface of the second interlayer insulating layer 120 and the gate cap pattern GP.

[0167] The first hard mask pattern 210 can be used as an etching mask to etch the gate cap pattern GP, ​​thereby forming a first recess that exposes the gate pattern GE. For example, the first recess can be formed on the gate pattern GE in a manner that extends along the second direction D2.

[0168] Figure 16 This is a top view of a semiconductor device according to an example embodiment. Figure 17 According to the example embodiment Figure 16 A cross-sectional view taken along lines A-A' and D-D'. Figure 18 According to the example embodiment Figure 16 A cross-sectional view taken along line B-B'. Figure 19 According to the example embodiment Figure 16 A cross-sectional view taken along line C-C'.

[0169] Reference Figures 16 to 19 The gate pattern GE exposed through the first recess can be removed. In this case, the upper channel pattern UCH and lower channel pattern LCH exposed along with the gate pattern GE can also be removed.

[0170] According to the example, portions of the bottom pattern BP and the device isolation layer ST disposed below the gate pattern GE can be removed together with the gate pattern GE to form a second recess. The horizontal height of the lower end of the second recess may be lower than the horizontal height of the lower end of the gate pattern GE and may be higher than the horizontal height of the upper end of the substrate 100.

[0171] According to the example, the separator 500L can be formed by filling the second recess with an insulating material. The separator 500L can be formed to cover the upper surface of the first hard mask pattern 210.

[0172] For example, the separator 500L may include an insulating material. For example, the separator 500L may include silicon oxide (SiO2), silicon nitride (SiN), silicon oxynitride (SiON), a high dielectric constant (high k) material having a higher dielectric constant than silicon oxide (SiO2), or a combination thereof, and may include silicon nitride (SiN).

[0173] Figure 20 This is a top view of a semiconductor device according to an example embodiment. Figure 21 According to the example embodiment Figure 20 A cross-sectional view taken along lines A-A' and D-D'. Figure 22 According to the example embodiment Figure 20 A cross-sectional view taken along line B-B'. Figure 23 According to the example embodiment Figure 20 A cross-sectional view taken along line C-C'.

[0174] Reference Figures 20 to 23 The separation pattern 500 can be formed by patterning the separation element 500L until the gate cap pattern GP is exposed. The planarization process can be performed using an etch-back process or a chemical mechanical polishing (CMP) process.

[0175] While performing the planarization process, the first hard mask pattern 210 can also be removed. For example, while performing the planarization process, the separator 500L on the first hard mask pattern 210 can be removed, and the first hard mask pattern 210 can also be removed. In this case, the separator 500L disposed between the first hard mask patterns 210 spaced apart along the second direction D2 can also be removed.

[0176] As described, since the separation pattern 500 can be formed at the location where the gate pattern GE can be removed, the width of the separation pattern 500 in the first direction D1 can be similar to or substantially the same as the width of the gate pattern GE in the first direction D1.

[0177] According to the example, the split pattern 500 may extend onto the third direction D3. For example, the upper surface of the split pattern 500 may be coplanar with the upper surface of the gate cap pattern GP. The horizontal height of the lower end of the split pattern 500 may be lower than the horizontal height of the lower end of the gate pattern GE.

[0178] Figure 24 This is a top view of a semiconductor device according to an example embodiment. Figure 25 According to the example embodiment Figure 24 A cross-sectional view taken along lines A-A' and D-D'. Figure 26 According to the example embodiment Figure 24 A cross-sectional view taken along line B-B'. Figure 27 According to the example embodiment Figure 24 A cross-sectional view taken along line C-C'.

[0179] Reference Figures 24 to 27 The insulating liner layer 610L and the gap-filling insulating layer 620L can be formed on the second direction D2 between a lower channel pattern LCH and an upper channel pattern UCH and another lower channel pattern LCH and another upper channel pattern UCH.

[0180] According to the example, a second hard mask pattern 310 may be formed on the second interlayer insulating layer 120, and the second hard mask pattern 310 may be used as an etching mask to etch portions of the first interlayer insulating layer 110 and the second interlayer insulating layer 120. An insulating liner layer 610L may be conformally applied to the area where a portion of the first interlayer insulating layer 110 and a portion of the second interlayer insulating layer 120 has been removed, and the space between the insulating liner layers 610L may then be filled using a gap-filling insulating layer 620L.

[0181] For example, the gap-filling insulating layer 620L may include silicon oxide (SiO2) and the insulating liner layer 610L may include silicon nitride (SiN).

[0182] According to the example, the insulating liner layer 610L can be conformally applied to the upper surface of the second hard mask pattern 310, the side surfaces of the second hard mask pattern 310, and the exposed side surfaces of the first interlayer insulating layer 110 and the second interlayer insulating layer 120. The gap-filling insulating layer 620L can cover the upper surface of the insulating liner layer 610L while filling the space between the insulating liner layers 610L.

[0183] According to the example, while the first interlayer insulating layer 110 and the second interlayer insulating layer 120 can be etched, the separation pattern 500 disposed between the gate patterns GE in the second direction D2 can be almost not etched. Therefore, the insulating liner layer 610L and the gap-filling insulating layer 620L can be omitted in the second direction D2.

[0184] Figure 28 This is a top view of a semiconductor device according to an example embodiment. Figure 29 According to the example embodiment Figure 28 A cross-sectional view taken along lines A-A' and D-D'. Figure 30 According to the example embodiment Figure 28 A cross-sectional view taken along line B-B'. Figure 31 According to the example embodiment Figure 28 A cross-sectional view taken along line E-E'.

[0185] Reference Figures 28 to 31The gate dicing pattern 600 can be formed by planarizing the insulating liner layer 610L and the gap-filling insulating layer 620L until the gate cap pattern GP is exposed. The planarization process can be performed using an etch-back process or a chemical mechanical polishing (CMP) process.

[0186] The second hard mask pattern 310 can also be removed while performing the planarization process. For example, while performing the planarization process, the gap-filling insulating layer 620L and the insulating liner layer 610L can be removed in sequence, and the second hard mask pattern 310 can also be removed.

[0187] Therefore, the gate dicing pattern 600 can be formed on the second direction D2 between a lower channel pattern LCH and an upper channel pattern UCH and another lower channel pattern LCH and another upper channel pattern UCH.

[0188] According to the example, as the separation pattern 500 can be disposed between the gate patterns GE in the second direction D2, the gate cutting pattern 600 may not be formed between the gate patterns GE in the second direction D2.

[0189] According to the example, the gate dicing pattern 600 may extend in the third direction D3. For example, the upper surface of the gate dicing pattern 600 may be coplanar with the upper surface of the second interlayer insulating layer 120. The horizontal height of the lower end of the gate dicing pattern 600 may be substantially the same as the horizontal height of the upper surface of the substrate 100.

[0190] Figure 32 This is a top view of a semiconductor device according to an example embodiment. Figure 33 According to the example embodiment Figure 32 A cross-sectional view taken along lines A-A' and D-D'. Figure 34 According to the example embodiment Figure 32 A cross-sectional view taken along line B-B'. Figure 35 According to the example embodiment Figure 32 A cross-sectional view taken along line E-E'. Figure 36 Based on some example embodiments Figure 32 A cross-sectional view taken along line E-E'.

[0191] Reference Figures 32 to 36 The recess can be formed by etching the gap in the gate dicing pattern 600 at the location where the through-hole 650 can be formed to fill the insulating layer 620.

[0192] According to the example, a third hard mask pattern 401 and a fourth hard mask pattern 402 can be formed on the second interlayer insulating layer 120. (See reference...) Figure 35According to the example, the third hard mask pattern 401 and the fourth hard mask pattern 402 may be formed in areas other than the area where the through-hole 650 may be formed. For example, the third hard mask pattern 401 and the fourth hard mask pattern 402 may be formed to cover the gate cap pattern GP and the separator pattern 500. However, embodiments of the present disclosure are not limited thereto, and the shape or position of the third hard mask pattern 401 and the fourth hard mask pattern 402 may be changed in various ways. For example, as Figure 36 As shown, the third hard mask pattern 401 and the fourth hard mask pattern 402 can be formed to cover the gate cap pattern GP but not the separation pattern 500.

[0193] For example, the third hard mask pattern 401 may include silicon oxide (SiO2), and the fourth hard mask pattern 402 may include a metal layer or a metal nitride layer.

[0194] According to the example, the insulating liner 610 and the separation pattern 500 may include materials that are etch-selective relative to the gap-filling insulating layer 620. For example, the gap-filling insulating layer 620 may include silicon oxide (SiO2), the insulating liner 610 may include silicon nitride (SiN), and the separation pattern 500 may include silicon nitride (SiN).

[0195] According to the example, the third hard mask pattern 401 and the fourth hard mask pattern 402 can be used as etching masks to etch the gap-filling insulating layer 620 of the gate cut pattern 600. In this case, the insulating liner 610 may not be etched.

[0196] Furthermore, the separation pattern 500 may not be etched during the etching process. For example, even when the third hard mask pattern 401 and the fourth hard mask pattern 402 cover the gate cap pattern GP but not the separation pattern 500, the separation pattern 500 may not be etched while the etching process for the gap-filling insulating layer 620 can be performed.

[0197] According to the example, at least a portion of the gap-filling insulating layer 620 may be removed during the etching process. In this case, the gap-filling insulating layer 620 may not be completely removed. For example, at least a portion of the gap-filling insulating layer 620 may remain between the separation patterns 500 in the first direction D1.

[0198] Figure 37 This is a top view of a semiconductor device according to an example embodiment. Figure 38 According to the example embodiment Figure 37 A cross-sectional view taken along lines A-A' and D-D'. Figure 39 According to the example embodiment Figure 37 A cross-sectional view taken along line B-B'. Figure 40 According to the example embodiment Figure 37A cross-sectional view taken along line E-E'. Figure 41 Based on some example embodiments Figure 37 A cross-sectional view taken along line E-E'.

[0199] Reference Figures 37 to 41 A passivation layer 710 can be formed in the area where the gap-filling insulating layer 620 can be removed, and the fourth hard mask pattern 402 can be removed.

[0200] According to the example, a passivation layer 710 may be formed in the area from which the gap-filling insulating layer 620 can be removed to protect the area exposed by removing the gap-filling insulating layer 620. The passivation layer 710 may fill the area of ​​the removable gap-filling insulating layer 620. For example, the passivation layer 710 may comprise a carbon material. The fourth hard mask pattern 402 is removable. In some examples, the step of forming the passivation layer 710 in the area of ​​the removable gap-filling insulating layer 620 may be omitted. In this case, a through-hole 650 may be formed in the area of ​​the removable gap-filling insulating layer 620.

[0201] According to the example, with the removable fourth hard mask pattern 402, such as Figure 40 As shown, the third hard mask pattern 401 can be retained on the gate cap pattern GP and the separation pattern 500. According to some examples, such as... Figure 41 As shown, the third hard mask pattern 401 is retained on the gate cap pattern GP and can expose the upper surface of the separation pattern 500.

[0202] Figure 42 This is a top view of a semiconductor device according to an example embodiment. Figure 43 According to the example embodiment Figure 42 A cross-sectional view taken along lines A-A' and D-D'. Figure 44 According to the example embodiment Figure 42 A cross-sectional view taken along line B-B'. Figure 45 According to the example embodiment Figure 42 A cross-sectional view taken along line E-E'.

[0203] Reference Figures 42 to 45 The passivation layer 710 can be removed, and a through-hole 650 can be formed in the area where the passivation layer 710 can be removed.

[0204] According to the example, the area from which the passivation layer 710 can be removed can be filled with a metallic material. For example, the metallic material may include aluminum (Al), copper (Cu), tungsten (W), molybdenum (Mo), titanium (Ti), tantalum (Ta), tungsten (W), nickel (Ni), cobalt (Co), platinum (Pt), titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), nickel nitride (NiN), cobalt nitride (CoN), platinum nitride (PtN), or combinations thereof.

[0205] As an example, the through-hole 650 can be formed by planarizing the metal material until the gate cap pattern GP is exposed. The planarization process can be performed using an etch-back process or a chemical mechanical polishing (CMP) process.

[0206] The third hard mask pattern 401 can also be removed during the planarization process. For example, in the planarization process, the third hard mask pattern 401 can be removed after the metal material on the third hard mask pattern 401 is removed.

[0207] As described above, according to this disclosure, since the gate dicing pattern 600 can be formed after the separation pattern 500 can be formed between the gate patterns GE in the second direction D2, the gate dicing pattern 600 may not overlap with the gate pattern GE in the second direction D2. Therefore, the through-piece 650 formed in the gate dicing pattern 600 may not overlap with the gate pattern GE in the second direction D2, and short circuits between the gate patterns GE can be prevented.

[0208] Then, return to the reference. Figure 6 and Figure 7 An upper source / drain contact aCA can be formed to contact the upper source / drain pattern USD. In some embodiments, an upper wiring structure can be formed that can be connected to the upper source / drain pattern USD via the upper source / drain contact aCA. The upper wiring structure may include upper wiring, upper through-hole, and upper insulating layer. The upper wiring and upper through-hole may comprise metal (copper, according to an example). The upper insulating layer may be disposed between the upper wiring and the upper through-hole to insulate them. The upper insulating layer may cover the second interlayer insulating layer 120. The upper wiring and upper through-hole may be disposed within the upper insulating layer.

[0209] When the substrate 100 and the bottom pattern BP comprise a semiconductor material such as (but not limited to) silicon (Si), the silicon (Si) can be removed and replaced with an insulating substrate 101. For example, the insulating substrate 101 may comprise silicon oxide (SiO2).

[0210] Subsequently, a lower source / drain contact bCA that can be connected to the lower source / drain pattern LSD can be formed, and a lower gate contact that can be connected to the lower gate pattern LGE can be formed.

[0211] For example, a portion of the dummy source / drain pattern 155 can be removed to form a contact hole through which the lower source / drain pattern LSD can be exposed. A lower source / drain contact bCA can be formed that is electrically connected to the lower source / drain pattern LSD while filling the contact hole.

[0212] A patterning process can be performed to remove a portion of the insulating substrate 101 or the device isolation layer ST, thereby forming a contact hole through which the lower gate pattern LGE of the gate pattern GE can be exposed. In this case, the contact hole can pass through the insulating substrate 101 or the device isolation layer ST. A lower gate contact that is electrically connected to the lower gate pattern LGE of the gate pattern GE can be formed while filling the contact hole.

[0213] A connection portion CM can be formed extending from below the lower source / drain contact bCA to below the through-hole 650. For example, after performing a patterning process, the connection portion CM can be formed by filling metal to connect the lower source / drain contact bCA and the through-hole 650.

[0214] Although the above describes the case where the lower source / drain contact bCA, the lower gate contact, and the connection portion CM can be formed by separate processes, the embodiments of this disclosure are not limited thereto, and the lower source / drain contact bCA, the lower gate contact, and the connection portion CM can be formed simultaneously, or the lower gate contact can be formed first, and then the lower source / drain contact bCA and the connection portion CM can be formed.

[0215] A lower wiring structure M1b may be formed in the lower end of the insulating substrate 101 and the device isolation layer ST, including a lower metal layer 420 electrically connected to the lower source / drain contact bCA, the lower gate contact and the connection portion CM, and a lower interlayer insulating layer 410 covering the lower metal layer 420.

[0216] While this disclosure has been described in conjunction with what is now considered a practical example, it should be understood that this disclosure is not limited to the disclosed examples. Rather, it is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims.

Claims

1. A semiconductor device, comprising: The lower channel pattern and the lower source / drain pattern are alternately disposed on the substrate in a first direction; The upper channel pattern on the lower channel pattern and the upper source / drain pattern on the lower source / drain pattern; Gate patterns spaced apart in a second direction intersecting the first direction and at least partially surrounding the lower channel pattern and the upper channel pattern; A separation pattern that at least partially passes through the gate pattern upwards on a third direction intersecting the first and second directions; as well as A through-hole member, which is spaced apart by the separation pattern in the first direction, extends upward in the third direction, and is coupled to at least one of the lower source / drain pattern or the upper source / drain pattern.

2. The semiconductor device according to claim 1, wherein, The through-hole is not between the gate patterns.

3. The semiconductor device according to claim 1, wherein, The lower source / drain pattern includes a first lower source / drain pattern and a second lower source / drain pattern. The upper source / drain pattern includes a first upper source / drain pattern and a second upper source / drain pattern. The semiconductor device further includes a gate dicing pattern in the second direction between the first lower source / drain pattern and the second lower source / drain pattern, and in the second direction between the first upper source / drain pattern and the second upper source / drain pattern. The through-hole member is disposed in the gate dicing pattern.

4. The semiconductor device of claim 3, further comprising a dummy lower source / drain pattern below the lower source / drain pattern. in, The lower end of the separation pattern is at a higher horizontal level than the lower end of the dummy source / drain pattern, and Wherein, the horizontal height of the lower end of the gate dicing pattern is higher than or equal to the horizontal height of the lower end of the dummy source / drain pattern.

5. The semiconductor device according to claim 3, wherein, The gate dicing pattern includes a gap-filling insulating layer and an insulating liner disposed on opposite sides of the gap-filling insulating layer in the second direction.

6. The semiconductor device according to claim 5, wherein, The through-hole member contacts the insulating liner in the second direction, and Wherein, the gap-filling insulating layer at least partially overlaps the through-piece in the third direction below the through-piece.

7. The semiconductor device according to claim 5, wherein, The gap-filling insulating layer comprises silicon oxide. The insulating liner comprises silicon nitride, and The separation pattern includes silicon nitride.

8. A semiconductor device, comprising: An insulating substrate, comprising a first side and a second side facing each other; The lower channel pattern and the lower source / drain pattern are alternately arranged on the first side in a first direction; The upper channel pattern on the lower channel pattern and the upper source / drain pattern on the lower source / drain pattern; Gate patterns spaced apart in a second direction intersecting the first direction and at least partially surrounding the lower channel pattern and the upper channel pattern; A separation pattern that at least partially passes through the gate pattern upwards on a third direction intersecting the first and second directions; A through-hole member, which is spaced apart by the separation pattern in the first direction, extends upward in the third direction, and is coupled to at least one of the lower source / drain pattern or the upper source / drain pattern; as well as The lower wiring structure is located on the second side and is coupled to the through-hole.

9. The semiconductor device according to claim 8, wherein, The through-hole is not between the gate patterns.

10. The semiconductor device of claim 8, further comprising: Upper source / drain contact element, which is on the upper source / drain pattern and coupled to the upper source / drain pattern; as well as Lower source / drain contacts are located below and coupled to the lower source / drain pattern. The upper source / drain contact and the lower source / drain contact are coupled to the through-hole.

11. The semiconductor device of claim 8, further comprising: The connection portion extends in the second direction below the lower source / drain contact and the through-hole, and couples the lower source / drain contact to the through-hole.

12. The semiconductor device according to claim 8, wherein, The lower source / drain pattern includes a first lower source / drain pattern and a second lower source / drain pattern. The upper source / drain pattern includes a first upper source / drain pattern and a second upper source / drain pattern. The semiconductor device further includes a gate dicing pattern in the second direction between the first lower source / drain pattern and the second lower source / drain pattern, and between the first upper source / drain pattern and the second upper source / drain pattern. The through-hole member is disposed in the gate dicing pattern.

13. The semiconductor device of claim 12, further comprising a dummy lower source / drain pattern disposed below the lower source / drain pattern. in, The lower end of the separation pattern is at a higher horizontal level than the lower end of the dummy source / drain pattern, and Wherein, the horizontal height of the lower end of the gate dicing pattern is higher than or equal to the horizontal height of the lower end of the dummy source / drain pattern.

14. The semiconductor device according to claim 13, wherein, The lower end of the separation pattern separates from the lower wiring structure in the third direction. Wherein, the lower end of the gate dicing pattern contacts the lower wiring structure, and The lower end of the dummy source / drain pattern contacts the lower wiring structure.

15. The semiconductor device according to claim 12, wherein, The gate dicing pattern includes a gap-filling insulating layer and an insulating liner disposed on opposite sides of the gap-filling insulating layer in the second direction.

16. The semiconductor device according to claim 15, wherein, The through-hole member contacts the insulating liner in the second direction, and Wherein, the gap-filling insulating layer at least partially overlaps the through-piece in the third direction below the through-piece.

17. The semiconductor device according to claim 15, wherein, The gap-filling insulating layer comprises silicon oxide. The insulating liner comprises silicon nitride, and The separation pattern includes silicon nitride.

18. A semiconductor device, comprising: The lower channel pattern and the lower source / drain pattern are alternately disposed on the substrate in a first direction; The upper channel pattern on the lower channel pattern and the upper source / drain pattern on the lower source / drain pattern; Gate patterns spaced apart in a second direction intersecting the first direction and at least partially surrounding the lower channel pattern and the upper channel pattern; A gate dicing pattern disposed in the second direction between one of the lower source / drain patterns and one of the upper source / drain patterns and the other of the lower source / drain patterns and the other of the upper source / drain patterns; A separation pattern that at least partially passes through the gate pattern upwards on a third direction intersecting the first and second directions; as well as A through-hole member, disposed in the gate dicing pattern, extending upward in the third direction, and coupled to at least one of the lower source / drain pattern or the upper source / drain pattern. The separation pattern and the through-hole are alternately arranged along the first direction.

19. The semiconductor device according to claim 18, wherein, The through-hole members are not disposed between the gate patterns.

20. The semiconductor device of claim 18, further comprising a dummy lower source / drain pattern below the lower source / drain pattern. in, The lower end of the separation pattern is at a higher horizontal level than the lower end of the dummy source / drain pattern, and Wherein, the horizontal height of the lower end of the gate dicing pattern is higher than or equal to the horizontal height of the lower end of the dummy source / drain pattern.

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