Storage unit, optical memory and method of manufacture, method of storing optical signals

Abstract

The application provides a storage unit, an optical memory and a preparation method, and a storage method of an optical signal, and relates to the technical field of information materials and devices. The storage unit comprises at least one transistor. The transistor comprises a substrate, a first gate, a first channel part, a first electrode and a second electrode, and a passivation layer. The material of the first channel part comprises amorphous oxide. The passivation layer has a first opening, and the first opening exposes at least part of the first channel part. According to the scheme, the amorphous oxide is used as the material of the first channel part of the transistor, and the first channel part can directly receive light signal irradiation. By using the light response characteristics of the amorphous oxide, the light signal can be directly mapped to the electrical state of the storage unit without additional photoelectric conversion circuit, the writing and keeping of the optical information are realized, the optical storage structure is simplified, and the power consumption and the delay are reduced.

Description

Technical Field

[0001] This application relates to the field of information materials and devices, and in particular to a storage unit, an optical memory and its preparation method, and a method for storing optical signals. Background Technology

[0002] With the rapid development of new-generation information technology, various application scenarios are placing higher demands on storage systems. Achieving efficient storage of optical signals at the semiconductor device level has become an important research direction in the fields of integrated circuits and information storage.

[0003] However, most existing optical storage technologies rely on dedicated photosensitive storage media or require the introduction of additional photoelectric conversion units. Their basic structure and working mechanism are primarily designed for electrical signals, requiring the optical signal to be converted into an electrical signal before being written to the storage device. This indirect optical storage method significantly increases system complexity, power consumption, and signal latency, hindering high-density integration. Furthermore, the design of existing storage cells is mainly optimized for electrical writing and reading, and their structure and bias conditions do not consider the impact of illumination on the device's electrical characteristics. The mechanisms for utilizing photogenerated carriers for information storage are still imperfect, or lack targeted structural designs, thus limiting the development of optical storage technology. Summary of the Invention

[0004] This application provides a storage unit, an optical memory, a method for fabricating the same, and a method for storing optical signals, aiming to achieve direct modulation of the storage unit state by optical signals by utilizing the photoresponse characteristics of amorphous oxide semiconductors.

[0005] To achieve the above objectives, the embodiments of this application adopt the following technical solutions: In a first aspect, a memory cell is provided, characterized in that it includes at least one transistor.

[0006] The transistor includes a substrate, a first gate, a first channel, a first electrode, a second electrode, and a passivation layer. The first gate is disposed on the substrate and extends along a first direction parallel to the substrate. The first channel is disposed on the side of the first gate away from the substrate and extends along a second direction parallel to the substrate and intersecting the first direction. The material of the first channel includes an amorphous oxide. The orthographic projection of the first channel onto the substrate at least partially overlaps with the orthographic projection of the first gate onto the substrate. The first electrode and the second electrode extend along the first direction and are spaced apart along the second direction. The orthographic projection of the portion between the first electrode and the second electrode onto the substrate overlaps with the orthographic projection of the first channel onto the substrate and also overlaps with the orthographic projection of the first gate onto the substrate. The passivation layer has a first opening that exposes at least a portion of the first channel.

[0007] In the storage cell provided in this application embodiment, amorphous oxide is used as the material for the first channel of the transistor, enabling the first channel to directly receive optical signal illumination. Utilizing the photoresponse characteristics of amorphous oxide, the optical signal can be directly mapped to the electrical state of the storage cell without the need for additional photoelectric conversion circuitry, achieving the writing and retention of optical information. This simplifies the optical storage structure and reduces power consumption and latency. Therefore, this storage cell achieves direct modulation, stable retention, and readability of optical signals, providing a feasible solution for optical storage.

[0008] In some embodiments, the material of the first channel portion includes an amorphous oxide of at least one element selected from In, Ga, Zn, Sn, and W.

[0009] In some embodiments, the first transistor further includes a gate dielectric layer located between the first channel and the first gate; the material of the gate dielectric layer includes SiO2 and SiN. x HfO2, HfZrO x HfAlO x HfSiO x HfLaO x 、HfZrLaO x HfZrAlO x ZrAlO x ZrLaO x At least one of them.

[0010] In some embodiments, the memory cell further includes at least one second transistor, the second transistor including a second gate, a third electrode, a fourth electrode, and a second channel; the second transistor is spaced apart from the first transistor; a passivation layer covers the second transistor and the second channel; the memory cell is configured as a multi-transistor single-capacitor memory cell or a capacitorless multi-transistor memory cell.

[0011] In some embodiments, the third electrode and the fourth electrode are disposed in the same layer as the first electrode and the second electrode; the second gate is disposed in the same layer as the first gate; and the second channel portion is disposed in the same layer as the first channel portion.

[0012] In some embodiments, the memory cell further includes a connection portion disposed on the same layer as the first electrode and the second electrode. The first transistor further includes a gate dielectric layer located between the first channel portion and the first gate, the gate dielectric layer having a second opening located on one side of the first channel portion along a first direction and exposing the first gate; one end of the connection portion is electrically connected to the fourth electrode, and the other end is located at least within the second opening and electrically connected to the first gate.

[0013] In a second aspect, an optical memory is provided, comprising peripheral circuitry and at least one storage unit provided in any of the embodiments of the first aspect. The peripheral circuitry is electrically connected to the storage unit.

[0014] The technical effects of optical memory in the second aspect can be seen in the technical effects of the design of the storage unit in the first aspect, and will not be repeated here.

[0015] Thirdly, a method for fabricating an optical memory is provided, comprising: forming a first gate on a substrate, forming a first channel on the side of the first gate away from the substrate, forming a first electrode and a second electrode on the side of the first channel away from the substrate, forming a passivation layer on the side of the first electrode and the second electrode away from the substrate, and forming a first opening in the passivation layer.

[0016] The first gate extends along a first direction, which is parallel to the substrate. A first channel extends along a second direction, which is parallel to the substrate and intersects the first direction. The material of the first channel includes amorphous oxide. The orthographic projection of the first channel onto the substrate at least partially overlaps with the orthographic projection of the first gate onto the substrate. A first electrode and a second electrode extend along the first direction and are spaced apart along the second direction. The orthographic projection of the portion between the first and second electrodes onto the substrate overlaps with the orthographic projection of the first channel onto the substrate and also overlaps with the orthographic projection of the first gate onto the substrate. A first opening exposes at least a portion of the first channel.

[0017] In some embodiments, forming a first channel portion on the side of the first gate away from the substrate includes: forming a channel material layer on the side of the first gate away from the substrate; forming a mask layer on the side of the channel material layer away from the substrate; removing the portion of the channel material layer not covered by the mask layer to form the first channel portion; and removing the remaining mask layer. The mask layer covers the region where the first channel portion is located.

[0018] Fourthly, a method for storing optical signals is provided, which utilizes the optical memory provided in the embodiments of the second aspect for storage, including optical writing to the optical memory, holding the optical writing, electrical reading, and electrical reset.

[0019] The process involves illuminating the first transistor, causing a change in the electrical state of the memory cell. After the illumination is removed, the memory cell maintains its electrical state to preserve the stored information. A read voltage is applied to the memory cell to read its electrical state. A reset voltage is applied to the memory cell to restore its electrical state to its initial state. Attached Figure Description

[0020] To more clearly illustrate the technical solutions in this application, the accompanying drawings used in some embodiments of this application will be briefly described below. Obviously, the drawings described below are only drawings of some embodiments of this application, and those skilled in the art can obtain other drawings based on these drawings. In addition, the drawings described below can be regarded as schematic diagrams and are not actual dimensions of the products or actual processes of the methods involved in the embodiments of this application.

[0021] Figure 1 A schematic diagram of a storage unit provided in an embodiment of this application; Figure 2 A top view of a storage unit provided in an embodiment of this application; Figure 3 A schematic diagram of an optical memory provided in an embodiment of this application; Figure 4 A flowchart illustrating a method for fabricating an optical memory provided in an embodiment of this application; Figures 5-13 A schematic diagram corresponding to each fabrication step of the optical memory provided in the embodiments of this application; Figure 14 This is a flowchart illustrating a method for storing optical signals provided in an embodiment of this application. Detailed Implementation

[0022] The technical solutions in some embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments provided in this application are within the scope of protection of this application.

[0023] In the description of this application, it should be understood that the terms "center", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application.

[0024] Unless the context otherwise requires, throughout the specification and claims, the term "comprising" is interpreted as open-ended and encompassing, meaning "including, but not limited to." In the description of the specification, terms such as "one embodiment," "some embodiments," "exemplary embodiment," "exemplary," or "some examples," etc., are intended to indicate that a particular feature, structure, material, or characteristic associated with that embodiment or example is included in at least one embodiment or example of this application. The illustrative representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the aforementioned particular features, structures, materials, or characteristics may be included in any suitable manner in any one or more embodiments or examples.

[0025] The terms "first," "second," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the embodiments of this application, unless otherwise stated, "multiple" means two or more.

[0026] Connection or link: can refer to a mechanical or physical connection relationship, that is, A and B are connected or linked. It can mean that there are fastened components (such as screws, bolts, rivets, etc.) between A and B, or that A and B are in contact with each other and are difficult to separate. A and B can be fixed, detachable, or integrated; they can be directly connected or indirectly connected through an intermediate medium.

[0027] As used herein, “parallel,” “perpendicular,” and “equal” include the described situation and situations that are similar to the described situation, within an acceptable deviation range, which is determined by those skilled in the art taking into account the measurement under discussion and the errors associated with the measurement of a particular quantity (i.e., the limitations of the measurement system). For example, “parallel” includes absolute parallelism and approximate parallelism, where an acceptable deviation range for approximate parallelism may be, for example, within 5°; “perpendicular” includes absolute perpendicularity and approximate perpendicularity, where an acceptable deviation range for approximate perpendicularity may also be, for example, within 5°; “equal” includes absolute equality and approximate equality, where an acceptable deviation range for approximate equality may be, for example, a difference between the two equals being less than or equal to 5% of either one.

[0028] This document describes exemplary embodiments with reference to sectional views and / or plan views, which are idealized exemplary drawings. In the drawings, the thickness of layers and regions is enlarged for clarity. Therefore, variations in shape relative to the drawings are contemplated due to, for example, manufacturing techniques and / or tolerances. Therefore, exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but rather include shape deviations due to, for example, manufacturing processes. Thus, the regions shown in the drawings are schematic in nature, and their shapes are not intended to show the actual shapes of the regions of the device, nor are they intended to limit the scope of the exemplary embodiments.

[0029] Furthermore, the scenarios described in the embodiments of this application are for the purpose of more clearly illustrating the technical solutions of the embodiments of this application, and do not constitute a limitation on the technical solutions provided in the embodiments of this application. As those skilled in the art will know, with the emergence of new scenarios, the technical solutions provided in the embodiments of this application are also applicable to similar technical problems.

[0030] Figure 1 This is a schematic diagram of a storage unit 100 provided in an embodiment of this application; Figure 2 This is a top view of the storage unit 100 provided in an embodiment of this application.

[0031] Figure 3 This is a schematic diagram of an optical memory 1000 provided in an embodiment of this application.

[0032] Figure 4 This is a flowchart of a method for fabricating an optical memory 1000 provided in an embodiment of this application.

[0033] Figures 5-13 This is a schematic diagram corresponding to each fabrication step of the optical memory 1000 provided in the embodiments of this application.

[0034] in, Figure 5 (a) ~ Figure 13 (a) are cross-sectional views corresponding to each preparation step. Figure 5 (b) ~ Figure 13 (b) are all top views corresponding to each preparation step.

[0035] This application provides a storage unit 100.

[0036] In some embodiments, see Figure 1 The storage cell 100 includes at least one first transistor 10.

[0037] For example, the storage unit 100 may include various storage structure types, such as 1T1C type, 2T0C type, 2T1C type, 3T1C type, etc. This application embodiment takes a 2T0C DRAM structure as an example. Figure 1 As shown, the memory cell 100 includes two transistors, wherein the first transistor 10 is a transistor with a first opening P1 on the right side.

[0038] Among them, see Figure 1 The first transistor 10 includes: a substrate 1, a first gate 21, a first channel 41, a first electrode 51, a second electrode 52, and a passivation layer 6.

[0039] For example, substrate 1 may include a base 11 and a silicon oxide layer 12. The base 11 may be one of glass, silicon wafer, SiC, diamond, or PI flexible substrate 1. Specific steps are as follows: For example, see Figure 5 The standard cleaning steps for preparing clean substrate 1 are as follows: Taking Si / SiO2 substrate 1 with good electrical insulation as an example, the standard RCA-1 cleaning method is adopted. A cleaning solution is prepared according to a volume ratio of deionized water: ammonia: hydrogen peroxide = 1:1:1. The substrate is immersed at 70°C for ten minutes, then ultrasonically cleaned in deionized water for ten minutes, and finally dried with high-purity nitrogen. The above cleaning steps effectively remove surface particles and organic contaminants, providing a clean substrate 1 for subsequent thin film deposition, thereby improving film uniformity and adhesion.

[0040] For example, the first electrode 51 and the second electrode 52 can be either the source or the drain, and can be the two electrodes located on both sides of the first channel portion 41 in the first transistor 10, i.e., the source or the drain, which can be distinguished according to the carrier type and voltage bias. It is understood that the source and drain are often interchangeable in structure, and this application does not make a specific distinction between the two; they can be used interchangeably. The same applies to the third electrode 53 and the fourth electrode 54 mentioned later.

[0041] See Figure 1 and Figure 6 (b) A first gate 21 is disposed on the substrate 1 and extends along a first direction X, which is parallel to the substrate 1.

[0042] See Figure 9 The first channel portion 41 is disposed on the side of the first gate 21 away from the substrate 1 and extends along the second direction Y; the second direction Y is parallel to the substrate 1 and intersects the first direction X; the material of the first channel portion 41 includes amorphous oxide. The orthographic projection of the first channel portion 41 on the substrate 1 at least partially overlaps with the orthographic projection of the first gate 21 on the substrate 1.

[0043] For example, in the first transistor 10, the first gate 21 serves as a voltage control terminal, and the conductivity of the first channel portion 41 is adjusted by applying an electric field. The orthographic projection of the first channel portion 41 on the substrate 1 at least partially overlaps with the orthographic projection of the first gate 21 on the substrate 1, ensuring that the electric field of the first gate 21 can effectively act on the channel region. When the voltage of the first gate 21 exceeds a threshold, a conductive channel is formed between it and the first channel portion 41, thereby controlling the current flow between the source and drain electrodes (i.e., the first electrode 51 and the second electrode 52); the cross arrangement of the first gate 21 and the first channel portion 41 (the first direction X intersects with the second direction Y) enables effective regulation of the carriers in the first channel portion 41.

[0044] Specifically, the first transistor 10 is an amorphous oxide semiconductor first transistor 10.

[0045] For example, amorphous oxides possess characteristics such as wide bandgap, low leakage current, and the ability to be fabricated uniformly over large areas at low temperatures, making them widely applicable in thin-film transistors and various devices. Compared to traditional silicon-based materials, the first channel portion 41 of the amorphous oxide semiconductor exhibits significant photoresponse characteristics to visible and ultraviolet light. Illumination can induce the generation of additional charge carriers in the first channel portion 41, or trigger charge trapping and release related to oxygen vacancies and interface defects, thereby altering the threshold, conductance, or subthreshold behavior of the first transistor 10.

[0046] The aforementioned photoresponse effect enables stable modulation of the electrical state of the amorphous oxide semiconductor first transistor 10 at the device level. After power is turned off or the light is removed, its state change can still be maintained for a period of time, thus providing a physical basis for mapping optical signals to storage states and providing a foundation for storage devices based on optical signal modulation.

[0047] In addition, the amorphous oxide semiconductor material that can be prepared at low temperatures makes the memory cell 100 suitable for back-end processes or monolithic three-dimensional integrated architecture, which facilitates the realization of optical storage arrays on high-density chips and improves the overall integration and functional scalability of the storage system.

[0048] See Figure 1 and Figure 11 The first electrode 51 and the second electrode 52 are disposed on the side of the first channel portion 41 away from the substrate 1; the first electrode 51 and the second electrode 52 extend along the first direction X and are spaced apart along the second direction Y; the orthographic projection of the portion between the first electrode 51 and the second electrode 52 on the substrate 1 overlaps with the orthographic projection of the first channel portion 41 on the substrate 1, and also overlaps with the orthographic projection of the first gate 21 on the substrate 1.

[0049] Specifically, the orthogonal projections of the first electrode 51 and the second electrode 52 on the substrate 1 overlap with the orthogonal projections of the first channel portion 41 and the first gate 21, which can ensure that the source and drain electrodes can effectively contact the channel region, while enabling the electric field of the first gate 21 to synchronously regulate the band alignment of the first channel portion 41 and the electrode contact region.

[0050] For example, the first electrode 51 and the second electrode 52 serve as source and drain contact electrodes, and can apply voltage to both ends of the first channel portion 41 to drive current. When the first gate 21 modulates the conductivity of the first channel portion 41 through the electric field, the first electrode 51 and the second electrode 52 can collect and output the modulated electrical signal, thereby ensuring that the photoelectric electrical state changes on the subsequent storage node A can be accurately read.

[0051] See Figure 1 The passivation layer 6 has a first opening P1, which exposes at least a portion of the first channel portion 41.

[0052] For example, see Figure 1 The first transistor 10 also includes a gate dielectric layer 3 located between the first channel portion 41 and the first gate 21. The storage node A corresponds to the area of ​​the gate dielectric layer 3 directly below the first channel portion 41 exposed by the first opening P1. The storage node A is configured to store the electrical state changes of the first transistor 10 after being illuminated by capturing or releasing charges.

[0053] It is worth noting that the orthographic projections of the aforementioned first electrode 51 and second electrode 52 onto the substrate 1 only partially overlap with the orthographic projection of the first channel portion 41 onto the substrate 1. This avoids completely covering the entire first channel portion 41 below, thus reserving a portion of the first channel portion 41 that is not obscured by the first electrode 51 and second electrode 52, allowing it to be directly exposed for easy reception of optical signals during subsequent operation. The partially exposed first channel portion 41 region is further defined by the first opening P1 on the passivation layer 6, and the gate dielectric layer 3 directly below this region is the memory node A.

[0054] Since the material of the first channel portion 41 is an amorphous oxide with photoresponsive characteristics, under illumination, photogenerated carriers are generated in the amorphous oxide semiconductor or charge trapping and release behaviors related to oxygen vacancies and interface defects are triggered, thereby causing changes in the threshold voltage, conductivity characteristics, or charge distribution of the storage node A of the first transistor 10. These changes in electrical state caused by photoresponsiveness are used as the physical carrier for storing information, that is, the storage node A can be used to store information, thereby realizing the direct modulation of the state of the storage cell 100 by the optical signal.

[0055] In different implementations, the information may be represented as the charge state of the storage capacitor, or as the storage state characterized by electrical parameters such as the threshold voltage and conductance state of the first transistor 10.

[0056] By applying a predetermined bias condition and adjusting the light intensity, light duration, or light wavelength, the electrical state of the storage cell 100 can be controllably changed and maintained for at least a predetermined time after the light exposure ends, thereby realizing the mapping of optical information to the storage state.

[0057] In the storage cell 100 provided in this embodiment, amorphous oxide is used as the material of the first channel portion 41 of the first transistor 10, enabling the first channel portion 41 to directly receive optical signal irradiation. Utilizing the photoresponse characteristics of amorphous oxide, the optical signal can be directly mapped to the electrical state of the storage cell 100 without the need for additional photoelectric conversion circuitry, achieving the writing and retention of optical information, thereby simplifying the optical storage structure and reducing power consumption and latency. Thus, the storage cell 100 achieves direct modulation, stable retention, and readability of optical signals, providing a feasible solution for optical storage.

[0058] For example, in the above embodiments, the first transistor 10 can be used alone or in combination to realize optical storage, or it can be combined with other transistors (e.g., the second transistor 20 mentioned later) to form a read-write separated storage unit 100, or it can be used in conjunction with a capacitor. It can be flexibly selected according to needs to adapt to different application scenarios.

[0059] In some embodiments, the material of the first channel portion 41 includes an amorphous oxide of at least one element selected from In, Ga, Zn, Sn, and W. The material composition of the first channel portion 41 can be controlled by adjusting the proportions of elements such as In, Ga, Zn, Sn, and W, thereby controlling the carrier concentration and achieving high mobility and forward V-axis displacement. th balance.

[0060] For example, amorphous oxides can include IGZO, IAZO, ITZO, CAAC-IGZO, IZO, ZnO, ITO, etc.

[0061] In some embodiments, see Figure 1 and Figure 2 The first transistor 10 further includes a gate dielectric layer 3 located between the first channel portion 41 and the first gate 21, and the material of the gate dielectric layer 3 includes SiO2 and SiN. x HfO2, HfZrO x HfAlO x HfSiO x HfLaO x 、HfZrLaO x HfZrAlO xZrAlO x ZrLaO x At least one of them.

[0062] That is, the gate dielectric layer 3 is made of a high-k material (such as HfO2, HfZrO). x (etc.), which can enhance the control capability of the first gate 21 over the first channel 41 while reducing leakage current and improving the switching characteristics of the device; at the same time, various doped oxide materials provide options for controlling defect state density and oxygen vacancy concentration, which is conducive to optimizing the capture and release behavior of photogenerated carriers and enhancing the optical storage effect.

[0063] In some embodiments, see Figure 1 The memory cell 100 further includes at least one second transistor 20, which includes a second gate 22, a third electrode 53, a fourth electrode 54, and a second channel portion 42; the second transistor 20 is disposed at a distance from the first transistor 10; the passivation layer 6 covers the second transistor 20 and the second channel portion 42; the memory cell 100 is configured as a multi-transistor single-capacitor memory cell or a capacitorless multi-transistor memory cell.

[0064] That is, the storage cell 100 provided in this embodiment is applicable to various optical storage implementations with different storage cell 100 structures, and is not limited to any specific form. For example, the storage cell 100 can be applied to various types, including but not limited to multi-transistor single-capacitor structures with capacitors (such as 2T1C, 3T1C) and multi-transistor structures without capacitors (such as 2T0C). This provides flexible selection for different application scenarios and facilitates compatibility with existing semiconductor manufacturing processes and array integration.

[0065] For example, the memory cell 100 can also be applied to a conventional 1T1C DRAM cell structure. Specifically, the first channel portion 41 of the first transistor 10 is made of amorphous oxide material, which can generate electrical state changes under illumination. Due to the low leakage current characteristics of this material, the state change can be maintained for a long time, thus achieving data storage functionality equivalent to a capacitor. At the same time, the second transistor 20 is equivalent to the access transistor (i.e., 1T) in a conventional 1T1C cell. It is covered by the passivation layer 6 and is unaffected by illumination. It is used to control access to memory node A (i.e., the storage state of the first transistor 10) during read operations, realizing electrical data reading.

[0066] For example, the storage cell 100 may also include a separate capacitor, in which the first transistor 10 may work in conjunction with the capacitor. For instance, the capacitor may be used to enhance the amount of stored charge or stabilize the potential of storage node A, while the first transistor 10 provides optical writing functionality; alternatively, the capacitor may serve as a primary storage element or an auxiliary storage element. This combination increases the flexibility of the storage cell 100, allowing for flexible selection of whether to configure a separate capacitor and how it works in conjunction with the first transistor 10, depending on the specific application requirements.

[0067] In some embodiments, see Figure 1 and Figure 2 The third electrode 53 and the fourth electrode 54 are disposed in the same layer as the first electrode 51 and the second electrode 52; the second gate 22 is disposed in the same layer as the first gate 21; and the second channel portion 42 is disposed in the same layer as the first channel portion 41.

[0068] In other words, the aforementioned co-layer layout allows two transistors (i.e., the first transistor 10 and the second transistor 20) to be formed simultaneously in the same process, without the need for additional process steps, simplifying the fabrication process and reducing production costs. Simultaneously, the co-layer arrangement ensures the uniformity of the channel materials and the consistency of critical dimensions between the two transistors, which helps improve device matching and makes the electrical state read of memory node A more accurate. Furthermore, the co-layer structure shortens the interconnection distance between transistors, reducing parasitic capacitance and contributing to improved read speed and storage density.

[0069] In some embodiments, see Figure 11 The storage unit 100 also includes a connection portion 55, which is disposed on the same layer as the first electrode 51 and the second electrode 52. (See reference...) Figure 10 The first transistor 10 further includes a gate dielectric layer 3 located between the first channel portion 41 and the first gate 21; the gate dielectric layer 3 has a second opening P2, which is located on one side of the first channel portion 41 along the first direction X, and exposes the first gate 21. (See reference...) Figure 11 One end of the connecting part 55 is electrically connected to the fourth electrode 54, and the other end is located at least in the second opening P2 and electrically connected to the first gate 21.

[0070] That is, the connection portion 55 achieves direct electrical connection between the fourth electrode 54 (the source or drain of the second transistor 20) and the first gate 21 below (the first transistor 10) through the second opening P2, forming an ohmic contact, and the connection portion 55 is disposed on the same layer as the first electrode 51 (as well as the second electrode 52, the third electrode 53 and the fourth electrode 54). This structure simplifies the signal path, shortens the interconnection distance, and reduces parasitic capacitance.

[0071] In practical operation, external signals can be applied to both the first gate 21 and the fourth electrode 54 simultaneously. The first gate 21 modulates the conductivity of the first channel portion 41 through an electric field, while the fourth electrode 54 participates in the collection or injection of charge carriers. This structure simplifies the signal path, enabling the electrical state changes mapped by light onto the storage cell 100 to be read and maintained more stably, thus providing a basis for the direct modulation of optical signals.

[0072] This application also provides an optical storage device 1000, see reference. Figure 3 The optical memory 1000 includes at least one storage unit 100 and peripheral circuitry 200 as described in the above embodiments.

[0073] The peripheral circuit 200 can be electrically connected to the storage unit 100, and can perform functions such as selecting the first transistor 10 in the storage unit 100 and controlling the operation timing, thereby ensuring the accuracy and orderliness of data reading and storage.

[0074] For example, the multiple storage cells 100 in the optical memory 1000 can be arranged in rows and columns to form a storage array, and can be interconnected with word lines, bit lines and peripheral control circuits to support selective or parallel optical writing operations, providing a foundation for large-scale optical storage systems and chip-level applications.

[0075] Furthermore, by optimizing the structure of the storage unit 100 and the optical writing bias conditions, the optically modulated storage state can remain stable after the illumination ends, while supporting multiple cycles of writing and reading, thus improving the reliability and repeatability of the optical memory 1000.

[0076] In specific application scenarios, the optical memory 1000 provides a feasible solution for high-density storage based on optical signals, and can be widely used in scenarios such as image sensing, environmental monitoring, and edge computing, providing a technical foundation for realizing high-speed, high-bandwidth optical information storage and on-chip optical processing.

[0077] It is understood that the characteristics and effects of each component in the storage unit 100 can be referred to the description of each component of the storage unit 100 and the corresponding effects in any of the foregoing embodiments, and will not be repeated here.

[0078] This application also provides a method for fabricating an optical memory, see reference. Figure 4 The preparation method includes steps S1 to S5: S1: See Figure 6 A first gate 21 is formed on substrate 1.

[0079] The first gate 21 extends along the first direction X; the first direction X is parallel to the substrate 1.

[0080] For example, this step involves depositing a first gate 21, defining the pattern of the first gate 21 using photolithography or electron beam lithography, and then forming the desired first gate 21 by stripping or etching, thereby forming a first gate 21 control electrode on the substrate 1 to provide switching control function for the first transistor 10.

[0081] For example, step S1 can be further refined as follows: 1. Spin-coat an electron beam photoresist PMMA 950K A4 (polymethyl methacrylate, molecular weight 950K) onto a cleaned substrate 1. The spin-coating parameters are set to 3000 rpm and 60 seconds. After spin-coating, bake at 170°C for 180 seconds.

[0082] 2. The region containing the first gate 21 was defined using a Raith 150 electron beam lithography system, with a dose of 400 μC / cm². 2 The electron beam irradiates the photolithographic area, causing the electron beam resist to denature and become easier to remove with the developer.

[0083] 3. Develop the sample using a developer solution of methyl isobutyl ketone (MIBK) and isopropanol (IPA) in a ratio of 1:3 for 60 seconds, fix it with IPA for 60 seconds, and then dry the sample with high-purity nitrogen. The photoresist that has been altered after photolithography will be dissolved, leaving the defined first gate 21 pattern on the sample.

[0084] 4. A metal electrode (i.e., the first gate 21) is deposited by electron beam evaporation, with an electrode thickness of 10 nm to 50 nm.

[0085] Alternatively, for example, magnetron sputtering can be used to deposit metallic materials such as Ti, Ni, Au, Pt, Pd, TiN, and W.

[0086] 5. Immerse in 90℃ stripper solution for 120 minutes. The metal on the non-exposed area is removed from the sample surface. Rinse the sample surface multiple times with a pipette and rinse in acetone and IPA in sequence. Then dry with a high-purity nitrogen gun. This completes the preparation of the first gate 21.

[0087] S2: See Figures 8-9 A first channel portion 41 is formed on the side of the first gate 21 away from the substrate 1.

[0088] The first channel portion 41 extends along the second direction Y; the second direction Y is parallel to the substrate 1 and intersects the first direction X; the material of the first channel portion 41 includes amorphous oxide; the orthographic projection of the first channel portion 41 on the substrate 1 at least partially overlaps with the orthographic projection of the first gate 21 on the substrate 1.

[0089] S3: See also Figure 11 A first electrode 51 and a second electrode 52 are formed on the side of the first channel portion 41 away from the substrate 1.

[0090] The first electrode 51 and the second electrode 52 extend along the first direction X and are spaced apart along the second direction Y. The orthogonal projection of the portion between the first electrode 51 and the second electrode 52 on the substrate 1 overlaps with the orthogonal projection of the first channel portion 41 on the substrate 1 and also overlaps with the orthogonal projection of the first gate 21 on the substrate 1.

[0091] For example, as described above, a third electrode 53, a fourth electrode 54, and a connection portion 55 are also disposed in the same layer as the first electrode 51 and the second electrode 52. In step S3, based on the completion of the second opening P2, conductive material is deposited to form the connection portion 55, ensuring that one end of it is electrically connected to the fourth electrode 54, and the other end forms a good ohmic contact with the first gate 21 through the second opening P2.

[0092] For example, step S3 can be further refined as follows: 1. Based on the subsequent step S202, spin-coat a polymethyl methacrylate (PMMA 950K A4) electron beam photoresist with a molecular weight of 950K. The spin-coating parameters are set to a rotation speed of 4000 rpm and a time of 60 seconds. After spin-coating, bake at 170°C for 180 seconds.

[0093] 2. The interconnects (i.e., the connection portion 55) and the contact metal area (i.e., the area where the first electrode 51, the second electrode 52, the third electrode 53 and the fourth electrode 54 are located) are defined using the Raith 150 electron beam exposure system. The photolithographic area is irradiated with an electron beam at a dose of 450 μC / cm2, which denatures the electron beam resist and makes it easier to be removed by the developer. 3. Development: Develop with a developer of methyl isobutyl ketone (MIBK): isopropanol (IPA) = 1:3 for 60 seconds, fix with IPA for 60 seconds, and then dry the sample with high-purity nitrogen. The photoresist that has been denatured after photolithography will be dissolved, leaving the defined contact metal areas and interconnect patterns on the sample.

[0094] 4. Electron beam evaporation: Deposit metal electrodes using electron beam evaporation, with an electrode thickness of 10 nm to 50 nm; or, deposit metal electrodes (e.g., metals such as Ti, Ni, Au, Pt, Pd, TiN, W, etc.) using sputtering.

[0095] 5. Stripping: Immerse in 90℃ adhesive remover for 120 minutes. The metal on the non-exposed area is removed from the sample surface. Rinse the sample surface multiple times with a pipette and rinse in acetone and IPA in turn. Then dry with a high-purity nitrogen gun. This completes the preparation of the interconnect (i.e., the connector 55) and the contact metal.

[0096] S4: See also Figure 12A passivation layer 6 is formed on the side of the first electrode 51 and the second electrode 52 away from the substrate 1.

[0097] For example, step S4 is implemented as follows: the sample after growing the first electrode 51 and the second electrode 52 is placed in a plasma generator, and 40 sccm of Ar and 10 sccm of O2 are introduced, the power is set to 30W, and the plasma treatment is performed for 3 minutes; then the sample is placed in PEALD, the plasma power is set to 100W, and a passivation layer 6 is deposited.

[0098] S5: See Figure 13 The first opening P1 is made in the passivation layer 6.

[0099] The first opening P1 exposes at least a portion of the first channel portion 41.

[0100] For example, the specific implementation process of step S5 is as follows: 1. Based on step S4, spin-coat electron beam photoresist AR-P 6200.13. The spin-coating parameters are set to a rotation speed of 4000 rpm and a time of 60 seconds. After spin-coating, bake at 150°C for 180 seconds.

[0101] 2. The position of the first aperture P1 was defined using a Raith 150 electron beam lithography system, with a dose of 140 μC / cm². 2 The electron beam irradiates the photolithographic area, causing the electron beam resist to denature and become easier to remove with the developer.

[0102] 3. Develop with methyl isobutyl ketone for 60 seconds, fix with IPA for 40 seconds, and then dry the sample with high-purity nitrogen. The photoresist that has been denatured after photolithography will be dissolved, and the defined first opening P1 pattern will remain on the sample.

[0103] 4. Dry etching: The exposed area is etched using an inductively coupled plasma system to form openings.

[0104] 5. Remove the mask layer: Use N-methylpyrrolidone remover to heat bath at 120°C for 3 hours to remove AR-P 6200.13 electron beam adhesive, then clean in acetone and IPA for 2 minutes in sequence, and then blow dry with high-purity nitrogen.

[0105] In some embodiments, see Figure 7 After step S1: forming the first gate 21 on the substrate 1, the method further includes: S11: A gate dielectric layer 3 is formed on the side of the first gate 21 away from the substrate 1.

[0106] For example, the specific implementation process of step S11 is as follows: 1. Place the sample with the first gate 21 grown in a plasma generator, introduce 40 sccm of Ar and 10 sccm of O2, set the power to 30W, and treat with plasma for 3 minutes to enhance the hydrophilicity of the substrate 1 surface.

[0107] 2. Place the sample in a PEALD, set the plasma power to 100W, and deposit the gate dielectric layer 3.

[0108] It is worth noting that PEALD, through plasma-activated deposition, can improve the film density, reduce the interface defect density, and enhance the controllability and reliability of Vth, thereby forming a high-quality dielectric layer and achieving leakage current suppression and good first gate control capability.

[0109] For example, see Figure 10 In step S2, after forming the first channel portion 41 on the side of the first gate 21 away from the substrate 1, the method further includes: S21: A second opening P2 is formed on the gate dielectric layer 3.

[0110] The second opening P2 is located on one side of the first channel portion 41 along the first direction X, and the second opening P2 exposes the first gate 21.

[0111] That is, a through hole is formed to expose the bottom first gate 21 metal.

[0112] For example, the specific implementation process of step S21 is as follows: 1. Based on step S2, spin-coat electron beam photoresist AR-P 6200.13. The spin-coating parameters are set to a rotation speed of 3000 rpm and a time of 60 seconds. After spin-coating, bake at 150°C for 180 seconds.

[0113] 2. The first channel section 41 isolation zone was defined using a Raith 150 electron beam lithography system, with a dose of 140 μC / cm². 2 The electron beam irradiates the photolithographic area, causing the electron beam resist to denature and become easier to remove with the developer.

[0114] 3. Develop with methyl isobutyl ketone for 60 seconds, fix with IPA for 40 seconds, and then dry the sample with high-purity nitrogen. The photoresist that has been denatured after photolithography will be dissolved, and the defined first channel 41 isolation pattern will remain on the sample.

[0115] 4. Dry etching: The exposed area is etched using an inductively coupled plasma system to form vias.

[0116] 5. Remove the mask layer: Use N-methylpyrrolidone remover to heat bath at 120°C for 3 hours to remove AR-P 6200.13 electron beam adhesive, then clean in acetone and IPA for 2 minutes in sequence, and then blow dry with high-purity nitrogen.

[0117] In some embodiments, see Figures 8-9 Step S2: Forming a first channel portion 41 on the side of the first gate 21 away from the substrate 1 includes: S201: See also Figure 8 A channel material layer 40 is formed on the side of the first gate 21 away from the substrate 1.

[0118] For example, step S201 is specifically implemented as follows: the plasma power is set to 100W, and the composition ratio of the amorphous oxide is set. An amorphous oxide semiconductor active layer (i.e., the channel material layer 40 in this embodiment) is deposited via PEALD. The material may include IGZO, IAZO, ITZO, CAAC-IGZO, IZO, ZnO, ITO, etc. By adjusting the proportions of elements such as In, Ga, and Zn, the material composition of the channel material layer 40 is controlled, thereby controlling the carrier concentration and achieving a balance between high mobility and forward Vth.

[0119] S202: A mask layer is formed on the side of the channel material layer 40 away from the substrate 1.

[0120] The mask layer covers the area where the first channel section 41 is located.

[0121] S203: See also Figure 9 Remove the channel material layer 40 that is not covered by the mask layer to form the first channel portion 41.

[0122] S204: Remove the remaining mask layer.

[0123] For example, the specific implementation process of steps S202 to S204 is as follows: 1. Based on step S201, spin-coat electron beam photoresist AR-P 6200.17, with spin-coating parameters set to 3000 rpm and 60 seconds, followed by baking at 150°C for 180 seconds.

[0124] 2. The first channel section 41 isolation zone was defined using a Raith 150 electron beam lithography system, with a dose of 150 μC / cm². 2 The electron beam irradiates the photolithographic area, causing the electron beam resist to denature and become easier to remove with the developer.

[0125] 3. Develop with methyl isobutyl ketone for 60 seconds, fix with IPA for 40 seconds, and then dry the sample with high-purity nitrogen. The photoresist that has been denatured after photolithography will be dissolved, and the defined first channel 41 isolation pattern will remain on the sample.

[0126] 4. Wet etching: Dilute concentrated hydrochloric acid at a ratio of 1:100 to prepare a dilute hydrochloric acid solution. Immerse the sample in the dilute hydrochloric acid for 30 seconds, then rinse with deionized water and dry with high-purity nitrogen.

[0127] 5. Remove the mask layer: Use N-methylpyrrolidone remover to heat bath at 120°C for 3 hours to remove AR-P 6200.17 electron beam adhesive, then clean in acetone and IPA for two minutes in sequence, and then blow dry with high-purity nitrogen.

[0128] Figure 14 This is a flowchart illustrating a method for storing optical signals provided in an embodiment of this application.

[0129] This application also provides a method for storing optical signals, see embodiments thereof. Figure 14 The optical memory 1000 provided in the foregoing embodiment is used for storage, and the storage method includes the following steps Y1 to Y4: Y1: Optical writing to optical memory 1000. Illumination is applied to the first transistor 10, causing a change in the electrical state of the memory cell 100.

[0130] Y2: Light-based write operation. After the light source is removed, the storage unit 100 maintains its electrical state to preserve the stored information.

[0131] Y3: Electrical readout. Apply a readout voltage to the storage cell 100 to read the electrical state of the storage cell 100.

[0132] Y4: Electrical reset. A reset voltage is applied to the storage cell 100 to restore its electrical state to its initial state.

[0133] For example, the change in the electrical state of the aforementioned storage cell 100 can manifest as follows: under illumination, photogenerated carriers generated in the amorphous oxide semiconductor can be injected into the gate dielectric layer 3 below it, or trigger charge trapping and release behaviors related to oxygen vacancies and interface defects in the gate dielectric layer 3, thereby causing changes in the threshold voltage, conductivity characteristics, or charge distribution of the storage node A of the first transistor 10. Such changes in electrical state are used as the physical carrier for storing information.

[0134] It is worth noting that in the storage method provided in this embodiment, the optical signal can participate in the storage process as a direct write signal source, rather than just as a trigger or auxiliary signal. By applying illumination under predetermined bias conditions and adjusting the illumination intensity, illumination time, or illumination wavelength, the electrical state of the storage cell 100 is controllably changed and maintained for at least a predetermined time after the illumination ends, thereby realizing the mapping of optical information to the storage state.

[0135] For example, taking a 2T0C DRAM structure as an example, the memory cell 100 of this structure includes two transistors, a first transistor 10 and a second transistor 20, which are respectively a write transistor and a read transistor. The specific storage method can be embodied as follows: 1. Optical writing step: While applying a predetermined write bias to the write transistor (i.e., the first transistor 10), light is applied to the amorphous oxide semiconductor first channel portion 41 of the write transistor (i.e., the first transistor 10). Under the illumination, photogenerated carriers are generated in the first channel portion 41 or charge trapping and release behaviors related to oxygen vacancies and interface defects are triggered, thereby changing the charge state of the storage node A or the threshold voltage state of the write transistor (i.e., the first transistor 10).

[0136] 2. Optical write-and-hold step: After the illumination is stopped, the write bias is maintained or removed, so that the electrical state change caused by the illumination is maintained for at least a predetermined time under no-light conditions, thereby completing the storage of optical information.

[0137] 3. Electrical readout step: Apply a readout voltage to the readout transistor (i.e., the second transistor 20), and determine the storage state corresponding to storage node A by detecting the current or voltage change of the readout transistor (i.e., the second transistor 20), thereby realizing the electrical readout of the optically written information.

[0138] 4. Electrical reset step: When it is necessary to clear the stored information, a reset voltage is applied to the write transistor (i.e., the first transistor 10) to cause the photogenerated carriers formed during the optical writing process to recombine or the trapped charges to be released, thereby restoring the storage node A to its initial state.

[0139] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions conceived by those skilled in the art within the scope of the technology disclosed herein should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A storage unit, characterized in that, include: At least one first transistor; the first transistor includes: Substrate; A first gate; disposed on the substrate and extending along a first direction, the first direction being parallel to the substrate; A first channel portion is disposed on the side of the first gate away from the substrate and extends along a second direction; the second direction is parallel to the substrate and intersects the first direction; the material of the first channel portion includes amorphous oxide; the orthographic projection of the first channel portion on the substrate at least partially overlaps with the orthographic projection of the first gate on the substrate; A first electrode and a second electrode are provided, which extend along the first direction and are spaced apart along the second direction; the orthographic projection of the portion between the first electrode and the second electrode on the substrate overlaps with the orthographic projection of the first channel portion on the substrate and also overlaps with the orthographic projection of the first gate on the substrate. A passivation layer having a first opening that exposes the first channel portion.

2. The storage unit according to claim 1, characterized in that, The material of the first channel includes an amorphous oxide of at least one element selected from In, Ga, Zn, Sn, and W.

3. The storage unit according to claim 1, characterized in that, The first transistor further includes: A gate dielectric layer is located between the first channel and the first gate; the material of the gate dielectric layer includes SiO2 and SiN. x HfO2, HfZrO x HfAlO x HfSiO x HfLaO x 、HfZrLaO x HfZrAlO x ZrAlO x ZrLaO x At least one of them.

4. The storage unit according to claim 1, characterized in that, Also includes At least one second transistor, the second transistor including a second gate, a third electrode, a fourth electrode, and a second channel; the second transistor is disposed at a distance from the first transistor; the passivation layer covers the second transistor and also covers the second channel; The storage unit is configured as a multi-transistor single-capacitor storage unit or a capacitorless multi-transistor storage unit.

5. The storage unit according to claim 4, characterized in that, The third and fourth electrodes are disposed in the same layer as the first and second electrodes; The second gate is disposed in the same layer as the first gate; The second channel section is disposed on the same layer as the first channel section.

6. The storage unit according to claim 4, characterized in that, Also includes: The connecting portion is disposed in the same layer as the first electrode and the second electrode; The first transistor further includes a gate dielectric layer located between the first channel portion and the first gate, the gate dielectric layer having a second opening located on one side of the first channel portion along the first direction, and the second opening exposing the first gate; one end of the connection portion is electrically connected to the fourth electrode, and the other end is located at least in the second opening and electrically connected to the first gate.

7. An optical storage device, characterized in that, include: At least one storage unit as described in any one of claims 1 to 6; The peripheral circuit is electrically connected to the storage unit.

8. A method for fabricating an optical memory, characterized in that, include: A first gate is formed on the substrate; The first gate extends along a first direction; The first direction is parallel to the substrate; A first channel portion is formed on the side of the first gate away from the substrate; the first channel portion extends along a second direction; the second direction is parallel to the substrate and intersects the first direction; the material of the first channel portion includes amorphous oxide; the orthographic projection of the first channel portion on the substrate at least partially overlaps with the orthographic projection of the first gate on the substrate; A first electrode and a second electrode are formed on the side of the first channel portion away from the substrate; the first electrode and the second electrode extend along the first direction and are spaced apart along the second direction; the orthographic projection of the portion between the first electrode and the second electrode on the substrate overlaps with the orthographic projection of the first channel portion on the substrate and also overlaps with the orthographic projection of the first gate on the substrate. A passivation layer is formed on the side of the first and second electrodes away from the substrate; A first opening is formed in the passivation layer; the first opening exposes at least a portion of the first channel portion.

9. The preparation method according to claim 8, characterized in that, The formation of a first channel portion on the side of the first gate away from the substrate includes: A channel material layer is formed on the side of the first gate away from the substrate; A mask layer is formed on the side of the channel material layer away from the substrate; the mask layer covers the area where the first channel portion is located; Remove the channel material layer not covered by the mask layer to form the first channel portion; Remove the remaining mask layer.

10. A method for storing optical signals, using the optical memory described in claim 7 for storage, characterized in that, include: Light is written into the optical memory; Illuminate the first transistor to cause a change in the electrical state of the memory cell; Keep the light written; After the light source is removed, the storage unit maintains the electrical state to preserve the stored information; Electrical readout; A read voltage is applied to the memory cell to read the electrical state of the memory cell; Electrical reset; A reset voltage is applied to the storage cell to restore the electrical state to its initial state.

Images