Three-dimensional stacking structure and method of infrared detector chip

Abstract

This invention relates to the field of infrared detector technology, specifically to a three-dimensional stacked structure and method for an infrared detector chip. The structure includes a readout and signal processing unit chip, a row gating circuit chip, and a detector array. The row gating circuit chip is stacked on top of and electrically connected to the readout and signal processing unit chip. The detector array is stacked on top of and electrically connected to the row gating circuit chip. This invention achieves three-dimensional stacking of the detector array, row gating circuit chip, and readout and signal processing unit chip in the vertical direction. This significantly reduces the planar footprint of the infrared detector chip, thereby reducing the chip package size, and also greatly increases the functional density, shortens the electrical path of some signals, thereby reducing signal transmission delay and lowering the overall power consumption of the chip.

Description

Technical Field

[0001] This invention relates to the field of infrared detector technology, specifically to a three-dimensional stacking structure and method for infrared detector chips. Background Technology

[0002] An infrared detector is an optoelectronic device that generates a temperature field distribution image by sensing the infrared radiation of a target. With its comprehensive advantages of low cost, small size and low power consumption, it has been widely used in security monitoring, industrial inspection and consumer electronics.

[0003] Current infrared detectors are rapidly evolving towards higher resolution, smaller pixel size, and lower power consumption. However, as circuit size and functionality increase, chip area is forced to increase, planar wiring resources are becoming increasingly scarce, and longer signal transmission paths lead to performance degradation. These factors collectively constrain the miniaturization process of devices. Summary of the Invention

[0004] The purpose of this invention is to provide a three-dimensional stacking structure and method for infrared detector chips, which can at least solve some of the defects in the prior art.

[0005] To achieve the above objectives, the technical solution of the present invention is a three-dimensional stacked structure of an infrared detector chip, including a readout and signal processing unit chip, a row gating circuit chip, and a detector array. The row gating circuit chip is stacked on the readout and signal processing unit chip and electrically connected to the readout and signal processing unit chip; the detector array is stacked on the row gating circuit chip and electrically connected to the row gating circuit chip.

[0006] As one implementation, the row selection circuit chip is provided with a vertical interconnect structure for connecting with the readout and signal processing unit chip and with the outside, and the vertical interconnect structure is arranged at intervals around the outer periphery of the detector array.

[0007] As one embodiment, the readout and signal processing unit chip includes a first device layer and a first metal interconnect layer disposed on the first device layer; the row selection circuit chip includes a second device layer and a second metal interconnect layer disposed on the second device layer; the second device layer and the first metal interconnect layer are connected by a first adhesive layer, and the vertical interconnect structure penetrates the second device layer and the second metal interconnect layer, and electrically connects the first metal interconnect layer and the second metal interconnect layer.

[0008] As one implementation method, the detector array is suspended above the row gating circuit chip, and both ends of each detector unit of the detector array are electrically connected to the row gating circuit chip through a cantilever beam.

[0009] As one embodiment, the cantilever beam includes a contact pad disposed on the detector unit, a metal pillar connected to the row selection circuit chip, and a metal layer for connecting the contact pad and the metal pillar.

[0010] The present invention also provides a three-dimensional stacking method for infrared detector chips, comprising the following steps:

[0011] Provides a readout and signal processing unit chip and a row gating circuit chip;

[0012] The row selection circuit chip is stacked on the readout and signal processing unit chip, and the two are electrically connected;

[0013] Fabricate a detector array on a row gating circuit chip.

[0014] As one implementation method, stacking the row selection circuit chip on the readout and signal processing unit chip and electrically connecting the two includes:

[0015] The back side of the row selection circuit chip is fixed to the front side of the readout and signal processing unit chip through the first adhesive layer;

[0016] A vertical interconnect structure is fabricated around the outer periphery of the detector array on the row gating circuit chip to electrically connect the row gating circuit chip to the readout and signal processing unit chip.

[0017] As one implementation method, the fabrication of a detector array on the row selection circuit chip includes:

[0018] Provide a detector chip;

[0019] The front side of the detector chip is fixed to the front side of the row selection circuit chip through the second adhesive layer;

[0020] Etch the detector chip to form a detector array;

[0021] The detector array is electrically connected to the row gating circuit chip.

[0022] As one implementation method, the electrical connection between the detector array and the row selection circuit chip includes:

[0023] A contact pad is deposited on the absorption layer, and a first insulating layer is covered on the surface of the detector array except at the location of the contact pad;

[0024] Holes are made in the first insulating layer and the second adhesive layer;

[0025] Deposit metal to form metal pillars inside the holes and form a metal layer on the surface of the contact pad and the first insulating layer;

[0026] A second insulating layer is deposited on the surface of the metal layer.

[0027] As one implementation method, after electrically connecting the detector array to the row selection circuit chip, the method further includes: etching away the second adhesive layer to suspend the detector array.

[0028] Compared with the prior art, the present invention has the following beneficial effects:

[0029] (1) The present invention overlaps the detector array, row selection circuit chip and readout and signal processing unit chip in three dimensions in the vertical direction, which not only greatly reduces the planar footprint of the infrared detector chip, thereby reducing the chip package size and laying a solid foundation for the miniaturization and micro-miniaturization of the infrared detector, but also greatly improves the functional density, shortens the electrical path of some signals, effectively reduces the parasitic capacitance and resistance generated by interconnection, thereby reducing signal transmission delay and reducing the overall power consumption of the chip.

[0030] (2) In this invention, the readout and signal processing unit chip and the row selection circuit chip can be manufactured in different foundries, which enhances the flexibility and freedom of chip manufacturing. Attached Figure Description

[0031] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0032] Figure 1 This is a three-dimensional schematic diagram of the structure of a traditional uncooled infrared detector chip in the background technology.

[0033] Figure 2 A cross-sectional schematic diagram of the three-dimensional stacked structure of the infrared detector chip provided in an embodiment of the present invention;

[0034] Figure 3 A three-dimensional schematic diagram of the three-dimensional stacked structure of the infrared detector chip provided in an embodiment of the present invention;

[0035] Figure 4 This is a stacked schematic diagram of the row selection circuit chip and the readout and signal processing unit chip provided in an embodiment of the present invention;

[0036] Figure 5 This is a schematic diagram illustrating the fabrication of TSV vias on a row selection circuit chip according to an embodiment of the present invention;

[0037] Figure 6 This is a schematic diagram of the TSV through-hole after filling according to an embodiment of the present invention;

[0038] Figure 7 This is a schematic diagram of the filling of the TSV through-hole provided in an embodiment of the present invention;

[0039] Figure 8 This is a schematic diagram of a detector chip stacked on a row selection circuit chip according to an embodiment of the present invention.

[0040] Figure 9 A schematic diagram showing the absorption layer exposed after etching the back side of the detector chip according to an embodiment of the present invention;

[0041] Figure 10 A cross-sectional schematic diagram of the three-dimensional stacked structure of the infrared detector chip provided in an embodiment of the present invention;

[0042] Figure 11 A schematic diagram of the detector provided in an embodiment of the present invention;

[0043] In the diagram: 1. Readout and signal processing unit chip; 2. Row selection circuit chip; 3. Detector array; 4. TSV conductive pillar; 5. First device layer; 6. First metal interconnect layer; 7. First metal line; 8. First pad; 9. First adhesive layer; 10. Second device layer; 11. Second metal interconnect layer; 12. Second metal line; 13. Second pad; 14. Second adhesive layer; 15. Reflective layer; 16. Absorbing layer; 17. Buffer layer; 18. Silicon substrate; 19. First insulating layer; 20. Contact pad; 21. Metal pillar; 22. Metal layer; 23. Second insulating layer; 24. TSV via; 25. TSV isolation layer; 26. Third pad. Detailed Implementation

[0044] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0045] In the description of this invention, it should be understood that the terms "center", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this invention.

[0046] The terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature; in the description of this invention, unless otherwise stated, "a plurality of" means two or more.

[0047] like Figure 1 As shown, a conventional infrared detector chip includes a ROIC (Readout Integrated Circuit) chip 100, a detector array 200 disposed on the ROIC chip 100, and pads 300 disposed on the ROIC chip 100 for external connection. After the ROIC chip 100 is fabricated, the detector array 200 is stacked on top of the ROIC chip 100. The two ends of the detectors are connected to the metal signal lines inside the ROIC chip 100 through cantilever beams, and each detector needs to be equipped with a detector control switch to control its selection state. The area in the device layer of the ROIC chip 100 below the detector array 200 is occupied by these switches, resulting in ROI... The circuitry of the C chip 100 can only be laid out in the device layer area surrounding the detector array 200. Therefore, the existing ROIC chip 100 generally includes two areas: one is the detector control switch area located directly below the detector array, which contains the detector control switch; the other is the circuit area arranged around the detector control switch area, which mainly integrates row selection logic circuits, pixel readout circuits, capacitor feedback transimpedance amplifiers, analog-to-digital converters, digital signal processing circuits, and timing control circuits. Thus, the ROIC chip 100 and the detector array 200 are actually planar layouts, which not only increases the overall chip area but also extends the transmission path of some signals, resulting in increased power consumption of the corresponding driving circuits.

[0048] To address the above issues, this embodiment provides a three-dimensional stacked structure for an infrared detector chip, including a readout and signal processing unit chip 1, a row gating circuit chip 2, and a detector array 3. The row gating circuit chip layer 2 is stacked on the readout and signal processing unit chip 1 and electrically connected to it; the detector array 3 is stacked on the row gating circuit chip 2 and electrically connected to it.

[0049] In this embodiment, the row gating circuit chip 2 integrates a row gating logic circuit and a detector control switch. The detector control switch is used to control the gating state of the detector unit, and the row gating logic circuit is used to control the gating of the detector array 3 row by row through the detector control switch, and transmit the detected infrared radiation signal to the readout and signal processing unit chip 1 in the form of an electrical signal. The readout and signal processing unit chip 1 integrates other circuits in the ROIC chip besides the row gating logic circuit and detector control switch, including but not limited to the pixel readout circuit, capacitor feedback transimpedance amplifier, sample and hold circuit, analog-to-digital converter, digital signal processing circuit, NUC correction circuit, and timing control circuit. Among them, the pixel readout circuit is used to collect the electrical signal transmitted by the row gating logic circuit and convert it into a current signal; the capacitor feedback transimpedance amplifier is used to amplify the current signal and convert it into a voltage signal; the sample and hold circuit is used to quickly capture the instantaneous voltage value and stabilize the voltage; the analog-to-digital converter is used to convert the analog voltage signal into a digital signal; the NUC correction circuit is used to perform non-uniformity correction on the digital signal; the digital signal processing circuit is used to further optimize the digital image; and the timing control circuit is used to control the sequence and timing of the entire system.

[0050] In this embodiment, the detector array 3, the row gating circuit chip 2, and the readout and signal processing unit chip 1 are three-dimensionally overlapped in the vertical direction. This not only significantly reduces the planar footprint of the infrared detector chip, thereby reducing the chip package size and laying a solid foundation for the miniaturization and micro-miniaturization of the infrared detector, but also improves the chip's integration, shortens the electrical path of some signals, and effectively reduces the parasitic capacitance and resistance generated by interconnection, thereby reducing signal transmission delay and overall chip power consumption. In addition, the readout and signal processing unit chip 1 and the row gating circuit chip 2 can be manufactured in different foundries, enhancing the flexibility and freedom of chip manufacturing.

[0051] By separating the detector array 3 and the row gating circuit from the traditional infrared detector chip, and integrating the detector control switch and the row gating circuit into the row gating circuit chip 2, and integrating the other circuits in the ROIC chip except for the row gating logic circuit and the detector control switch into the readout and signal processing unit chip 1, and then three-dimensionally overlapping the detector array 3, the row gating circuit chip 2 and the readout and signal processing unit chip 1 in the vertical direction, the overall package size and power consumption are effectively reduced while ensuring performance through the separation and reconstruction of functional layers, thus opening up a feasible technical path for the development of a new generation of miniaturized infrared detectors.

[0052] like Figure 2 and Figure 3As shown, detector array 3 is located at the top of the three-dimensional stacked structure. It is used to receive infrared radiation from the target and convert the infrared radiation signal within the target range into an analog electrical signal that can be processed by the integrated circuit. Row gating circuit chip 2 is located below detector array 3. It contains row gating logic circuit and detector control switch. It mainly transmits the infrared radiation signal detected by detector array 3 row by row to readout and signal processing unit chip 1 in the form of electrical signal by controlling the detector switch. Readout and signal processing unit chip 1 is located below row gating circuit chip 2. It mainly integrates pixel readout circuit, capacitor feedback transimpedance amplifier, sample and hold circuit, analog-to-digital converter, digital signal processing circuit, NUC correction circuit and timing control circuit, etc. It receives analog electrical signals related to the radiation magnitude from detector array 3, and converts them into digital signals for processing through sampling, amplification and quantization steps.

[0053] In some embodiments, the row gate circuit chip 2 is provided with a vertical interconnect structure for connection with the readout and signal processing unit chip 1 and external connections, and the vertical interconnect structure is arranged at intervals around the outer periphery of the detector array 3. The vertical interconnect structure enables short-distance interconnection between the readout and signal processing unit chip 1 and the row gate circuit chip 2, and directs the signals from the readout and signal processing unit chip 1 to the surface of the row gate circuit chip 2, further reducing long-distance winding and lowering signal delay and parasitic effects.

[0054] Furthermore, the readout and signal processing unit chip 1 includes a first device layer 5 and a first metal interconnect layer 6 disposed on the first device layer 5; the row selection circuit chip 2 includes a second device layer 10 and a second metal interconnect layer 11 disposed on the second device layer 10; the second device layer 10 and the first metal interconnect layer 6 are connected by a first adhesive layer 9, and the vertical interconnect structure passes through the second device layer 10 and the second metal interconnect layer 11, and electrically connects the first metal interconnect layer 6 and the second metal interconnect layer 11. The first metal interconnect layer 6 has a first metal line 7 inside, and a first pad 8 connected to the first metal line 7 on its surface. The first pad 8 connects the signal on the first metal line 7 inside the signal processing unit chip 1 to the surface and serves as a connection point to the row selection circuit chip 2. The second metal interconnect layer 11 has a second metal line 12 inside, and a second pad 13 connected to the second metal line 12 on its surface. The second pad 13 connects the signal on the second metal line 12 inside the row selection circuit chip 2 to the surface and serves as a connection point to the detector unit. The second metal interconnect layer 11 also has a third pad 26 connected to the second metal line 12 on its surface. The third pad 26 connects to the package pins via gold wires and is used for functions such as powering the stacked chips from an external power source, transmitting signals, and outputting test signals.

[0055] Preferably, the vertical interconnect structure is a TSV conductive pillar 4, such as... Figure 3 and Figure 10 As shown, the TSV conductive pillar 4 is located in the row select circuit chip 2, serving as a signal transmission channel between the select circuit chip and the readout and signal processing unit chip 1. Part of the TSV conductive pillar 4 has its two ends connected to the first pad 8 on the front of the readout and signal processing unit chip 1 and the third pad 26 on the front of the row select circuit chip 2 for packaging connection, respectively. The other two ends of the TSV conductive pillar 4 are connected to the first pad 8 on the front of the readout and signal processing unit chip 1 and the second metal line 12 inside the row select circuit chip 2 for signal transmission, respectively. The TSV process achieves a short-distance interconnection between the row select circuit chip 2 and the readout and signal processing unit chip 1, and brings the pads for packaging connection on the surface of the readout and signal processing unit chip 1 to the front of the row select circuit chip 2.

[0056] In some embodiments, the detector array 3 is suspended above the row gating circuit chip 2, and both ends of each detector unit of the detector array 3 are electrically connected to the row gating circuit chip 2 via cantilever beams. The cantilever beams achieve signal transmission and thermal isolation between the detector and the row gating circuit chip 2, reducing the influence of the lower chip on the detection signal and significantly improving detection sensitivity, making it particularly suitable for uncooled infrared detectors.

[0057] Furthermore, the cantilever beam includes a contact pad 20 disposed on the detector unit, a metal pillar 21 connected to the row selection circuit chip 2, and a metal layer 22 for connecting the contact pad 20 and the metal pillar 21. Figure 11 As shown, the detector unit includes a reflective layer 15 and an absorber layer 16 disposed on the reflective layer 15. A contact pad 20 is disposed on the absorber layer 16. The lower end of a metal pillar 21 is connected to a second pad 13 on the surface of the row select circuit chip 2, and the upper end of the metal pillar 21 is connected to one end of a metal layer 22. The other end of the metal layer 22 is connected to the contact pad 20, ensuring electrical connection between the detector unit and the row select circuit chip 2. Furthermore, the surface of the detector array 3, except for the contact pad 20, is covered by a first insulating layer 19, and the surface of the metal layer 22 is covered by a second insulating layer 23.

[0058] This embodiment also provides a three-dimensional stacking method for infrared detector chips, including the following steps:

[0059] Provides a readout and signal processing unit chip 1 and a row gating circuit chip 2;

[0060] The row selection circuit chip 2 is stacked on the readout and signal processing unit chip 1, and the two are electrically connected;

[0061] A detector array 3 is fabricated on the row gating circuit chip 2.

[0062] In this embodiment, the detector array 3 and the row gating circuit are separated from the traditional infrared detector chip, and the detector control switch and the row gating circuit are integrated into the row gating circuit chip 2. The other circuits in the ROIC chip, except for the row gating logic circuit and the detector control switch, are integrated into the readout and signal processing unit chip 1. The row gating circuit chip 2 and the readout and signal processing unit chip 1 are then three-dimensionally overlapped in the vertical direction, and the detector array 3 is fabricated on the row gating circuit chip 2. This not only significantly reduces the planar footprint of the infrared detector chip, thereby reducing the chip package size and laying a solid foundation for the miniaturization and micronization of infrared detectors, but also greatly improves the functional density, shortens the electrical path of some signals, and effectively reduces the parasitic capacitance and resistance generated by interconnection, thereby reducing signal transmission delay and reducing the overall power consumption of the chip. In addition, the readout and signal processing unit chip 1 and the row gating circuit chip 2 can be manufactured in different foundries, enhancing the flexibility and freedom of chip manufacturing.

[0063] In some embodiments, stacking the row selection circuit chip 2 on the readout and signal processing unit chip 1 and electrically connecting the two includes:

[0064] The back side of the row selection circuit chip 2 is fixed to the front side of the readout and signal processing unit chip 1 through the first adhesive layer 9;

[0065] A vertical interconnect structure is fabricated around the outer periphery of the detector array 3 on the row selection circuit chip 2, which electrically connects the row selection circuit chip 2 to the readout and signal processing unit chip 1.

[0066] Specifically, before the back side of the row selection circuit chip 2 is fixed to the front side of the readout and signal processing unit chip 1 via the first adhesive layer 9, the contact interface between the two, i.e., the back side of the row selection circuit chip 2 and the front side of the readout and signal processing unit chip 1, is cleaned to remove particles and residues that may cause defects or poor adhesion. Subsequently, an adhesive with high-temperature stability, good chemical stability, ease of use, and excellent adhesive strength is applied to the back side of the row selection circuit chip 2 and the front side of the readout and signal processing unit chip 1. Then, the back side of the selection circuit chip and the front side of the readout and signal processing unit chip 1 are aligned and bonded together to form the first adhesive layer 9, thereby fixing the row selection circuit chip 2 to the readout and signal processing unit chip 1. Figure 4 As shown. Preferably, the back side of the gating circuit chip and the front side of the readout and signal processing unit chip 1 are precisely aligned according to the design position of the TSV conductive pillars 4. The adhesive used to form the first adhesive layer 9 must remain stable under the high-temperature environment of the subsequent three-dimensional stacking process, ensuring that the relative positions of the two chips remain unchanged, and that no chemical reaction occurs during TSV etching, isolation layer preparation, and filling.

[0067] Furthermore, a vertical interconnect structure is fabricated around the outer periphery of the detector array 3 on the row selection circuit chip 2, electrically connecting the row selection circuit chip 2 to the readout and signal processing unit chip 1, including:

[0068] A second TSV via 24 is prepared on the front side of the row selection circuit chip 2 to expose the first pad 8 on the front side of the readout and signal processing unit chip 1 and the second metal line 12 inside the row selection circuit chip 2.

[0069] A TSV isolation layer 25 is deposited on the sidewall of the second TSV via 24;

[0070] Metal is electroplated in the second TSV through-hole 24 to form a TSV conductive pillar 4, which connects the first pad 8 to the second metal line 12.

[0071] Specifically, the method for fabricating the second TSV via 24 is as follows: Using an etching process, based on the designed position of the TSV conductive pillars 4, etching begins from the front side of the row select circuit chip 2 until the first pad 8 on the front side of the readout and signal processing unit chip 1 is exposed. Simultaneously, the second metal line 12 within the row select circuit chip 2 is exposed within the second TSV via 24. Figure 5 As shown. Optional etching processes include laser etching, deep reactive ion etching, potassium hydroxide wet etching, and photo-assisted electrochemical etching. When making a selection, factors such as cost, etching rate, aperture size, and aspect ratio must be considered to determine the most suitable TSV fabrication process.

[0072] A TSV isolation layer 25 is deposited on the sidewall of the second TSV via 24 to achieve electrical isolation between adjacent second TSV vias 24 and between the second TSV via 24 and the doped silicon substrate 18, such as Figure 7 As shown. Simultaneously, it is essential to ensure that the surfaces of the first pad 8 and the second metal line 12 connected to the second TSV via 24 are not completely covered by the TSV isolation layer 25, to prevent poor contact between the second TSV via 24 and the first pad 8 on the front side of the readout and signal processing unit chip 1, and the second metal line 12 inside the row selection circuit chip 2. An ideal TSV isolation layer 25 should possess the following characteristics: high resistivity, high breakdown voltage, low stress, compatibility with process temperature, not covering the surfaces of the first pad 8 and the second metal line 12, and good coverage and uniformity. Commonly used TSV isolation layer 25 materials include silicon dioxide, silicon nitride, and insulating organic polymers. In practical applications, the selection of the TSV isolation layer 25 material and its deposition method must be comprehensively weighed according to specific requirements.

[0073] In this embodiment, metal is electroplated inside the second TSV via 24 to form a TSV conductive pillar 4, thereby realizing the electrical connection between the second metal line 12 inside the row selection circuit chip 2 and the first pad 8 on the surface of the readout and signal processing unit chip 1, such as... Figure 6 and Figure 7 As shown. When selecting electroplating metal materials, their electrical conductivity and thermal stress characteristics should be given priority consideration. When determining the filling method, factors such as the filling rate, the impact of the filling process on the state and structure of other components in the stacked chip, and the filling depth need to be comprehensively evaluated. Commonly used electroplating metal materials include copper, silver, and tungsten. Annealing treatment is also required after the electroplating process.

[0074] After establishing the signal connection between the readout and signal processing unit chip 1 and the row selection circuit chip 2 via the TSV conductive pillar 4, the pads on the surface of the readout and signal processing unit chip 1 used for package connection are also brought to the front side of the row selection circuit chip 2, facilitating subsequent package interconnection, such as... Figure 2 As shown, the third pad 26 on the front side of the row select circuit chip 2 is used for external connection.

[0075] In some embodiments, fabricating the detector array 3 on the row gating circuit chip 2 includes:

[0076] Provide a detector chip;

[0077] The front side of the detector chip is fixed to the front side of the row selection circuit chip 2 by the second adhesive layer 14;

[0078] Etch the detector chip to form detector array 3;

[0079] Connect detector array 3 to row selection circuit chip 2 electrically.

[0080] In this embodiment, the detector chip includes a silicon substrate 18, a buffer layer 17, an absorption layer 16 and a reflective layer 15 arranged sequentially. For example, the buffer layer 17 is a silicon oxide layer, the absorption layer 16 is a silicon / germanium layer, and a silicon / silicon-germanium quantum well is used as an infrared detector.

[0081] Furthermore, fixing the front side of the detector chip to the front side of the row selection circuit chip 2 via the second adhesive layer 14 includes:

[0082] The front side of the row selection circuit chip 2 is pre-processed to expose the second pad 13;

[0083] The front side of the detector chip and the front side of the row selection circuit chip 2 are cleaned to remove particles and residues that may cause defects or affect adhesion.

[0084] Adhesive is applied to the front side of the detector chip and the front side of the row selection circuit chip 2. The front sides of the detector chip and the row selection circuit chip 2 are aligned and bonded together to form a second adhesive layer 14, thereby fixing the detector chip onto the row selection circuit chip 2. Figure 8 As shown.

[0085] The preprocessing of the front side of the row selection circuit chip 2 to expose the second pad 13 includes:

[0086] Chemical mechanical polishing removes the diffusion shielding layer, adhesion layer, and seed layer material deposited on the front side of the row select circuit chip 2, exposing the second pad 13. This achieves a chip surface with low damage, high flatness, and low roughness while preventing problems such as delamination, cracking, and filler metal protrusions.

[0087] Furthermore, the etched detector chip forms a detector array 3, comprising:

[0088] Remove the silicon substrate 18 and buffer layer 17 on the back of the detector chip to expose the absorber layer 16 of the detector chip, as shown below. Figure 9 As shown;

[0089] Etching the absorber layer 16 and reflective layer 15 of the detector chip to form the detector array 3, such as Figure 10 As shown.

[0090] The removal of the silicon substrate 18 and buffer layer 17 on the back of the detector chip can be achieved by etching rather than chemical mechanical polishing, in order to avoid the significant stress introduced by the polishing process.

[0091] Furthermore, the electrical connection between the detector array 3 and the row selection circuit chip 2 includes:

[0092] A contact pad 20 is deposited on the absorption layer 16, and a first insulating layer 19 is covered on the surface of the detector array 3 except at the location of the contact pad 20;

[0093] An opening is made in the first insulating layer 19 and the second adhesive layer 14 to expose the second pad 13 on the front side of the row selection circuit chip 2.

[0094] Metal is deposited to form metal pillars 21 inside the holes and metal layers 22 are formed on the surfaces of the contact pad 20 and the first insulating layer 19.

[0095] A second insulating layer 23 is deposited on the surface of the metal layer 22.

[0096] The contact pads 20 are made of metal, and are deposited at both ends of each detector. The openings in the first insulating layer 19 and the second adhesive layer 14 are created using an etching process until the second pad 13 on the front side of the row selection circuit chip 2 is exposed. The metal pillars 21 deposited in the holes serve both electrical connection and mechanical support functions, enabling signal transmission between the detector and the lower row selection circuit chip 2 while also providing effective thermal isolation between them. Figure 11 As shown, each detector has openings on both sides and metal pillars 21 deposited thereon; a metal layer 22 is deposited on the surface of the contact pad 20 and the first insulating layer 19 as patterned metal lines to connect the contact pad 20 and the corresponding metal pillars 21; the infrared radiation signal of the absorption layer 16 is transmitted to the second pad 13 through the contact pad 20, the metal layer 22 and the metal pillars 21.

[0097] In some embodiments, after electrically connecting the detector array 3 to the row selection circuit chip 2, the method further includes etching away the second adhesive layer 14 to suspend the detector array 3. By etching away the second adhesive layer 14 between the detector array 3 and the row selection circuit chip 2, the detector array 3 is suspended, achieving thermal isolation and significantly improving detection sensitivity, which is particularly suitable for uncooled infrared detectors.

[0098] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A three-dimensional stacked structure for an infrared detector chip, characterized in that: It includes a readout and signal processing unit chip, a row gating circuit chip, and a detector array. The row gating circuit chip is stacked on the readout and signal processing unit chip and electrically connected to the readout and signal processing unit chip. The detector array is stacked on the row gating circuit chip and electrically connected to the row gating circuit chip.

2. The three-dimensional stacked structure as described in claim 1, characterized in that: The row selection circuit chip is provided with a vertical interconnect structure for connecting with the readout and signal processing unit chip and with the outside, and the vertical interconnect structure is arranged at intervals around the outer periphery of the detector array.

3. The three-dimensional stacked structure as described in claim 2, characterized in that: The readout and signal processing unit chip includes a first device layer and a first metal interconnect layer disposed on the first device layer; the row selection circuit chip includes a second device layer and a second metal interconnect layer disposed on the second device layer; the second device layer and the first metal interconnect layer are connected by a first adhesive layer, and the vertical interconnect structure passes through the second device layer and the second metal interconnect layer, and electrically connects the first metal interconnect layer and the second metal interconnect layer.

4. The three-dimensional stacked structure as described in claim 1, characterized in that: The detector array is suspended above the row gating circuit chip, and both ends of each detector unit in the detector array are electrically connected to the row gating circuit chip through a cantilever beam.

5. The three-dimensional stacked structure as described in claim 4, characterized in that: The cantilever beam includes a contact pad disposed on the detector unit, a metal pillar connected to the row selection circuit chip, and a metal layer for connecting the contact pad and the metal pillar.

6. A three-dimensional stacking method for infrared detector chips, characterized in that, Includes the following steps: Provides a readout and signal processing unit chip and a row gating circuit chip; The row selection circuit chip is stacked on the readout and signal processing unit chip, and the two are electrically connected; Fabricate a detector array on a row gating circuit chip.

7. The three-dimensional stacking method as described in claim 6, characterized in that, The step of stacking the row selection circuit chip on the readout and signal processing unit chip and electrically connecting the two includes: The back side of the row selection circuit chip is fixed to the front side of the readout and signal processing unit chip through the first adhesive layer; A vertical interconnect structure is fabricated around the outer periphery of the detector array on the row gating circuit chip to electrically connect the row gating circuit chip to the readout and signal processing unit chip.

8. The three-dimensional stacking method as described in claim 6, characterized in that, The fabrication of the detector array on the row gating circuit chip includes: Provide a detector chip; The front side of the detector chip is fixed to the front side of the row selection circuit chip through the second adhesive layer; Etch the detector chip to form a detector array; The detector array is electrically connected to the row gating circuit chip.

9. The three-dimensional stacking method as described in claim 8, characterized in that, The step of electrically connecting the detector array to the row selection circuit chip includes: A contact pad is deposited on the absorption layer, and a first insulating layer is covered on the surface of the detector array except at the location of the contact pad; Holes are made in the first insulating layer and the second adhesive layer; Deposit metal to form metal pillars inside the holes and form a metal layer on the surface of the contact pad and the first insulating layer; A second insulating layer is deposited on the surface of the metal layer.

10. The three-dimensional stacking method as described in claim 8, characterized in that, After electrically connecting the detector array to the row selection circuit chip, the method further includes: etching away the second adhesive layer to suspend the detector array.

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