Substrate assembly and method of manufacturing the same, package substrate, package structure, and electronic device

Abstract

The application relates to the packaging technical field and provides a substrate assembly, a preparation method of the substrate assembly, a packaging substrate, a packaging structure and electronic equipment. The preparation method of the substrate assembly comprises the following steps: providing a glass substrate, the glass substrate comprising a first surface and a second surface opposite to each other; preparing a sacrifice layer on the first surface; preparing an annular hole on the second surface, the annular hole penetrating through the glass substrate, the glass substrate forming a glass column located on the inner circumferential side of the annular hole, and the glass column being connected with the sacrifice layer; preparing a first buffer layer in the annular hole; and removing the sacrifice layer and the glass column to form a first through hole. The preparation method provided by the application can form an annular hole on the glass substrate, then prepare an annular first buffer layer in the annular hole, and naturally form a first through hole after the sacrifice layer and the glass column are removed, so that secondary punching is not needed, and the thickness uniformity of the first buffer layer in the circumferential direction of the first through hole is improved, so that the buffering effect of the first buffer layer is improved.

Description

Technical Field

[0001] This application belongs to the field of packaging technology, and more specifically, relates to a substrate assembly and its preparation method, a packaging substrate, a packaging structure, and an electronic device. Background Technology

[0002] With the rapid development of high-performance chips and their packaging technologies, glass substrates are gradually replacing organic substrates due to their superior physical, chemical, and electrical properties.

[0003] Through-Glass Vias (TGVs) are a core component of chip substrates. After TGV vias are formed, conductive structures need to be filled inside. Stress mismatch between the conductive structure and the glass can cause the glass to crack. Therefore, a buffer layer needs to be added between the conductive structure and the glass within the via. Specifically, the TGV via is filled with a buffer layer, then a hole is drilled in the buffer layer, and finally the conductive structure is filled. It is difficult to keep the hole in the buffer layer concentric with the TGV via, resulting in inconsistent thickness of the buffer layer around the TGV via, leading to poor buffering performance. Summary of the Invention

[0004] The purpose of this application is to provide a substrate assembly and its preparation method, a packaged substrate, a packaged structure, and an electronic device to improve the buffering effect of the buffer layer.

[0005] To achieve the above objectives, the technical solution adopted in this application is as follows: In a first aspect, a method for fabricating a substrate assembly is provided, the method comprising: A glass substrate is provided, the glass substrate including opposing first and second surfaces; A sacrificial layer is prepared on the first surface; An annular hole is formed on the second surface, penetrating the glass substrate. A glass pillar is formed on the glass substrate located on the inner periphery of the annular hole, and the glass pillar is connected to the sacrificial layer. A first buffer layer is prepared within the annular hole; Remove the sacrificial layer and glass column to form the first through hole.

[0006] Through the above technical solution, the preparation method provided in this application can form an annular hole on a glass substrate, and then prepare an annular first buffer layer in the annular hole. After removing the sacrificial layer and glass pillars, the first through hole is naturally formed. This eliminates the need for secondary drilling and helps to improve the uniformity of the thickness of the first buffer layer in the circumferential direction of the first through hole, thereby improving the buffering effect of the first buffer layer.

[0007] In some embodiments, after the sacrificial layer is prepared on the first surface and before the first buffer layer is prepared within the annular hole, the preparation method further includes: A vent hole is formed on the side of the sacrificial layer away from the glass substrate. The vent hole penetrates the sacrificial layer and is connected to the annular hole.

[0008] Through the above technical solution, the preparation method provided in this application prepares vent holes on the sacrificial layer and makes the vent holes connected with the annular holes. In this way, when the first buffer layer is prepared in the annular holes, the air in the annular holes can be discharged from the vent holes, which helps to reduce the air pressure in the annular holes. This facilitates the entry of the material for preparing the first buffer layer into the annular holes, thereby making it easier to prepare the first buffer layer.

[0009] Optionally, multiple vent holes are provided, spaced apart circumferentially along the annular hole. This facilitates the timely discharge of gas from the annular hole, allowing the material for the first buffer layer to enter the annular hole uniformly, thereby improving the uniformity of the first buffer layer.

[0010] Optionally, the vent includes a first vent and a second vent with different diameters. The first vent and the second vent are alternately arranged along the circumference of the annular hole, which facilitates the timely discharge of gas from the annular hole.

[0011] Optionally, the orthographic projection of the vent hole on the first surface does not overlap with the orthographic projection of the glass column on the first surface. This helps to increase the connection area between the glass column and the sacrificial layer, thereby increasing the strength of the connection between the glass column and the sacrificial layer, which in turn facilitates the removal of the glass column when the sacrificial layer is removed.

[0012] Optionally, the orthographic projection of the vent hole on the first surface is located within the orthographic projection of the annular hole on the first surface, which facilitates the timely discharge of gas from the annular hole.

[0013] In some embodiments, the second surface includes an annular region, and an annular hole is formed on the second surface, the method of which includes: The glass substrate is modified in the annular region to form an annular modified structure; Remove the modified structure to form an annular hole.

[0014] Through the above technical solution, the preparation method provided in this application can form a weakened modified structure, which is easy to remove and thus facilitates the formation of annular pores.

[0015] Optionally, the glass substrate is modified in the annular region by laser irradiation of the glass substrate in the annular region, which can form a weakened modified structure.

[0016] Optionally, removing the modified structure to form an annular hole includes etching the glass substrate.

[0017] In some embodiments, the annular region includes multiple sub-regions. After modifying the glass substrate in the annular region and before removing the modified structure to form the annular hole, the preparation method includes: The glass substrate is modified again in the sub-region.

[0018] Through the above technical solution, after the modified structure is formed and before it is removed, the preparation method provided in this application can further modify and weaken the modified structure in a sub-region of the annular region, which facilitates the removal of the modified structure.

[0019] Optionally, the sub-regions are circular regions, and multiple sub-regions are spaced apart along the circumference of the annular region, which facilitates the weakening of the modified structure.

[0020] In some embodiments, after preparing the first buffer layer within the annular hole and before removing the sacrificial layer and the glass column, the preparation method provided in this application further includes: A second buffer layer is prepared on the second surface; A second through-hole is prepared on the second buffer layer, and the second through-hole exposes at least the glass column.

[0021] Through the above technical solution, the preparation method provided in this application can prepare a second buffer layer on the second surface, which can reduce the stress when the glass substrate is connected to other components. Furthermore, a second through hole is prepared on the second buffer layer so that the second through hole exposes at least the glass pillar, which can prevent the glass pillar from being connected to the second buffer layer and facilitate the removal of the glass pillar.

[0022] Optionally, the second through-hole exposes at least a portion of the first buffer layer, which facilitates the fabrication of conductive connections within the first through-hole in subsequent processes.

[0023] In some embodiments, the material of the sacrificial layer is different from the material of the glass substrate, and the material of the sacrificial layer includes at least one of organic materials, metallic materials, and inorganic materials.

[0024] In this way, the preparation method provided in this application can avoid removing the sacrificial layer when preparing the annular hole by etching.

[0025] Alternatively, the organic material of the sacrificial layer may include non-photosensitive polyimide.

[0026] Alternatively, the sacrificial layer may be made of chromium or chromium oxide.

[0027] Alternatively, the inorganic material of the sacrificial layer may include silicon nitride or silicon dioxide.

[0028] Secondly, this application provides a substrate assembly, which is manufactured by the preparation method of any of the above embodiments. The substrate assembly provided by this application has the same or similar technical effects as the preparation methods of any of the above embodiments, and will not be described again here.

[0029] Thirdly, this application provides a packaging substrate, which includes a substrate, a conductive connection portion, a first circuit layer and a second circuit layer. The substrate includes at least one substrate assembly as described in the above embodiments. The conductive connection portion is disposed in a first through hole and includes a first connection end and a second connection end along the thickness direction of the glass substrate. The first circuit layer is disposed on one side of the substrate in the thickness direction and is connected to the first connection end of the conductive connection portion. The second circuit layer is disposed on the side of the substrate away from the first circuit layer and is connected to the second connection end of the conductive connection portion.

[0030] The packaging substrate provided in this application has the same or similar technical effects as the substrate assembly of the above embodiments, and will not be described again here.

[0031] Fourthly, this application provides a packaging structure, which includes a packaging substrate and a chip as described in the above embodiments, wherein the chip is packaged on the packaging substrate and is electrically connected to the packaging substrate.

[0032] The packaging structure provided in this application has the same or similar technical effects as the packaging substrate of the above embodiments, and will not be described again here.

[0033] Fifthly, this application provides an electronic device that includes the packaging structure and circuit board of the above embodiments, wherein the circuit board is electrically connected to the packaging structure.

[0034] The electronic device provided in this application has the same or similar technical effects as the packaging structure of the above-described embodiments, and will not be described again here.

[0035] The above description is only an overview of the technical solution of this application. In order to better understand the technical means of this application and to implement it in accordance with the contents of the specification, and to make the above and other objects, features and advantages of this application more obvious and understandable, the following are specific embodiments of this application. Attached Figure Description

[0036] To more clearly illustrate the technical solutions in the embodiments of this application, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0037] Figure 1This is a schematic diagram of the structure of the electronic device provided in the embodiments of this application; Figure 2 This is one of the cross-sectional structural schematic diagrams of the packaging substrate provided in the embodiments of this application; Figure 3 This is a second cross-sectional view of the packaging substrate provided in the embodiments of this application; Figure 4 for Figure 2 One of the magnified views of a section at point A in the middle; Figure 5 for Figure 2 Second magnified view of a portion of point A in the middle; Figure 6 for Figure 2 One of the magnified views of a section at point B in the middle; Figure 7 for Figure 2 Second magnified view of a section at point B; Figure 8 This is one of the structural schematic diagrams of the packaging substrate provided in the embodiments of this application during the fabrication process; Figure 9 for Figure 8 One of the C-direction views; Figure 10 for Figure 8 The second view from direction C; Figure 11 for Figure 10 A magnified view of a portion of point D; Figure 12 This is the second schematic diagram of the structure of the packaging substrate provided in the embodiments of this application during the manufacturing process; Figure 13 for Figure 12 One of the E-direction views; Figure 14 for Figure 12 View 2 in direction E; Figure 15 for Figure 14 A magnified view of a portion of point F in the middle; Figure 16 This is the third schematic diagram of the structure of the packaging substrate provided in the embodiments of this application during the manufacturing process; Figure 17 This is the fourth schematic diagram of the structure of the packaging substrate provided in the embodiments of this application during the manufacturing process; Figure 18 Fifth schematic diagram of the structure of the packaging substrate provided in the embodiments of this application during the manufacturing process; Figure 19 This is the sixth schematic diagram of the structure of the packaging substrate provided in the embodiments of this application during the manufacturing process; Figure 20This is the seventh schematic diagram of the structure of the packaging substrate provided in the embodiments of this application during the manufacturing process; Figure 21 This is the eighth schematic diagram of the structure of the packaging substrate provided in the embodiment of this application during the manufacturing process.

[0038] The following are the labeling elements in the figure: Electronic device 1000; Packaging structure 1100; Packaging substrate 1101; Chip 1102; Circuit board 1200; Substrate assembly 100; glass substrate 10; first surface 1001; second surface 1002; mounting hole 1003; annular region 101; sub-region 1011; annular hole 102; first through hole 103; modified structure 11; sub-structure 111; sacrificial layer 12; glass pillar 13; vent hole 120; first vent hole 121; second vent hole 122; first buffer layer 20; second buffer layer 30; second through hole 301; Conductive connection portion 200; first connection end 201; second connection end 202; first conductive connection sub-port 210; second conductive connection sub-port 220; Seed layer 300; First seed layer 310; Second seed layer 320; Third buffer layer 400; Third through hole 401; First circuit layer 500; first dielectric layer 510; first conductive line 520; first solder mask layer 530; first opening 531; first surface treatment layer 540; first conductive connection bump 550; Second circuit layer 600; second dielectric layer 610; second conductive line 620; second solder resist layer 630; second opening 631; second surface treatment layer 640; second conductive connection bump 650. Detailed Implementation

[0039] To make the technical problems, technical solutions, and beneficial effects to be solved by this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and are not intended to limit the scope of this application.

[0040] It should be noted that when a component is referred to as being "fixed to" or "set on" another component, it can be directly on or indirectly on that other component. When a component is referred to as being "connected to" another component, it can be directly connected to or indirectly connected to that other component.

[0041] It should be understood that the terms "length", "width", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application.

[0042] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0043] This application provides an electronic device 1000, which can be, for example, a mobile phone, tablet computer, personal digital assistant (PDA), television, smart wearable products (e.g., smartwatch, smart bracelet), virtual reality (VR) terminal device, augmented reality (AR) terminal device, rechargeable small household appliances (e.g., soymilk maker, robot vacuum cleaner), drone, radar, aerospace equipment, vehicle-mounted equipment, vehicle, or other different types of user equipment or terminal devices; the electronic device 1000 can also be a network device such as a base station. This application does not impose any special limitations on the specific form of the electronic device 1000.

[0044] Please see Figure 1 The electronic device 1000 includes a circuit board 1200 and a package structure 1100, with the circuit board 1200 and the package structure 1100 being electrically connected.

[0045] For example, the package structure 1100 is disposed on the circuit board 1200.

[0046] For example, the circuit board 1200 may be a printed circuit board (PCB), a flexible printed circuit (FPC), or a rigid-flex circuit board 1200.

[0047] For example, electronic device 1000 may include an integrated circuit disposed on circuit board 1200.

[0048] For example, the package structure 1100 is integrated into the integrated circuit.

[0049] Please continue reading. Figure 1 The packaging structure 1100 includes a packaging substrate 1101 and a chip 1102. The chip 1102 is packaged on the packaging substrate 1101 and is electrically connected to the packaging substrate 1101. The packaging substrate 1101 provides support for the chip 1102. For example, the chip 1102 can be integrated into an integrated circuit.

[0050] For example, the chip 1102 provided in this application embodiment can be a logic chip 1102, which can implement functions such as "AND", "OR", and "NOT". Alternatively, the chip 1102 can be a memory chip 1102, which can realize data storage. This application embodiment does not limit the specific type of chip 1102. For example, the chip 1102 can also be a power integrated circuit (PIC) or other types of integrated circuits, or it can also be a circuit module, etc.

[0051] Exemplary, the packaging structure 1100 provided in this application embodiment may further include DC... Electrical components such as DC / DC converters, voltage regulator modules (VRMs), and integrated voltage regulators (IVRs) can be mounted on and electrically connected to the packaging substrate 1101.

[0052] For example, the chip 1102 provided in this application embodiment can be a surface acoustic wave device (SAW device). A surface acoustic wave device is a type of microelectronic component that utilizes the physical properties of surface acoustic waves (SAW) propagating on the surface of piezoelectric materials to achieve the conversion and processing of "electrical signal-acoustic signal-electrical signal". It is widely used in communication, sensing, radio frequency (RF) circuits and other fields.

[0053] Specifically, surface acoustic wave (SAW) devices include signal processing SAW devices (SAW filters, SAW resonators, SAW delay lines, etc.) and sensing SAW devices (temperature sensors, pressure sensors, gas sensors, etc.).

[0054] Taking filters as an example, filters are generally located at the front end of the RF module and belong to the signal processing chip 1102.

[0055] For example, the chip 1102 provided in this application embodiment can adapt to the high requirements of AI chip 1102 for computing power and bandwidth, thereby shortening the signal transmission path and reducing power consumption.

[0056] For example, the chip 1102 provided in this application embodiment can be integrated into a large-scale antenna array to meet the data rate requirements of over GHz in GHz scenarios.

[0057] With the rapid development of high-performance chips 1102 and their packaging technologies, glass substrates 10 are gradually replacing organic substrates due to their superior physical, chemical, and electrical properties. During the packaging process, glass substrates 10 can withstand higher temperatures better than organic substrates, and their coefficient of thermal expansion is similar to that of silicon, thus reducing stress warping problems caused by thermal mismatch. The electrical insulation and thermal stability of glass substrates 10 provide mechanical support and electrical insulation for microelectromechanical systems (MHS), reducing parasitic capacitance and improving device performance, making them applicable to products such as miniature mass spectrometers and inertial sensors. Furthermore, the high flatness and low roughness of the glass surface allow for denser wiring, and the extremely low dielectric constant and dielectric loss of the glass material can improve signal transmission speed and signal integrity. Simultaneously, the excellent chemical stability of the glass material effectively resists environmental corrosion such as moisture and acids / alkalis.

[0058] Through-Glass Vias (TGVs) are a core component of the 1102 chip substrate. After TGV vias are formed, conductive structures need to be filled inside. Stress mismatch between the conductive structure and the glass can cause glass cracking, necessitating the addition of a buffer layer between the conductive structure and the glass. The specific process involves filling the TGV via with a buffer layer, then drilling holes in the buffer layer, and finally filling with the conductive structure. However, it's difficult to keep the holes in the buffer layer concentric with the TGV vias, resulting in inconsistent buffer layer thickness around the TGV vias and poor buffering performance.

[0059] To address the aforementioned technical problems, embodiments of this application provide a substrate assembly 100 and its preparation method, a packaged substrate 1101, a packaged structure 1100, and an electronic device 1000, to improve the buffering effect of the buffer layer.

[0060] The purpose of this application is to provide a substrate assembly 100 and its preparation method, a packaged substrate 1101, a packaged structure 1100, and an electronic device 1000 to improve the buffering effect of the buffer layer.

[0061] Please refer to the following: Figure 2 and Figure 3 The packaging substrate 1101 provided in this application embodiment includes at least one substrate assembly 100, the substrate assembly 100 includes a glass substrate 10, the glass substrate 10 is provided with a mounting hole 1003, and the mounting hole 1003 penetrates the glass substrate 10.

[0062] It is understandable that the number of substrate components 100 can be 1, 2, 3, etc.

[0063] For example, please refer to Figure 2 The packaging substrate 1101 provided in this application embodiment includes a substrate assembly 100.

[0064] For example, please refer to Figure 3 The packaging substrate 1101 provided in this application embodiment includes two substrate assemblies 100.

[0065] The packaging substrate 1101 provided in this embodiment further includes a conductive connection portion 200, which is disposed within the first through-hole 103. The conductive connection portion 200 includes a first connection end 201 and a second connection end 202 along the thickness direction Z of the laminated structure. The conductive connection portion 200 can be made of a conductive metal such as copper. In this way, the conductive connection portion 200 can be connected to other components through the first connection end 201 and the second connection end 202.

[0066] The packaging substrate 1101 provided in this embodiment further includes a first circuit layer 500. The first circuit layer 500 is disposed on one side of the substrate assembly 100 in the thickness direction Z, and the first circuit layer 500 is connected to the first connection end 201 of the conductive connection portion 200. In this way, the first circuit layer 500 can be connected to the conductive connection portion 200, so that the first circuit layer 500 can transmit electrical signals.

[0067] The packaging substrate 1101 provided in this embodiment further includes a second circuit layer 600. The second circuit layer 600 is disposed on the side of the substrate assembly 100 opposite to the first circuit layer 500, and the second circuit layer 600 is connected to the second connection terminal 202 of the conductive connection portion 200. In this way, the second circuit layer 600 can be connected to the conductive connection portion 200, so that the second circuit layer 600 can transmit electrical signals.

[0068] Please continue reading. Figure 2 and Figure 3 The substrate assembly 100 further includes a first buffer layer 20, which is disposed within the mounting hole 1003. The first buffer layer 20 has a first through hole 103 extending through it, and a conductive connection portion 200 is disposed within the first through hole 103. In this way, the first buffer layer 20 can absorb the stress between the glass substrate 10 and the conductive connection portion 200, thus reducing the stress on the glass substrate 10 and making it less prone to breakage, thereby reducing the manufacturing difficulty.

[0069] Optionally, the material of the first buffer layer 20 includes organic materials. In this way, the first buffer layer 20 has a good buffering effect.

[0070] Optionally, the material of the first buffer layer 20 includes Ajinomoto Build-up Film (ABF).

[0071] Please see Figure 2 , Figure 4 and Figure 5 Optionally, the substrate assembly 100 provided in this application embodiment further includes a second buffer layer 30. The glass substrate 10 includes a first surface 1001 and a second surface 1002 that are opposite each other in the thickness direction Z. The second buffer layer 30 is disposed on the second surface 1002. The second buffer layer 30 is provided with a second through hole 301 that communicates with the first through hole 103. The second circuit layer 600 is disposed on the side of the second buffer layer 30 that is away from the first circuit layer 500. The second connection end 202 of the conductive connection portion 200 passes through the second through hole 301 and is connected to the second circuit layer 600.

[0072] Please see Figure 4 Optionally, the second buffer layer 30 covers the first buffer layer 20.

[0073] Please see Figure 5 Optionally, the second through-hole 301 exposes the first buffer layer 20.

[0074] Optionally, the material of the second buffer layer 30 includes organic materials. In this way, the second buffer layer 30 has a good buffering effect.

[0075] Optionally, the material of the second buffer layer 30 includes Ajinomoto Build-up Film (ABF).

[0076] Please see Figure 2 , Figure 6 and Figure 7 Optionally, the packaging substrate 1101 provided in this application embodiment further includes a third buffer layer 400. The third buffer layer 400 is disposed on the first surface 1001. The third buffer layer 400 is provided with a third through hole 401 communicating with the first through hole 103. The first circuit layer 500 is disposed on the side of the third buffer layer 400 away from the first circuit layer 500. The first connection end 201 of the conductive connection portion 200 passes through the third through hole 401 and is connected to the first circuit layer 500.

[0077] Please see Figure 6 Optionally, the third buffer layer 400 covers the first buffer layer 20.

[0078] Please see Figure 7Optionally, the third through-hole 401 exposes the first buffer layer 20.

[0079] Optionally, the material of the third buffer layer 400 may include organic materials. In this way, the third buffer layer 400 has a good buffering effect.

[0080] Optionally, the material of the third buffer layer 400 includes Ajinomoto Build-up Film (ABF).

[0081] Please continue reading. Figure 2 and Figure 3 The packaging substrate 1101 provided in this application embodiment also includes a seed layer 300, which is disposed on the outer periphery of the conductive connection portion 200, thus facilitating the fabrication of the conductive connection portion 200.

[0082] Optionally, please refer to Figure 3 The conductive connection portion 200 includes a first conductive connection sub-portion 210 and a second conductive connection sub-portion 220. The seed layer 300 includes a first seed layer 310 and a second seed layer 320. The first seed layer 310 is provided on the outer periphery of the first conductive connection sub-portion 210, which facilitates the processing of the first conductive connection sub-portion 210. The second seed layer 320 is provided on the outer periphery of the second conductive connection sub-portion 220, which facilitates the processing of the second conductive connection sub-portion 220.

[0083] Please continue reading. Figure 2 , Figure 6 and Figure 7 Optionally, the first circuit layer 500 includes a first dielectric layer 510 and a first conductive line 520 alternately stacked in sequence. The first conductive line 520 can be connected to the conductive connection portion 200. The first dielectric layer 510 is located between two adjacent first conductive lines 520 and can separate two adjacent first conductive lines 520. The material of the first conductive line 520 can be copper, aluminum, nickel, gold, etc.

[0084] Optionally, the first circuit layer 500 further includes a first solder mask layer 530 covering the outermost first conductive line 520. The first solder mask layer 530 may have a first opening 531, exposing the outermost first conductive line 520. The first opening 531 is filled with a first surface treatment layer 540, and the surface of the first surface treatment layer 540 is provided with first conductive connection bumps 550, which facilitates the connection of the first circuit layer 500 to other components through the first conductive connection bumps 550.

[0085] Please continue reading. Figure 2 , Figure 4 and Figure 5Optionally, the second circuit layer 600 includes a second dielectric layer 610 and a second conductive line 620 alternately stacked in sequence. The second conductive line 620 can be connected to the conductive connection portion 200. The second dielectric layer 610 is located between two adjacent second conductive lines 620 and can separate two adjacent second conductive lines 620. The material of the second conductive line 620 can be copper, aluminum, nickel, gold, etc.

[0086] Optionally, the second circuit layer 600 further includes a second solder mask layer 630 covering the outermost second conductive line 620. The second solder mask layer 630 may have a second opening 631, which exposes the outermost second conductive line 620. The second opening 631 is filled with a second surface treatment layer 640, and the surface of the second surface treatment layer 640 is provided with second conductive connection bumps 650, which facilitates the connection of the second circuit layer 600 to other components through the second conductive connection bumps 650.

[0087] It is understandable that the materials for the first conductive line 520 and the second conductive line 620 can be selected according to specific product requirements.

[0088] The following is based on Figures 8 to 21 The preparation method of the substrate assembly 100 provided in the embodiments of this application will be described.

[0089] The method for fabricating the substrate assembly 100 provided in this application includes: S100, please refer to Figure 8 A glass substrate 10 is provided, the glass substrate 10 including a first surface 1001 and a second surface 1002 opposite to each other; S200, a sacrificial layer 12 is prepared on the first surface 1001; S300, please refer to Figure 12 An annular hole 102 is prepared on the second surface 1002, the annular hole 102 penetrates the glass substrate 10, and a glass pillar 13 is formed on the inner peripheral side of the annular hole 102 on the glass substrate 10, the glass pillar 13 being connected to the sacrificial layer 12. S500, a first buffer layer 20 is prepared within the annular hole 102; S800, remove the sacrificial layer 12 and the glass column 13 to form the first through hole 103.

[0090] Through the above technical solution, the preparation method provided in this application embodiment can form an annular hole 102 on the glass substrate 10, and then prepare an annular first buffer layer 20 in the annular hole 102. After removing the sacrificial layer 12 and the glass pillar 13, the first through hole 103 is naturally formed. This eliminates the need for secondary drilling and helps to improve the uniformity of the thickness of the first buffer layer 20 in the circumferential direction of the first through hole 103, thereby improving the buffering effect of the first buffer layer 20.

[0091] The annular hole 102 can be prepared by processes such as etching.

[0092] In some embodiments, the material of the sacrificial layer 12 is different from the material of the glass substrate 10, and the material of the sacrificial layer 12 includes at least one of organic materials, metallic materials, and inorganic materials.

[0093] In this way, the preparation method provided in this application embodiment can avoid removing the sacrificial layer 12 when preparing the annular hole 102 by etching.

[0094] Alternatively, the organic material of the sacrificial layer 12 may include a non-photosensitive polyimide.

[0095] Optionally, the metallic material of the sacrificial layer 12 may include chromium or chromium oxide.

[0096] Optionally, the inorganic material of the sacrificial layer 12 may include silicon nitride or silicon dioxide.

[0097] Please see Figure 8 , Figure 9 , Figure 10 and Figure 11 In some embodiments, the second surface 1002 includes an annular region 101. In step S300, an annular hole 102 is formed on the second surface 1002. The preparation method provided in this application embodiment includes: S310, the glass substrate 10 is modified in the annular region 101 to form an annular modified structure 11; S330, Remove the modified structure 11 to form an annular hole 102.

[0098] Through the above technical solution, the preparation method provided in this application embodiment can form a weakened modified structure 11, which is convenient to remove the modified structure 11, thereby facilitating the formation of annular holes 102.

[0099] Optionally, modifying the glass substrate 10 in the annular region 101 includes: irradiating the glass substrate 10 in the annular region 101 with a laser, thereby forming a weakened modified structure 11. That is, the preparation method provided in this application embodiment can use laser irradiation to weaken the glass substrate 10 in the annular region 101 to form the modified structure 11.

[0100] Optionally, removing the modified structure 11 to form the annular hole 102 includes etching the glass substrate 10, for example, by using wet etching to remove the modified structure 11. That is, the preparation method provided in this application embodiment can use an etching process to remove the modified structure 11.

[0101] In some embodiments, the annular region 101 includes a plurality of sub-regions 1011. After the glass substrate 10 is modified by the annular region 101, and before the modified structure 11 is removed to form the annular hole 102, that is, after step S310 and before step S330, the preparation method provided in this application embodiment includes: S320, the glass substrate 10 is modified again in sub-region 1011.

[0102] Through the above technical solution, after the modified structure 11 is formed and before the modified structure 11 is removed, the preparation method provided in this application embodiment can further modify and weaken the modified structure 11 in the sub-region 1011 of the annular region 101, which facilitates the removal of the modified structure 11.

[0103] Optionally, the sub-region 1011 is a circular region, and multiple sub-regions 1011 are arranged at intervals along the circumference of the annular region 101, which facilitates the weakening of the modified structure 11.

[0104] It is understandable that the modified structure 11 in subregion 1011 is a substructure 111 that has been modified and weakened twice. This can further weaken the modified structure 11 and make it easier to remove the modified structure 11.

[0105] Please see Figure 12 , Figure 13 , Figure 14 and Figure 15 In some embodiments, after the sacrificial layer 12 is prepared on the first surface 1001 and before the first buffer layer 20 is prepared in the annular hole 102, that is, after step S200 and before step S500, the preparation method provided in this application embodiment further includes: S400. A vent hole 120 is formed on the side of the sacrificial layer 12 away from the glass substrate 10. The vent hole 120 penetrates the sacrificial layer 12 and is connected to the annular hole 102.

[0106] Step S400 can be performed before or after step S300.

[0107] Through the above technical solution, the preparation method provided in this application embodiment prepares a vent 120 on the sacrificial layer 12 and makes the vent 120 communicate with the annular hole 102. In this way, when the first buffer layer 20 is prepared in the annular hole 102, the air in the annular hole 102 can be discharged from the vent 120, which helps to reduce the air pressure in the annular hole 102, thereby facilitating the entry of the material for preparing the first buffer layer 20 into the annular hole 102, and thus making it easier to prepare the first buffer layer 20.

[0108] Please see Figure 13 , Figure 14 and Figure 15Optionally, there are multiple vent holes 120, which are spaced apart circumferentially along the annular hole 102. This facilitates the discharge of gas from the annular hole 102 through the multiple vent holes 120, and allows the gas to be discharged in a timely manner. This, in turn, helps the material for preparing the first buffer layer 20 to enter the annular hole 102 uniformly, thereby improving the uniformity of the first buffer layer 20.

[0109] Please see Figure 14 and Figure 15 Optionally, the vent 120 includes a first vent 121 and a second vent 122 with different diameters. The first vent 121 and the second vent 122 are alternately arranged along the circumference of the annular hole 102, which is conducive to the timely discharge of gas in the annular hole 102.

[0110] Optionally, the orthographic projection of the vent 120 on the first surface 1001 does not overlap with the orthographic projection of the glass column 13 on the first surface 1001. This helps to increase the connection area between the glass column 13 and the sacrificial layer 12, thereby increasing the strength of the connection between the glass column 13 and the sacrificial layer 12, which facilitates the removal of the glass column 13 when the sacrificial layer 12 is removed.

[0111] Optionally, the orthographic projection of the vent 120 on the first surface 1001 is located within the orthographic projection of the annular hole 102 on the first surface 1001, which facilitates the timely discharge of gas from the annular hole 102.

[0112] In other embodiments, the sacrificial layer 12 may be made of a breathable material, so that when the first buffer layer 20 is prepared, the air in the annular hole 102 can be discharged from the sacrificial layer 12, which helps to reduce the air pressure in the annular hole 102, thereby facilitating the entry of the material for preparing the first buffer layer 20 into the annular hole 102, and thus making it easier to prepare the first buffer layer 20.

[0113] Please see Figure 16 and Figure 17 In some embodiments, after the first buffer layer 20 is prepared in the annular hole 102 and before the sacrificial layer 12 and the glass column 13 are removed, that is, after step S500 and before step S800, the preparation method provided in this application embodiment further includes: S600, a second buffer layer 30 is prepared on the second surface 1002; S700, a second through hole 301 is prepared on the second buffer layer 30, the second through hole 301 exposing at least the glass column 13.

[0114] Through the above technical solution, the preparation method provided in this application embodiment can prepare a second buffer layer 30 on the second surface 1002, which can reduce the stress when the glass substrate 10 is connected to other components, and prepare a second through hole 301 on the second buffer layer 30, so that the second through hole 301 exposes at least the glass pillar 13, so that the glass pillar 13 is not connected to the second buffer layer 30, which facilitates the removal of the glass pillar 13.

[0115] Optionally, the second through-hole 301 exposes at least a portion of the first buffer layer 20, which facilitates the fabrication of the conductive connection portion 200 within the first through-hole 103 in subsequent processes.

[0116] Please see Figure 17 and Figure 18 In step S800, the sacrificial layer 12 is removed by laser ablation. The sacrificial layer 12 is connected to the glass column 13. When the sacrificial layer 12 is removed, the glass column 13 can be taken out, thereby forming the first through hole 103.

[0117] Please refer to Figure 19 The preparation method provided in this application embodiment further includes: In step S900, a third buffer layer 400 is prepared on the first surface 1001, and a third through hole 401 is prepared, so that it can play a buffering role when the substrate assembly 100 is connected to other components.

[0118] Please refer to Figure 20 and Figure 21 The preparation method provided in this application embodiment further includes: Step S1000: A seed layer 300 is prepared in the first through hole 103. The seed layer 300 has a ring structure. In step S1100, a conductive connection portion 200 is prepared in the first through hole 103. The conductive connection portion 200 is located on the inner peripheral side of the seed layer 300.

[0119] In this way, the preparation method provided in this application first prepares the seed layer 300 and then prepares the conductive connection part 200, which facilitates the preparation of the conductive connection part 200.

[0120] The substrate assembly 100 provided in this application embodiment is manufactured by the preparation method of any of the above embodiments. The substrate assembly 100 has the same or similar technical effects as the preparation method of any of the above embodiments, which will not be repeated here.

[0121] The packaging substrate 1101 provided in this application embodiment includes a substrate, a conductive connection portion 200, a first circuit layer 500, and a second circuit layer 600. The substrate includes at least one substrate assembly 100 as described in the above embodiment. The conductive connection portion 200 is disposed in a first through hole 103, and the conductive connection portion 200 includes a first connection end 201 and a second connection end 202 along the thickness direction of the glass substrate 10. The first circuit layer 500 is disposed on one side of the substrate in the thickness direction and is connected to the first connection end 201 of the conductive connection portion 200. The second circuit layer 600 is disposed on the side of the substrate away from the first circuit layer 500 and is connected to the second connection end 202 of the conductive connection portion 200.

[0122] The packaging substrate 1101 provided in this application embodiment has the same or similar technical effects as the substrate assembly 100 in the above embodiment, and will not be described again here.

[0123] The packaging structure 1100 provided in this application includes the packaging substrate 1101 and chip 1102 of the above embodiments. The chip 1102 is packaged on the packaging substrate 1101 and is electrically connected to the packaging substrate 1101.

[0124] The packaging structure 1100 provided in this application embodiment has the same or similar technical effects as the packaging substrate 1101 in the above embodiment, and will not be described again here.

[0125] The electronic device 1000 provided in this application includes the packaging structure 1100 and circuit board 1200 of the above embodiments, and the circuit board 1200 is electrically connected to the packaging structure 1100.

[0126] The electronic device 1000 provided in this application embodiment has the same or similar technical effects as the packaging structure 1100 in the above embodiment, and will not be described again here.

[0127] The above are merely specific embodiments of this application and are not intended to limit this application. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A method for preparing a substrate assembly, characterized in that, include: A glass substrate is provided, the glass substrate including opposing first and second surfaces; A sacrificial layer is prepared on the first surface; An annular hole is formed on the second surface, the annular hole penetrating the glass substrate, and a glass pillar is formed on the glass substrate located on the inner periphery of the annular hole, the glass pillar being connected to the sacrificial layer; A first buffer layer is prepared within the annular hole; Remove the sacrificial layer and the glass pillar to form a first through hole.

2. The preparation method according to claim 1, characterized in that, After preparing the sacrificial layer on the first surface and before preparing the first buffer layer within the annular hole, the preparation method further includes: A vent hole is formed on the side of the sacrificial layer opposite to the glass substrate. The vent hole penetrates the sacrificial layer and communicates with the annular hole. Preferably, there are multiple vent holes, and the multiple vent holes are arranged at intervals along the circumference of the annular hole; Preferably, the vent hole includes a first vent hole and a second vent hole with different diameters, and the first vent hole and the second vent hole are alternately arranged along the circumference of the annular hole; Preferably, the orthographic projection of the vent hole on the first surface does not overlap with the orthographic projection of the glass column on the first surface; Preferably, the orthographic projection of the vent hole on the first surface lies within the orthographic projection of the annular hole on the first surface.

3. The preparation method according to claim 1, characterized in that, The second surface includes an annular region, and the process of forming an annular hole on the second surface includes: The glass substrate is modified in the annular region to form an annular modified structure; The modified structure is removed to form an annular hole; Preferably, modifying the glass substrate in the annular region includes: irradiating the glass substrate with a laser in the annular region; Preferably, removing the modified structure to form an annular hole includes etching the glass substrate.

4. The preparation method according to claim 3, characterized in that, The annular region includes multiple sub-regions. After modifying the glass substrate in the annular region, and before removing the modified structure to form the annular hole, the preparation method includes: The glass substrate is further modified in the sub-region; Preferably, the sub-region is a circular region, and multiple sub-regions are arranged at circumferential intervals along the annular region.

5. The preparation method according to claim 1, characterized in that, After preparing the first buffer layer within the annular hole and before removing the sacrificial layer and the glass column, the preparation method further includes: A second buffer layer is prepared on the second surface; A second through-hole is formed on the second buffer layer, the second through-hole exposing at least the glass column; Preferably, the second through-hole exposes at least a portion of the first buffer layer.

6. The preparation method according to claim 1, characterized in that, The material of the sacrificial layer is different from the material of the glass substrate, and the material of the sacrificial layer includes at least one of organic materials, metallic materials, and inorganic materials; Preferably, the organic material of the sacrificial layer comprises non-photosensitive polyimide; Preferably, the metallic material of the sacrificial layer includes chromium or chromium oxide; Preferably, the inorganic material of the sacrificial layer includes silicon nitride or silicon dioxide.

7. A substrate assembly, characterized in that, It is prepared by the preparation method according to any one of claims 1 to 6.

8. A packaging substrate, characterized in that, include: A substrate, comprising at least one substrate assembly as described in claim 7; A conductive connection portion is disposed within the first through hole, including a first connection end and a second connection end along the thickness direction of the glass substrate; A first circuit layer is disposed on one side of the substrate in the thickness direction and is connected to the first connection end of the conductive connection portion; The second circuit layer is disposed on the side of the substrate opposite to the first circuit layer and is connected to the second connection end of the conductive connection portion.

9. A packaging structure, characterized in that, include: The packaging substrate as described in claim 8; The chip is packaged on the packaging substrate and is electrically connected to the packaging substrate.

10. An electronic device, characterized in that, include: The packaging structure as described in claim 9; The circuit board is electrically connected to the package structure.

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