An IC carrier board reliability evaluation method

Abstract

This invention relates to the field of circuit board technology, specifically to a method for evaluating the reliability of IC carrier boards. The method involves fabricating the IC carrier board material to be tested into a single test substrate, dividing the substrate into multiple test areas, and setting copper-free isolation and groove weakening structures between each area. This allows for manual disassembly and reliability testing. The tests include HAST, TCT temperature cycling, tinning, peel strength, and impedance testing, covering key indicators such as interlayer insulation, line-to-line insulation, via insulation, conduction chain reliability, and high-speed signal transmission. By cross-referencing data from different test pieces on the same substrate, the overall reliability of the material under different aperture, via spacing, and layer count conditions can be accurately evaluated. This method is applicable to IC carrier board materials with 1-8 layer structures, 50-200μm apertures, and 100-500μm via spacing, enabling multi-functional testing on a single substrate.

Description

Technical Field

[0001] This invention relates to the field of circuit board technology, and more specifically to a method for evaluating the reliability of IC carrier boards. Background Technology

[0002] As a critical connection carrier between chips and printed circuit boards, the reliability of IC packaging substrates directly affects the lifespan and stability of electronic products. With the rapid development of 5G communication, artificial intelligence, and high-performance computing, IC substrates are evolving towards higher density, finer lines, and multilayer structures, placing higher demands on materials' resistance to damp heat, thermal shock, insulation reliability, and impedance consistency. The industry commonly employs methods such as High Accelerated Stress Testing (HAST), Temperature Cycling Testing (TCT), High Temperature Storage Testing (HTST), tinning tests, and impedance testing to assess the reliability of substrate materials. Relevant testing methods can be performed according to standards such as IPC-6921, JEDEC JESD22, and IPC-TM-650.

[0003] For reliability testing of IC substrate materials, some integrated test board designs exist in the prior art. For example, Chinese patent CN109526135B discloses a circuit board reliability evaluation method, which integrates multiple reliability tests on the same test circuit board. It uses the drilled area for circuit connectivity testing and the hole wall condition testing area for impact resistance and bonding strength testing, thus achieving a comprehensive evaluation of the circuit board substrate and processing technology. However, the problem is that it does not differentiate the design for sub-scenarios such as interlayer insulation, line insulation, and hole insulation, and the test board is a fixed integral structure that cannot be disassembled to perform reliability tests under different conditions in parallel.

[0004] It is evident that current IC substrate reliability evaluation testing still has significant shortcomings: First, it cannot perform independent testing of different zones, failing to simultaneously cover multi-dimensional evaluation requirements such as insulation reliability, mechanical strength, environmental stability, and electrical performance consistency. This often necessitates the use of multiple testing devices, resulting in low testing efficiency and high costs. Second, it suffers from poor adaptability. Existing test boards typically support only a single layer number, fixed aperture, and fixed aperture center distance, failing to flexibly adapt to testing requirements with different layer numbers (1-8 layers), aperture diameters (50-200μm), and spacing (100-500μm), thus limiting its applicability. Third, test boards are difficult to manually disassemble. Most test boards have a fixed integral structure, making it difficult to manually disassemble them and send them in parallel to different testing equipment for reliability testing under different conditions. This results in long testing cycles and poor data traceability. Therefore, there is an urgent need to develop an IC substrate reliability evaluation method that can flexibly adapt to various testing requirements, allow for independent testing of different zones, and enable manual disassembly. Summary of the Invention

[0005] To address the problems of poor adaptability, inability to perform independent testing of different zones, and difficulty in manual disassembly in existing IC substrate reliability testing, this invention provides a method for evaluating IC substrate reliability. This method fabricates the material under test into a single test substrate, with multiple reliability test areas divided into regions and isolation structures between them. Individual test pieces can be manually disassembled along the isolation structures, and HAST, TCT, solder drift, and impedance tests can be performed in parallel on each. Finally, test data from the same substrate are cross-analyzed. This invention, through its integrated and detachable design, achieves multi-dimensional parallel evaluation, provides strong data traceability, and can flexibly adapt to testing requirements of 1 to 8 layers, 50-200μm apertures, and 100-500μm pitch.

[0006] The technical solution of this invention is as follows: A method for evaluating the reliability of an IC carrier board includes the following steps: (1) The IC substrate material to be tested is made into an integrated test substrate, and the integrated test substrate is divided into multiple reliability test areas, and an isolation structure is provided between each area; (2) Manually disassemble the integrated test substrate along the isolation structure to separate the required independent test areas; (3) Perform different types of reliability tests on each of the separated independent test areas; (4) Cross-compare and analyze the test data obtained from different independent test pieces from the same substrate.

[0007] Furthermore, the fabrication steps of the integrated test substrate are as follows: S1. Inner layer processing: Conductive through holes and positioning holes are made by mechanical drilling, and inner layer conductive lines are made by laser direct imaging technology. The via positions of each test area are reserved, and copper-free gaps are processed between each test area before lamination. S2. Outer layer circuit and surface treatment: Fabricate outer layer test pads and circuits, cover the circuits with ink, make SMD openings on the pads, and plate the surface with nickel-gold. S3. Shape and Groove Machining: Create grooves and simultaneously machine the outer contour of the substrate; S4. Finished Product Inspection: Check the width of the copper-free gap, the depth of the groove, and the structural integrity of the test area, and conduct a breakage test for verification.

[0008] Furthermore, the plurality of reliability test areas include at least area A, area B, area C, area D, area E, and area F. Area A is provided with an interlayer insulation test structure, area B is provided with an inter-line insulation test structure, area C is provided with a peel strength test structure and a QVP quality verification test structure, area D is provided with an environmental and continuity reliability test structure, area E is provided with an inter-hole insulation and thermal stress test structure, and area F is provided with an impedance test structure.

[0009] Furthermore, the width of the copper-free gap is 1.5-3mm, and the depth of the groove is 0.8-1.2mm, to achieve electrical isolation between test areas and manual separation.

[0010] Furthermore, the thickness of the nickel-gold plating is as follows: the nickel layer thickness is 3-9 μm, and the gold layer thickness is 0.05-0.15 μm.

[0011] Furthermore, the interlayer insulation test structure in region A includes test units formed by alternating stacking of 1-8 dielectric and conductive layers. Each conductive layer is provided with an array of test pads. The test units are provided with interlayer vias with apertures of 50-200μm. The center-to-center distance between the vias includes five different spacings: 110μm, 130μm, 150μm, 180μm, and 200μm. The vias correspond one-to-one with the pads and are used to test the interlayer insulation reliability under different numbers of layers, apertures, and spacings.

[0012] Furthermore, the inter-line insulation test structure in region B includes 1-8 conductive line layers, with a line width of not less than 15μm and a spacing of not less than 50μm between the edge of the conductive line and the edge of the via. It is equipped with vias with a diameter of 50-200μm, which are electrically connected to the line layers for evaluating the inter-line insulation performance.

[0013] Furthermore, region C is equipped with a peel strength test structure and a QVP quality verification test structure. The peel strength test structure in region C has a stepped peel groove with a depth of 500-1000 μm and a width of 8-12 mm, and the groove wall is coated with an anti-corrosion coating. The QVP quality verification test structure includes an interconnect structure with a pore size of 50-200 μm and a pore center distance of 100-500 μm. The interconnect structure achieves interlayer conductivity through laser drilling and copper metallization.

[0014] Furthermore, the environmental and conductivity reliability testing structure of region D includes 1-8 layers of blind via interconnection chains. The diameter of the blind vias in the blind via interconnection chains is 50-100μm, and the center-to-center distance between the vias includes 110μm, 130μm, and 150μm. The blind via interconnection chains include at least one of 1-8 layers of full-layer blind via interconnection chains, 2-7 layers of five-layer via interconnection chains, and 1-4 layers of three-layer blind via interconnection chains. The inter-via insulation and thermal stress testing structure of region E includes an array-type via structure. The array-type via structure is a 1-8 layer full-through via structure with a diameter of 50-100μm and a center-to-center distance between the vias of 100-500μm. The array-type via structure is also provided with pads connected to the vias to accommodate thermal stress tin drift testing.

[0015] Furthermore, the impedance test structure of the region F includes 1-8 layers of transmission lines, the characteristic impedance of which includes at least two standard values: 50Ω and 85Ω, and is equipped with grounding vias with apertures of 50-100μm and a center-to-center distance of 150-300μm, for evaluating the dielectric properties and impedance consistency of the material.

[0016] The beneficial effects of this invention are as follows: 1. This invention adopts an integrated test substrate design, which integrates multiple reliability testing functions on the same substrate. Multiple independent test areas can be obtained through one processing, avoiding the problem of having to prepare multiple test substrates separately in traditional methods. This significantly reduces test costs and preparation cycle, and improves test efficiency.

[0017] 2. By setting copper-free isolation areas and groove weakening structures between each test area, electrical isolation and controllable separation of the test area are achieved. It can be quickly separated into independent test pieces by hand without the need for special cutting equipment. This not only makes the operation simple, but also effectively avoids secondary damage to the test structure during the cutting process, thereby improving the reliability and consistency of the test results.

[0018] 3. This invention targets key reliability indicators of IC substrates by dividing them into multiple dedicated test areas, such as interlayer insulation, inter-line insulation, inter-via insulation, continuity reliability, peel strength, and impedance. The structure and parameters of each area are independently designed, which can cover combinations of different numbers of layers, different apertures, and different aperture center distances. This enables a comprehensive evaluation of the material's performance in various application scenarios. Compared with existing single-function testing methods, the testing dimensions are more comprehensive and the results are more accurate.

[0019] 4. Since all test areas originate from the same integrated substrate, their material batches and processing technologies are completely consistent, making the data between different test items naturally comparable. Cross-comparison analysis can effectively eliminate interference caused by material differences and process fluctuations, improving the accuracy and traceability of data analysis.

[0020] 5. The technical solution of this invention can adapt to various reliability testing requirements such as HAST, TCT, tin floating and impedance, and has good environmental adaptability and versatility. It can be widely used in the performance verification and quality evaluation of different types of IC substrate materials and has high engineering application value. Attached Figure Description

[0021] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, for those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0022] Figure 1 This is a top view of the overall structure of the carrier plate of the present invention.

[0023] Figure 2 This is a partial enlarged view of the structure at the boundary between regions A and B of the carrier plate of the present invention.

[0024] Figure 3 This is a detailed diagram of the peeling groove in the carrier plate area C and the QVP test structure of the present invention.

[0025] Figure 4 This is a layout diagram of the carrier plate region D of the present invention.

[0026] Figure 5 This is a schematic diagram of the blind hole conductive chain structure in region D of the carrier plate of the present invention.

[0027] Figure 6 This is a schematic diagram of the E / F structure of the carrier plate region of the present invention. Detailed Implementation

[0028] To enable those skilled in the art to better understand the technical solutions of this invention, the technical solutions of the embodiments of this invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this invention, and not all embodiments. Based on the embodiments of this invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of this invention.

[0029] Example 1 This embodiment provides a method for reliability evaluation of IC substrate materials, including the preparation of an integrated test substrate and a multi-dimensional reliability testing process.

[0030] 1. Fabrication of integrated test substrate Select the IC substrate material to be tested and prepare an integrated test substrate according to the multilayer substrate manufacturing process. The preparation steps are as follows: (1) Inner layer processing: Conductive vias and positioning holes are processed on the copper surface of the inner layer substrate by mechanical drilling. The via diameter is 50-200μm. Then, the inner layer conductive lines are fabricated by laser direct imaging (LDI) process. Via positions are reserved in each test area, and a copper-free interval area with a width of 2mm is processed between adjacent test areas. After the pattern transfer is completed, etching and film removal are performed. Then, the lamination is performed according to the designed number of layers (6 layers in this embodiment). The lamination temperature is controlled at 200℃ and the holding time is 60min.

[0031] (2) Outer layer circuit and surface treatment: Test pads and conductive circuits are fabricated on the outer layer of the laminated substrate. Solder resist ink is used to cover the non-soldering area, and SMD windows are opened on the pads. Then, nickel-gold plating is performed on the surface, with a nickel layer thickness of 5μm and a gold layer thickness of 0.1μm, to improve oxidation resistance and soldering reliability.

[0032] (3) Shape and groove processing: According to the boundary position of each test area, a groove with a depth of 1mm is processed by mechanical milling, and the outer contour of the substrate is processed at the same time, with the dimensional accuracy controlled within ±0.1mm.

[0033] (4) Finished product inspection: The integrated test substrate is inspected, focusing on whether the copper-free gap width is 2mm, the groove depth is 1mm, and whether the structure of each test area is complete; then a manual break test is performed to verify that each area can be smoothly separated along the groove position.

[0034] 2. Test area structure design The integrated test substrate is divided into six test areas, namely area A to area F: Area A: Used for interlayer insulation testing, it adopts a 6-layer dielectric and conductive layer alternating stacked structure, with arrayed test pads on each layer, and three sizes of interlayer vias with apertures of 50μm, 100μm and 150μm, and the center distances of the apertures are 110μm, 150μm and 200μm respectively. Area B: Used for line-to-line insulation testing, with a multi-layer conductive circuit structure, a line width of 20μm, and a distance of 60μm between the line and the edge of the via; Region C: Used for peel strength and pore quality verification, with stepped peel grooves, groove depths of 500μm, 750μm and 1000μm, and groove width of 10mm, and interconnection structures with different pore diameters and spacings are also provided; Region D: Used for conductive chain reliability testing. A blind via conductive chain structure is designed with a hole diameter of 75μm and a hole center distance of 130μm. A conductive path is formed by connecting different interlayer blind vias in series. Area E: Used for inter-hole insulation and thermal stress testing, with an array of through-hole structures, the hole diameter is 80μm, and the hole spacing is available in two specifications: 100μm and 300μm. Area F: Used for impedance testing, setting up inner and outer transmission lines, with designed characteristic impedances of 50Ω and 85Ω, and configured with grounding via structures.

[0035] 3. Testing Process (1) Sample splitting: According to the test requirements, apply external force to the integrated test substrate along the groove between each test area to manually break it apart and obtain independent test pieces in areas A to F respectively.

[0036] (2) Reliability testing: Each test area will be tested separately. HAST test (regions A, B, E): Test the insulation resistance change for 96 hours at 130℃ and 85%RH. TCT test (region D): Cyclic test is performed between -65℃ and 150℃, each temperature is held for 15 minutes, for a total of 1000 cycles, and the rate of change of on-resistance is recorded. Tin Bleaching Test (Area E): Immerse the sample in a 260℃ tin bath for 10 seconds, repeat 3 times, and observe the bonding status between the pad and the via. Impedance test (area F): Test the transmission line impedance in the frequency range of 50MHz to 10GHz and record the impedance deviation; Peel test (area C): The peel strength of peel grooves at different depths is measured using a tensile testing device.

[0037] (3) Data analysis: The data obtained from each test area are summarized and cross-analyzed based on the same batch of materials to establish the correlation between different structural parameters (pore size, spacing, number of layers) and reliability indicators, which is used to evaluate the comprehensive performance of the material.

[0038] 4. Test Results Analysis The integrated testing method of this embodiment can complete multi-dimensional reliability testing on the same substrate, improving testing efficiency by about 80% compared to traditional methods. At the same time, due to the high consistency of data sources, the accuracy and comparability of test results are significantly improved.

[0039] Example 2 This embodiment provides a method for evaluating the reliability of IC substrate materials. Based on Embodiment 1, it verifies the material adaptability in high-density wiring and high-speed application scenarios, including the preparation of an integrated test substrate and a multi-dimensional reliability testing process.

[0040] 1. Fabrication of integrated test substrate Select the IC substrate material to be tested (taking high-TG, low-dielectric-loss resin-based copper clad laminate as an example), and prepare an integrated test substrate according to the multilayer substrate manufacturing process. The preparation steps are as follows: (1) Inner layer processing: Conductive vias and positioning holes are processed on the copper surface of the inner layer substrate by mechanical drilling. The via diameter is 50-150μm. The inner layer conductive lines are fabricated by laser direct imaging (LDI) process. Via positions are reserved in each test area, and a copper-free gap area with a width of 1.5mm is processed between adjacent test areas. After the pattern transfer is completed, etching and film removal are performed. Then, the lamination is performed according to the designed number of layers (8 layers in this embodiment). The lamination temperature is controlled at 205-215℃ and the holding time is 70min.

[0041] (2) Outer layer circuit and surface treatment: Test pads and conductive circuits are fabricated on the outer layer of the laminated substrate. Solder resist ink is used to cover the non-soldering area, and SMD windows are opened on the pads. Then, nickel-gold plating is performed on the surface, with a nickel layer thickness of 6μm and a gold layer thickness of 0.08μm, to improve the corrosion resistance in high temperature and high humidity environments.

[0042] (3) Shape and groove processing: According to the boundary position of each test area, a groove with a depth of 0.8mm is processed by mechanical milling, and the outer contour of the substrate is processed at the same time, with the dimensional accuracy controlled within ±0.1mm.

[0043] (4) Finished product inspection: The integrated test substrate is inspected, focusing on whether the copper-free gap width is 1.5mm, the groove depth is 0.8mm, and whether the structure of each test area is complete; then a manual break test is performed to verify that each area can be smoothly separated along the groove position.

[0044] 2. Test area structure design The integrated test substrate is divided into six test areas, namely area A to area F: Area A: Used for interlayer insulation testing, it adopts an 8-layer dielectric and conductive layer alternating stacked structure, with arrayed test pads on each layer, and interlayer vias with two specifications of apertures of 50μm and 75μm, with center-to-center distances of 110μm and 130μm respectively. Area B: Used for line-to-line insulation testing, with a high-density conductive line structure, a line width of 15μm, and a distance of 50μm between the line and the edge of the via; Region C: Used for peel strength and hole quality verification, with stepped peel grooves, groove depths of 500μm and 800μm, and groove width of 8mm, and a high-density interconnect structure is also provided; Region D: Used for conductive chain reliability testing. A blind via conductive chain structure is designed, using a multi-layer stacked via form, with a via diameter of 60μm and a center-to-center distance of 120μm. Area E: Used for inter-hole insulation and thermal stress testing, with an array of through-hole structures, the hole diameter is 70μm, and the hole spacing is available in two specifications: 100μm and 200μm. Area F: Used for impedance testing, setting up a high-speed transmission line structure with a designed characteristic impedance of 50Ω, introducing a differential impedance structure, and configuring a grounding via array.

[0045] 3. Testing Process (1) Sample splitting: According to the test requirements, apply external force to the integrated test substrate along the groove between each test area to manually break it apart and obtain independent test pieces in areas A to F respectively.

[0046] (2) Reliability testing: Each test area will be tested separately. HAST test (regions A, B, E): Test the insulation resistance change for 96 hours at 130℃ and 85%RH. TCT test (region D): Cyclic test was performed between -65℃ and 150℃, with each temperature held for 15 minutes, for a total of 1200 cycles, and the rate of change of on-resistance was recorded. Tin Bleaching Test (Area E): Immerse the sample in a 260℃ tin bath for 10 seconds, repeat 5 times, and observe the bonding status between the pads and vias. Impedance test (area F): Test the transmission line impedance in the frequency range of 100MHz to 15GHz and record the impedance deviation; Peel test (area C): The peel strength of peel grooves at different depths is measured using a tensile testing device.

[0047] (3) Data analysis: The data obtained from each test area are summarized and cross-analyzed based on the same batch of materials. Correlation analysis is conducted on the performance changes under different pore sizes, spacing and number of layers.

[0048] 4. Test Results Analysis The integrated testing method in this embodiment enables multi-dimensional reliability testing even under high-density wiring and high-frequency application conditions. This embodiment further verifies that the method of the present invention still has good applicability and stability under conditions of smaller aperture, smaller spacing and higher layer count, and can accurately reflect the performance of materials in extreme application scenarios, while maintaining high data consistency and testing efficiency.

[0049] Although the present invention has been described in detail with reference to the accompanying drawings and preferred embodiments, the present invention is not limited thereto. Various equivalent modifications or substitutions can be made to the embodiments of the present invention by those skilled in the art without departing from the spirit and essence of the invention, and such modifications or substitutions should all be within the scope of the present invention. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should also be covered within the protection scope of the present invention.

Claims

1. A method for evaluating the reliability of an IC carrier board, characterized in that, Includes the following steps: (1) The IC substrate material to be tested is made into an integrated test substrate, and the integrated test substrate is divided into multiple reliability test areas, and an isolation structure is provided between each area; (2) Manually disassemble the integrated test substrate along the isolation structure to separate the required independent test areas; (3) Perform different types of reliability tests on each of the separated independent test areas; (4) Cross-compare and analyze the test data obtained from different independent test pieces from the same substrate.

2. The IC carrier board reliability evaluation method as described in claim 1, characterized in that, The fabrication steps of the integrated test substrate are as follows: S1. Inner layer processing: Conductive through holes and positioning holes are made by mechanical drilling, and inner layer conductive lines are made by laser direct imaging technology. The via positions of each test area are reserved, and copper-free gaps are processed between each test area before lamination. S2. Outer layer circuit and surface treatment: Fabricate outer layer test pads and circuits, cover the circuits with ink, make SMD openings on the pads, and plate the surface with nickel-gold. S3. Shape and Groove Machining: Create grooves and simultaneously machine the outer contour of the substrate; S4. Finished Product Inspection: Check the width of the copper-free gap, the depth of the groove, and the structural integrity of the test area, and conduct a breakage test for verification.

3. The IC carrier board reliability evaluation method as described in claim 1, characterized in that, The multiple reliability test areas include at least area A, area B, area C, area D, area E, and area F. Area A is equipped with an interlayer insulation test structure, area B is equipped with an inter-line insulation test structure, area C is equipped with a peel strength test structure and a QVP quality verification test structure, area D is equipped with an environmental and continuity reliability test structure, area E is equipped with an inter-hole insulation and thermal stress test structure, and area F is equipped with an impedance test structure.

4. The IC carrier board reliability evaluation method as described in claim 2, characterized in that, The width of the copper-free gap is 1.5-3mm, and the depth of the groove is 0.8-1.2mm, so as to achieve electrical isolation between test areas and manual separation.

5. The IC carrier board reliability evaluation method as described in claim 2, characterized in that, The thickness of the nickel-gold plating is as follows: the nickel layer thickness is 3-9 μm, and the gold layer thickness is 0.05-0.15 μm.

6. The IC carrier board reliability evaluation method as described in claim 3, characterized in that, The interlayer insulation test structure in region A includes test units formed by alternating stacking of 1-8 dielectric and conductive layers. Each conductive layer has an array of test pads. The test units are equipped with interlayer vias with apertures of 50-200μm. The center-to-center distance between the vias includes five different spacings: 110μm, 130μm, 150μm, 180μm, and 200μm. The vias correspond one-to-one with the pads and are used to test the interlayer insulation reliability under different numbers of layers, apertures, and spacings.

7. The IC carrier board reliability evaluation method as described in claim 3, characterized in that, The inter-line insulation test structure in region B includes 1-8 conductive line layers. The line width of the conductive line layer is not less than 15μm, and the distance between the edge of the conductive line and the edge of the via is not less than 50μm. It is equipped with vias with a diameter of 50-200μm, which are electrically connected to the line layers to evaluate the inter-line insulation performance.

8. The IC carrier board reliability evaluation method as described in claim 3, characterized in that, Region C is equipped with a peel strength test structure and a QVP quality verification test structure. The peel strength test structure in Region C has a stepped peel groove with a depth of 500-1000 μm and a width of 8-12 mm, and the groove wall is coated with an anti-corrosion coating. The QVP quality verification test structure includes an interconnect structure with a pore size of 50-200 μm and a pore center distance of 100-500 μm. The interconnect structure achieves interlayer conductivity through laser drilling and copper metallization.

9. The IC carrier board reliability evaluation method as described in claim 3, characterized in that, The environmental and conductivity reliability testing structure in region D includes 1-8 layers of blind via interconnect chains. The diameter of the blind vias in the blind via interconnect chains is 50-100μm, and the center-to-center distance between the vias is 110μm, 130μm, and 150μm. The blind via interconnect chains include at least one of 1-8 layers of full-layer blind via interconnect chains, 2-7 layers of five-layer via interconnect chains, and 1-4 layers of three-layer blind via interconnect chains. The inter-via insulation and thermal stress testing structure in region E includes an array-type via structure. The array-type via structure is a 1-8 layer full-through via structure with a diameter of 50-100μm and a center-to-center distance between the vias of 100-500μm. The array-type via structure is also provided with pads connected to the vias to accommodate thermal stress tin drift testing.

10. The IC carrier board reliability evaluation method as described in claim 3, characterized in that, The impedance test structure of region F includes 1-8 layers of transmission lines. The characteristic impedance of the transmission lines includes at least two standard values: 50Ω and 85Ω. It is equipped with grounding vias with apertures of 50-100μm and a center-to-center distance of 150-300μm to evaluate the dielectric properties and impedance consistency of the materials.

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