Voltage regulator

Abstract

This application relates to voltage regulators. An apparatus includes a push-pull regulation loop (PPRL), an input terminal, an output terminal, and a plurality of FC circuits. The PPRL includes a PMOS transistor, an NMOS transistor, and a first plurality of capacitors. The input terminal and the output terminal are coupled to the PPRL via the first plurality of capacitors. The plurality of FC circuits include a second plurality of capacitors. The FC circuits in the plurality of FC circuits are coupled to each other and to a rail between the input and the output terminals. Each FC circuit in the plurality of FC circuits includes at least a first transistor switch and a second transistor switch, the first transistor switch and the second transistor switch being coupled to corresponding capacitors in the second plurality of capacitors.

Description

Technical Field

[0001] This disclosure relates to voltage regulators. Background Technology

[0002] Encrypting circuits such as the Advanced Encryption Standard (AES) are vulnerable to Correlation Power Analysis (CPA) side-channel attacks (SCA), where adversaries monitor the current signatures or electromagnetic traces generated by the die to decipher the value of the embedded key. For example, an attacker might construct Hamming-weight (HW) and Hamming-distance (HD) models of vulnerable circuit nodes for various key guesses and calculate the correlation between measured signatures and these switching-activity models. With a sufficient number of measurements, a correct key guess may emerge, exhibiting a significantly higher correlation with the physical data and compromising the cryptographic security. Summary of the Invention

[0003] According to one aspect of this application, an apparatus is provided, comprising: a PMOS transistor including a drain terminal coupled to a first terminal of an encryption circuit; an NMOS transistor including a drain terminal coupled to a source terminal of the PMOS transistor; and a first capacitor including a first terminal and a second terminal, the first terminal of the first capacitor being coupled to the source terminal of the PMOS transistor; and the second terminal of the first capacitor being coupled to a second terminal of the encryption circuit.

[0004] According to another aspect of this application, an apparatus is provided, comprising: a push-pull regulation loop (PPRL) including a PMOS transistor, an NMOS transistor, and a first plurality of capacitors; an input terminal and an output terminal coupled to the PPRL via the first plurality of capacitors; and a plurality of flying capacitor (FC) circuits including a second plurality of capacitors, the plurality of FC circuits being coupled to each other and to a rail between the input terminal and the output terminal, wherein the FC circuits of the plurality of FC circuits further include at least a first transistor switch and a second transistor switch, the first transistor switch and the second transistor switch being coupled to corresponding capacitors in the second plurality of capacitors.

[0005] According to another aspect of this application, a method for manufacturing a voltage regulator is provided, comprising: coupling a PMOS transistor, an NMOS transistor, a controller circuit, and a first plurality of capacitors to form a push-pull regulation loop (PPRL); coupling the PPRL to an input terminal and an output terminal via the first plurality of capacitors; coupling a plurality of flying capacitors (FC) and a plurality of transistor switches to form a plurality of FC circuits; coupling one of the plurality of FC circuits to the input terminal, the output terminal, and the first plurality of capacitors; and coupling a subset of the plurality of FC circuits to the FC circuit. Attached Figure Description

[0006] In the accompanying drawings, the same numbers may describe the same or similar components or features in different views. The same numbers with different letter suffixes may represent different instances of similar components. Some embodiments are shown in the illustrations of the drawings listed below by way of example and not limitation.

[0007] Figure 1 A block diagram of a secure integrated voltage regulator (SIVR) architecture according to some embodiments is shown, illustrating the insertion of a third reset stage.

[0008] Figure 2 This is a block diagram of an SIVR with a push-pull regulation loop (PPRL) according to some embodiments.

[0009] Figure 3 The diagram illustrates the use of some embodiments by Figure 2 A diagram illustrating the charging, transfer, and reset phases performed by SIVR.

[0010] Figure 4 According to some embodiments, from Figure 2 The curve of the input current observed by SIVR is presented.

[0011] Figure 5 For use as a reset stage according to some embodiments (e.g., in...) Figure 2 Block diagram of a push-pull amplifier in SIVR.

[0012] Figure 6 This is a flowchart of an example method for manufacturing SIVR according to some embodiments.

[0013] Figure 7 A block diagram of an example machine is shown, through which any one or more of the operations / techniques (e.g., methods) discussed herein can be performed. Detailed Implementation

[0014] The following detailed description refers to the accompanying drawings. The same reference numerals may be used to identify the same or similar elements in different drawings. In the following description, specific details, such as specific structures, architectures, interfaces, technologies, etc., are set forth for explanation and not limitation in order to provide a thorough understanding of various aspects of the various embodiments. However, it will be apparent to those skilled in the art, who will have the benefits of this disclosure, that various aspects of the various embodiments may be implemented in other examples departing from these specific details. In some cases, descriptions of well-known devices, circuits, and methods have been omitted to avoid redundant details obscuring the description of the various embodiments.

[0015] The following description and accompanying drawings fully illustrate specific embodiments to enable those skilled in the art to practice these embodiments. Other embodiments may include structural, logical, electrical, process, and other variations. Some portions and features of some embodiments may be included in or replace features of other embodiments. The embodiments set forth in the claims cover all available equivalents of these claims.

[0016] As used herein, the term "chip" (or die) refers to a piece of material, such as semiconductor material, that includes circuitry (e.g., an integrated circuit or a portion thereof). The term "memory IP" refers to memory intellectual property. The terms "memory IP," "memory device," "memory chip," and "memory" are interchangeable.

[0017] The term "processor" as configured to perform a specific operation includes both a single processor configured to perform all operations (such as the operations or methods disclosed herein) and multiple processors configured to perform some or all operations (which may overlap), such that the processors combine to perform all operations.

[0018] As used herein, the term "IO" indicates input / output. As used herein, the term "RC" indicates resistance and capacitance. As used herein, the term "Rx" indicates receiver (or receive). As used herein, the term "Tx" indicates transmitter (or transmit). As used herein, the term "TRX" indicates transceiver. As used herein, the term "UCIe" indicates Universal Chiplet Interconnect Express. As used herein, the term "Vref" indicates reference voltage. As used herein, the terms "Vin" indicate input voltage and "Vout" indicate output voltage. As used herein, the terms "series coupling," "series connection," and "serial connection" are synonymous with each other and indicate a series connection between two or more components / circuits, where the series connection may be based on a direct or indirect electrical connection between the two or more components / circuits. As used herein, the terms "parallel coupling," "parallel connection," and "parallel connection" are synonymous with each other and indicate a parallel connection between two or more components / circuits, where the parallel connection may be based on a direct or indirect electrical connection between the two or more components / circuits. In some respects, countermeasures to enhance SCA resistance may include integrated voltage regulators, random masking, repeated data paths, and current balancing using switched capacitors and pseudo-hysteresis controllers, which result in higher area or performance overhead.

[0019] While low-dropout (LDO) regulators, shunts, and buck converters with randomized noise injection offer significant side-channel suppression in the time domain, they are less efficient against frequency domain attacks. In contrast, arithmetic countermeasures such as random masking, heterogeneous Galois-field operations, and current equalization modify the frequency content of the current trajectory within the periodic boundaries without significantly altering time-domain characteristics. The disclosed techniques include a Secure Integrated Voltage Regulator (SIVR) that achieves efficient side-channel leakage suppression consistent across time and frequency domains (SCA) by breaking the correlation between the measured current signature and the data-related in-die switching activity. Therefore, attackers attempting CPA attacks against the underlying encryption engine are presented with a flat current distribution, rendering the attack ineffective.

[0020] The aforementioned anti-SCA schemes are inefficient for combined time-domain / frequency-domain analysis and impose significant area / energy overhead on the underlying cryptographic engine. These schemes also typically rely on the cryptographic algorithms used in the engine. On the other hand, the disclosed SIVR provides a cryptographically independent solution that protects the underlying engine from the specific algorithms / arithms being computed.

[0021] The proposed SIVR architecture is an integrated voltage regulator scheme based on switched capacitors, designed to completely isolate the input current signature from the downstream encryption engine (physically and electrically), breaking the correlation between the measured current signature and the data-related switching activity within the die. This results in a flat current distribution at the input, independent of the encryption engine type and relevant load variations during encryption.

[0022] Figure 1 A block diagram of a Safety Integrated Voltage Regulator (SIVR) architecture 100 according to some embodiments illustrates the insertion of a third reset stage. (Refer to...) Figure 1 The SIVR architecture 100 may include a voltage source 108 and charging capacitors 110 and 112. The SIVR architecture 100 may be configured to operate in three phases, such as a charging phase 102, a transfer phase 104, and a reset phase 106. The corresponding voltage distributions for phases 102, 104, and 106 are shown in voltage curves 118, 120, and 122, respectively.

[0023] During the transmission phase 104, the stored charge of charging capacitors 110 and 112 is discharged (used) by AES circuit 114.

[0024] During the reset phase 106, regulator 116 may be configured to regulate the voltage (and current) to a pre-configured reset level (e.g., Vrst). In some aspects, regulator 116 may be configured as a push-pull regulation loop (PPRL) (e.g., Figure 2 PPRL202).

[0025] Unlike traditional switched-capacitor converters with charging and discharging phases, the proposed SIVR enables a third “reset” phase (e.g., reset phase 106) in addition to the charging and discharging phases. This ensures that the capacitor charging phase always restarts at the same point as the previous cycle, thereby ensuring that the input current distribution is independent of cryptographic engine activity. This correct-by-construction method helps eliminate any correlation between the load and the input current, resulting in a flat current distribution when an attacker attempts to launch a CPA attack on the underlying cryptographic engine.

[0026] Figure 2 A block diagram of an SIVR 200 with a push-pull regulating loop (PPRL) according to some embodiments. Reference Figure 2The SIVR 200 includes PPRL 202, multiple flying capacitor (FC) circuits (e.g., FC circuits 204, 206, 208, and 210), transistor switches (or switches) 248, 250, 252, and 242, and rail 205 coupled between input 201 and output 203. In some respects, the FC circuits may also be referred to as FC blocks.

[0027] In some respects, input 201 is coupled to voltage source 244, and output 203 is coupled to encryption circuit input 246.

[0028] In some aspects, FC circuit 210 includes FC 234 and switches 230 and 232. In some aspects, FC circuit 208 includes FC 228 and switches 224 and 226. In some aspects, FC circuit 206 includes FC 222 and switches 218 and 220. In some aspects, FC circuit 204 includes FC 216 and switches 212 and 214.

[0029] In some respects, switches 248, 250, and 252 couple their respective FC circuits 206, 208, and 210 to ground.

[0030] In some respects, FC circuits 204, 206 and 208 are coupled to FC circuit 210 at node C.

[0031] PPRL 202 can be configured to include a PMOS transistor 236, an NMOS transistor 238, and control circuitry 240, all of which are as follows: Figure 2 The phase coupling is shown. In some aspects, the control circuit 240 can be configured to activate or deactivate the switch (as described below) to enable the charging phase 102, the transmission phase 104, and the reset phase 106.

[0032] In some respects, PPRL 202 can be configured as Figure 5 The reset stage 500. In some respects, PPRL 202 is coupled at node N to rail 205 (e.g., Figure 2 (As shown).

[0033] Figure 2 The switches in the document are also referenced as indicating one of groups 1, 2, 3, or 4 that can be associated with them. For example, switch group 1 may include switches 214, 220, 226, 252, and 232. Switch group 2 may include switches 248, 250, 212, 218, and 224. Switch group 3 may include switch 242. Switch group 4 may include switch 230.

[0034] In some respects, the charging phase 102 can be initiated (e.g. by control circuit 240) by turning on the switches of groups 1 and 3 (ON) and turning off the switches of groups 2 and 4 (OFF).

[0035] In some respects, the transmission phase 104 can be initiated by turning on the switches of groups 2 and 4 (ON) and turning off the switches of groups 1 and 3 (OFF) (e.g., by control circuit 240 for transferring charge to terminal 246 of the encryption circuit).

[0036] In some respects, the reset phase 106 can be initiated (e.g., by control circuit 240) by turning on the switch of group 1 (ON) and turning off the switches of groups 2, 3 and 4 (OFF).

[0037] In some respects, when the switch of group 1 is activated, charge is transferred between FC circuit 210 and FC circuits 208, 206 and 204 via node B.

[0038] Figure 3 The sorting and activation of switches in different groups during the three disclosed phases are also shown.

[0039] Figure 3 The diagram illustrates the use of some embodiments by Figure 2 Illustration 300 shows the charging, transfer, and reset phases performed by the SIVR 200. (Reference) Figure 3 Figure 300 illustrates the activation of the switch during the sequential phases (including reset phase 302, charging phase 304, transmission phase 306, reset phase 308, and charging phase 310).

[0040] The proposed SIVR architecture (e.g.) Figure 2 (As shown) can be configured as a boost charge pump, which takes the input voltage and generates 1.33*Vin as the output voltage, unlike the traditional approach that typically uses a 1:1 ratio. This allows the SOC to have other IPs that operate directly from the input power supply without the efficiency losses from another IVR as seen in LDO / SC / Buck solutions.

[0041] In some respects, the SIVR 200 ratio can be selected as 1:1.33 to optimize capacitor counts and values ​​as well as associated area overhead, minimize switching area, and provide a higher voltage to the encryption engine while ensuring capacitor reset to begin charging at the same point at the end of the cycle, all while providing reasonable efficiency. Timing diagram of a 2-phase SIVR (…) Figure 3 The diagram shows the charging, discharging, and reset phases of the proposed SIVR. Figure 4 The transient simulation results of the proposed SIVR are shown.

[0042] Figure 4According to some embodiments, from Figure 2 The proposed SIVR observation curve is shown in Figure 400. Figure 4 As shown, the input current observed from the proposed SIVR exhibits insensitivity to changes in the encryption engine load of 20-120mA, validating the effectiveness of the proposed IVR architecture.

[0043] Figure 5 For use as a reset stage according to some embodiments (e.g., Figure 2 Block diagram of the push-pull amplifier 500 (PPRL 202 in SIVR). Reference Figure 5 Amplifier 500 may include PMOS transistor 502, NMOS transistor 504, control circuitry 506, and capacitors 508 and 510. Amplifier 500 may be configured to couple to PMOS transistor 502 and capacitors 508 and 510 (e.g., Figure 5 The encryption circuit (e.g., AES circuit 512) is supplied with voltage.

[0044] Figure 5 The push-pull LDO architecture in the diagram can be used to restore capacitor voltages (e.g., the voltages of capacitors 508 and 510) to their initial starting point (e.g., performing a reset to Vrst as described above). While the reset stage implementation is shown as a push-pull LDO, this concept can be extended to other implementations (e.g., another switched capacitor or buck regulator), depending on the available area.

[0045] Figure 6 This is a flowchart of an example method 600 for manufacturing a voltage regulator according to some embodiments. (See also...) Figure 6 Method 600 includes operations 602, 604, 606, 608, and 610, which may be performed by a processor, an embedded controller, receiver circuitry, transceiver circuitry, or another processor of a computing device (e.g., Figure 7 The hardware processor 702 of the machine 700 shown may include a combination of Figure 1-5 The discussion involves one or more circuits. In some embodiments, in conjunction with... Figure 1-5 One or more circuits discussed can perform with Figure 6 The associated functions (or including configurations / circuits), and one or more examples listed below.

[0046] In operation 602, the PMOS transistor, NMOS transistor, controller circuit and first plurality of capacitors are coupled to form a push-pull regulation loop (PPRL).

[0047] In operation 604, PPRL is coupled to the input and output terminals via a first plurality of capacitors.

[0048] In operation 606, multiple flying capacitors (FC) and multiple transistor switches are coupled to form multiple FC circuits.

[0049] In operation 608, one of the multiple FC circuits is coupled to the input, the output and a first plurality of capacitors.

[0050] In operation 610, a subset of multiple FC circuits is coupled to the FC circuit.

[0051] Figure 7 A block diagram of an example machine 700 is shown, through which any one or more of the techniques (e.g., methods) discussed herein can be performed. In alternative embodiments, machine 700 may operate as a standalone device or may be connected (e.g., networked) to other machines. In a networked deployment, machine 700 may act as a server machine, a client machine, or both in a server-client network environment. In the example, machine 700 may operate as a peer node in a peer-to-peer (P2P) (or other distributed) network environment. Machine 700 may be a personal computer (PC), tablet PC, set-top box (STB), personal digital assistant (PDA), portable communication device, mobile phone, smartphone, network device, network router, switch or bridge, or any other computing device capable of executing instructions (sequential or otherwise) specifying the actions to be taken by the machine. Furthermore, although only a single machine is illustrated, the term "machine" should be understood to include any collection of machines that individually or collaboratively execute a set (or more) of instructions to perform any one or more of the methods discussed herein, such as cloud computing, Software as a Service (SaaS), or other computer cluster configurations. The terms “machine,” “computing device,” and “computer system” are used interchangeably.

[0052] Machine (e.g., computer system) 700 may include hardware processor 702 (e.g., central processing unit (CPU), graphics processing unit (GPU), hardware processor core, or any combination thereof), main memory 704, and static memory 706, some or all of which may communicate with each other via interconnect (e.g., bus) 708. In some aspects, main memory 704, static memory 706, or any other type of memory used by machine 700 (including cache memory) may be configured based on the disclosed techniques, or the disclosed memory devices may be implemented.

[0053] Specific examples of main memory 704 include random access memory (RAM) and semiconductor memory devices, which in some embodiments may include storage locations in a semiconductor, such as registers. Specific examples of static memory 706 include: non-volatile memory, such as semiconductor memory devices (e.g., electrically programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM)) and flash memory devices; disks, such as internal hard disks and removable disks; magneto-optical disks; RAM; and CD-ROMs and DVD-ROMs.

[0054] Machine 700 may also include a display device 710, an input device 712 (e.g., a keyboard), and a user interface (UI) navigation device 714 (e.g., a mouse). In the example, the display device 710, input device 712, and UI navigation device 714 may be a touchscreen display. Machine 700 may additionally include a storage device (e.g., a drive unit or another mass storage device) 716, a signal generation device 718 (e.g., a speaker), a network interface device 720, and one or more sensors 721, such as a Global Positioning System (GPS) sensor, a compass, an accelerometer, or other sensors. Machine 700 may include an output controller 728, connected serially (e.g., Universal Serial Bus (USB)), in parallel, or other wired or wirelessly (e.g., infrared (IR), near field communication (NFC), etc.) to communicate with or control one or more peripheral devices (e.g., a printer, a card reader, etc.). In some embodiments, hardware processor 702 and / or instructions 724 may include processing circuitry and / or transceiver circuitry.

[0055] Storage device 716 may include machine-readable medium 722 on which one or more sets of data structures or instructions 724 (e.g., software) embodying any one or more of the technologies or functions described herein, or used by any one or more of the technologies or functions described herein, may be stored. Instructions 724 may also reside wholly or at least partially in main memory 704, static memory 706, or hardware processor 702 during execution by machine 700. For example, one or any combination of hardware processor 702, main memory 704, static memory 706, or storage device 716 may constitute a machine-readable medium.

[0056] Specific examples of machine-readable media may include: non-volatile memory, such as semiconductor memory devices (e.g., EPROM or EEPROM) and flash memory devices; disks, such as internal hard disks and removable disks; magneto-optical disks; RAM; and CD-ROM and DVD-ROM optical discs.

[0057] Although machine-readable medium 722 is shown as a single medium, the term "machine-readable medium" can include a single medium or multiple media (such as centralized or distributed databases and / or associated caches and servers) configured to store instructions 724.

[0058] The apparatus of machine 700 may be one or more of the following: a hardware processor 702 (e.g., a central processing unit (CPU), a graphics processing unit (GPU), a hardware processor core, or any combination thereof), main memory 704 and static memory 706, one or more sensors 721, a network interface device 720, one or more antennas 760, a display device 710, an input device 712, a UI navigation device 714, a storage device 716, an instruction set 724, a signal generation device 718, and an output controller 728. The apparatus may be configured to perform one or more of the methods and / or operations discussed herein. The apparatus may be a component of machine 700 to perform one or more of the methods and / or operations discussed herein, and / or as part of performing one or more of the methods and / or operations discussed herein. In some embodiments, the apparatus may include pins or other means for receiving power. In some embodiments, the apparatus may include power regulation hardware.

[0059] The term "machine-readable medium" can include any medium capable of storing, encoding, or carrying instructions executable by machine 700 and causing machine 700 to perform any one or more of the technologies disclosed herein, or any medium capable of storing, encoding, or carrying data structures used or associated with such instructions. Examples of non-limiting machine-readable media include solid-state memory, as well as optical and magnetic media. Specific examples of machine-readable media include: non-volatile memory, such as semiconductor memory devices (e.g., electrically programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM)) and flash memory devices; magnetic disks, such as internal hard disks and removable hard disks; magneto-optical disks; random access memory (RAM); and CD-ROM and DVD-ROM optical disks. In some examples, machine-readable media can include non-transitory machine-readable media. In some examples, machine-readable media can include machine-readable media that are not transient propagating signals.

[0060] Instruction 724 can also be transmitted or received over communication network 726 via network interface device 720 using any of a variety of transport protocols (such as Frame Relay, Internet Protocol (IP), Transmission Control Protocol (TCP), User Datagram Protocol (UDP), Hypertext Transfer Protocol (HTTP), etc.). Example communication networks may include: Local Area Network (LAN), Wide Area Network (WAN), Packet Data Network (e.g., the Internet), Mobile Phone Network (e.g., Cellular Network), Plain Old Telephone (POTS) Network, and Wireless Data Network (e.g., IEEE 802.11 series standards i.e. Wi-Fi®, IEEE 802.16 series standards i.e. WiMax®), IEEE 802.8.4 series standards, Long Term Evolution (LTE) series standards, Universal Mobile Telecommunications System (UMTS) series standards, Point-to-Point (P2P) networks, etc.

[0061] In the example, network interface device 720 may include one or more physical jacks (e.g., Ethernet, coaxial, or telephone jacks) or one or more antennas for connection to communication network 726. In the example, network interface device 720 may include one or more antennas 760 for wireless communication using at least one single-input multiple-output (SIMO), multiple-input multiple-output (MIMO), or multiple-input single-output (MISO) technology. In some examples, network interface device 720 may use multi-user MIMO technology for wireless communication. The term "transmission medium" should be understood to include any intangible medium capable of storing, encoding, or carrying instructions for execution by machine 700, and includes digital or analog communication signals and other intangible media to facilitate communication of such software.

[0062] The examples described herein may include logic or multiple components, modules, or mechanisms, or operations based on these. A module is a tangible entity (e.g., hardware) capable of performing a specified operation and may be configured or arranged in a particular manner. In the examples, circuitry may be arranged in a specified manner (e.g., internally or involving external entities, such as other circuitry) as a module. In the examples, all or part of one or more computer systems (e.g., stand-alone, client, or server computer systems), or one or more hardware processors, may be configured by firmware or software (e.g., instructions, application portions, or applications) to operate to perform a specified operation. In the examples, the software may reside on a machine-readable medium. In the examples, the software causes the hardware to perform the specified operation when executed by the underlying hardware of the module.

[0063] Therefore, the term "module" is understood to encompass tangible entities that are physically constructed, specifically configured (e.g., hardwired), or temporarily (e.g., programmable) to operate or perform some, all, or any of the operations described herein in a specified manner. Consider the example of modules being temporarily configured, where each module does not need to be instantiated at any particular time. For example, in the case where modules include general-purpose hardware processors configured using software, the general-purpose hardware processors can be configured as correspondingly different modules at different times. The software can accordingly configure the hardware processors, for example, to constitute a particular module at one time and a different module at another time.

[0064] Some embodiments may be implemented wholly or partially in software and / or firmware. This software and / or firmware may take the form of instructions contained in or on a non-transitory computer-readable storage medium. These instructions may then be read and executed by one or more processors to cause the operations described herein to be performed. The instructions may take any suitable form, such as, but not limited to, source code, compiled code, interpreted code, executable code, static code, dynamic code, etc. Such computer-readable media may include any tangible non-transitory medium for storing information in a form readable by one or more computers, such as, but not limited to, read-only memory (ROM), random access memory (RAM), disk storage media, optical storage media, flash memory, etc.

[0065] The above detailed description includes references to the accompanying drawings, which form part of the detailed description. The drawings illustrate specific embodiments that can be implemented by way of example. These embodiments are also referred to herein as "examples". Such examples may include elements other than those shown or described. However, examples that include elements shown or described are also contemplated. Furthermore, examples using any combination or arrangement of those elements (or one or more aspects thereof) shown or described are contemplated, whether for a particular example (or one or more aspects thereof) or for other examples (or one or more aspects thereof) shown or described herein.

[0066] The publications, patents, and patent documents cited herein are incorporated herein as if they were individually incorporated. Where there is any inconsistency between the usage in this document and those incorporated by reference, the usage in the incorporated (or combined) references(s) shall supplement this document; in the event of any inconsistency, the usage in this document shall prevail.

[0067] In this document, as is common in patent literature, the terms “a” or “an” are used to include one or more of a single entity, independent of any other instance or use of “at least one” or “one or more.” In this document, the term “or” is used to indicate non-exclusivity, such that “A or B” includes “A but not B,” “B but not A,” and “A and B,” unless otherwise stated. In the appended claims, the terms “including” and “in which” are used as common English equivalents to the corresponding terms “comprising” and “wherein.” Furthermore, in the claims, the term “comprising” is open-ended, meaning that a system, apparatus, article, or method that includes elements other than those listed following such a term in the claim is still considered to fall within the scope of the claim. Additionally, in the claims, the terms “first,” “second,” “third,” etc., are used merely as labels and are not intended to suggest a numerical order of their objects.

[0068] The embodiments described above can be implemented in various hardware configurations, which may include a processor for executing instructions that perform the described techniques. Such instructions may be contained in a machine-readable medium, such as a suitable storage medium, memory, or other processor-executable medium.

[0069] The embodiments described herein can be implemented in various environments, such as part of a system-on-a-chip, a set of intercommunicating functional blocks, etc., but the scope of this disclosure is not limited thereto.

[0070] The described implementation of the subject matter may include one or more features, individually or in combination, as illustrated below by example.

[0071] Example 1 is an apparatus comprising: a PMOS transistor including a drain terminal coupled to a first end of an encryption circuit; an NMOS transistor including a drain terminal coupled to the source end of the PMOS transistor; and a first capacitor including a first end and a second end, the first end of the first capacitor being coupled to the source end of the PMOS transistor; and the second end of the first capacitor being coupled to a second end of the encryption circuit.

[0072] In Example 2, the subject of Example 1 includes a PMOS transistor whose gate is coupled to the gate of an NMOS transistor.

[0073] In Example 3, the subject of Example 2 includes the source of an NMOS transistor coupled to ground.

[0074] In Example 4, the subject of Example 3 includes: a control circuit, including an input and an output, the input of which is coupled to the gate of a PMOS transistor.

[0075] In Example 5, the subject of Example 4 includes: a second capacitor, comprising a first terminal and a second terminal, the first terminal of the second capacitor being coupled to the input terminal of the control circuit.

[0076] In Example 6, the subject of Example 5 includes a second terminal of the second capacitor coupled to a second terminal of the encryption circuit and a second terminal of the first capacitor.

[0077] In Example 7, the subject of Example 6 includes a second terminal of a first capacitor and a second terminal of a second capacitor coupled to an input voltage terminal via a first switching circuit.

[0078] In Example 8, the subject of Example 7 includes a second terminal of the first capacitor and a second terminal of the second capacitor coupled to the output voltage terminal via a second switching circuit.

[0079] In Example 9, the subject of Example 8 includes: a third capacitor, comprising a first terminal and a second terminal, wherein the second terminal of the first capacitor and the second terminal of the second capacitor are coupled to the first terminal of the third capacitor.

[0080] In Example 10, the subject of Example 9 includes: one or more additional capacitors coupled to the second end of a third capacitor.

[0081] In Example 11, the subject matter of Examples 5-10 includes: a system-on-a-chip (SoC) that includes an integrated circuit (IC) that includes at least two of the following: an NMOS transistor, a PMOS transistor, a first capacitor, a second capacitor, or control circuitry.

[0082] In Example 12, the subject of Example 11 includes that the SoC further includes at least one connector, and that the at least one connector conforms to at least one of the following: Universal Serial Bus (USB), High-Definition Multimedia Interface (HDMI), Thunderbolt, Peripheral Component Interconnect Express (PCIe), or Ethernet specification.

[0083] Example 13 is an apparatus comprising: a push-pull regulation loop (PPRL) including a PMOS transistor, an NMOS transistor, and a first plurality of capacitors; an input and an output coupled to the PPRL via the first plurality of capacitors; and a plurality of flying capacitor (FC) circuits including a second plurality of capacitors, the plurality of FC circuits being coupled to each other and to a rail between the input and the output, wherein the FC circuits of the plurality of FC circuits further include at least a first transistor switch and a second transistor switch, the first transistor switch and the second transistor switch being coupled to corresponding capacitors in the second plurality of capacitors.

[0084] In Example 14, the subject of Example 13 includes: a third transistor switch coupled between the input and the node of the PPRL; and a fourth transistor switch coupled between the node of the PPRL and the output.

[0085] In Example 15, the subject of Example 14 includes a first transistor switch associated with a first plurality of transistor switches corresponding to a plurality of FC circuits, and a second transistor switch associated with a second plurality of transistor switches corresponding to a plurality of FC circuits.

[0086] In Example 16, the subject of Example 15 includes: a controller circuit that, based on activating a third transistor switch and a first plurality of transistor switches and deactivating a fourth transistor switch and a second plurality of transistor switches, charges one or more of the second plurality of capacitors.

[0087] In Example 17, the subject of Example 16 includes a controller circuit based on deactivating a third transistor switch and a first plurality of transistor switches and activating a fourth transistor switch and a second plurality of transistor switches, such that the charge of one or more of the second plurality of capacitors is transferred to the output.

[0088] In Example 18, the subject of Example 17 includes a controller circuit that activates a first plurality of transistor switches and deactivates a third transistor switch, a fourth transistor switch, and a second plurality of transistor switches, such that the voltage at the node of PPRL is reset.

[0089] In Example 19, the subject of Examples 13-18 includes an FC of a first FC circuit in a plurality of FC circuits coupled to a rail, and one or more FCs in a subset of the plurality of FCs being coupled in series with each other and coupled to the FC in the first FC circuit.

[0090] Example 20 is a process for manufacturing a voltage regulator, comprising: coupling a PMOS transistor, an NMOS transistor, a controller circuit, and a first plurality of capacitors to form a push-pull regulation loop (PPRL); coupling the PPRL to an input and an output via the first plurality of capacitors; coupling a plurality of flying capacitors (FC) and a plurality of transistor switches to form a plurality of FC circuits; coupling one of the plurality of FC circuits to the input, the output, and the first plurality of capacitors; and coupling a subset of the plurality of FC circuits to the FC circuit.

[0091] Example 21 is at least one machine-readable medium including instructions that, when executed by processing circuitry, cause the processing circuitry to perform an operation to implement any one of Examples 1-20.

[0092] Example 22 is an apparatus that includes means for implementing any one of Examples 1-20.

[0093] Example 23 is a system that implements any one of Examples 1-20.

[0094] Example 24 is a method for implementing any one of Examples 1-20.

[0095] The above description is intended to be illustrative and not restrictive. For example, the above examples (or one or more aspects thereof) may be used in combination with other examples. For example, those skilled in the art may use other embodiments after reading the above description. The abstract is provided to allow the reader to quickly determine the nature of the technical disclosure. The abstract is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims. Furthermore, in the above detailed description, various features may be grouped to simplify the disclosure. However, the claims may not set forth every feature disclosed herein, as embodiments may include a subset of said features. In addition, embodiments may include fewer features than disclosed in a particular example. Therefore, the claims are incorporated into the detailed description, and the claims themselves are independent embodiments. The scope of the embodiments disclosed herein is determined by the appended claims, and by the full scope of their equivalents.

Claims

1. An apparatus comprising: A PMOS transistor, including a drain terminal coupled to the first end of the encryption circuit; An NMOS transistor, including a drain terminal coupled to the source terminal of the PMOS transistor; as well as A first capacitor includes a first terminal and a second terminal, the first terminal of the first capacitor being coupled to the source terminal of the PMOS transistor; and the second terminal of the first capacitor being coupled to the second terminal of the encryption circuit.

2. The apparatus according to claim 1, wherein, The gate of the PMOS transistor is coupled to the gate of the NMOS transistor.

3. The apparatus according to claim 2, wherein, The source of the NMOS transistor is coupled to the ground terminal.

4. The apparatus according to claim 3, further comprising: The control circuit includes an input terminal and an output terminal, wherein the input terminal of the control circuit is coupled to the gate of the PMOS transistor.

5. The apparatus according to claim 4, further comprising: The second capacitor includes a first terminal and a second terminal, with the first terminal of the second capacitor coupled to the input terminal of the control circuit.

6. The apparatus according to claim 5, wherein, The second terminal of the second capacitor is coupled to the second terminal of the encryption circuit and the second terminal of the first capacitor.

7. The apparatus according to claim 6, wherein, The second terminal of the first capacitor and the second terminal of the second capacitor are coupled to the input voltage terminal via the first switching circuit.

8. The apparatus according to claim 7, wherein, The second terminal of the first capacitor and the second terminal of the second capacitor are coupled to the output voltage terminal via the second switching circuit.

9. The apparatus according to claim 8, further comprising: The third capacitor includes a first terminal and a second terminal, wherein the second terminal of the first capacitor and the second terminal of the second capacitor are coupled to the first terminal of the third capacitor.

10. The apparatus according to claim 9, further comprising: One or more additional capacitors are coupled to the second terminal of the third capacitor.

11. The apparatus according to claim 5, further comprising: A system-on-a-chip (SoC) includes an integrated circuit (IC) that includes at least two of the following: the NMOS transistor, the PMOS transistor, the first capacitor, the second capacitor, and the control circuitry.

12. The apparatus according to claim 11, wherein, The SoC also includes at least one connector, wherein the at least one connector conforms to at least one of the following: Universal Serial Bus (USB) specification, High Definition Multimedia Interface (HDMI) specification, Thunderbolt specification, Peripheral Component Interconnect Fast (PCIe) specification, or Ethernet specification.

13. An apparatus comprising: The push-pull regulation loop (PPRL) includes a PMOS transistor, an NMOS transistor, and a first plurality of capacitors; The input terminal and the output terminal are coupled to the PPRL via the first plurality of capacitors; as well as Multiple flying capacitor (FC) circuits, including a second plurality of capacitors, the multiple FC circuits being coupled to each other and to a rail between the input and the output, the multiple FC circuits further including at least a first transistor switch and a second transistor switch, the first transistor switch and the second transistor switch being coupled to corresponding capacitors in the second plurality of capacitors.

14. The apparatus of claim 13, further comprising: A third transistor switch is coupled between the input terminal and the node of the PPRL; as well as A fourth transistor switch is coupled between the node of the PPRL and the output terminal.

15. The apparatus according to claim 14, wherein, The first transistor switch is associated with a first plurality of transistor switches corresponding to the plurality of FC circuits, and wherein the second transistor switch is associated with a second plurality of transistor switches corresponding to the plurality of FC circuits.

16. The apparatus of claim 15, further comprising: A controller circuit that charges one or more of the second plurality of capacitors by activating the third transistor switch and the first plurality of transistor switches and deactivating the fourth transistor switch and the second plurality of transistor switches.

17. The apparatus according to claim 16, wherein, The controller circuit is based on deactivating the third transistor switch and the first plurality of transistor switches and activating the fourth transistor switch and the second plurality of transistor switches, so that the charge of one or more of the second plurality of capacitors is transferred to the output terminal, and The controller circuit is based on activating the first plurality of transistor switches and deactivating the third transistor switch, the fourth transistor switch, and the second plurality of transistor switches, thereby resetting the voltage at the node of the PPRL.

18. The apparatus according to any one of claims 13-17, wherein, The FC of the first FC circuit in the plurality of FC circuits is coupled to the rail, and wherein one or more FCs in a subset of the plurality of FC circuits are coupled in series with each other and coupled to the FC in the first FC circuit.

19. A method for manufacturing a voltage regulator, comprising: The PMOS transistor, NMOS transistor, controller circuit, and a plurality of capacitors are coupled to form a push-pull regulation loop (PPRL). The PPRL is coupled to the input and output terminals via the first plurality of capacitors; Multiple flying capacitors (FC) and multiple transistor switches are coupled together to form multiple FC circuits; One of the plurality of FC circuits is coupled to the input terminal, the output terminal, and the plurality of capacitors; as well as A subset of the plurality of FC circuits is coupled to the FC circuit.

20. The method of claim 19, further comprising: The third transistor switch is coupled between the input terminal and the node of the PPRL.

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