Processor fault detection method and device, electronic equipment and readable medium

Abstract

This invention provides a processor fault detection method, apparatus, electronic device, and readable medium, relating to the field of computer technology. The method determines the error frequency of the memory modules managed by the memory controller by periodically extracting the ECC error count value corresponding to the memory controller. If the error frequency indicates a fault risk in the memory module, the fault risk level of the memory module is further determined based on the ECC error type value corresponding to the memory controller. Finally, fault description information is generated for the memory module based on the fault risk level, and a fault warning is provided based on the fault description information. This improves operational efficiency and device reliability.

Description

Technical Field

[0001] This invention relates to the field of computer technology, and in particular to a method, apparatus, electronic device, and readable medium for detecting processor faults. Background Technology

[0002] In the current processor architecture, the memory controller of the main processor core is responsible for reading and writing data to the memory module. The stability of the memory module determines the continuity of business. If a memory module malfunctions and is not detected in time, it may lead to problems such as data corruption, interruption of equipment services, and system crashes.

[0003] In related technologies, maintenance personnel often only become aware of the fault and begin troubleshooting when the memory module malfunctions and causes the device to malfunction, resulting in reduced device reliability and low maintenance efficiency. Summary of the Invention

[0004] This invention provides a processor fault detection method, apparatus, electronic device, and readable medium, which can solve the problems of reduced device reliability and low maintenance efficiency.

[0005] To address the aforementioned problems, this invention discloses a fault detection method for a processor, applied to a coprocessor core, the method comprising: The number of ECC errors corresponding to the memory controller is periodically extracted to determine the error frequency of the memory modules managed by the memory controller. When the error frequency indicates that the memory module has a failure risk, the failure risk level of the memory module is determined based on the ECC error type value corresponding to the memory controller. Based on the fault risk level, fault description information is generated for the memory module, and fault prompts are given based on the fault description information.

[0006] On the other hand, embodiments of the present invention disclose a fault detection device applied to a coprocessor core in a processor, the device comprising: The first determining module is used to periodically extract the number of ECC errors corresponding to the memory controller and determine the error frequency of the memory modules managed by the memory controller. The second determining module is used to determine the failure risk level of the memory module based on the ECC error type value corresponding to the memory controller when the error frequency indicates that the memory module has a failure risk. The prompting module is used to generate fault description information for the memory module based on the fault risk level, and to provide fault prompts based on the fault description information.

[0007] In another aspect, embodiments of the present invention disclose an electronic device, including: a processor, a memory, a communication interface, and a communication bus, wherein the processor, the memory, and the communication interface communicate with each other through the communication bus; the memory is used to store at least one executable instruction, the executable instruction causing the processor to execute the aforementioned method.

[0008] This invention also discloses a machine-readable medium storing instructions that, when executed by one or more processors, cause the processors to perform the methods described above.

[0009] The embodiments of this invention offer the following advantages: By periodically extracting the number of ECC errors corresponding to the memory controller, the error frequency of the memory modules managed by the memory controller is determined. When the error frequency indicates a potential failure risk in the memory module, the failure risk level of the memory module is further determined based on the ECC error type value corresponding to the memory controller. Finally, fault description information is generated for the memory module based on the fault risk level, and fault alerts are provided based on the fault description information. In this way, before a serious anomaly in the memory module causes the device to malfunction, the failure risk is periodically detected based on ECC error data, and fault alerts are provided. This allows maintenance personnel to promptly perform targeted repairs on the memory module in case of anomalies, thereby improving maintenance efficiency. Furthermore, it reduces the probability of memory failures causing the device to malfunction, improving the reliability of the device. Attached Figure Description

[0010] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the description of the embodiments of the present invention will be briefly introduced below.

[0011] Figure 1 This is a flowchart of the steps of a processor fault detection method provided in an embodiment of the present invention; Figure 2 This is a schematic diagram of a hardware architecture provided in an embodiment of the present invention; Figure 3 This is a block diagram of a fault detection device provided in an embodiment of the present invention; Figure 4 This is a schematic diagram of the structure of an electronic device provided in an embodiment of the present invention. Detailed Implementation

[0012] The technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention.

[0013] First, an application scenario related to an embodiment of the present invention will be described. The processor fault detection method provided in this embodiment can be applied to a processor in a motherboard. The processor includes a main processor core and a memory controller. The main processor core performs read and write operations on data in the memory module through the memory controller. In related technologies, the memory controller uses Error Checking and Correcting (ECC) technology to collect ECC error data, but lacks a fault detection and warning mechanism for the memory module managed by the memory controller, making it difficult for maintenance personnel to predict memory fault risks in advance. ECC technology is a technique for identifying and correcting memory errors. ECC technology achieves error detection and correction by adding extra parity bits to the memory data. When data is written, a parity bit is calculated and stored for the data. When data is read, the corresponding parity bit is recalculated and compared with the stored parity bit. If the stored parity bit is inconsistent with the recalculated parity bit, the error bit in the data is identified based on the difference in the parity bit, and the identified single-bit error is corrected. Accordingly, the memory controller records ECC error data through registers.

[0014] In related technologies, maintenance personnel only become aware of the fault and begin troubleshooting each component when a serious anomaly in the memory module causes the device to malfunction. Only after the memory module is identified do they manually obtain ECC error data for fault analysis. This approach results in lengthy fault analysis, low maintenance efficiency, and the limitation of maintenance conditions due to the device's inability to operate normally, ultimately leading to lower device reliability.

[0015] Therefore, this invention provides a method for detecting processor faults, which will be described in detail below.

[0016] Figure 1 This is a flowchart illustrating the steps of a processor fault detection method provided in an embodiment of the present invention, applied to a coprocessor core, such as... Figure 1 As shown, the fault detection method for this processor may include the following steps: Step 101: Periodically extract the number of ECC errors corresponding to the memory controller to determine the error frequency of the memory modules managed by the memory controller.

[0017] Step 102: When the error frequency indicates that the memory module has a failure risk, determine the failure risk level of the memory module based on the ECC error type value corresponding to the memory controller.

[0018] Step 103: Generate fault description information for the memory module based on the fault risk level, and provide fault prompts based on the fault description information.

[0019] In one application scenario, this fault detection method can be applied to processors on the Loongson platform. Currently, the Loongson platform, as an independently controllable RISC instruction set architecture platform, integrates a 132-core lightweight auxiliary processing unit as a coprocessor core. Accordingly, in this scenario, the coprocessor core can be this 132-core. The specific processor model of the 132-core is not limited.

[0020] The number of ECC errors is stored in the ECC error count register, and the ECC error type is stored in the ECC error type register. These registers are used by the memory controller to store ECC errors. The ECC error count is the value of the ECC error count register, and the ECC error type is the value of the ECC error type register. The ECC error count represents the number of ECC errors occurring in the managed memory modules as counted by the memory controller, and the ECC error type represents the type of ECC error that occurred. Furthermore, the error frequency of the memory module can be determined based on the ECC error count. The error frequency of the memory module represents its error occurrence rate; a higher error frequency indicates a higher error occurrence rate.

[0021] There can be multiple memory controllers, and different memory controllers can manage different memory modules. The specific memory modules managed by a memory controller can be predefined, and this embodiment of the invention does not impose any restrictions on this. The memory controller can be the memory controller of the main processor core. In practical applications, electronic devices can have multiple main processor cores, and one main processor core can have multiple memory controllers. One memory controller can manage one memory module. If the error frequency is greater than a preset error frequency threshold, the memory module is considered to have a failure risk.

[0022] Of course, multiple memory modules can be managed. When multiple memory modules are managed, the value of the ECC error count register corresponding to the memory controller represents the number of ECC errors occurring in these multiple memory modules. Accordingly, if the error frequency exceeds a preset error frequency threshold, these multiple memory modules are considered to be at risk of failure.

[0023] For any memory controller, the coprocessor core can identify the memory modules managed by the memory controller according to the fault detection method of the processor described above, identify whether there is a fault risk in the memory module, and provide a fault prompt if there is a fault risk.

[0024] Since error frequency can characterize the failure risk of a memory module, specifically, a higher error frequency indicates lower reliability and a higher failure risk; conversely, a lower error frequency indicates higher reliability and a lower failure risk. Therefore, the existence of a memory module failure risk can be assessed based on error frequency. In cases of failure risk, a failure risk level is determined for the memory module according to the ECC error type value (i.e., the ECC error type represented by the ECC error type value), allowing users to easily understand the current degree of abnormality of the memory module. A higher failure risk level indicates a higher degree of abnormality of the memory module. Furthermore, fault description information is generated for the memory module based on the failure risk level, and fault prompts are provided based on this information. The fault description information characterizes the current failure status of the memory module.

[0025] In summary, the processor fault detection method provided in this embodiment of the invention determines the error frequency of the memory modules managed by the memory controller by periodically extracting the ECC error count value corresponding to the memory controller. When the error frequency indicates a fault risk in the memory module, the fault risk level of the memory module is further determined based on the ECC error type value corresponding to the memory controller. Finally, fault description information is generated for the memory module based on the fault risk level, and fault prompts are provided based on the fault description information. In this way, before a serious anomaly occurs in the memory module causing the device to malfunction, the fault risk is periodically detected based on ECC error data, and fault prompts are provided. This allows maintenance personnel to promptly perform targeted repairs on the memory module in case of anomalies, thereby improving maintenance efficiency. Furthermore, it reduces the probability of memory faults causing the device to malfunction, improving the reliability of the device.

[0026] Optionally, in this embodiment of the invention, the step of determining the error frequency of the memory module managed by the memory controller may specifically include: Step 1011: According to the preset detection cycle, the value of the first error count register is obtained in real time as the first count, and the value of the second error count register is obtained as the second count; the first error count register is used to record the cumulative value of the detected ECC correctable errors, and the second error count register is used to record the cumulative value of the ECC errors detected consecutively at the same physical address.

[0027] Step 1012: Calculate the ratios of the first quantity and the second quantity to the total recording time, respectively, to obtain the first error frequency and the second error frequency.

[0028] The embodiments of the present invention may further include: Step S21: If the first error frequency is greater than the first frequency threshold and the second error frequency is greater than the second frequency threshold, then the error frequency is determined to indicate that the memory module has a corresponding fault risk.

[0029] In this embodiment of the invention, the ECC error count register, the ECC error type register, and the ECC error address register are all registers in the memory controller used to record ECC error data. They can be collectively referred to as memory controller error status observation registers, and each memory controller has these registers.

[0030] Specifically, the ECC error count register can include a first error count register and a second error count register. The first error count register serves as a cumulative counter for correctable ECC errors, while the second error count register serves as a counter for consecutive ECC errors at the same physical address. Specifically, the second error count register includes m statistical bits, each occupying 8 bytes. The m statistical bits correspond to the m most recent physical addresses where ECC errors occurred. For any physical address among the m most recent physical addresses where ECC errors occurred, if an ECC error is subsequently detected at that physical address, the value of the corresponding statistical bit is incremented by 1, thus recording the cumulative value of consecutive ECC errors at the same physical address.

[0031] For example, for the physical address where the most recent ECC error occurred, 0x1001, if 5 consecutive ECC errors occurred at address 0x1001, then the value of the statistical bit corresponding to the most recent ECC error is 5. Accordingly, the sum of the values ​​represented by the m statistical bits can be used as the second quantity. The value of the first error quantity register is read as the first quantity. The first quantity represents the total number of all ECC errors occurring in the memory modules managed by this memory controller, and the second quantity represents the total number of consecutive ECC errors occurring at the same physical address in the memory modules managed by this memory controller. Under normal circumstances, the first quantity is not less than the second quantity.

[0032] The first error count register can be represented as Mci_ecc_cnt, and the second error count register can be represented as Mci_ecc_cs_cnt. The first count is the value of Mci_ecc_cnt in this memory controller, and the second count is the value of Mci_ecc_cs_cnt in this memory controller. Here, i indicates that this register belongs to the i-th memory controller of the main processor core. For example, taking the 0th memory controller of the main processor core as an example, the first error count register in the 0th memory controller can be denoted as Mc0_ecc_cnt, and the second error count register in the 0th memory controller can be denoted as Mc0_ecc_cs_cnt.

[0033] Furthermore, the error frequency of the memory module can include the aforementioned first error frequency and second error frequency. Since both the first error count register and the second error count register are used to record cumulative values, the first error frequency can be obtained by calculating the ratio of the value of the first error count register (i.e., the first count) to the total recording time; correspondingly, the second error frequency can be obtained by calculating the ratio of the value of the second error count register (i.e., the first count) to the total recording time. The total recording time can be the time elapsed since the memory controller started operating, and the units for the first and second error frequencies can be times per hour. For example, assuming the first error count register stores 100 counts and the total recording time is 10 hours, then the first error frequency is 10 times per hour.

[0034] The preset error frequency thresholds include a first frequency threshold and a second frequency threshold. These thresholds are pre-configured by the developers. For example, the coprocessor core is also connected to the BMC controller of the electronic device, and the configured first and second frequency thresholds can be defined in the coprocessor core through the BMC controller. Accordingly, during comparison, the coprocessor core can read the pre-configured first and second frequency thresholds. The first and second frequency thresholds can be the same or different. The specific values ​​of the first and second frequency thresholds can be set by the developers. In one implementation, the first frequency threshold can be greater than the second frequency threshold. For example, the first frequency threshold can be 50 times / hour, and the second frequency threshold can be 10 times / hour, or the first frequency threshold can be 100 times / hour; this embodiment of the invention does not limit this. Specifically, the error occurrence rate can be compared with the frequency thresholds to determine whether the error frequency indicates a potential failure risk in the memory module. If the first error frequency is greater than the first frequency threshold and the second error frequency is greater than the second frequency threshold, it indicates that the memory module currently has low reliability and a potential failure risk, meaning a failure is imminent or has already occurred. Otherwise, it indicates that the memory module currently has high reliability, and therefore, it can be determined that there is no risk of failure. The process of comparing the error occurrence rate with a frequency threshold to determine whether the error frequency indicates a risk of failure in the memory module can be considered a primary diagnostic process performed by the coprocessor.

[0035] In this embodiment of the invention, the preset detection period may include the interval between each detection, which is the time between the current moment and the last time step 1011 was executed. Once this interval is reached, the process resumes from step 1011 again, thereby achieving periodic real-time detection. The interval can be preset as needed and may be positively correlated with the load rate of the main processor; this embodiment of the invention does not impose any limitations on this. For example, in one implementation, the coprocessor core can dynamically adjust the interval according to the load rate of the main processor to achieve dynamic adaptation between the preset interval and the load rate.

[0036] Specifically, the coprocessor core can obtain the current load rate of the main processor core by reading registers. For example, the main core load register value can be read, for instance, according to a preset read cycle. The main core load register records the current load rate of the main processor core; that is, the main core load register value represents the current load rate. If the current load rate is less than a first load rate threshold, the interval is set to a first duration. If the current load rate is not less than the first load rate threshold and is less than a second load rate threshold, the interval is set to a second duration. If the current load rate is greater than the second load rate threshold, the interval is set to a third duration. The first load rate threshold is less than the second load rate threshold, the first duration is less than the second duration, and the second duration is less than the third duration. The specific values ​​of the first load rate threshold, the second load rate threshold, the first duration, the second duration, and the third duration can be preset by the developers. For example, the first load rate threshold can be 50%, the second load rate threshold can be 80%, the first duration can be 100μs, the second duration can be 200μs, and the third duration can be 500μs. This embodiment of the invention does not impose limitations on these values. The first load rate threshold, the second load rate threshold, the first duration, the second duration, and the third duration can be stored locally on the coprocessor core, for example, in the parameter list of the coprocessor core. Accordingly, the coprocessor core can read the first load rate threshold, the second load rate threshold, the first duration, the second duration, and the third duration from this parameter list. In this embodiment of the invention, setting a longer interval duration when the current load rate of the main processor core is higher can avoid frequent detection under high load conditions, preventing excessive consumption of processor resources, increasing the load on the main processor core, and thus affecting the normal operation of the main processor core.

[0037] Shorter intervals result in higher execution frequencies and better real-time performance of the processor's fault detection method, but also greater performance degradation of the main processor core. Conversely, longer intervals result in lower execution frequencies and lower real-time performance of the processor's fault detection method, but less performance degradation of the main processor core. In this embodiment of the invention, the interval is dynamically adjusted according to the current load rate of the main processor core, allowing the execution frequency of the processor's fault detection method to match the current load rate. When the current load rate is high, the interval is set to a longer duration; when the current load rate is low, the interval is set to a shorter duration, thereby balancing real-time performance and performance degradation of the main processor core.

[0038] In this embodiment of the invention, according to a preset detection cycle, the value of a first error count register is obtained as a first count, and the value of a second error count register is obtained as a second count. The ratios of the first count and the second count to the total recording time are calculated respectively to obtain the first error frequency and the second error frequency. If the first error frequency is greater than a first frequency threshold and the second error frequency is greater than a second frequency threshold, then the error frequency is determined to indicate a risk of memory module failure. Thus, by comparing the error frequency with the frequency threshold, it is convenient to determine whether the error frequency indicates a risk of memory module failure, which can, to a certain extent, ensure the efficiency of failure risk assessment.

[0039] In this embodiment of the invention, if only the first error frequency is greater than the first frequency threshold, only the second error frequency is greater than the second frequency threshold, or the first error frequency is greater than the first frequency threshold and the second error frequency is greater than the second frequency threshold, it can be determined that the error frequency indicates that the memory module does not have a fault risk. If the next detection cycle is reached, the process returns to step 1011 to continue execution.

[0040] Optionally, in this embodiment of the invention, the step of determining the fault risk level of the memory module may specifically include: Step 1021: If the ECC error type value does not represent a multi-bit error type, the fault risk level is determined to be the first level.

[0041] Step 1022: When the ECC error type value represents a multi-bit error type, the fault risk level is determined to be the second level; the second level is higher than the first level.

[0042] In this embodiment of the invention, after performing the first-level diagnosis (i.e., comparing the error occurrence rate with the frequency threshold to determine whether the error frequency indicates that the memory module has a corresponding fault risk), the above steps 1021 to 1022 can be continued to achieve the second-level diagnosis.

[0043] Specifically, the ECC error type register can be an ECC error check code register, which can be represented as Mci_ecc_code. Taking the memory controller 0 of the main processing core as an example, the ECC error type register in memory controller 0 can be recorded as Mc0_ecc_code. The ECC error type value is the value of the ECC error type register, which is the ECC error check code recorded in the ECC error type register. For example, it can be the check code of the most recently occurred ECC error. Furthermore, the error type corresponding to the ECC error type value can be found from the correspondence between error check codes and error types. The correspondence between error check codes and error types can be pre-stored in the coprocessor core. This correspondence can represent the error check codes for various error types. For example, it can include the error check codes for six types of faults: single-bit error type, multi-bit error type, address parity error type, control information error type, data bus error type, and other types. Among them, single-bit error type indicates that only one bit of data is erroneous during transmission or storage, which can be corrected by the ECC mechanism; multi-bit error type indicates that two or more bits of data are erroneous simultaneously during transmission or storage, which cannot be corrected by the ECC mechanism; address parity error type indicates that the parity information on the memory address bus does not match the address data, which may cause data to be written to the wrong location, but the data itself is not erroneous; control information error type indicates that the control signals or command information related to memory operation are erroneous, but the data itself is not erroneous; data bus error type indicates that the error is caused by the data bus; other types indicate errors for which no specific cause has been identified.

[0044] Since multi-bit errors cannot be corrected by the ECC mechanism and are caused by errors in the data itself, a multi-bit error indicates a high-risk error and can be classified as Level 2. Conversely, a non-multi-bit error indicates a lower risk and can be classified as Level 1. A higher risk level indicates a greater degree of abnormality in the memory module. The representation of Level 1 and Level 2 can be predefined by developers in the coprocessor core using write commands. For example, Level 1 can be a warning (represented as "1") and Level 2 can be severe (represented as "2").

[0045] In this embodiment of the invention, when the ECC error type value does not represent a multi-bit error type, the fault risk level is determined to be a first level. For example, the fault risk level field can be recorded as 1 for the memory module managed by the memory controller; for instance, fault_level = 1. When the ECC error type value represents a multi-bit error type, the fault risk level is determined to be a higher second level. For example, the fault risk level field can be recorded as 2 for the memory module managed by the memory controller; for instance, fault_level = 2. This ensures that the fault risk level of the memory module accurately represents the current degree of abnormality, thereby ensuring accurate fault prompts can be provided to the user subsequently.

[0046] Optionally, the processor in this embodiment of the invention further includes a main processor core, and the embodiment of the invention may further include the following steps: Step S31: Obtain the ECC error address value of the memory controller, and obtain the main core page table of the main processor core.

[0047] Step S32: Based on the main core page table, identify whether the representation address corresponding to the ECC error address value is an active address.

[0048] Accordingly, in specific embodiments of the present invention, step 1022a may be included: when the ECC error type value represents a multi-bit error type and the represented address is an active address, the fault risk level is determined to be the second level.

[0049] In this embodiment of the invention, the secondary diagnostic stage can further incorporate verification based on address activity. Specifically, the ECC error address register can be an ECC error physical address register, which can be represented as Mci_ecc_addr. Taking the memory controller 0 of the main processing core as an example, the ECC error address register in memory controller 0 can be denoted as Mc0_ecc_addr. The ECC error address value is the physical address where the ECC error occurred, recorded in the ECC error address register. For example, it can be the physical address of the most recently occurring ECC error. When updating the ECC error address register, the physical address of the most recently occurring ECC error can be used to overwrite the current value of the ECC error address register.

[0050] It should be noted that the coprocessor core can connect to the memory controller via an internal bus, allowing the coprocessor core to directly and securely access the values ​​of its error status observation registers. The main processor core's co-processor module can grant the coprocessor core only access to the memory controller's registers and page table (read-only access) to avoid impacting main processor core operations. Since the coprocessor core and main processor core use the same instruction set architecture, the coprocessor core can use instructions supported by the instruction set architecture (e.g., the `la_cross_core_ld` instruction) to read the main processor core's memory controller registers or page tables.

[0051] Each memory controller's error status observation register is mapped to a different address. To obtain the value of a specific error status observation register for a memory controller, the value can be obtained by accessing the address corresponding to that register. For example, for the ECC error address register, the value of the ECC error type register can be obtained by accessing the address corresponding to that ECC error address register. Exemplarily, the address to which a register is mapped is related to the memory controller to which that register belongs and the host processor core to which that memory controller belongs. For example, the four registers—the first error count register, the second error count register, the ECC error type register, and the ECC error address register—are pre-allocated with different base addresses. These base addresses can be 0x1fe0_0610, 0x1fe0_0618, 0x1fe0_0620, and 0x1fe0_0628, respectively. For any memory controller managed by any host processor core, the value is determined based on the specific address of the memory controller's error status observation register, the base address of that error status observation register, the controller ID of the memory controller (denoted as mc_id), and the node ID of the host processor core (denoted as node_id). The value of node_id can range from 0 to 255.

[0052] Specifically, the node_id, mc_id, and base address can be combined sequentially from the most significant bit to the least significant bit to obtain the specific address. For example, the specific address of the memory controller's error status observation register can be represented as: base address | mc_id << 16 | node_id << 44. For instance, the specific addresses of the first error count register, the second error count register, the ECC error type register, and the ECC error address register can be represented as: 0x1fe0_0610 | mc_id << 16 | node_id << 44, 0x1fe0_0618 | mc_id << 16 | node_id << 44, 0x1fe0_0620 | mc_id << 16 | node_id << 44, 0x1fe0_0628 | mc_id << 16 | node_id << 44. Specifically, mc_id can be shifted left by 16 bits, node_id can be shifted left by 44 bits, and then the three can be bitwise ORed to obtain the specific address of the error status observation register, which the coprocessor core can then use to read the value of the corresponding register based on these specific addresses.

[0053] The main processor core's page table manages the mapping between virtual memory and physical memory, recording the mapping relationship between the virtual address space and the physical address space. The main processor core dynamically establishes and maintains the page table during system startup and process runtime based on hardware architecture specifications, physical memory layout, and the memory requirements of the currently running process. The page table is stored in main memory. After obtaining the ECC error address value, the virtual address corresponding to the physical address represented by that ECC error address value can be found from this mapping relationship. Next, the access frequency of that virtual address can be obtained. If the access frequency is greater than a preset frequency threshold, the address corresponding to the ECC error address value is determined to be an active address, i.e., a hot data address. If the access frequency is not greater than the preset frequency threshold, it is determined to be an inactive address, i.e., a cold data address. The preset frequency threshold can be pre-set by the developers. For example, developers can pre-write a preset frequency threshold into the parameter list of the coprocessor core for its use. Furthermore, the access frequency of each virtual address can be recorded using performance analysis tools, and the access frequency of that virtual address can be found from the data recorded by the performance analysis tools. Assuming the preset frequency threshold is 100 times / hour, the virtual address corresponding to the physical address represented by the ECC error address value is 0x85654000. Among the access frequencies of each virtual address recorded by the performance analysis tool, 0x85654000 corresponds to an access frequency of 110 times / hour. Therefore, it can be determined that the address represented by the ECC error address value is an active address.

[0054] Furthermore, in the secondary diagnostic process, if the ECC error type value represents a multi-bit error type and the corresponding representation address is an active address, the fault risk level is then determined to be the second level, thereby eliminating the possibility of misjudgment of cold data addresses.

[0055] In this embodiment of the invention, the ECC error address value of the memory controller and the main core page table of the main processor core are obtained. Based on the main core page table, it is determined whether the address corresponding to the ECC error address value is an active address. Only when the ECC error type value represents a multi-bit error type and the corresponding address is an active address is the fault risk level determined to be level two. Thus, by judging the fault risk level through two dimensions—error type and whether it is an active address—the possibility of misjudgment of the fault risk level can be reduced, thereby ensuring the accuracy of the fault risk level.

[0056] Optionally, in this embodiment of the invention, before the step of generating fault description information for the memory module based on the fault risk level, the following steps may also be included: Step S41: Based on the historically collected ECC error count, calculate the error count growth rate per unit time.

[0057] Step S42: If the error rate growth rate is greater than a preset growth rate threshold, increase the fault risk level.

[0058] In this embodiment of the invention, three-level diagnosis is achieved by executing steps S41-S42 described above. Specifically, in one implementation, three-level diagnosis can be performed after two-level diagnosis, i.e., the fault risk level is determined to be level two. In this approach, it is equivalent to using three-level diagnosis to determine whether to raise the fault risk level from level two to a higher level.

[0059] Alternatively, in another implementation, tertiary diagnosis can be performed after completing secondary diagnosis, i.e., determining the fault risk level of the memory module. The fault risk level determined by secondary diagnosis may be level one or level two. In this approach, tertiary diagnosis is equivalent to determining whether to raise the fault risk level from level two to level three, or whether to raise the fault risk level from level one to level two.

[0060] Specifically, the error rate growth rate per unit time can be calculated based on the historically collected value of the first error count register. Fault data within a preset analysis period (i.e., the value of the first error count register) can be saved for subsequent analysis. After analyzing the fault data within the preset analysis period, this fault data can be cleared to save storage resources. The preset analysis period can be set according to actual conditions. For example, a longer preset analysis period can be set when the coprocessor core has high processing power, thus providing sufficient fault data while avoiding excessive analysis burden on the coprocessor core. For example, the preset analysis period can be 72 hours, but this embodiment of the invention does not limit this.

[0061] Accordingly, the value of the first error count register recorded within the previous 72 hours can be obtained. Next, a sliding window algorithm is used to determine the error count growth rate, i.e., to analyze the error growth trend. For example, the historically collected values ​​of the first error count register can be arranged sequentially from oldest to most recent collection time to obtain an error count sequence. Then, a fixed-size time window (e.g., 1 hour) is used, sliding backwards on the error count sequence at preset intervals (e.g., 10 minutes), and calculating the error count growth rate corresponding to each window after each slide. A fixed-size time window is considered a unit of time. Specifically, the difference between the total number of errors in the current window and the total number of errors in the previous window can be calculated, and the ratio of this difference to the total number of errors in the previous window is taken as the error count growth rate corresponding to the current window. The starting time of the previous window is separated from the starting time of the current window by a preset step. If the error count growth rate corresponding to the current window is greater than the preset growth rate threshold, it indicates that the error growth trend is too rapid, the fault is worsening, and the abnormality of the memory module is high. Therefore, the determined fault risk level can be increased by one level. The preset growth rate threshold can be set in advance. For example, the preset growth rate threshold can be 60%, but this embodiment of the invention does not limit it.

[0062] For example, the coprocessor can calculate the sum of the values ​​of the first error count register recorded in the current window within this one hour as the total number of errors in the current window. Assuming the total number of errors in the current window is 300 and the total number of errors in the previous window is 90, the difference between the total number of errors in the current window and the total number of errors in the previous window is 210. Next, the coprocessor can calculate 210 / 300 = 70%, obtaining the error count growth rate corresponding to the current window. Assuming a preset growth rate threshold of 60%, since the error count growth rate of 70% corresponding to the current window is greater than 60%, the fault risk level of the memory module can be increased by one level.

[0063] Suppose there are four fault risk levels: Normal, Warning, Critical, and Fatal. These four levels can be represented using four numerical codes (e.g., 0, 1, 2, 3). The coprocessor core detects the error frequency of the memory modules associated with the memory controller. If the error frequency indicates that the memory module has no fault risk, then the current fault risk level of the memory module is Normal. If the error frequency indicates that the memory module has a fault risk, then the fault risk level of the memory module can be further subdivided, specifically whether it belongs to Warning, Critical, or Fatal.

[0064] In this context, "Warning" represents the first level, "Severe" represents the second level, and "Critical" represents the third level. After executing step 102, if the determined fault risk level is "Warning," then during the third-level diagnosis, if the error rate growth rate exceeds the preset growth rate threshold, the fault risk level of the memory module will be upgraded from "Warning" to "Severe." Specifically, the "Fault Risk Level Field = 1" recorded for the memory module managed by the memory controller can be modified to "Fault Risk Level Field = 2," and the recorded fault_level will be 2. Otherwise, if the error rate growth rate does not exceed the preset growth rate threshold, it will remain unchanged. If the determined fault risk level is "Severe," then during the third-level diagnosis, if the error rate growth rate exceeds the preset growth rate threshold, the fault risk level of the memory module will be upgraded from "Severe" to "Critical." Specifically, the "Fault Risk Level Field = 2" recorded for the memory module managed by the memory controller can be modified to "Fault Risk Level Field = 3," and the recorded fault_level will be 3. Otherwise, if the error growth rate detected through steps S41-S42 is not greater than the preset growth rate threshold, it remains unchanged. It is understood that if the determined fault risk level is the highest level, the level remains unchanged, and steps S41-S42 can be omitted to save processing resources.

[0065] In this embodiment of the invention, before generating fault description information for the memory module based on the fault risk level, the error quantity growth rate per unit time is further calculated based on historically collected ECC error quantity values. If the error quantity growth rate exceeds a preset growth rate threshold, the fault risk level is increased. This multi-level intelligent diagnosis accurately identifies faults, improving fault detection accuracy. Furthermore, further optimizing the fault risk level based on the error quantity growth rate can improve the reliability of the fault risk level to some extent, thereby ensuring the accuracy of the fault description information subsequently generated based on the fault risk level and providing an accurate basis for subsequent fault prompts.

[0066] Optionally, in this embodiment of the invention, the step of generating fault description information for the memory module based on the fault risk level may specifically include: Step 1031: Determine the risk value of the memory module based on the fault risk level.

[0067] Step 1032: Obtain error-related information of the memory module; the error-related information includes at least error address information, error quantity information, and error type information.

[0068] Step 1033: Write the fault risk level, the risk value, the error address information, the error quantity information, and the error type information into a preset information structure template to obtain the fault description information.

[0069] In this embodiment of the invention, the risk value is positively correlated with the fault risk level. The risk value is used to characterize the level of risk of an uncorrectable error (UCE) occurring in the memory module. This risk value can also be called the UCE risk value, and can be represented as risk_value. The higher the UCE risk value, the greater the probability of a UCE occurring; conversely, the lower the UCE risk value, the less likely a UCE will occur. The range of the UCE risk value can be 0~100, or 0~1.0 can be used as the range of the UCE risk value. This embodiment of the invention does not limit this. In one implementation, corresponding risk values ​​can be pre-set for different levels in the correspondence between levels and risk values. The higher the level, the larger the risk value set. Accordingly, the risk value corresponding to the currently determined fault risk level is found by searching the correspondence between levels and risk values, and used as the risk value of the memory module. The risk value is written into a preset information structure template by setting parameters. For example, assuming the risk value is 80, the "risk_value" field in the information structure template can be set to 80 to obtain the fault description information. Alternatively, in another implementation, the judgment can be further combined with the first quantity. For example, the weighted sum of the first quantity and the fault risk level can be used as the risk value of the memory module. The risk value is positively correlated with the fault risk level and the first quantity.

[0070] Furthermore, the error address information can include the error physical address and the faulty memory bank (Bank) address. The error physical address can be represented as `error_addr`, which is the value of `Mci_ecc_addr` obtained in this instance. The coprocessor core can retrieve the value by reading the most recently read `Mci_ecc_addr`. A Bank is a basic storage unit in the memory module, and the faulty Bank address can be represented as `bank_id`. The coprocessor core can look up the corresponding Bank address from the address mapping table of the memory system, using it as the faulty Bank address.

[0071] The error count information can include the first count and the second count mentioned above. The first count can be represented as ecc_cnt, and the second count can be represented as ecc_cs_cnt. The error count information can be obtained by reading the value of the most recently acquired first error count register and the value of the second error count register.

[0072] Error type information can be an error type code, represented as `error_type`. For example, corresponding to the aforementioned six types of faults: single-bit error type, multi-bit error type, address parity error type, control information error type, data bus error type, and other types, the corresponding error type codes can be set in the ECC error check code and error type code correspondence: 0, 1, 2, 3, 4, and 5 respectively. The coprocessor core can obtain the code corresponding to the error type represented by the ECC error type value (i.e., the error check code recorded in the ECC error type register) by looking up this ECC error check code and error type code correspondence, and use it as the error type information.

[0073] It should be noted that error-related information may also include other information, such as memory controller identification information, operating parameter information, and reporting timestamps. Identification information may include the memory controller's controller ID (i.e., the aforementioned `mc_id`) and the node ID of the main processor core to which it belongs (i.e., the aforementioned `node_id`). Operating parameter information may include ambient temperature parameters and operating voltage parameters. The ambient temperature parameter can be represented as `env_temp` and stored in the form of °C × 10. The coprocessor core can read the temperature sensor's detection value (in °C) and multiply it by 10 to obtain the ambient temperature parameter, i.e., amplify the temperature sensor's detection value (in °C) by 10. This facilitates storage; for example, if the temperature sensor's detection value is 25.5 °C, only the integer 255 needs to be stored. The operating voltage parameter can be the detection value of a voltage sensor. The coprocessor core can read the voltage sensor's detection value as the operating voltage parameter, which can be represented as `voltage`, and the unit of the operating voltage parameter can be mV. The coprocessor core communicates with the temperature sensor and voltage sensor via the I2C bus. The reporting timestamp can be the current timestamp when the fault description information is generated. The reporting timestamp can be represented as report_time, and the unit is seconds.

[0074] Furthermore, the preset information structure template can be pre-defined. For example, using fault_level to represent the fault risk level, the preset information structure template can be represented as follows: struct mc_error_report { uint8_t node_id; uint8_t mc_id; uint8_t bank_id; uint32_t ecc_cnt; uint16_t ecc_cs_cnt; uint8_t error_type; uint64_t error_addr; uint8_t fault_level; uint16_t risk_value; uint16_t env_temp; uint16_t voltage; uint32_t report_time; }; In this embodiment of the invention, the risk value of the memory module is determined based on the fault risk level. Error-related information of the memory module is obtained; this information includes at least error address information, error quantity information, and error type information. The fault risk level, risk value, error address information, error quantity information, and error type information are written into a preset information structure template to obtain structured fault description information, which is then used by the coprocessor core to provide fault alerts. By writing multiple pieces of information into the structure template, structured fault description information can be obtained, ensuring the efficiency of fault description information generation to a certain extent. Simultaneously, generating structured fault description information facilitates subsequent automated parsing and analysis, thereby improving subsequent information processing efficiency to some extent. Furthermore, the fault description information carries multiple pieces of information, allowing users to accurately locate the fault.

[0075] Optionally, in this embodiment of the invention, the step of providing fault indication based on the fault description information may specifically include: Step 1034: Send the fault description information to the BMC controller; wherein, the BMC controller is used to generate a fault prompt item based on the fault description information and control the display screen to display the fault prompt item.

[0076] And / or, in step 1035, the color mode corresponding to the fault risk level in the fault description information is taken as the target color mode, and the prompt is output in the target color mode.

[0077] In this embodiment of the invention, a visual display can be achieved on a screen using a BMC controller. The coprocessor core is also connected to a fault indicator light on the electronic device. Accordingly, the fault indicator light can be controlled to operate according to a target color mode to provide fault indication. Specifically, the specific model of the BMC controller can be selected as needed; this embodiment of the invention does not limit this. The processor containing the coprocessor core can connect to the BMC controller via an Intelligent Platform Management Interface (IPMI) Keyboard Controller Style (KCS) interface. The BMC controller has a pre-configured adapter module, which includes a developed receive driver based on the IPMI KCS interface to ensure that the BMC controller can receive and parse fault description information. The coprocessor core can interact with the BMC controller via this interface for data and command exchange.

[0078] The coprocessor core can report generated fault description information to the BMC controller, which analyzes the information to obtain the risk value and reporting timestamp of the received fault description. Based on this risk value and its reporting timestamp, as well as historical risk values ​​and their reporting timestamps, a risk trend curve is generated. The horizontal axis of this curve represents the reporting timestamp corresponding to the risk value, and the vertical axis represents the risk value. This risk trend curve visually displays the trend of risk value changes over time. The BMC controller can store the received fault description information in a designated register (e.g., the Mailbox register), and the generation of the risk trend curve can be implemented by the Web User Interface (WebUI) module.

[0079] Each time a fault description is received, the risk value and reporting timestamp are extracted to form a coordinate value (reporting timestamp, risk value). A linear fit is performed on multiple constructed coordinate values ​​(including the currently generated coordinate value and coordinate values ​​generated based on historical risk values ​​and their reporting timestamps) to obtain the risk trend curve corresponding to the memory module. For example, assuming multiple coordinate values ​​include (08:00, 60), (08:30, 60), (08:35, 65), (08:45, 75), (09:00, 80), and (09:05, 85), these six coordinate values ​​can be input into the curve fitting program in the WebUI module. The output of this program is the risk trend curve. In this example, the fitted risk trend curve can be a gradually rising shape.

[0080] Furthermore, module options representing different memory modules can be pre-created, and these options can be set to a specified style, such as being marked in red or highlighted. Correspondingly, the fault indication item can include the specified style module options and a risk trend curve. Fault indication is achieved by displaying the specified style module options and the risk trend curve. Information from the fault description (e.g., error type, error address, error quantity, etc.) can also be associated with the specified style module options. When the user clicks on a specified style module option, the associated parameters can pop up, allowing the user to easily view fault details. It should be noted that the BMC controller can also record the fault description information in the system event log and supports log export. This allows users to obtain the recorded fault information by exporting the logs, thus facilitating user access.

[0081] When sending fault description information to the BMC controller, an immediate reporting mechanism can be adopted. Specifically, the operation of sending the fault description information to the BMC controller can be performed immediately after the fault description information is generated. Alternatively, the operation of sending the fault description information to the BMC controller can be performed directly if the fault risk level is not lower than a specified level. If the fault risk level is lower than the specified level, reporting can only be performed after the time elapsed since the last reporting operation reaches a preset reporting time threshold. The specified level can be preset. For example, the specified level can be a severity level, meaning warning level faults are reported once every preset reporting time threshold, for example, every 30 minutes. Severe level faults and fatal level faults are reported immediately. This can reduce the reporting frequency to a certain extent, thereby reducing the energy consumption of the processor's fault detection method and achieving efficient reporting.

[0082] Furthermore, after receiving the fault description information, the BMC controller can return a response message. If the coprocessor core does not receive the response message within a preset response time, a retransmission will be performed. The preset response time can be pre-set; for example, it can be 100ms. The maximum number of retransmissions can not exceed a preset threshold (e.g., 3 times). This ensures transmission reliability while avoiding the problem of wasting processing resources through continuous retransmissions.

[0083] Before sending the fault description information, the coprocessor core can also generate a checksum for the fault description information and send it to the BMC controller, for example, by generating a CRC32 checksum. The BMC controller generates a checksum for the fault description information in the same way before generating the fault indication item based on the fault description information.

[0084] For example, taking the Loongson platform as an example, a checksum generation instruction (e.g., crc[c].w.{b / h / w / d}.w instruction) can be used to generate a checksum. If the generated checksum is the same as the received checksum, it is determined that the integrity check has passed, and the operation of generating a fault message item based on the fault description information can be performed; otherwise, the operation of generating a fault message item based on the fault description information is not performed.

[0085] In this embodiment of the invention, fault description information is sent to the BMC controller, which then generates fault prompts based on the fault description information and controls the display screen to show the fault prompts, thus realizing a visual display of faults and making it convenient for users to view.

[0086] In the method of indicating faults via fault indicator lights, the fault indicator light can be a motherboard memory indicator light. This indicator light can support flashing in multiple color modes, with each color mode corresponding to a fault risk level. Accordingly, a correspondence between fault risk levels and color modes can be pre-established and stored in the coprocessor core. For example, the fault indicator light can support green, yellow, and red modes, and can be a tri-color LED. In the correspondence between fault risk levels and color modes, these three color modes correspond to fault risk levels: warning, severe, and fatal. When the fault indicator light is off, it indicates normal operation and no memory module is at risk of failure. When the fault indicator light is flashing green, there is a memory module with a warning fault level; when it is flashing yellow, there is a memory module with a severe fault level; and when it is flashing red, there is a memory module with a fatal fault level.

[0087] The coprocessor core can load a pre-stored mapping between fault risk levels and color modes from its internal storage. It then finds the color mode corresponding to the fault risk level in the fault description information as the target color mode. For example, if the fault risk level in the fault description information is "Warning," the green mode is used as the target color mode, and the fault indicator light flashes green. If the fault risk level is "Severe," the yellow mode is used as the target color mode, and the fault indicator light flashes yellow. If the fault risk level is "Critical," the red mode is used as the target color mode, and the fault indicator light flashes red, thus providing different color modes for different fault risk levels. Furthermore, multiple communication pins (e.g., GPIO pins) are provided between the coprocessor core and the fault indicator light, with each communication pin corresponding to a different color mode. A current-limiting resistor (e.g., a 220Ω resistor) can also be connected in series between the coprocessor core and the fault indicator light to prevent overcurrent and ensure hardware safety.

[0088] Accordingly, the coprocessor core can set the communication pin corresponding to the target color mode to a high level to control the fault indicator light to operate in the target color mode, that is, to flash with the target color light. It should be noted that, in another implementation, the BMC controller and the fault indicator light can also be connected, and the BMC controller can implement the above step 1035 according to the above implementation method. This embodiment of the invention does not limit this.

[0089] In this embodiment of the invention, the color mode corresponding to the fault risk level in the fault description information is further used as the target color mode, and the prompt output is displayed in the target color mode. By using a more intuitive hardware indicator light to provide fault prompts, the probability of attracting user attention is higher, enabling users to perceive the fault prompts in a timely manner and achieving efficient feedback. Furthermore, the hierarchical prompts using different color modes allow users to intuitively distinguish the degree of memory abnormality.

[0090] Optionally, in this embodiment of the invention, the BMC controller is further configured to perform memory isolation on the memory module when the risk value corresponding to the fault description information is not lower than a preset risk value threshold.

[0091] The preset risk threshold can be predefined; for example, it can be 60. If the coprocessor detects that the risk value in the fault description information of a memory module is not lower than the preset risk threshold, it indicates that the memory module is likely to have a UCE fault, and there are signs of a potential UCE fault, which could lead to the device malfunctioning. Therefore, the memory module can be isolated to prevent it from causing the device to malfunction. For example, the BMC controller can proactively cut off the power supply circuit of the memory module when the risk value is not lower than the preset risk threshold to quickly achieve memory isolation; for example, disconnecting the power supply circuit can often be completed within 1μs. Furthermore, an isolation flag can be added to the module options of the memory module, allowing users to easily know that the memory module has been isolated.

[0092] In this embodiment of the invention, by reporting fault description information to the BMC controller, the BMC controller can detect early signs of UCE faults based on the risk values ​​contained therein. Furthermore, if the risk value in the fault description information is not lower than a preset risk value threshold, proactive memory isolation can be performed first to avoid memory faults causing the device to malfunction and reduce the risk of service interruption.

[0093] In this embodiment of the invention, a communication link is established between the coprocessor core and the memory controller and BMC controller of the main processor core. The aforementioned processor fault detection method can be implemented in the form of firmware. This firmware for fault detection can be pre-programmed into the coprocessor core. In practical applications, during the boot process of the main processor core, the main processor core can wake up the coprocessor core through inter-core communication instructions. The coprocessor core automatically loads the pre-programmed detection firmware and initializes the detection parameters (i.e., the pre-set duration, threshold, correspondence, etc. required in the aforementioned processor fault detection method). Since the coprocessor core, memory controller, and BMC controller belong to the same hardware architecture platform, the data transmission success rate between the coprocessor core, memory controller, and BMC controller can be ensured, ensuring that the detection firmware can execute normally.

[0094] In one implementation, the detection firmware can be developed using the C language. The detection firmware may include a real-time detection module, a multi-level intelligent diagnostic module, and a structured fault reporting module. The above-mentioned fault detection method for the processor is implemented by dynamically scheduling these modules.

[0095] Specifically, the coprocessor core can schedule the core function (read_mc_error() function) in the real-time detection module through function calls to accurately obtain the number of ECC errors, the type of ECC errors, and the address of ECC errors. It can also schedule the core function (judge_ecc_error() function) in the multi-level intelligent diagnosis module to identify whether the error occurrence rate indicates a fault risk in the memory module and determine the fault risk level of the memory module. Finally, it can schedule the core function (report_mc_error()) in the structured fault reporting module to generate fault description information for the memory module based on the fault risk level and send the fault description information to the BMC controller.

[0096] In this embodiment of the invention, the fault detection method for the aforementioned processor can be implemented through three core functions. Therefore, the total code size of the detection firmware is relatively small. In one implementation, the total code size does not exceed 6KB, which better adapts to scenarios where coprocessor cores have resource constraints. Furthermore, due to the small total code size, the memory occupied and power consumption increase during the execution of the detection firmware are relatively small. For example, in one implementation scenario, the memory occupied by the detection firmware is ≤256KB, the power consumption increase is ≤4%, and the main processor core performance loss is <3%, achieving lightweight and low-interference detection, which can adapt to the needs of scenarios such as server, industrial control terminal, and embedded gateway deployment.

[0097] Figure 2This is a schematic diagram of a hardware architecture provided by an embodiment of the present invention. The architecture includes a coprocessor core, a memory controller, a BMC controller, a temperature sensor, a voltage sensor, and a fault indicator light. The coprocessor core can obtain ECC error data from the error status observation register of the memory controller. Based on the ECC error data, fault description information is generated. During the generation of the fault description information, the detection values ​​of the temperature sensor and voltage sensor can be obtained to determine the required operating parameter information. The fault description information is reported to the BMC controller, which then performs visual fault display based on the fault description information and controls the fault indicator light to provide fault prompts.

[0098] In this embodiment of the invention, for a scenario where the processor includes a coprocessor core and the memory controller has a dedicated register for recording ECC error data, the invention focuses on the ECC error data recorded in the memory controller register, actively collects ECC error data, and proactively diagnoses and provides feedback (i.e., provides fault alerts) to the memory module. This achieves integrated end-to-end memory fault handling, forming a closed-loop processing mechanism. It is deeply compatible with coprocessor core + dedicated register architecture designs, filling the technical gap of lacking fault data collection, diagnosis, and feedback mechanisms, and solving the problem of platforms lacking memory fault monitoring mechanisms. Simultaneously, fault alerts based on fault description information allow users to perceive memory anomalies in advance, predict memory fault risks, and promptly identify memory anomalies for direct memory maintenance, thereby significantly shortening fault handling time and preventing fault escalation.

[0099] Reference Figure 3 This diagram illustrates a block diagram of a processor fault detection device provided in an embodiment of the present invention, applied to a coprocessor core, such as... Figure 3 As shown, the fault detection device may specifically include: The first determining module 201 is used to periodically extract the ECC error count value corresponding to the memory controller and determine the error frequency of the memory module managed by the memory controller. The second determining module 202 is used to determine the failure risk level of the memory module based on the ECC error type value corresponding to the memory controller when the error frequency indicates that the memory module has a failure risk. The prompting module 202 is used to generate fault description information for the memory module based on the fault risk level, and to provide fault prompts based on the fault description information.

[0100] Optionally, the first determining module 201 is specifically used for: According to the preset detection cycle, the value of the first error count register is obtained in real time as the first count, and the value of the second error count register is obtained as the second count; the first error count register is used to record the cumulative value of the detected ECC correctable errors, and the second error count register is used to record the cumulative value of the ECC errors detected consecutively at the same physical address; Calculate the ratios of the first quantity and the second quantity to the total recording time to obtain the first error frequency and the second error frequency; The device further includes a third determining module, configured to determine that the error frequency indicates a potential fault risk in the memory module when the first error frequency is greater than a first frequency threshold and the second error frequency is greater than a second frequency threshold.

[0101] Optionally, the second determining module 202 is specifically used for: If the ECC error type value does not represent a multi-bit error type, the fault risk level is determined to be the first level; When the ECC error type value represents a multi-bit error type, the fault risk level is determined to be the second level; the second level is higher than the first level.

[0102] Optionally, the device further includes: The acquisition module is used to acquire the ECC error address value of the memory controller and the main core page table of the main processor core; The identification module is used to identify whether the representation address corresponding to the ECC error address value is an active address based on the main core page table; The second determining module 202 is further configured to: determine the fault risk level as the second level when the ECC error type value represents a multi-bit error type and the represented address is an active address.

[0103] Optionally, the device further includes: The calculation module is used to calculate the error growth rate per unit time based on historically collected ECC error counts before the prompting module 203 generates fault description information for the memory module based on the fault risk level. An increase module is used to increase the fault risk level when the error quantity growth rate exceeds a preset growth rate threshold.

[0104] Optionally, the prompting module 203 is specifically used for: Based on the aforementioned fault risk level, the risk value of the memory module is determined; Obtain error-related information of the memory module; the error-related information includes at least error address information, error quantity information, and error type information; The fault risk level, the risk value, the error address information, the error quantity information, and the error type information are written into a preset information structure template to obtain the fault description information.

[0105] Optionally, the prompting module 203 is further used for: The fault description information is sent to the BMC controller; wherein the BMC controller is used to generate a fault prompt item based on the fault description information and control the display screen to display the fault prompt item; And / or, use the color mode corresponding to the fault risk level in the fault description information as the target color mode, and output the prompt in the target color mode.

[0106] Optionally, the BMC controller is further configured to perform memory isolation on the memory module if the risk value corresponding to the fault description information is not lower than a preset risk value threshold.

[0107] In summary, the processor fault detection device provided in this embodiment of the invention determines the error frequency of the memory modules managed by the memory controller by periodically extracting the ECC error count value corresponding to the memory controller. When the error frequency indicates a fault risk in the memory module, the fault risk level of the memory module is further determined based on the ECC error type value corresponding to the memory controller. Finally, fault description information is generated for the memory module based on the fault risk level, and fault prompts are provided based on the fault description information. In this way, before a serious anomaly occurs in the memory module causing the device to malfunction, the fault risk is periodically detected based on ECC error data, and fault prompts are provided. This allows maintenance personnel to promptly perform targeted repairs on the memory module in case of an anomaly, thereby improving maintenance efficiency. Furthermore, it reduces the probability of memory faults causing the device to malfunction, improving the reliability of the device.

[0108] Reference Figure 4 This is a schematic diagram of the structure of the electronic device provided in an embodiment of the present invention. For example... Figure 4 As shown, the electronic device includes: a processor, a memory, a communication interface, and a communication bus.

[0109] The processor, the memory, and the communication interface communicate with each other via the communication bus; the memory stores at least one executable instruction, which causes the processor to execute the fault detection method of the processor in the aforementioned embodiment. The executable instructions can form a program.

[0110] This invention provides a machine-readable medium storing instructions that, when executed by one or more processors, enable the processors to perform the processor fault detection method of the aforementioned embodiments. The machine-readable medium can be one or more.

[0111] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. The same or similar parts between the various embodiments can be referred to each other.

[0112] Those skilled in the art will understand that embodiments of the present invention can be provided as methods, apparatus, or computer program products. Therefore, embodiments of the present invention can take the form of entirely hardware embodiments, entirely software embodiments, or embodiments combining software and hardware aspects. Furthermore, embodiments of the present invention can take the form of computer program products implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0113] It should be noted that all actions involving the acquisition of signals, information, or data in this application are carried out in compliance with the relevant data protection laws and policies of the country where the application is located, and with the authorization granted by the owner of the relevant device.

[0114] Embodiments of the present invention are described with reference to flowchart illustrations and / or block diagrams of methods, terminal devices (systems), and computer program products according to embodiments of the invention. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing terminal device to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing terminal device, generate instructions for implementing the flowchart illustrations and / or block diagrams. Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0115] These computer program instructions may also be stored in a computer-readable storage medium capable of directing a computer or other programmable data processing terminal device to operate in a predictive manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0116] These computer program instructions can also be loaded onto a computer or other programmable data processing terminal equipment, causing a series of operational steps to be performed on the computer or other programmable terminal equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable terminal equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0117] Although preferred embodiments of the present invention have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of the embodiments of the present invention.

[0118] Finally, it should be noted that in this paper, relational terms such as first and second are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations.

[0119] Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or terminal device that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or terminal device. Without further limitation, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or terminal device that includes said element.

[0120] The present invention has provided a detailed description of a processor fault detection method, a fault detection device, an electronic device, and a readable medium. Specific examples have been used to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only for the purpose of helping to understand the method and core ideas of the present invention. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of the present invention. Therefore, the content of this specification should not be construed as a limitation of the present invention.

Claims

1. A method for detecting processor faults, characterized in that, Applied to a coprocessor core, the method includes: The number of ECC errors corresponding to the memory controller is periodically extracted to determine the error frequency of the memory modules managed by the memory controller. When the error frequency indicates that the memory module has a failure risk, the failure risk level of the memory module is determined based on the ECC error type value corresponding to the memory controller. Based on the fault risk level, fault description information is generated for the memory module, and fault prompts are given based on the fault description information.

2. The method according to claim 1, characterized in that, Determining the error frequency of the memory modules managed by the memory controller includes: According to the preset detection cycle, the value of the first error count register is obtained in real time as the first count, and the value of the second error count register is obtained as the second count; the first error count register is used to record the cumulative value of the detected ECC correctable errors, and the second error count register is used to record the cumulative value of the ECC errors detected consecutively at the same physical address; Calculate the ratios of the first quantity and the second quantity to the total recording time to obtain the first error frequency and the second error frequency; The method further includes: if the first error frequency is greater than a first frequency threshold and the second error frequency is greater than a second frequency threshold, then the error frequency is determined to indicate that the memory module has a corresponding failure risk.

3. The method according to claim 1, characterized in that, Determining the fault risk level of the memory module includes: If the ECC error type value does not represent a multi-bit error type, the fault risk level is determined to be the first level; When the ECC error type value represents a multi-bit error type, the fault risk level is determined to be the second level; the second level is higher than the first level.

4. The method according to claim 3, characterized in that, The method further includes: Obtain the ECC error address value of the memory controller, and obtain the main core page table of the main processor core; Based on the main core page table, it is determined whether the representation address corresponding to the ECC error address value is an active address; The method further includes: when the ECC error type value represents a multi-bit error type and the represented address is an active address, determining the fault risk level as the second level.

5. The method according to claim 1, characterized in that, Before generating fault description information for the memory module based on the fault risk level, the method further includes: Based on the historically collected ECC error count values, calculate the error count growth rate per unit time. If the error rate growth rate exceeds a preset growth rate threshold, the fault risk level is increased.

6. The method according to claim 1, characterized in that, The process of generating fault description information for the memory module based on the fault risk level includes: Based on the aforementioned fault risk level, the risk value of the memory module is determined; Obtain error-related information of the memory module; the error-related information includes at least error address information, error quantity information, and error type information; The fault risk level, the risk value, the error address information, the error quantity information, and the error type information are written into a preset information structure template to obtain the fault description information.

7. The method according to any one of claims 1-6, characterized in that, The coprocessor core is connected to the BMC controller of the electronic device; Then, the step of providing fault prompts based on the fault description information includes: The fault description information is sent to the BMC controller; wherein the BMC controller is used to generate a fault prompt item based on the fault description information and control the display screen to display the fault prompt item; And / or, use the color mode corresponding to the fault risk level in the fault description information as the target color mode, and output the prompt in the target color mode.

8. The method according to claim 7, characterized in that, The BMC controller is also used to perform memory isolation on the memory module when the risk value corresponding to the fault description information is not lower than a preset risk value threshold.

9. A fault detection device for a processor, characterized in that, The device, applied to a coprocessor core, includes: The first determining module is used to periodically extract the number of ECC errors corresponding to the memory controller and determine the error frequency of the memory modules managed by the memory controller. The second determining module is used to determine the failure risk level of the memory module based on the ECC error type value corresponding to the memory controller when the error frequency indicates that the memory module has a failure risk. The prompting module is used to generate fault description information for the memory module based on the fault risk level, and to provide fault prompts based on the fault description information.

10. An electronic device, characterized in that, include: The processor, memory, communication interface, and communication bus are provided, wherein the processor, memory, and communication interface communicate with each other via the communication bus. The memory is used to store executable instructions that cause the processor to perform the method as described in any one of claims 1 to 8.

11. A machine-readable medium, characterized in that, It stores instructions that, when executed by one or more processors, cause the processors to perform the method as described in any one of claims 1 to 8.

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