Chip soft error rate determination method and device, computer device, storage medium and program product

Abstract

This application relates to a method, apparatus, computer device, storage medium, and program product for determining chip soft error rate. The method includes: determining the target high-energy neutron single-event effect cross section of a single-bit memory cell in the chip under evaluation based on a preset correspondence, the target chip type, and the target process node; determining the high-energy neutron flux in the actual environment where the chip under evaluation is located based on the altitude of the chip in the actual application scenario; determining a first soft error rate of the chip under evaluation induced by high-energy neutrons in the actual environment based on a first product of the high-energy neutron flux, the target high-energy neutron single-event effect cross section, and the total number of single-bit memory cells in the chip under evaluation; determining a second soft error rate of the chip under evaluation induced by thermal neutrons in the actual environment based on the material of the chip under evaluation; and reducing the testing cycle and cost of determining the chip soft error rate of the chip under evaluation based on the first and second soft error rates.

Description

Technical Field

[0001] This application relates to the field of chip technology, and in particular to a method, apparatus, computer equipment, storage medium, and program product for determining chip soft error rate. Background Technology

[0002] For applications with high reliability requirements, such as aviation, communications, power grids, and automotive electronics, neutron-induced chip soft errors are a key issue affecting chip reliability. To ensure the safe and reliable operation of chips under actual atmospheric radiation conditions, it is necessary to assess their soft error rate. Existing methods for assessing chip soft error rates include accelerated irradiation experiments based on ground-based simulated radiation sources.

[0003] In traditional technologies, atmospheric neutrons provided by accelerators, reactors, etc., are used to simulate the process of neutrons incident on chips, test the impact of atmospheric neutrons on chips, and evaluate the soft error rate of chips induced by atmospheric neutrons.

[0004] However, there is currently a problem with the high cost of soft error rate assessment. Summary of the Invention

[0005] Therefore, it is necessary to provide a chip soft error rate determination method, apparatus, computer equipment, storage medium, and program product that can reduce the cost of soft error rate assessment in response to the above-mentioned technical problems.

[0006] Firstly, this application provides a method for determining the soft error rate of a chip, including:

[0007] Based on the preset correspondence, the target chip type and target process node of the chip to be evaluated, the target high-energy neutron single-event effect cross section of the single-bit memory cell in the chip to be evaluated is determined; the preset correspondence includes the correspondence between the chip type, process node, and the high-energy neutron single-event effect cross section of the single-bit memory cell in the chip.

[0008] Based on the altitude of the chip under evaluation in the actual application scenario, determine the high-energy neutron flux in the actual environment where the chip under evaluation is located;

[0009] The first soft error rate of the chip under evaluation induced by high-energy neutrons in a real environment is determined by the first product of the high-energy neutron flux, the single-event effect cross section of the target high-energy neutron, and the total number of single-bit storage cells in the chip under evaluation.

[0010] Based on the material of the chip to be evaluated, determine the second soft error rate of the chip to be evaluated induced by thermal neutrons in a real environment;

[0011] The chip soft error rate of the chip to be evaluated is determined based on the first soft error rate and the second soft error rate.

[0012] In one embodiment, the high-energy neutron flux in the actual environment where the chip to be evaluated is located is determined based on the altitude of the chip in the actual application scenario, including:

[0013] Determine the second product of the first preset coefficient and the altitude;

[0014] Determine the power value with the natural constant as the base and the second product as the exponent;

[0015] The high-energy neutron flux is determined by the third product of the second preset coefficient and the power value.

[0016] In one embodiment, determining the second soft error rate of the chip under evaluation induced by thermal neutrons in a real-world environment, based on the material of the chip under evaluation, includes:

[0017] If the material of the chip to be evaluated meets the preset conditions, the second soft error rate is determined to be zero;

[0018] Among them, meeting the preset conditions includes the chip to be evaluated containing thermal neutron shielding process materials, and / or the chip to be evaluated not containing boron-10 isotope.

[0019] In one embodiment, the method further includes:

[0020] If the material of the chip to be evaluated does not meet the preset conditions, the target thermal neutron single-event effect cross section of the single-bit memory cell is determined according to the target high-energy neutron single-event effect cross section and the first preset multiple.

[0021] The thermal neutron flux in the actual environment is determined based on the high-energy neutron flux and the second preset multiple.

[0022] The second soft error rate is determined by the fourth product of thermal neutron flux, the target thermal neutron single-event effect cross section, and the total number.

[0023] In one embodiment, the second soft error rate is determined based on a fourth product of the thermal neutron flux, the target thermal neutron single-event effect cross section, and the total number of neutrons, including:

[0024] The fourth product is determined to be the second soft error rate.

[0025] In one embodiment, determining the chip soft error rate of the chip to be evaluated based on a first soft error rate and a second soft error rate includes:

[0026] The sum of the first soft error rate and the second soft error rate is determined as the chip soft error rate of the chip to be evaluated.

[0027] Secondly, this application also provides a chip soft error rate determination device, the device comprising:

[0028] The first determining module is used to determine the target high-energy neutron single-event effect cross section of a single-bit memory cell in the chip to be evaluated based on a preset correspondence, the target chip type and the target process node of the chip to be evaluated; the preset correspondence includes the correspondence between the chip type, the process node and the high-energy neutron single-event effect cross section of a single-bit memory cell in the chip;

[0029] The second determining module is used to determine the high-energy neutron flux in the actual environment where the chip to be evaluated is located, based on the altitude of the chip in the actual application scenario.

[0030] The third determining module is used to determine the first soft error rate of the chip to be evaluated induced by high-energy neutrons in the actual environment based on the first product of the high-energy neutron flux, the target high-energy neutron single-event effect cross section, and the total number of single-bit storage units in the chip to be evaluated.

[0031] The fourth determination module is used to determine the second soft error rate of the chip under evaluation induced by thermal neutrons in a real environment, based on the material of the chip under evaluation.

[0032] The fifth determining module is used to determine the chip soft error rate of the chip to be evaluated based on the first soft error rate and the second soft error rate.

[0033] Thirdly, this application also provides a computer device, including a memory and a processor, wherein the memory stores a computer program, and the processor executes the computer program to implement the steps of any of the above methods.

[0034] Fourthly, this application also provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the steps of any of the above methods.

[0035] Fifthly, this application also provides a computer program product, including a computer program that, when executed by a processor, implements the steps of any of the above methods.

[0036] The aforementioned chip soft error rate determination method, apparatus, computer equipment, storage medium, and program product determine the target high-energy neutron single-event effect cross section of a single-bit memory cell in the chip under evaluation based on a preset correspondence, the target chip type, and the target process node of the chip under evaluation. They then determine the high-energy neutron flux in the actual environment where the chip under evaluation is located, based on the altitude of the chip in the actual application scenario. Finally, they determine the first soft error rate of the chip under evaluation induced by high-energy neutrons in the actual environment, based on the first product of the high-energy neutron flux, the target high-energy neutron single-event effect cross section, and the total number of single-bit memory cells in the chip under evaluation. Based on the material of the chip under evaluation, they determine the second soft error rate of the chip under evaluation induced by thermal neutrons in the actual environment. Finally, they determine the chip soft error rate of the chip under evaluation based on the first and second soft error rates. Traditional technologies require the development of dedicated online single-event effect testing systems for chips and the selection of suitable radiation sources for accelerated irradiation experiments, resulting in long cycles and high costs for soft error rate assessment. In contrast, this embodiment does not require the development of dedicated online single-event effect testing systems for chips, nor does it require the use of ground-based simulated radiation sources such as accelerators or reactors to provide an accelerated irradiation environment, thus reducing the soft error rate testing cycle and cost. Attached Figure Description

[0037] To more clearly illustrate the technical solutions in the embodiments of this application or related technologies, the drawings used in the description of the embodiments of this application or related technologies will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0038] Figure 1 This is a flowchart illustrating a chip soft error rate determination method provided in an embodiment of this application;

[0039] Figure 2 This is a flowchart illustrating a method for determining high-energy neutron flux provided in an embodiment of this application;

[0040] Figure 3 This is a flowchart illustrating a second soft error rate determination method provided in an embodiment of this application;

[0041] Figure 4 This is a schematic diagram of the structure of a chip soft error rate determination device provided in an embodiment of this application;

[0042] Figure 5 This is an internal structural diagram of a computer device in one embodiment. Detailed Implementation

[0043] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0044] It should be noted that the terms "first," "second," etc., used in this application can be used to describe various elements, but these elements are not limited by these terms. These terms are only used to distinguish the first element from the second element. The terms "comprising" and "having," and any variations thereof, used in this application, are intended to cover non-exclusive inclusion. The term "multiple" used in this application refers to two or more. The term "and / or" used in this application refers to one of the embodiments, or any combination of multiple embodiments.

[0045] In one exemplary embodiment, such as Figure 1 As shown, Figure 1 This is a flowchart illustrating a chip soft error rate determination method provided in an embodiment of this application. The method can be applied to computer devices and includes the following steps:

[0046] S101, based on the preset correspondence, the target chip type and target process node of the chip to be evaluated, determine the target high-energy neutron single-event effect cross section of the single-bit memory cell in the chip to be evaluated.

[0047] The pre-defined correspondences include those between chip type, process node, and the high-energy neutron single-event effect cross-section of a single-bit memory cell within the chip. A single-bit memory cell is the smallest basic unit of data storage within a chip, used to store one bit of binary data. A chip is composed of a large number of single-bit memory cells, and the high-energy neutron single-event effect cross-section of a single-bit memory cell characterizes the sensitivity of that individual cell to soft errors induced by atmospheric neutrons, making it a core parameter for evaluating the chip's soft error rate.

[0048] For example, as shown in Table 1 below, Table 1 shows the correspondence between chip type, process node, and high-energy neutron single-event effect cross section of single-bit memory cell in the chip.

[0049] Table 1

[0050]

[0051] The SRAM types can include SRAM, Cache, Register, Flip-flop, SRAM-type FPGA, Latch, and Buffer. There are no specific restrictions on the process node for SRAM chip types, meaning that the high-energy neutron single-event effect cross section of a single bit storage cell can be 1E-13 cm⁻¹ at any process node.2 / bit; DRAM types can include SDRAM, DDR, DDR2; Flash types can include NOR Flash, NAND Flash, EEPROM, NVRAM. 1E-13 indicates 1E-15 indicates And so on, which will not be explained in detail here.

[0052] As shown in Table 1 above, for example, if the target chip type to be evaluated is Flash and the process node is 60~100 nanometers (nm), then according to the correspondence shown in Table 1, the target high-energy neutron single-event effect cross section of a single bit memory cell of the chip to be evaluated can be determined to be 1E-17 square centimeters / bit (cm²). 2 / bit).

[0053] S102, determine the high-energy neutron flux in the actual environment where the chip to be evaluated is located, based on the altitude of the chip in the actual application scenario.

[0054] The actual environment in which the chip under evaluation is located refers to the actual environment in which the chip under evaluation is located in a real-world application scenario. The high-energy neutron flux in the actual environment in which the chip under evaluation is located can be determined using the following formula. :

[0055] (1)

[0056] Where t represents the altitude of the chip being evaluated in the actual application scenario, and e is a natural constant. This is the first preset coefficient. The high-energy neutron flux can also be obtained based on a modified formula of the above formula (1), for example, by using the above... The result obtained by adding or subtracting a first preset value is taken as the high-energy neutron flux in the actual environment of the chip being evaluated. Alternatively, the first preset coefficient in formula (1) can be adjusted. The value of .

[0057] S103, determine the first soft error rate of the chip under evaluation induced by high-energy neutrons in the actual environment based on the first product of the high-energy neutron flux, the target high-energy neutron single-event effect cross section, and the total number of single-bit storage cells in the chip under evaluation.

[0058] The first soft error rate can be equal to the product of the high-energy neutron flux in the actual environment of the chip being evaluated and the high-energy neutron single-event effect cross section of the chip being evaluated. That is, the first soft error rate can be determined based on the following formula (2):

[0059] First soft error rate = × (2)

[0060] in, , This represents the high-energy neutron single-event effect cross section of the chip to be evaluated. The target high-energy neutron single-event effect cross section represents a single-bit memory cell in the chip to be evaluated, and M represents the total number of single-bit memory cells in the chip to be evaluated.

[0061] The first soft error rate of the chip to be evaluated can also be calculated based on a modified formula of the above formula (2), for example, by using... The result obtained by multiplying it by a second preset value is used as the first soft error rate.

[0062] S104, based on the material of the chip to be evaluated, determine the second soft error rate of the chip to be evaluated induced by thermal neutrons in a real environment.

[0063] In one possible implementation, the second soft error rate is determined to be zero if the material of the chip to be evaluated meets preset conditions.

[0064] Among them, meeting the preset conditions includes the chip to be evaluated containing thermal neutron shielding process materials, and / or the chip to be evaluated not containing boron-10 isotope.

[0065] Second soft error rate (3)

[0066] in, This represents the thermal neutron flux in the actual environment in which the chip being evaluated is located. This represents the thermal neutron single-event effect cross section of the chip to be evaluated.

[0067] If the material of the chip to be evaluated meets the preset conditions, it can be determined that the thermal neutron single-event effect cross section of the chip to be evaluated is equal to 0. Then, it can be determined that the second soft error rate is equal to the product of the thermal neutron single-event effect cross section of the chip to be evaluated and the thermal neutron flux in the actual environment in which the chip to be evaluated is located. This product is determined as the second soft error rate.

[0068] If the material of the chip to be evaluated meets the preset conditions, it can be determined that... And because Therefore, the second soft error rate can be determined. .

[0069] S105, determine the chip soft error rate of the chip to be evaluated based on the first soft error rate and the second soft error rate.

[0070] The chip soft error rate of the chip to be evaluated is represented by λ, which can be expressed by the following formula (4):

[0071] (4)

[0072] The chip soft error rate of the chip to be evaluated can also be obtained based on a modified formula of formula (4), for example, by... Multiply by a third preset value to get the first result, then combine the first result with... The sum of these values ​​represents the chip soft error rate of the chip to be evaluated.

[0073] In this embodiment, the target high-energy neutron single-event effect cross section of a single-bit memory cell in the chip to be evaluated is determined based on a preset correspondence, the target chip type, and the target process node of the chip to be evaluated. The high-energy neutron flux in the actual environment where the chip to be evaluated is located is determined based on the altitude of the chip to be evaluated in the actual application scenario. The first soft error rate of the chip to be evaluated induced by high-energy neutrons in the actual environment is determined based on the first product of the high-energy neutron flux, the target high-energy neutron single-event effect cross section, and the total number of single-bit memory cells in the chip to be evaluated. The second soft error rate of the chip to be evaluated induced by thermal neutrons in the actual environment is determined based on the material of the chip to be evaluated. Finally, the chip soft error rate of the chip to be evaluated is determined based on the first soft error rate and the second soft error rate. Traditional technologies require the development of dedicated online single-event effect testing systems for chips and the selection of suitable radiation sources for accelerated irradiation experiments. The high cost of radiation sources leads to long and costly soft error rate assessment cycles. In contrast, this embodiment eliminates the need to develop dedicated online single-event effect testing systems for chips and avoids the need to utilize ground-based simulated radiation sources such as accelerators or reactors to provide an accelerated irradiation environment. This reduces the soft error rate testing cycle and cost.

[0074] In one exemplary embodiment, such as Figure 2 As shown, Figure 2 This is a flowchart illustrating a method for determining high-energy neutron flux provided in an embodiment of this application. Based on the above embodiment, step S102, determining the high-energy neutron flux in the actual environment where the chip to be evaluated is located, according to the altitude of the chip in the actual application scenario, may include the following steps:

[0075] S201, determine the second product of the first preset coefficient and the altitude.

[0076] S202, determine the power value with the natural constant as the base and the second product as the exponent.

[0077] Wherein, the power value is equal to .

[0078] S203, determine the high-energy neutron flux based on the third product of the second preset coefficient and the power value.

[0079] As shown in formula (1) above, the second preset coefficient can be equal to 6.706, and the third product of the second preset coefficient and the power value can be determined as the high-energy neutron flux.

[0080] The first and second preset coefficients mentioned above can be determined based on actual historical test data, which can be the actual high-energy neutron flux measured.

[0081] It should be noted that the high-energy neutron flux can also be calculated based on a modified formula of formula (1).

[0082] In this embodiment, by determining the second product of the first preset coefficient and the altitude, a power value with the natural constant as the base and the second product as the exponent is determined. Based on the third product of the second preset coefficient and the power value, the high-energy neutron flux is determined, which can improve the efficiency of obtaining the high-energy neutron flux.

[0083] In an exemplary embodiment, based on the above embodiments, the determination of the second soft error rate of the chip under evaluation induced by thermal neutrons in a real environment in S104, according to the material of the chip under evaluation, can be achieved in the following way:

[0084] If the material of the chip to be evaluated meets the preset conditions, the second soft error rate is determined to be zero;

[0085] Among them, meeting the preset conditions includes the chip to be evaluated containing thermal neutron shielding process materials, and / or the chip to be evaluated not containing boron-10 isotope.

[0086] The inclusion of thermal neutron shielding materials in the chip under evaluation refers to materials such as boron carbide and cadmium in the chip package.

[0087] In this embodiment, when the material of the chip to be evaluated meets the preset conditions, the second soft error rate is determined to be zero. This realizes the determination of the second soft error rate in combination with the material of the chip to be evaluated, thereby improving the accuracy of the obtained second soft error rate and thus improving the accuracy of the obtained chip soft error rate of the chip to be evaluated.

[0088] In one exemplary embodiment, such as Figure 3 As shown, Figure 3 This is a flowchart illustrating a method for determining a second soft error rate according to an embodiment of this application. Based on the above embodiment, step S104, determining the second soft error rate of the chip under evaluation induced by thermal neutrons in a real-world environment based on the material of the chip under evaluation, may include the following steps:

[0089] S301, if the material of the chip to be evaluated does not meet the preset conditions, determine the target thermal neutron single-event effect cross section of the single-bit memory cell based on the target high-energy neutron single-event effect cross section and the first preset multiple.

[0090] For example, the first preset multiple is equal to 2.42, and the target thermal neutron single-event effect cross section of a single-bit storage cell can be equal to the product of 2.42 and the target high-energy neutron single-event effect cross section.

[0091] Due to the thermal neutron single-event effect cross section of the chip to be evaluated =Target thermal neutron single-event effect cross section of a single-bit storage cell × M, = =Target high-energy neutron single-event effect cross section of a single-bit memory cell in the chip to be evaluated × M, therefore It can be equal to the first preset multiple. For example, it can be equal to 2.42 × .

[0092] S302, determine the thermal neutron flux in the actual environment based on the high-energy neutron flux and the second preset multiple.

[0093] For example, a second preset multiple equals 0.76. The product of the second preset multiple and the high-energy neutron flux can be used as the thermal neutron flux in the actual environment.

[0094] S303, the second soft error rate is determined based on the fourth product between thermal neutron flux, target thermal neutron single-event effect cross section, and total number.

[0095] The product of the target thermal neutron single-event effect cross section and the total number represents the thermal neutron single-event effect cross section of the chip to be evaluated. The product of the thermal neutron flux and the thermal neutron single-event effect cross section of the chip to be evaluated can be used as the second soft error rate.

[0096] Alternatively, the second soft error rate can be determined based on a modified formula of the above formula (3), for example, by using the sum of the fourth product and a fourth preset value as the second soft error rate.

[0097] In this embodiment, when the material of the chip to be evaluated does not meet the preset conditions, the target thermal neutron single-event effect cross section of the single-bit memory cell is determined based on the target high-energy neutron single-event effect cross section and the first preset multiple. The thermal neutron flux in the actual environment is determined based on the high-energy neutron flux and the second preset multiple. Then, the second soft error rate is determined based on the fourth product between the thermal neutron flux, the target thermal neutron single-event effect cross section and the total number. This realizes the determination of the second soft error rate in combination with the material of the chip to be evaluated, improves the accuracy of the obtained second soft error rate, and thus improves the accuracy of the obtained chip soft error rate of the chip to be evaluated.

[0098] In an exemplary embodiment, the above-described S303, which determines the second soft error rate based on the fourth product between the thermal neutron flux, the target thermal neutron single-event effect cross section, and the total number, can be implemented as follows:

[0099] The fourth product is determined to be the second soft error rate.

[0100] In this embodiment, the fourth product can be directly determined as the second soft error rate, thereby improving the efficiency of obtaining the second soft error rate.

[0101] In an exemplary embodiment, the process of determining the chip soft error rate of the chip to be evaluated based on the first soft error rate and the second soft error rate in step S105 above can be implemented in the following way:

[0102] The sum of the first soft error rate and the second soft error rate is determined as the chip soft error rate of the chip to be evaluated.

[0103] In this embodiment, the sum of the first soft error rate and the second soft error rate is directly determined as the chip soft error rate of the chip to be evaluated, thereby improving the efficiency of obtaining the chip soft error rate of the chip to be evaluated.

[0104] It should be understood that although the steps in the flowcharts of the above embodiments are shown sequentially according to the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. Moreover, at least some steps in the flowcharts of the above embodiments may include multiple steps or multiple stages. These steps or stages are not necessarily completed at the same time, but can be executed at different times. The execution order of these steps or stages is not necessarily sequential, but can be performed alternately or in turn with other steps or at least some of the steps or stages in other steps. It is understood that the steps in different embodiments can be freely combined as needed, and all non-contradictory solutions formed by such combinations are within the scope of protection of this application.

[0105] Based on the same inventive concept, this application also provides a chip soft error rate determination apparatus for implementing the chip soft error rate determination method described above. The solution provided by this apparatus is similar to the implementation described in the above method; therefore, the specific limitations in one or more embodiments of the chip soft error rate determination apparatus provided below can be found in the limitations of the chip soft error rate determination method described above, and will not be repeated here.

[0106] In one exemplary embodiment, such as Figure 4 As shown, Figure 4This is a schematic diagram of a chip soft error rate determination device 400 provided in an embodiment of this application. The chip soft error rate determination device 400 includes:

[0107] The first determining module 401 is used to determine the target high-energy neutron single-event effect cross section of a single-bit memory cell in the chip to be evaluated based on a preset correspondence, the target chip type and the target process node of the chip to be evaluated; the preset correspondence includes the correspondence between the chip type, the process node and the high-energy neutron single-event effect cross section of a single-bit memory cell in the chip;

[0108] The second determining module 402 is used to determine the high-energy neutron flux in the actual environment where the chip to be evaluated is located, based on the altitude of the chip in the actual application scenario.

[0109] The third determining module 403 is used to determine the first soft error rate of the chip to be evaluated induced by high-energy neutrons in the actual environment based on the first product of the high-energy neutron flux, the target high-energy neutron single-event effect cross section and the total number of single-bit storage units in the chip to be evaluated.

[0110] The fourth determining module 404 is used to determine the second soft error rate of the chip to be evaluated induced by thermal neutrons in a real environment, based on the material of the chip to be evaluated.

[0111] The fifth determining module 405 is used to determine the chip soft error rate of the chip to be evaluated based on the first soft error rate and the second soft error rate.

[0112] In an exemplary embodiment, the second determining module 402 is specifically used to determine the second product of the first preset coefficient and the altitude; determine the power value with the natural constant as the base and the second product as the exponent; and determine the high-energy neutron flux based on the third product of the second preset coefficient and the power value.

[0113] In an exemplary embodiment, the fourth determining module 404 is specifically used to determine that the second soft error rate is zero when the material of the chip to be evaluated meets preset conditions; wherein, meeting the preset conditions includes that the chip to be evaluated contains thermal neutron shielding process material, and / or that the chip to be evaluated does not contain boron-10 isotope.

[0114] In an exemplary embodiment, the fourth determining module 404 is specifically configured to, when the material of the chip to be evaluated does not meet the preset conditions, determine the target thermal neutron single-event effect cross section of a single-bit memory cell based on the target high-energy neutron single-event effect cross section and a first preset multiple; determine the thermal neutron flux in the actual environment based on the high-energy neutron flux and a second preset multiple; and determine the second soft error rate based on the fourth product between the thermal neutron flux, the target thermal neutron single-event effect cross section, and the total number.

[0115] In one exemplary embodiment, the fourth determining module 404 is specifically configured to determine the fourth product as the second soft error rate.

[0116] In an exemplary embodiment, the fifth determining module 405 is specifically configured to determine the sum of the first soft error rate and the second soft error rate as the chip soft error rate of the chip to be evaluated.

[0117] The modules in the aforementioned chip soft error rate determination device can be implemented entirely or partially through software, hardware, or a combination thereof. These modules can be embedded in the processor of a computer device in hardware form or independent of it, or stored in the memory of the computer device in software form, so that the processor can call and execute the corresponding operations of each module.

[0118] In one exemplary embodiment, a computer device is provided, which may be a terminal, and its internal structure diagram may be as follows: Figure 5 As shown, the computer device includes a processor, memory, input / output interfaces, a communication interface, a display unit, and an input device. The processor, memory, and input / output interfaces are connected via a system bus, and the communication interface, display unit, and input device are also connected to the system bus via the input / output interfaces. The processor provides computational and control capabilities. The memory includes non-volatile storage media and internal memory. The non-volatile storage media stores the operating system and computer programs. The internal memory provides the operating environment for the operation of the operating system and computer programs stored in the non-volatile storage media. The input / output interfaces are used for exchanging information between the processor and external devices. The communication interface is used for wired or wireless communication with external terminals; wireless communication can be achieved through Wi-Fi, mobile cellular networks, Near Field Communication (NFC), or other technologies. When executed by the processor, the computer program implements a chip soft error rate determination method. The display unit is used to form a visually visible image and can be a display screen, a projection device, or a virtual reality imaging device. The display screen can be an LCD screen or an e-ink screen. The input device of the computer device can be a touch layer covering the display screen, or buttons, trackballs, or touchpads set on the casing of the computer device, or external keyboards, touchpads, or mice, etc.

[0119] Those skilled in the art will understand that Figure 5 The structure shown is merely a block diagram of a portion of the structure related to the present application and does not constitute a limitation on the computer device to which the present application is applied. Specific computer devices may include more or fewer components than those shown in the figure, or combine certain components, or have different component arrangements.

[0120] In one exemplary embodiment, a computer device is provided, including a memory and a processor. The memory stores a computer program, and the processor executes the computer program to implement the steps of any of the method embodiments described above. The technical principles and effects are similar and will not be repeated here.

[0121] In one embodiment, a computer-readable storage medium is provided, on which a computer program is stored, which, when executed by a processor, implements the steps of any of the above method embodiments. The technical principles and effects are similar and will not be repeated here.

[0122] In one embodiment, a computer program product is provided, including a computer program that, when executed by a processor, implements the steps of any of the method embodiments described above. Its technical principles and effects are similar and will not be repeated here.

[0123] It should be noted that the user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data used for analysis, data stored, data displayed, etc.) involved in this application are all information and data authorized by the user or fully authorized by all parties, and the collection, use and processing of the relevant data must comply with relevant regulations.

[0124] Those skilled in the art will understand that all or part of the processes in the methods of the above embodiments can be implemented by a computer program instructing related hardware. The computer program can be stored in a non-volatile computer-readable storage medium, and when executed, it can include the processes of the embodiments of the above methods. Any references to memory, databases, or other media used in the embodiments provided in this application can include at least one of non-volatile memory and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetic random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memory can include random access memory (RAM) or external cache memory, etc. By way of illustration and not limitation, RAM can take many forms, such as Static Random Access Memory (SRAM) or Dynamic Random Access Memory (DRAM). The databases involved in the embodiments provided in this application may include at least one type of relational database and non-relational database. Non-relational databases may include, but are not limited to, blockchain-based distributed databases. The processors involved in the embodiments provided in this application may be general-purpose processors, central processing units, graphics processing units, digital signal processors, programmable logic devices, quantum computing-based data processing logic devices, artificial intelligence (AI) processors, etc., and are not limited to these.

[0125] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this application.

[0126] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of this patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this application should be determined by the appended claims.

Claims

1. A method for determining the soft error rate of a chip, characterized in that, The method includes: Based on the preset correspondence, the target chip type and target process node of the chip to be evaluated, the target high-energy neutron single-event effect cross section of the single-bit memory cell in the chip to be evaluated is determined; the preset correspondence includes the correspondence between the chip type, the process node, and the high-energy neutron single-event effect cross section of the single-bit memory cell in the chip. The high-energy neutron flux in the actual environment where the chip under evaluation is located is determined based on the altitude of the chip in the actual application scenario. The first soft error rate of the chip under evaluation induced by high-energy neutrons in the actual environment is determined by the first product of the high-energy neutron flux, the target high-energy neutron single-event effect cross section and the total number of single-bit storage cells in the chip to be evaluated. Based on the material of the chip to be evaluated, determine the second soft error rate of the chip to be evaluated induced by thermal neutrons in the actual environment; The chip soft error rate of the chip to be evaluated is determined based on the first soft error rate and the second soft error rate.

2. The method according to claim 1, characterized in that, The step of determining the high-energy neutron flux in the actual environment of the chip under evaluation based on the altitude of the chip in the actual application scenario includes: Determine the second product of the first preset coefficient and the altitude; Determine the power value with the natural constant as the base and the second product as the exponent; The high-energy neutron flux is determined by the third product of the second preset coefficient and the power value.

3. The method according to claim 1 or 2, characterized in that, The step of determining the second soft error rate of the chip under evaluation induced by thermal neutrons in the actual environment, based on the material of the chip under evaluation, includes: If the material of the chip to be evaluated meets the preset conditions, the second soft error rate is determined to be zero; Among them, meeting the preset conditions includes the chip to be evaluated containing thermal neutron shielding process materials, and / or the chip to be evaluated not containing boron-10 isotope.

4. The method according to claim 3, characterized in that, The method further includes: If the material of the chip to be evaluated does not meet the preset conditions, the target thermal neutron single-event effect cross section of the single-bit memory cell is determined according to the target high-energy neutron single-event effect cross section and the first preset multiple. The thermal neutron flux in the actual environment is determined based on the high-energy neutron flux and the second preset multiple. The second soft error rate is determined based on a fourth product between the thermal neutron flux, the target thermal neutron single-event effect cross section, and the total number.

5. The method according to claim 4, characterized in that, The step of determining the second soft error rate based on the fourth product of the thermal neutron flux, the target thermal neutron single-event effect cross section, and the total number includes: The fourth product is determined to be the second soft error rate.

6. The method according to claim 1 or 2, characterized in that, Determining the chip soft error rate of the chip to be evaluated based on the first soft error rate and the second soft error rate includes: The sum of the first soft error rate and the second soft error rate is determined as the chip soft error rate of the chip to be evaluated.

7. A chip soft error rate determination device, characterized in that, The device includes: The first determining module is used to determine the target high-energy neutron single-event effect cross section of a single-bit memory cell in the chip to be evaluated based on a preset correspondence, the target chip type and the target process node of the chip to be evaluated; the preset correspondence includes the correspondence between the chip type, the process node and the high-energy neutron single-event effect cross section of the single-bit memory cell in the chip. The second determining module is used to determine the high-energy neutron flux in the actual environment where the chip to be evaluated is located, based on the altitude of the chip in the actual application scenario. The third determining module is used to determine the first soft error rate of the chip under evaluation induced by high-energy neutrons in the actual environment based on the first product of the high-energy neutron flux, the target high-energy neutron single-event effect cross section and the total number of single-bit storage units in the chip to be evaluated. The fourth determining module is used to determine the second soft error rate of the chip under evaluation induced by thermal neutrons in the actual environment, based on the material of the chip under evaluation. The fifth determining module is used to determine the chip soft error rate of the chip to be evaluated based on the first soft error rate and the second soft error rate.

8. A computer device comprising a memory and a processor, wherein the memory stores a computer program, characterized in that, When the processor executes the computer program, it implements the steps of the method according to any one of claims 1 to 6.

9. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by a processor, it implements the steps of the method according to any one of claims 1 to 6.

10. A computer program product, comprising a computer program, characterized in that, When the computer program is executed by a processor, it implements the steps of the method according to any one of claims 1 to 6.

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