Memory operation command processing method, device, component and chip
By generating ECC operation commands and data operation commands, and using the ECC cache to respond to these commands, the problem of wasted DRAM access frequency and bandwidth resources in the inline ECC scheme is solved, thereby improving the efficiency and reliability of memory operations.
CN122285368APending Publication Date: 2026-06-26XINXIN HANGTU (SUZHOU) TECHNOLOGY CO LTD
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Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- XINXIN HANGTU (SUZHOU) TECHNOLOGY CO LTD
- Filing Date
- 2024-12-18
- Publication Date
- 2026-06-26
AI Technical Summary
Technical Problem
In existing technologies, inline ECC schemes increase the number of DRAM accesses and waste bandwidth resources, especially in DDR Burst operations where the amount of parity bit data is small, leading to low efficiency.
Method used
By generating ECC operation commands and data operation commands, and using ECC caching to respond to these commands, direct access to the memory controller is reduced, the caching and update mechanism of ECC codes is optimized, and frequent access to DRAM is reduced.
Benefits of technology
This effectively reduces the number of times the memory controller accesses DRAM, reduces the waste of bandwidth resources, and improves the efficiency and reliability of memory operations.
✦ Generated by Eureka AI based on patent content.
Smart Images
Figure CN122285368A_ABST
Abstract
This application relates to the field of integrated circuit technology and provides a memory operation command processing method, apparatus, component, and chip. The method includes: acquiring a memory operation command; generating an ECC operation command and a data operation command based on the memory operation command; responding to the ECC operation command based on a preset ECC cache; the ECC cache is used to cache ECC codes; and sending the data operation command to a preset memory controller to instruct the memory controller to respond to the data operation command. This application embodiment enables the memory operation command processing component to respond to the ECC operation command based on the ECC cache and the ECC codes in the ECC cache, avoiding the situation where the memory controller needs to execute an ECC read command or ECC write command every time the upstream device sends a memory operation command, thus reducing the occurrence of frequent DRAM access by the memory controller.
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