Memory circuit

Abstract

Reduce dynamic power during memory access operations. The memory circuit includes: multiple memory groups, each containing multiple memories with multiple memory cells; multiple memory group control units; a first memory control unit that outputs a request signal received from the outside to an adjacent memory group control unit; and a first data conversion unit that divides a first write data signal received from the first memory control unit into n second write data signals and outputs them sequentially to adjacent memory group control units. The multiple memory group control units, when the write address signal included in the request signal indicates a corresponding memory group, sequentially write the n second write data signals to any one memory in the corresponding memory group; when the write address signal does not indicate a corresponding memory group, they transmit the request signal and the n second write data signals to the subsequent memory group control unit.

Description

Technical Field

[0001] This invention relates to a memory circuit. Background Technology

[0002] A memory circuit is known in which a memory and a memory control unit for controlling the memory are repeatedly arranged, and the memory control unit sequentially transmits control signals to a subsequent memory control unit. Each memory control unit outputs a memory access request to the corresponding memory when the address included in the memory access request indicates the corresponding memory, and outputs a memory access request to the subsequent memory control unit when the memory access request includes a request to an address other than the corresponding memory (for example, see Patent Documents 1 and 2).

[0003] Another known SRAM (Static Random Access Memory) capable of performing burst read and burst write operations includes multiple memory cells connected to a word line, a sense amplifier shared among the memory cells, and a selection switch configured between the memory cells and the sense amplifier. In a burst read operation, this SRAM uses the sense amplifier to sequentially amplify the data signals read in parallel from the multiple memory cells via the activation of the word line, and outputs them as serial data signals. In a burst write operation, the memory cell array uses the sequentially activated selection switch to write the serial data signals as parallel data signals to the memory cells. The word line is activated only at the beginning of the burst access operation, or during the burst access operation (e.g., see Patent Documents 3 and 4).

[0004] <Prior art documents>

[0005] <Patent Documents>

[0006] Patent Document 1: International Publication No. 2023-089778

[0007] Patent Document 2: Japanese Patent Application Publication No. 2006-65697

[0008] Patent Document 3: U.S. Patent Application Publication No. 2021 / 0193196

[0009] Patent Document 4: U.S. Patent Application Publication No. 2023 / 0075959 Summary of the Invention

[0010] <Problem to be solved by this invention>

[0011] For example, during a read operation, if only a portion of the data read from multiple memory cells connected to word lines and amplified by a sense amplifier is output to an external terminal, amplification of data not output from external data terminals is unnecessary, thus wasting power. Furthermore, the larger the bit width of the data signals input / output to the memory block containing memory cells, the greater the charging and discharging current of the data lines transmitting data signals within the memory block, resulting in higher dynamic power. In particular, in memory circuits with repeatedly configured memory and memory control units, data lines tend to become longer, increasing the impact of the charging and discharging current of the data lines on the dynamic power of the memory circuit.

[0012] The present invention was developed in view of the above problems, and its purpose is to reduce the dynamic power during memory access operations.

[0013] <Methods for solving problems>

[0014] In one embodiment of the present invention, the memory circuit includes: a plurality of memory groups, each containing a plurality of memories having a plurality of memory cells, performing a write operation or a read operation according to a request signal; a plurality of memory group control units, each corresponding to the plurality of memory groups; a first memory control unit, which outputs a request signal received from an external source to an adjacent memory group control unit; a first data conversion unit, which divides a first write data signal received from the first memory control unit into n second write data signals, and sequentially outputs the second write data signals to the adjacent memory group control unit, wherein n is an integer greater than or equal to 2; the plurality of memory group control units, when the write address signal included in the request signal received from the first memory control unit or the preceding memory group control unit indicates a corresponding memory group, sequentially write the divided n second write data signals into any one of the memories of the corresponding memory group, and when the write address signal does not indicate a corresponding memory group, transmit the request signal and the n second write data signals to the following memory group control unit.

[0015] <The Effects of the Invention>

[0016] According to the technology disclosed herein, it is possible to reduce the dynamic power during memory access operations. Attached Figure Description

[0017] Figure 1 This is a block diagram illustrating an example of the structure of the memory circuit according to the first embodiment.

[0018] Figure 2 It is shown Figure 1 A block diagram of an example of a memory control unit.

[0019] Figure 3 It is shown Figure 1 A block diagram illustrating an example of the structure of a storage block.

[0020] Figure 4 It is shown Figure 3 A block diagram illustrating the structure of a memory bank.

[0021] Figure 5 It is shown Figure 4 A block diagram illustrating the structure of a storage unit.

[0022] Figure 6 It is shown Figure 5 A block diagram illustrating an example of the internal structure of a memory MEM contained within a storage cell.

[0023] Figure 7 This is shown from the perspective of each data reading signal. Figure 6 The diagram shows the reading operation of the series circuit.

[0024] Figure 8 This is shown from the perspective of each written data signal. Figure 6 The diagram shows the write operation of the series circuit.

[0025] Figure 9 An example of a memory circuit is shown, comprising a memory block for receiving 512-bit write data signals from a memory control unit and outputting 512-bit read data signals to the memory control unit.

[0026] Figure 10 It is shown Figure 9 A block diagram illustrating an example of the internal structure of a sub-memory.

[0027] Figure 11 It is shown Figure 6 The memory circuit's memory cell contains the memory MEM and Figure 10 A timing diagram outlining the read operations of the sub-memories contained in the memory block of the memory circuit.

[0028] Figure 12 It is shown Figure 6 , Figure 7 and Figure 8 A timing diagram of an example of read and write operations in a memory.

[0029] Figure 13 It is shown Figure 10 A timing diagram of an example of read and write operations in a sub-memory.

[0030] Figure 14 It is shown Figure 1 A block diagram illustrating an example of the structure of a memory group control unit.

[0031] Figure 15This is a timing diagram illustrating an example of generating the memory clock signal MCLK from the memory clock signal MCLKxN.

[0032] Figure 16 It is shown Figure 4 A state transition diagram illustrating the transformation of the operational state of a storage unit.

[0033] Figure 17 It is shown Figure 14 A flowchart illustrating an example of the operation of the memory group control unit.

[0034] Figure 18 It is shown Figure 17 A flowchart of an example of step S100.

[0035] Figure 19 It is shown Figure 17 A flowchart of an example of step S200.

[0036] Figure 20 It is shown Figure 19 A flowchart of an example of step S220.

[0037] Figure 21 It is shown Figure 17 A flowchart of an example of step S300.

[0038] Figure 22 It is shown in Figure 1 An illustration of an example of the operation in a memory circuit that converts a memory cell to an effective mode.

[0039] Figure 23 It is shown Figure 22 A timing diagram of an example of the timing of the signal when transitioning to an effective mode.

[0040] Figure 24 It is shown Figure 23 The subsequent timing diagram.

[0041] Figure 25 It is shown Figure 1 An illustration of an example of a write operation in a memory circuit.

[0042] Figure 26 It is shown Figure 18 A timing diagram of an example of the signal timing during a write operation.

[0043] Figure 27 It is shown Figure 26 The subsequent timing diagram.

[0044] Figure 28 It is shown Figure 1 An illustration of an example of the read operation of a memory circuit.

[0045] Figure 29 It is shown Figure 28 A timing diagram of an example of the signal timing during a read operation.

[0046] Figure 30 It is shown Figure 29 The subsequent timing diagram.

[0047] Figure 31 It is shown Figure 30 The subsequent timing diagram.

[0048] Figure 32 It is shown Figure 31 The subsequent timing diagram.

[0049] Figure 33 It is shown Figure 1 Another example of the timing diagram for the signals during a read operation of a memory circuit.

[0050] Figure 34 It is shown Figure 33 The subsequent timing diagram.

[0051] Figure 35 It is shown Figure 34 The subsequent timing diagram.

[0052] Figure 36 It is shown Figure 35 The subsequent timing diagram.

[0053] Figure 37 This is a block diagram illustrating an example of the structure of the memory circuit according to the second embodiment.

[0054] Figure 38 It shows that it is installed Figure 1 A block diagram illustrating an example of the structure of a memory circuit system. Detailed Implementation

[0055] The embodiments will now be described using the accompanying drawings. Hereinafter, signal lines that transmit information such as signals will be represented by the same symbols as the signal names. Furthermore, signal lines indicated by thick lines indicate that they consist of multiple bits. Additionally, signal lines indicated by single lines may sometimes also consist of multiple bits.

[0056] Figure 1 An example of the structure of the memory circuit of the first embodiment is shown. Figure 1The memory circuit 100 shown is installed, for example, in a semiconductor device such as a system LSI used for processing image data. For example, the semiconductor device including the memory circuit 100 is installed in a camera device such as a surveillance camera, a head-mounted device such as AR / VR (Augmented Reality / Virtual Reality) glasses, or a digital camera to generate animated image data to be displayed on a display device.

[0057] The memory circuit 100 includes a memory block MBLK, a memory control unit 200 (input side) connected in series with the input side of the memory block MBLK, a data conversion unit PSCNV, a data conversion unit SPCNV connected in series with the output side of the memory block MBLK, and the memory control unit 200 (output side). The memory control unit 200 (input side) is an example of a first memory control unit, and the memory control unit 200 (output side) is an example of a second memory control unit. In the following description, unless it is necessary to distinguish between the memory control unit 200 (input side) and 200 (output side), it will be referred to as the memory control unit 200.

[0058] The memory block MBLK includes multiple memory groups (MGs) and multiple memory group control units (MCNTs). The multiple memory groups (MGs) are arranged in one direction and include multiple memory cells. The multiple memory group control units (MCNTs) are configured on the input side of the respective signals of the multiple memory groups (MGs). Furthermore, the memory block MBLK has memory group control units (MCNTs) configured on the output side of the signals of the final memory group (MG). For example, each memory group (MG) is configured between a pair of memory group control units (MCNTs). In other words, the memory group control units (MCNTs) and memory groups (MGs) are configured alternately. The memory group control units (MCNTs) function as interface circuits for signals input and output between the memory control unit 200 and the memory groups (MGs), or as interface circuits for signals input and output between the memory group control units (MCNTs).

[0059] Each memory bank control unit (MCNT) has a trigger circuit FF for receiving access request signals (control signal CMD, address signal A, etc.), write data signals D, and read data signals Q, respectively. When each memory bank control unit (MCNT) receives an access request signal for an adjacent memory bank (MG) on the output side (hereinafter also referred to as its own memory bank MG), it outputs the access request signal to its own memory bank MG.

[0060] In this case, apart from the signals used in the final segment's memory group control unit (MCNT), each memory group control unit (MCNT) suppresses the output of access request signals to the subsequent segment's memory group control unit (MCNT). The subsequent segment's memory group control unit (MCNT) refers to the memory group control unit (MCNT) located on the output side of the memory control unit 200, separated from the memory group control unit (MCNT) of interest by one memory group (MG).

[0061] Furthermore, when each memory group control unit (MCNT) receives an access request signal for a memory group MG other than its own memory group MG, it transmits the access request signal to the subsequent memory group control unit (MCNT). In this case, each memory group control unit (MCNT) suppresses the output of access request signals to its own memory group MG.

[0062] Each memory group control unit (MCNT) transmits the read data signal Q, which is read from its own memory group (MG) or transmitted by the front-end memory group control unit (MCNT), to the back-end memory group control unit (MCNT) during a read operation. The front-end memory group control unit (MCNT) refers to the memory group control unit (MCNT) located on the input side of the memory control unit 200, which is located one memory group (MG) away from the memory group control unit (MCNT) of interest.

[0063] Therefore, the memory block MBLK can control access to each memory group MG through the memory group control unit MCNT. In the memory block MBLK, since the control line CMD, address line A, write data line D, and read data line Q are not long-distance wirings spanning multiple memory groups MG, the increase in wiring load can be suppressed. As a result, the increase in access time of the memory circuit 100 can be suppressed, while the increase in dynamic power consumption during access operations can also be suppressed.

[0064] Furthermore, the clock cycles required for transmitting access request signals, write data signals D, and read data signals Q between a pair of memory bank control units (MCNTs) configured on both sides of the memory bank MG are set to the same value. Therefore, timing design can be easily performed even when redesigning other memory circuits with different storage capacities by increasing or decreasing the number of memory banks MG.

[0065] The memory control unit 200 is connected to the system bus SBUS of the semiconductor device and the peripheral bus CNTL for inputting and outputting various control signals. While not specifically limited, the system bus SBUS can, for example, input and output signals according to ARM's AXI4 (Advanced eXtensible Interface 4). The memory control unit 200 functions as an interface circuit for inputting and outputting signals to the system bus SBUS and to the memory bank control unit MCNT.

[0066] Figure 1 The diagram shows an example where the columns of the memory group control unit MCNT and the memory group MG are connected in series between the memory control unit 200 (input side) and the memory control unit 200 (output side). However, the columns of the memory group control unit MCNT and the memory group MG can also be configured in a U-shape with one side open. In this case, the memory control unit 200 (input side) and the memory control unit 200 (output side) are centrally located at one end of the configuration area of ​​the memory group control unit MCNT and the memory group MG.

[0067] The memory control unit 200 (input side) receives, via the system bus SBUS, a request signal REQ, an address signal ADR, and a write data signal WD from a higher-level controller such as the CPU (Central Processing Unit) to cause the memory circuit 100 to perform memory access operations (read or write operations). The request signal REQ corresponds to an access request signal that causes the memory bank MG to perform a write or read operation. The access request signal indicates a write request or a read request. Furthermore, in... Figure 1 To simplify the accompanying drawings, only the flow of the main information signals is shown. Although the illustrations are omitted, there are additional information, signals indicating whether each signal is valid or invalid, and control signals indicating output or reception commands for data signals.

[0068] The memory control unit 200 (input side) generates a control signal CMD containing additional information for accessing memory within the memory group MG, based on the address signal ADR and the request signal REQ, which includes information such as request ID or access size. The memory control unit 200 (input side) outputs the generated control signal CMD to the initial memory group control unit MCNT.

[0069] For example, the memory control unit 200 (input side) outputs a 512-bit write data signal D to the data conversion unit PSCNV whenever the received 64-bit write data signal WD reaches 8 times. The write data signal WD is an example of the third write data signal. The data conversion unit PSCNV sequentially converts the 512-bit write data signal D output by the memory control unit 200 (input side) into four 128-bit write data signals D, and sequentially outputs the four converted write data signals D to the initial memory group control unit MCNT. The 512-bit write data signal D is an example of the first write data signal, the four 128-bit write data signals D are an example of the second write data signal, and the data conversion unit PSCNV is an example of the first data conversion unit.

[0070] Furthermore, the memory control unit 200 (input side) receives a control signal CNTL via the peripheral bus for setting the operating specifications of at least one of the memory group MG and the memory group control unit MCNT. Additionally, the memory control unit 200 (input side) outputs the operating specifications of at least one of the memory group MG and the memory group control unit MCNT as the control signal CNTL to the peripheral bus. For example, the peripheral bus is an interface that is slower than the system bus SBUS.

[0071] The memory control unit 200 (output side) receives access control signals such as control signals CMD and address signals A from the final-stage memory group control unit MCNT. Additionally, the memory control unit 200 (output side) receives a read data signal Q from the final-stage memory group control unit MCNT via the data conversion unit SPCNV, and outputs it as a read data signal RD to the system bus SBUS. The read data signal RD is an example of a third read data signal. For example, whenever the memory control unit 200 (output side) receives a 512-bit read data signal Q from the data conversion unit SPCNV, it outputs the 64-bit read data signal RD eight times. That is, the memory control unit 200 converts the parallel read data signal Q, read from the memory group MG and output from the data conversion unit SPCNV, into a serial read data signal RD and outputs it to the system bus SBUS.

[0072] The data conversion unit SPCNV converts the four 128-bit read data signals Q sequentially output from the memory group control unit MCNT of the final segment into 512-bit read data signals Q, and outputs the converted read data signals Q to the memory control unit 200 (output side). The four 128-bit read data signals Q are an example of the first read data signal, and the 512-bit read data signal Q is an example of the second read data signal.

[0073] The data conversion unit SPCNV has four trigger circuits FF connected in series. Each trigger circuit FF holds a 128-bit read data signal Q and outputs it to the memory control unit 200 (output side). After removing the trigger circuit FF of the final segment, the held 128-bit read data signal Q is output to the trigger circuit FF of the next segment. The data conversion unit SPCNV is an example of a second data conversion unit.

[0074] In this embodiment, the 512-bit write data signal D output from the memory control unit 200 (input side) is converted into four 128-bit write data signals D by the data conversion unit PSCNV and provided to the memory block MBLK. Therefore, compared with the case where the data conversion unit PSCNV is not used, the number of write data lines D wired in the memory block MBLK can be reduced to 1 / 4.

[0075] Similarly, the four 128-bit read data signals Q output from the memory block MBLK are converted into 512-bit read data signals Q by the data conversion unit SPCNV and output to the memory control unit 200 (output side). Therefore, compared with the case where the data conversion unit SPCNV is not used, the number of read data lines Q wired in the memory block MBLK can be reduced to 1 / 4.

[0076] The 128-bit data signal input / output to the memory block MBLK is twice the 64-bit data signal input / output to the system bus SBUS. Therefore, the ideal operating frequency of the memory block MBLK can be half the operating frequency of the system bus SBUS. Thus, compared to the case of inputting / outputting 64-bit data signals to the memory block MBLK, the power consumption during memory block MBLK access operations can be reduced. Because the operating frequency of the memory block MBLK can be reduced, the memory bank control unit MCNT and the memory bank MG can have sufficient operating margin, and the timing settings of the execution circuits can be easily configured.

[0077] In addition, the number of bits of the data signals input and output to the storage block MBLK is 2 raised to the power of k (k is an integer greater than or equal to 1, and in this example, k=1).

[0078] Figure 2 Show Figure 1 An example of a circuit block of the memory control unit 200. The memory control unit 200 (input side) includes a system bus input control unit 202, buffers 204 and 206, a peripheral bus control unit 208, an overall management unit 210, a memory status management unit 212, and an input interface control unit 214. The memory control unit 200 (output side) includes an output interface control unit 220, buffers 222 and 224, and a system bus output control unit 226.

[0079] The system bus input control unit 202 generates an address signal A and a control signal CMD containing additional information for memory control based on the address signal ADR and the request signal REQ, which contains information such as request ID or access size, and stores them in the buffer 204. The system bus input control unit 202 stores a total of 513 bits (hereinafter, unless otherwise specified, the description of the Last signal is omitted and it is considered to be a total of 512 bits) of write data signal WD received from the system bus SBUS up to 8 times, and 1 bit of additional information (Last information) in the buffer 206.

[0080] Buffers 204 and 206 are, for example, FIFO (First-In First-Out) buffers. Buffer 204 outputs the control signal CMD and the address signal A to the input interface control unit 214 in the order they are stored. Buffer 206 outputs the write data signal WD to the input interface control unit 214 in the order they are stored.

[0081] When the control signal CMD received from buffer 204 is valid, the input interface control unit 214 outputs the control signal CMD and the address signal A, which cause the memory block MBLK to perform a write or read operation, to the memory block MBLK. Additionally, the input interface control unit 214 outputs a 512-bit write data signal D, corresponding to the write request signal indicating a write request from buffer 204, to the data conversion unit PSCNV.

[0082] The peripheral bus control unit 208 outputs various control signals CNTL received from the peripheral bus to the overall management unit 210. Furthermore, the peripheral bus control unit 208 outputs various control signals CNTL received from the overall management unit 210 to the peripheral bus.

[0083] The overall management unit 210 includes multiple registers (not shown) for setting the memory group MG ( Figure 1 The overall management unit 210 sets the operating mode specifications based on various control signals (CNTL) from the peripheral bus. For example, operating modes include shutdown mode, sleep mode, and active mode. For example, the switching between shutdown mode, sleep mode, and active mode is performed on a memory unit (MU) basis, as described later. The switching unit for shutdown mode, sleep mode, and active mode is not limited to the memory unit (MU).

[0084] For example, in power-off mode, the power supply to the storage cell area in the storage unit MU of the object to be powered off is cut off, and the power supply to the peripheral circuits outside the storage cell area that are unrelated to power-off and sleep control is also cut off. In sleep mode, the power supply to the storage cell area in the storage unit MU of the object to be powered off is reduced to a low voltage sufficient to maintain the data held in the storage cell, and the power supply to the peripheral circuits outside the storage cell area that are unrelated to power-off and sleep control is also cut off.

[0085] Furthermore, in this embodiment, an example is described in which the memory block MBLK itself has a built-in power supply circuit for power-off and sleep functions. However, even if the memory block MBLK itself does not have a power supply circuit, if a power supply circuit provided outside the memory block MBLK can be used to adjust the power supply voltage of the memory cell area, adjust the power supply voltage of the peripheral circuit outside the memory cell area, or cut off the power supply in units of memory cell MU or memory group MG, then switching control of power-off mode, sleep mode, and active mode can be performed.

[0086] In active mode, write or read operations can be performed. Furthermore, the registers of the memory status management unit 212 can be set to remain in active mode until transitioning to sleep mode if no access is made.

[0087] The memory status management unit 212 manages the operating mode of the memory unit MU based on the settings of multiple built-in registers. In addition, the memory status management unit 212 can also maintain fault information indicating the location of faulty memory cells within the memory bank MG, access normal memory cells to replace faulty memory cells, and implement fault recovery management.

[0088] During the read operation of memory block MBLK, the output interface control unit 220 stores the control signal CMD and address signal A received from memory block MBLK in buffer 222. Additionally, the output interface control unit 220 stores the 512-bit read data signal Q received from data conversion unit SPCNV in buffer 224.

[0089] Buffers 222 and 224 are, for example, FIFO buffers. Buffer 222 outputs the control signal CMD and the address signal A, which contain additional information for memory control, to the system bus output control unit 226 in a sequential manner. Buffer 224 outputs the 512-bit read data signal Q received from the output interface control unit 220 to the system bus output control unit 226.

[0090] Furthermore, the memory control unit 200 has the function of converting the frequency of data signals input / output to the system bus SBUS and the frequency of data signals input / output to the memory block MBLK. For example, in the memory control unit 200, the input sides of buffers 204 and 206 operate according to the system clock signal SCLK used in the system bus SBUS. In the memory control unit 200, the output sides of buffers 204 and 206 operate according to the memory clock signal MCLK used in the memory block MBLK.

[0091] Similarly, in the memory control unit 200, the input sides of buffers 222 and 224 operate according to the memory clock signal MCLK used in the memory block MBLK. In the memory control unit 200, the output sides of buffers 222 and 224 operate according to the system clock signal SCLK used in the system bus SBUS. Thus, buffers 204, 206, 222, and 224 also operate as clock switching circuits.

[0092] The system bus output control unit 226 receives a control signal CMD and an address signal A containing additional information for memory control, output from buffer 222, and a 512-bit read data signal Q output from buffer 224. Based on the control signal CMD and the address signal A containing the additional information for memory control, the system bus output control unit 226 outputs the 512-bit read data signal Q as up to eight 64-bit read data signals RD sequentially to the system bus SBUS. Depending on the size information contained in the address signal A and the additional information, the 512-bit read data signal Q may sometimes contain data signals other than those accessed. For the system bus SBUS, only data signals related to the accessed data are output.

[0093] Figure 3 Show Figure 1 Here is an example of the structure of a memory block MBLK. The following description assumes that the memory block MBLK comprises four memory groups MG (MG1, MG2, MG3, MG4). Each memory group MG includes four memory cells MU. Furthermore, the number of memory groups MG installed in the memory block MBLK and the number of memory cells MU installed within each memory group MG are not limited to... Figure 3 The example shown.

[0094] The memory block MBLK includes memory group control units MCNT (MCNT1, MCNT2, MCNT3, MCNT4) configured on the input side of each memory group MG. Additionally, the memory block MBLK includes a memory group control unit MCNT5 configured on the output side of the last memory group MG4.

[0095] Although not specifically limited, each memory unit (MU) is 8k words × 128 bits (= 1M bits) in size, and each MU inputs and outputs 128 bits of data signals. The memory block (MG) comprising four memory units (MUs) is 32k words × 128 bits (= 4M bits) in size. The memory block (MBLK) comprising four memory blocks (MGs) is 128k words × 128 bits (= 16M bits) in size.

[0096] In this embodiment, the switching unit between power-off mode, sleep mode, and active mode is a memory unit (MU). Sleep mode is an example of a low-power mode. Here, power-off mode, sleep mode, and active mode can be switched on a unit of two memory units (MU), or the memory units (MU) can be further subdivided into multiple columns, and switching can be performed on a column-by-column basis. Alternatively, power-off mode, sleep mode, and active mode can also be switched on a unit of memory group (MG).

[0097] For example, in each storage unit (MU), the power consumption in power-off mode is about 1 / 10 of the standby power consumption in active mode, and the power consumption in sleep mode is about 1 / 3 of the standby power consumption in active mode.

[0098] The memory group control unit (MCNT) adjacent to the input side of each memory group (MG) outputs a control signal CMD, an address signal A, and a write data signal D to the memory group (MG) and the memory group control unit (MCNT) on the output side of the memory group (MG). Each memory group (MG) outputs a read data signal Q to the memory group control unit (MCNT) on its output side. For example... Figure 3 As shown, the control line CMD and address line A are routed per memory group MG and do not span multiple memory groups MG. Therefore, it is possible to suppress the increase in the routing load of the control line CMD and address line A, and to suppress the increase in the access time of the memory circuit 100, while also suppressing the increase in power consumption.

[0099] Figure 4 Show Figure 3 This is an example of the structure of a memory bank MG. The memory bank MG is assumed to consist of four memory cells MU (MU0-MU3) for illustration. The symbol (i) appended to the end of a signal indicates an input signal, and the symbol (o) appended to the end of a signal indicates an output signal. The memory bank MG receives the memory clock signal MCLKxN, 16 chip enable signals CEB[15:0], write enable signal WEB, and bit write enable signal BWEB[127:0] from the memory bank control unit MCNT, as... Figure 3 The control signal CMD is used in the chip. Sixteen chip enable signals CEB are provided in four-by-four increments to memory cells MU (MU0-MU3) to select the memory cell MU. Figure 3The four memory modules (MEMs) within each memory unit (MU) shown are illustrated. Figure 5 (MEM0-MEM3). In addition, the memory group MG receives 128-bit write data signals D[127:0] from the memory group control unit MCNT. The number of data terminals in the memory group MG that receive the write data signals D is 1 / 4 of the number of data terminals in the memory control unit 200 that output the write data signals D.

[0100] Signals appended with the symbol B are negative logic signals, while signals without the symbol B are positive logic signals. The bit write enable signal BWEB[127:0] is a signal that controls the writing of data signals in units of bits, and the bit of the bit write enable signal BWEB corresponding to the bit masked in the write data signal D is set to a high level.

[0101] For example, the memory clock signal MCLKxN is a clock signal obtained by multiplying the frequency of the memory clock signal MCLK by four times. Furthermore, the multiplier of the memory clock signal MCLKxN can be set to be equal to the number of memory cells MEM installed in each memory unit MU. That is, the multiplier of the memory clock signal MCLKxN can be set to be equal to the number of memory cells MEM installed in response to one read instruction RCMD. Figure 12 The number of read data signals Q continuously read from the memory cell MU during a read operation. Additionally, the multiplier of the memory clock signal MCLKxN can be set to be equal to the number of read data signals Q continuously read from the memory cell MU by a single write instruction WCMD. Figure 12 The number of write data signals D that are continuously written to the memory cell MU during the write operation.

[0102] In addition, the memory group MG receives the address signal A and four 128-bit write data signals D[127:0] corresponding to the address signal A, and outputs four 128-bit read data signals Q[127:0]. The number of data terminals in the memory group MG that output the read data signals Q is 1 / 4 of the number of data terminals in the memory control unit 200 that receive the read data signals Q.

[0103] Four 128-bit write data signals D are provided to any one of the four memory cells MU0-MU3 within the memory bank MG. The memory bank MG has multiple selectors SEL for sequentially selecting any one of the 128-bit read data signals Q output from the four memory cells MU and outputting it to the memory bank control unit MCNT (not shown).

[0104] Furthermore, the memory group MG, as shown in the unillustrated memory group control unit MCNT, serves as... Figure 3The control signal CMD receives the power-off signal SD (SD0-SD3) and the sleep signal SLP (SLP0-SLP3). See reference... Figure 3 As explained, in this embodiment, the switching between power-off mode, sleep mode, and active mode is implemented on a per-memory unit (MU). Therefore, a power-off signal SD and a sleep signal SLP are provided for each memory unit (MU).

[0105] Figure 5 Show Figure 4 This is an example of the structure of a memory unit MU. The memory unit MU includes four memory modules MEM. The size of each memory module MEM is 2k words × 128 bits (= 256k bits). Memory modules MEM0-MEM3 become enabled when their respective chip enable signals CEB[0]-CEB[3] are active (e.g., low). Then, one of the enabled memory modules MEM (any one of MEM0-MEM3) performs a read or write operation in accordance with the logic level of the write enable signal WEB.

[0106] The 128-bit read data signal Q[127:0] read from the memory MEM performing the read operation is output as the data signal Q[127:0](o) read from the memory cell MU via one or more selectors SEL. The memory MEM performing the write operation receives the 128-bit write data signal D[127:0] and writes it to the memory cell (not shown). For example, the memory MEM includes multiple SRAM memory cells, but may also include memory cells of other volatile memories. In addition, the memory MEM may also include memory cells of non-volatile memories such as MRAM (Magnetoresistive Random Access Memory) or ReRAM (Resistive Random Access Memory). Furthermore, the number of memory MEMs installed in the memory cell MU is not limited to... Figure 5 The example shown.

[0107] Furthermore, the power-off signal SD and sleep signal SLP can be further subdivided. For example, by providing the power-off signal SD and sleep signal SLP with every two memory modules MEM, peak current can be further suppressed.

[0108] Figure 6 Show Figure 5This is an example of the internal structure of the memory MEM included in the memory cell MU. The memory MEM includes a row decoder RDEC, a memory array control circuit MEMCNT, a memory cell array ARY, a precharge circuit PRE, a sense amplifier SA, a read latch RLT, and data input / output circuit I / O. The data input / output circuit I / O includes a read switch RSW and a buffer BUF (not shown). Hereinafter, the precharge circuit PRE, sense amplifier SA, read latch RLT, read switch RSW, and buffer BUF will also be referred to as column circuits. The read latch RLT is an example of a data latch, and the read switch RSW is an example of a data selection section.

[0109] For example, the storage primitive array ARY includes Figure 6 The 512 horizontal lines WL extend in the horizontal direction. Figure 6 The system consists of 512 complementary bit line pairs (BL and BLB) extending vertically, and multiple memory cells (MCs) arranged in a matrix. Each memory cell (MC) is positioned at the intersection of a word line (WL) and the complementary bit line pairs (BL and BLB). All word lines (WL) are connected to the 512 memory cells (MCs) arranged horizontally.

[0110] Figure 3 The instruction signal CMD shown includes the read instruction RCMD and the write instruction WCMD. Based on the read instruction RCMD, the... Figure 4 as well as Figure 5 When the write enable signal (memory instruction signal) WEB is high, the memory (MEM0-MEM3) operates in read mode. On the other hand, according to the write instruction WCMD, the memory... Figure 4 as well as Figure 5 When the write enable signal (memory instruction signal) is low under WEB control, the memory (MEM0-MEM3) operates in write mode.

[0111] For reference Figure 12 As explained, from the control signal CMD ( Figure 3 The system identifies the 512 memory cells MC on word line WL by issuing a read instruction RCMD once, and simultaneously reads the data signal. The read data signal is transmitted to four units: a precharge circuit PRE with 128 bits, a sense amplifier SA, a read latch RLT, and a read switch RSW. Furthermore, in the initial clock cycle, the first data signal is selected by the read switch RSW every four units and output as a 128-bit read data signal Q[127:0].

[0112] From the 2nd to the 4th clock cycle, the next data signal in every 4 units is sequentially selected by the read switch RSW and output as a 128-bit read data signal Q[127:0]. Ultimately, 512 read data signals Q are output over 4 clock cycles. Additionally, Figure 6 The circuitry used for reading operations is shown, while the circuitry used only for writing operations is omitted.

[0113] Figure 7 This is shown from the perspective of various data reading signals. Figure 6 The diagram shows the reading operation performed by the columnar circuit. Figure 7 In the diagram, the 512 memory cells MC connected to the word line WL are represented in four units as MC[k]_0, MC[k]_1, MC[k]_2, and MC[k]_3 (where k = 0 to 127). For the bit line pairs BL and BLB connected to the memory cells MC, the precharge circuit PRE, sense amplifier SA, and read latch RLT are configured in a one-to-one relationship. Simultaneously, all data read from the bit line pairs BL and BLB is latched into the read latch RLT via the sense amplifier SA.

[0114] During the read operation, after the pre-charging of BL and BLB by the pre-charge circuit PRE stops, the data signal is read from the 512 memory cells MC connected to one of the word lines WL selected by the line decoder RDEC, and amplified by the sense amplifier SA. The data signal amplified by the sense amplifier SA is latched by the read latch RLT.

[0115] Then, the 512 data signals latched by the read latch RLT are selected in 128 increments per read cycle according to the four column read signals COL_R[3:0] generated by the memory array control circuit MEMCNT and provided to the read switch RSW. In the initial clock cycle, the read switch RSW, which is selected to receive the column read signal COL_R[0], reads 128 data signals from the memory primitive MC[k]_0 (where k = 0 to 127) and outputs them as the read data signal Q[k] (where k = 0 to 127) via the buffer BUF.

[0116] During the second to fourth clock cycles, the read switches RSW for receiving column read signals COL_R[1], COL_R[2], and COL_R[3] are selected sequentially. Furthermore, the 128 data signals read from storage cells MC[k]_1, MC[k]_2, and MC[k]_3 each clock cycle are output as the read data signal Q[k] via the buffer BUF. Finally, all the data held in the 512 storage cells MC are output using 4 clock cycles. This embodiment shows a 4-bit column read signal system, but it is not limited to this and can also be an 8-bit or 16-bit system. Additionally, with the data provided... Figure 6 The external address signal of the memory MEM is independent, and the column read signal COL_R[0]-COL_R[3] is generated by the memory array control circuit MEMCNT.

[0117] In addition, to prevent hazards in the individual bits of the read data signal Q[127:0] when switching column read signals COL_R[3:0], a latch can be configured, for example, between the read switch RSW and the buffer BUF.

[0118] Figure 8 This is shown from the perspective of each write data signal. Figure 6 The column system circuit shown performs a write operation. During the write operation, besides... Figure 6 In addition to the circuit shown, a trigger circuit D-FF, a write selector WSEL, a write latch WLT, and a write buffer WBUF are also used. The write selector WSEL is an example of a data selection unit, and the write latch WLT is an example of a data latch.

[0119] The trigger circuit D-FF is configured to correspond to each bit of the write data signal D[127:0]. Each bit of the 128 write data signals D is selected by any one of the four write selectors WSEL, which receive the four column write signals COL_W[3:0] generated sequentially by the memory array control circuit MEMCNT. The write latch WLT, write buffer WBUF, and precharge circuit PRE are configured in a one-to-one relationship with the bit lines BL and BLB. In each write cycle, the write latch WLT is selectively connected to the output of the trigger circuit D-FF via the write selector WSEL. The write buffer WBUF drives the bit lines BL and BLB according to the data from the write latch WLT. The precharge circuit PRE precharges the bit lines BL and BLB.

[0120] In the initial clock cycle, the write data signal is latched to the write latch WLT connected to the system of memory cell MC[k]_0 (where k = 0 to 127) via the write selector WSEL selected by the column write signal COL_W[0]. In the second to fourth clock cycles, the write selectors WSEL receiving the column write signals COL_W[1], COL_W[2], and COL_W[3] are selected respectively. Then, the write data signal is sequentially latched to the write latch WLT connected to one of the systems of memory cells MC[k]_1, MC[k]_2, and MC[k]_3 (where k = 0 to 127) via the write selector WSEL selected in each clock cycle.

[0121] After latching the write data signals in all write latches WLT connected to memory bases MC[k]_0, MC[k]_1, MC[k]_2, and MC[k]_3 over four clock cycles, the latched write data signals are written to the 512 memory bases MC selected by word lines WL via write buffers WBUF. When performing a write cycle in four cycles, the write buffer WBUF corresponding to each clock cycle is enabled, and the data for bit line pairs BL and BLB is determined sequentially. In the next clock cycle after the fourth clock cycle, the desired word line WL is activated, and all write data is written to the memory base MC. This suppresses unwanted charging and discharging currents in bit line pairs BL and BLB caused by virtual reads when word lines WL are activated.

[0122] Figure 9 An example of a memory circuit 110 is shown, comprising a memory block MBLK120 that receives a 512-bit write data signal D from the memory control unit 200 and outputs a 512-bit read data signal Q to the memory control unit 200. Regarding... Figure 1 For elements that are the same, detailed descriptions are omitted. Figure 9 The memory circuit 110 shown does not have Figure 1 The data conversion units PSCNV and SPCNV are shown. In the memory circuit 110, in addition to transmitting a 512-bit write data signal D simultaneously within the memory block MBLK120 during a write operation, and transmitting a 512-bit read data signal Q simultaneously within the memory block MBLK120 during a read operation, and replacing... Figure 1 The memory group MG has the same structure as the memory group MGb, except that the memory group MGb has the same structure as the memory group MGb. Figure 1The memory circuit 100 is identical. Each memory group MGb has 4 memory cells MUb (MUb0-MUb3), and each memory cell MUb has 4 memory cells MEMb (MEMb0-MEMb3). Furthermore, each memory cell MEMb has a sub-memory SubMEMb for reading and writing 128-bit data after dividing 512-bit data into 4 parts.

[0123] Figure 10 Show Figure 9 The diagram shows an example of the internal structure of the sub-memory SubMEMb. Figure 6 The memory MEM can respond to a single memory access request by performing the equivalent of 512 bits of data access in 128 bits × 4 clock cycles, while for example... Figure 10 The sub-memory SubMEMb performs one 128-bit data access for each memory access request. Therefore, it is possible to configure the system to perform 128-bit × 4 accesses, equivalent to 512 bits of data access, by executing 4 memory access requests, or as... Figure 9 In this way, with a data range of 512 bits, the sub-memory SubMEMb of the upper and lower 4 systems is prepared, and 512 bits of data are accessed at a time.

[0124] In addition, relative to Figure 6 In this structure, the bit lines BL, BLB, precharge circuit PRE, sense amplifier SA, read latch RLT, and read switch RSW are configured in a one-to-one relationship. Figure 10 The difference lies in the fact that the bit line pairs BL and BLB, as well as the precharge circuit PRE, form a 4-to-1 relationship with the sense amplifier SA and the read latch RTL via the multiplexer MUX. Furthermore, comparing the operation of the word line WL and the bit line pairs BL and BLB, relative to... Figure 6 When the memory MEM outputs 512 bits of data every 4 clock cycles in 128-bit increments, the word line WL and bit lines BL and BLB are activated and deactivated only once. Figure 10 The difference between SubMEMb and other sub-memory is that the word line WL and bit line pairs BL and BLB are repeatedly activated and deactivated every 4 clock cycles. Furthermore, Figure 10 Unlike Figure 6 The key difference is that the multiplexer MUX is configured in Figure 6 The precharge circuit PRE and the sensing amplifier SA are connected, and there is no read switch RSW, but the multiplexer MUX can also be constructed with a read switch RSW.

[0125] The memory array control circuit MEMCNT decodes the externally input address signal A of the slave sub-memory SubMEMb (not shown) and sets any one of the four decoded signals COL_R[3:0] to an active level. A multiplexer MUX is configured for every four memory cells MC. The multiplexer MUX outputs 512 pairs (512 bits) of data signals from the corresponding memory cell MC to bit-line pairs BL and BLB, selectively inputting 128 pairs (128 bits) of data signals to the sense amplifier SA via the multiplexer MUX. Each sense amplifier SA differentially amplifies the input data signals and outputs them to the read latch RLT. Then, a 128-bit read data signal Q[127:0] is output via the read latch RLT.

[0126] exist Figure 10 In the memory circuit 110 shown, of the 512 bits of data signal read from the memory cell MC during a read operation, only 128 bits are output as read data signals Q[127:0], while the other 384 bits of data signals are not output. In the read and write operations of memory circuits such as SRAM, the power consumption due to the charging and discharging of the bit lines BL and BLB is dominant relative to the overall power consumption. Therefore, for example, the power consumption of each bit of the data signal read during the read operation of memory circuit 110 reaches a certain level. Figure 6 The power consumption of each bit of data signal read during the read operation of the memory MEM is nearly four times that of the memory, resulting in wasted power.

[0127] Figure 11 Show Figure 6 The memory circuit 100 includes a memory MEM and a memory cell MU in its memory cell MU. Figure 10 A summary of the timing of read operations for the sub-memory SubMEMb included in the memory block MBLK120 of the memory circuit 110. For example, Figure 6 MEM and Figure 10 The sub-memory SubMEMb operates synchronously with the memory clock signal MCLKxN.

[0128] The memory cell MU of the memory circuit 100 Figure 5 The upper two bits of the address signal A (=RA0) received along with the read instruction RCMD are decoded to generate the chip enable signal CEB[3:0]. Figure 5 The system selects one of the following: memory MEM0, memory MEM1, memory MEM2, and memory MEM3. The row decoder RDEC in the selected memory MEM decodes the 3rd to 11th bits of the address signal RA0, selects, for example, word line WL0 from the 512 word lines WL, and reads 512 bits of data signal from the memory primitive array ARY.

[0129] Then, the memory MEM decodes the lower two bits of the address signal RA0 within the memory array control circuit MEMCNT, sequentially generating the column read signals COL_R[3:0], and outputs the 128-bit data signal in four parts as read data signals Qa, Qb, Qc, and Qd. This output data is then processed by the selector SEL ( ) within the memory cell MU. Figure 5 The data signals read from the memory MEM are output to the read data terminals Q[127:0](o) of the memory unit MU. Thus, all data signals read from the memory MEM can be output to the outside of the memory circuit 100 via a single read instruction RCMD. In the case of the memory MEM, the column read signal COL_R[3:0] is generated by the memory array control circuit MEMCNT, therefore the lower two bits of the address signal RAn are not required.

[0130] In the case of the sub-memory SubMEMb of memory circuit 110, four address signals A (=RA0-RA3) must be generated sequentially for one read instruction RCMD. SubMEMb sequentially selects word lines WL0-WL3 corresponding to address signals RA0-RA3, and selects 128-bit data signals according to column read signals COL_R[3:0] for the 512-bit data signals read from the memory primitives MC connected to each selected word line WL0-WL3. Then, memory block MBLK120 sequentially outputs 128-bit read data signals Qa, Qb, Qc, and Qd for each read instruction RCMD. And, the same word line WL can be selected four times, just like the address signal A received with the read instruction RCMD. In the case of sub-memory SubMEMb, the column read signals COL_R[3:0] are generated by decoding the lower two bits of external address RAn.

[0131] Figure 12 Show Figure 6 , Figure 7 and Figure 8 This illustrates an example of the timing of read and write operations in a memory module (MEM). Figure 12 In the read and write operations shown, we assume a burst length of 4 and a read latency of 1. Figure 12 In the text, the symbol [j] of the character line WL represents any number.

[0132] At the beginning of the timing diagram, while the chip enable signal CEB is high, the memory MEM is set to standby mode, and all word lines WL are deactivated to low. The precharge circuit PRE receives the low-level precharge signal NPCG, which enables the precharge signal, and precharges the bit lines BL and BLB to high.

[0133] The memory MEM, during clock cycle CYC1, receives a low-level chip enable signal CEB and a high-level write enable signal WEB along with the address signal A (=RA0) to identify a read operation. The read cycle occurs 5 clock cycles after the read operation is identified.

[0134] The memory MEM activates the word line WL, indicated by the address signal RA0, to a high level. During the activation of the word line WL, the memory MEM stops the pre-charge operation of the pre-charge circuit PRE on bit line pairs BL and BLB by controlling the pre-charge signal NPCG to a high level, thus setting the bit line pairs BL and BLB to a floating high level. Then, by activating the word line WL, the memory MEM reads the data signal from the 512 memory cells MC into the 512 bit line pairs BL and BLB.

[0135] The 512 data signals read from bit lines BL and BLB do not have sufficient amplitude. Therefore, the memory MEM differentially amplifies each of the 512 data signals using 512 sense amplifiers SA. The memory MEM then latches all 512 data signals amplified by the sense amplifiers SA into read latches RLT (corresponding to each sense amplifier SA in a 1-to-1 manner). Figure 7 In the memory MEM, after latching 512 data signals into the read latch RLT, the word line WL is deactivated, stopping the operation of the sense amplifier SA. Furthermore, the memory MEM precharges the bit lines BL and BLB to a high level by changing the precharge signal NPCG to a low level.

[0136] During clock cycles CYC2-CYC5, the memory array control circuit MEMCNT generates column read signals COL_R[3:0] sequentially, thereby enabling read switches RSW ( Figure 7 The system reads 512 bits of data from the 512 memory cells MC held by the read latch RLT, and outputs them sequentially in 128-bit increments. The data signals sequentially output from the read switch RSW are then buffered by BUF and output as the read data signal Q, ending the read cycle. Figure 12 In this context, the memory MEM sequentially generates four column read signals COL_R[3:0] and outputs the read data signal Q over four clock cycles. However, it is not limited to this; it can also output the read data signal Q over eight or sixteen clock cycles. Furthermore, in... Figure 12 In the process, the initial clock cycle for outputting read data is CYC2, that is, read latency = 1, but it can also be read latency = 2 or 3, for example.

[0137] During the write cycle, the memory MEM, in clock cycle CYC6, receives the low-level chip enable signal CEB and the low-level write enable signal WEB along with the address signal A (=WA0), thus recognizing the write operation. The write cycle continues for 5 clock cycles after the write operation is recognized. When the write cycle is recognized in clock cycle CYC5, the memory MEM sets the precharge signal NPCG high and de-charges the bit lines BL and BLB.

[0138] During clock cycles CYC6 to CYC9, the memory MEM sequentially generates column write signals COL_W[3:0]. The memory MEM, synchronized with each column write signal COL_W[3:0], uses the write selector WSEL ( Figure 8 In each clock cycle, a 128-bit write data signal D is selected and sequentially latched into the corresponding write latch WLT. Each write latch WLT then sequentially outputs the latched data signal to the write buffer WBUF. Figure 8 The data signal D is transmitted to the corresponding bit line pairs BL and BLB to determine the data of the 512 bit line pairs BL and BLB.

[0139] During clock cycle CYC10, the memory MEM activates the word line WL corresponding to the address signal A (=WA0) and writes the logic value of the 512-bit data signal transmitted to each bit line pair BL and BLB to the memory cell MC. After writing the data to the memory cell MC, the memory MEM deactivates the word line WL to a low level and sets the precharge signal NPCG to a low level, thereby precharging the bit line pairs BL and BLB and ending the write cycle.

[0140] exist Figure 12 In the write cycle, four column write signals COL_W[0:3] are generated sequentially, and the write data signal D is latched in the write latch WLT and written to the memory cell MC in four clock cycles. However, it is not limited to this; the write data signal D can also be latched in the write latch WLT in eight or sixteen clock cycles. Additionally, in... Figure 12 In the diagram, the cycle for writing data to the memory cell MC is shown only as the clock cycle following the latching of the write data signal D after all write latches WLT have been completed. However, it is not limited to this; the clock cycle for writing data to the memory cell MC can also be the clock cycle in which the final data is latched, or it can be two clock cycles after the final data is latched. Furthermore, the number of cycles for writing data to the memory cell MC is not limited to one clock cycle; it can also be two or three clock cycles.

[0141] Figure 13 Show Figure 10An example of the timing of read and write operations in the sub-memory (SubMEMb). Regarding... Figure 12 The same actions are described in detail below. The waveforms of the memory clock signal MCLKxN, the chip enable signal CEB, and the write enable signal WEB are similar to... Figure 12 same.

[0142] During the read cycle, the sub-memory (SubMEMb) receives address signals A (RA0-RA3) every four clock cycles (CYC1-CYC4) along with the read instruction RCMD, and selects the word line WL corresponding to address signals RA0-RA3. Even if the same word line WL is selected in each clock cycle (CYC1-CYC4), the activation and deactivation of word line WL need to be repeated every clock cycle. Therefore, the 512 bit line pairs BL and BLB also repeatedly perform data signal read and precharge operations.

[0143] The sub-memory SubMEMb reads the data signal from the 512 memory cells MC into 512 bit pairs BL and BLB each time a word line WL is selected. The memory block MBLK120 decodes the two bits allocated to address signal A to generate column read signals COL_R[3:0]. 128 bits of the 512 data signals read from the memory cells MC are selected sequentially by the column read signals COL_R[3:0] at clock cycles CYC1~CYC4 via the multiplexer MUX and then by the sense amplifier SA. Figure 10 (Enlarge)

[0144] The sub-memory SubMEMb outputs a 128-bit read data signal Q sequentially for each read operation, ending the read cycle. Of the 512 data signals read from the memory cell MC, 384 bits are not output from the memory circuit 110.

[0145] During the write cycle, SubMEMb receives the address signal A (WA0-WA3) and the 128-bit write data signal D along with the write instruction WCMD every 4 clock cycles CYC5-CYC8. SubMEMb first latches the 128-bit write data signal D, and then decodes the 2 bits contained in the address signal A to generate the column write signal COL_W[0:3].

[0146] The sub-memory SubMEMb selects the word line WL corresponding to the address signals WA0-WA3 and reads the 512 bits of data stored in the memory cell MC as data signals to the bit line pairs BL and BLB. On the other hand, the latched 128 bits of write data selectively drive the write buffer corresponding to the column write signal COL_W[0:3] and overwrite the data read into the corresponding bit line pairs BL / BL, thereby writing the data into the memory cell MC. Of the 512 bits of read data, 128 bits are overwritten, and the remaining 384 bits are not used but are precharged along with the inactivation of the word line WL. The same operation is repeated during the four clock cycles of write cycles CYC5 to CYC8, while sequentially activating the write signal COL_W[0:3].

[0147] Figure 14 Show Figure 1 This is an example of the structure of a memory bank control unit (MCNT). The MCNT includes multiple trigger circuits FF (FF1, FF2, FF3, FF4, FF5, FF6, FF7), a relay control unit (RCNT), and multiple mask circuits MSK (MSKC, MSKW1, MSKW2, MSKR). Multiple trigger circuits FF connected to thick signal lines are configured. Signals ending with (i) indicate input signals, and signals ending with (o) indicate output signals.

[0148] The memory clock signals MCLK, MCLKxN, and clock enable signal MCLK_E are provided to buffer BUF1. The memory clock signals MCLK, MCLKxN, and clock enable signal MCLK_E output from buffer BUF1 are then output to the next-stage memory bank control unit MCNT via buffer BUF2. Additionally, the memory clock signals MCLK, MCLKxN output from buffer BUF1 are output as memory clock signals IMCLK, IMCLKxN via buffer BUF3 to their own memory bank MG (the next-stage memory bank MG).

[0149] The memory clock signals MCLK and MCLKxN are also transmitted to the synchronization circuits within the memory bank control unit (MCNT) via buffer BUF1. That is, the synchronization circuits within the MCNT operate synchronously with either the memory clock signal MCLK or the memory clock signal MCLKxN. For example, the memory clock signal MCLK controls the instruction address signal CAWD (control signal CMD and address signal A), and the memory clock signal MCLKxN controls the write data signal D and the read data signal Q.

[0150] Trigger circuit FF1, when the instruction address enable signal CAEN is active, maintains and outputs the received instruction address signal CAWD. The instruction address enable signal CAEN, along with the control signal CMD and the address signal A, is output from the memory control unit 200. Trigger circuit FF2 transmits the instruction address enable signal CAEN received from the memory control unit 200 or the preceding memory group control unit MCNT to the following memory group control unit MCNT.

[0151] Trigger circuit FF3, when the write data enable signal WDEN is active, maintains and outputs the received 128-bit write data signal D[127:0]. The write data enable signal WDEN and the write data signal D are output together from memory control unit 200. Trigger circuit FF4 transmits the write data enable signal WDEN received from memory control unit 200 or the preceding memory group control unit MCNT to the following memory group control unit MCNT.

[0152] The selector SELQ selects between a 128-bit read data signal Q[127:0] read from the preceding memory bank MG or a 129-bit read data signal Q[128:0] transmitted from the preceding memory bank control unit MCNT, based on the level of the control signal from the relay control unit RCNT. The selector SELQ outputs the selected read data signal Q to the trigger circuit FF5. Through the selector SELQ, regardless of the location of the memory bank MG used to perform the read operation and output the read data signal Q, the memory bank control unit MCNT can operate as a relay circuit to transmit the read data signal Q to the memory control unit 200.

[0153] The trigger circuit FF5 operates when the read data enable signal RDEN received from the previous memory bank control unit MCNT is at an active level. For example, the active level of the read data enable signal RDEN is high. The read data enable signal RDEN is output from either the previous memory bank control unit MCNT or a unit prior to the previous memory bank control unit.

[0154] The trigger circuit FF5 receives and holds a 129-bit read data signal Q[128:0] (1 bit is the Last information) from the memory bank control unit MCNT of the previous stage or a 128-bit read data signal Q[127:0] from the memory bank MG of the previous stage via the selector SELQ. The trigger circuit FF5 outputs the held read data signal Q to the mask circuit MSKR.

[0155] Here, the preceding memory group MG refers to the memory group MG that is arranged adjacent to the memory control unit 200 (input side) relative to the memory group control unit MCNT of interest. The operation of the preceding memory group MG is controlled by the memory group control unit MCNT preceding the memory group control unit MCNT of interest.

[0156] The trigger circuit FF6 holds the read data enable signal RDEN received from the preceding memory group control unit MCNT and transmits it to the following memory group control unit MCNT via the OR circuit OR. Furthermore, the initial memory group control unit MCNT does not receive the read data signal Q from its own memory group MG. The second memory group control unit MCNT does not receive the read data signal Q from the other memory group control unit MCNT.

[0157] The trigger circuit FF7 receives and holds the read data enable signal IRDEN output by the relay control unit RCNT, and outputs it to the OR circuit. The read data enable signal IRDEN is set to an active level when reading data signals from its own memory group MG.

[0158] While controlling the operation of the relay control unit RCNT itself, the relay control unit RCNT also controls the operation of the downstream memory group MG. The downstream memory group MG refers to the memory group MG that is disposed adjacent to the memory group control unit MCNT on the output side of the memory control unit 200, and whose operation is controlled by the memory group control unit MCNT.

[0159] The relay control unit RCNT operates based on the logic values ​​of the parameter signals PARAM output from the memory control unit 200 to each memory group control unit MCNT. The memory control unit 200 outputs the parameter signals PARAM, each with a logic value corresponding to the position of the memory group control unit MCNT, to the corresponding memory group control unit MCNT. That is, the parameter signals PARAM have a unique logic value for each memory group control unit MCNT and indicate which segment the memory group control unit MCNT belongs to.

[0160] The relay control unit (RCNT) can detect the memory bank MG performing write or read operations by decoding the instruction address signal CAWD (control signal CMD and address signal A) from the trigger circuit FF1. Upon detecting a write operation in the downstream memory bank MG, the RCNT outputs a low-level chip enable signal CEB, a low-level write enable signal WEB, address A, and a bit write enable signal BWEB to the downstream memory bank MG. The RCNT then generates a chip enable signal CEB and a write enable signal WEB corresponding to the four memory cells MU within the downstream memory bank MG.

[0161] The relay control unit (RCNT), upon detecting a read operation from the downstream memory bank MG, outputs a low-level chip enable signal CEB, a high-level write enable signal WEB, and address A to the memory cell MU to be read. Upon detecting a transition from sleep mode to power-off mode in the downstream memory bank MG, the RCNT outputs a sleep signal SLP and a power-off signal SD of specified logic levels to the controlled memory cell MU. The sleep signal SLP and power-off signal SD are generated corresponding to the four memory cells MU within the downstream memory bank MG.

[0162] The relay control unit (RCNT), upon determining that the downstream memory bank MG has been released from sleep or power-off mode, outputs a low-level sleep signal SLP and a low-level power-off signal SD to the downstream memory bank MG. Here, the release from sleep or power-off mode occurs during a write or read operation.

[0163] For example, in power-off mode, the sleep signal SLP and the power-off signal SD are set to low and high levels, respectively. In sleep mode, the sleep signal SLP and the power-off signal SD are set to high and low levels, respectively. In active mode, both the sleep signal SLP and the power-off signal SD are set to low level.

[0164] Furthermore, when the memory circuit 100 is started, the sleep signal SLP and the power-off signal SD are set to low and high levels respectively, and all memory groups MG are set to power-off mode. Then, only the memory cell MU to be operated is switched from power-off mode to active mode to perform write or read operations. Additionally, if there is no access during the specified period of active mode, the memory cell MU in active mode will be switched to sleep mode under the control of the corresponding memory group control unit MCNT. This allows... Figure 2 The setting value of the register of the memory status management unit 212 is changed to determine the period of transition from active mode to sleep mode.

[0165] Furthermore, memory units (MUs) in sleep or active mode can be switched to power-off mode according to instructions from the memory control unit 200. Thus, memory units (MUs) performing write or read operations are set to active mode, while other memory units (MUs) are set to sleep or power-off mode. By minimizing the number of memory units (MUs) set to active mode, the power consumption of the memory circuit 100 can be reduced.

[0166] The relay control unit RCNT detects the read data signal Q output by the memory group MG (or a memory group upstream of the front end) based on the control signal CMD and address signal A received from the memory group control unit MCNT (front end). When the RCNT receives the read data signal Q from the memory group MG, it uses a selector SELQ to select the read data signal Q transmitted by the memory group control unit MCNT (front end).

[0167] The relay control unit RCNT deactivates the masking state of the masking circuit MSKR when the read data enable signal RDEN is active, and sets the masking circuit MSKR to masking mode when the read data enable signal RDEN is inactive. Therefore, the memory bank control unit MCNT, upon receiving a 128-bit read data signal Q by executing a read operation on the front-end memory bank MG, can relay the read data signal Q to the back-end memory bank control unit MCNT.

[0168] Furthermore, the relay control unit RCNT, when not receiving the read data signal Q from the front end, suppresses the transmission of invalid read data signal Q from the front end to the memory bank control unit MCNT in the back end. Therefore, it is possible to suppress the transmission of invalid read data signal Q between the memory bank control units MCNT on the front end of the memory bank MG performing the read operation, thereby reducing power consumption during the read operation.

[0169] The relay control unit RCNT detects the read data signal Q output by its own memory group MG based on the control signal CMD, address signal A, and instruction address signal CAWD containing additional information received from the front-end memory group control unit MCNT. When the RCNT receives the read data signal Q from its own memory group MG, it outputs a valid read data enable signal IRDEN to the trigger circuit FF7. The trigger circuit FF7 then outputs the read data enable signal IRDEN to the back-end memory group control unit MCNT via the OR circuit.

[0170] The relay control unit RCNT outputs a read data enable signal IRDEN with the same clock cycle as the chip enable signal CEB used to enable the downstream memory bank MG to perform a read operation. Therefore, the read data enable signal IRDEN output from the trigger circuit FF7 is provided to the downstream memory bank control unit MCNT one clock cycle after the start of the read operation of the downstream memory bank MG. Thus, the downstream memory bank control unit MCNT can maintain the read data signal Q received from the corresponding memory bank MG in the trigger circuit FF5.

[0171] In the case of a read operation performed by the memory group MG in the preceding or previous stage, the relay control unit RCNT demasks the mask state of the mask circuit MSKR in order to transmit the read data signal Q to the memory group control unit MCNT of the subsequent stage. During the read operation, the memory group control unit MCNT of the final stage can control the output of the control signal CMD, the address signal A, the instruction address signal CAWD containing additional information, and the read data signal Q to the memory control unit 200.

[0172] Furthermore, when a write operation is performed by the memory group MG in the downstream or subsequent memory group, the relay control unit RCNT demasks the masking state of the masking circuit MSKW1 in order to transmit the write data signal D to the memory group control unit MCNT in the downstream. Conversely, to prevent the write data signal D from being transmitted to its own memory group MG, the masking circuit MSKW2 is set to a masking state.

[0173] The relay control unit (RCNT) demasks the masking circuit MSKC to transmit the control signal CMD, address signal A, and instruction address signal CAWD (containing additional information) to the downstream memory bank control unit (MCNT). Conversely, when a write operation is performed by the downstream or subsequent memory bank MG, the RCNT demasks the MSKC to transmit the control signal CMD, address signal A, and instruction address signal CAWD (containing additional information) to the downstream memory bank control unit MCNT. When a write operation is performed by its own memory bank MG, the RCNT sets the MSKC to a masked state to prevent the transmission of the instruction address signal CAWD to the downstream memory bank control unit MCNT.

[0174] When the relay control unit RCNT performs a write operation on its own memory bank MG, in order to suppress the transmission of the write data signal D to the downstream memory bank control unit MCNT, the mask circuit MSKW1 is set to a mask state. Furthermore, in order to transmit the write data signal D to the memory bank MG, the mask state of the mask circuit MSKW2 is deactivated.

[0175] In the case of a write operation performed by the memory group MG downstream of the preceding segment, the relay control unit RCNT demasks the masked state of the mask circuit MSKW1 in order to transmit the write data signal D to the memory group control unit MCNT downstream of the preceding segment. In the case of a write operation performed by the memory group MG downstream of the preceding segment, the relay control unit RCNT sets the mask circuit MSKW2 to a masked state in order to suppress the transmission of the write data signal D to the memory group MG.

[0176] Figure 15 An example of generating the memory clock signal MCLK from the memory clock signal MCLKxN is shown. For example, each memory group control unit (MCNT) can generate the memory clock signal MCLK by receiving the memory clock signal MCLK and the clock enable signal MCLK_EN from the memory control unit 200, and dividing the frequency of the memory clock signal MCLKxN by 4. In this case, each memory group control unit (MCNT) generates the memory clock signal MCLK synchronously with the rising edge of the memory clock signal MCLKxN that occurs during the high level of the clock enable signal MCLK_EN. Furthermore, the method for generating the memory clock signal MCLK is not limited to... Figure 15 The method shown.

[0177] Figure 16 Show Figure 4 The illustration shows an example of the operational state transition of the memory unit MU. Figure 16 The state transition is managed by the memory group control unit MCNT, which controls the operation of the memory unit MU. However, the process of switching to the power-off mode SD is performed by setting the registers of the memory state management unit 212 of the memory control unit 200.

[0178] and, Figure 16 This illustrates state transitions in units of switching between Power Off Mode (SD), Sleep Mode (SLP), and Active Mode (ACT). Therefore, when the unit of switching between Power Off Mode (SD), Sleep Mode (SLP), and Active Mode (ACT) is the memory bank (MG), Figure 16 This illustrates the state transitions of the memory bank MG. When switching operating modes using memory units MEM within the memory cell MU, Figure 16 The state transitions are shown in units of memory MEM. The following will illustrate an example of control in units of memory MU.

[0179] Figure 1When the memory circuit 100 starts up, all memory cells MUs are set to the power-off mode SD. Memory cells MUs that have generated write or read requests transition from power-off mode SD to active transition mode ATRNS, for example, by turning on the power to the peripheral circuits outside the memory cell area. Then, after a period of power stabilization, the memory cells MUs transition to active mode ACT and perform write or read operations. In active mode ACT, a write or read operation is performed whenever a write or read request is generated by a memory cell MU.

[0180] In Active Mode (ACT), if a non-accessible state without write or read requests persists for a specified period, the memory unit (MU) will transition to Sleep Mode (SLP). Sleep Mode (SLP) is an example of a low-power mode that preserves data within the memory unit (MU) while suppressing power consumption. By switching memory units (MUs) that do not perform write or read operations for a specified period from Active Mode (ACT) to Sleep Mode (SLP), the power consumption of the memory circuitry 100 can be reduced. In Sleep Mode (SLP), memory units (MUs) that have generated write or read requests are transitioned to Active Switching Mode (ATRNS).

[0181] The storage unit MU is switched to shutdown mode SD when a shutdown command is generated in active mode ACT or sleep mode SLP. For example, by receiving... Figure 2 The control signal CNTL is used to set the register of the memory status management unit 212 to issue a shutdown command. Alternatively, depending on the application, it can also be implemented by switching the memory cell MU to shutdown mode SD after the sleep mode SLP has lasted for a predetermined time. In this case, it is possible to... Figure 2 The duration of sleep mode SLP is preset in the register of the overall management unit 210.

[0182] Automatic conversion to shutdown mode (SD) is possible, for example, in the processing of moving images, where frame image data held by memory circuit 100 must be accessed within a certain time, and if it has not been accessed for a certain period of time, it ensures that the data held therein is not used. For instance, when memory access processing is performed at a certain screen size, and the process switches to a smaller screen size while continuing memory access processing, unused memory areas are generated in the memory areas used when processing at the initial screen size. In this case, compared to issuing a shutdown command from the outside, automatically converting to a shutdown signal (SD) based on the duration of sleep mode (SLP) simplifies access control of memory circuit 100.

[0183] Additionally, statistical information such as access frequency can be obtained, and the duration of sleep mode SLP until switching to power-off mode SD can be set based on the obtained statistical information. In this case, an acquisition circuit and a duration calculation circuit are added to the memory control unit 200. The acquisition circuit is used to obtain statistical information such as the time from switching to sleep mode to switching to active mode, the frequency of switching from active mode to sleep mode, and the access frequency in active mode.

[0184] Figures 17 to 21 Show Figure 14 This is an example of the operation of the memory group control unit (MCNT). The relay control unit (RCNT) of the multiple memory group control units (MCNTs) within the memory circuit 100 executes [operations] in each memory cell (MU). Figures 17 to 21 The processing is shown. Additionally, in Figures 17 to 21 The process shown illustrates an example where the switching unit for power-off mode (SD), sleep mode (SLP), and active mode (ACT) is a storage unit (MU).

[0185] First, in step S10, the relay control unit RCNT waits until a positive edge of the system clock signal SCLK is detected, and if a positive edge is detected, it executes step S12. In step S12, if a state transition request is issued, the relay control unit RCNT executes step S100 (state transition processing); otherwise, it executes step S14. An example of step S100 is shown below. Figure 18 As shown.

[0186] A state transition request refers to an activation command to switch to active mode (ACT), a sleep command to switch to sleep mode (SLP), or a shutdown command to switch to power-off mode (SD). For example, when the memory cell MU to be accessed is in power-off mode (SD) or sleep mode (SLP), an activation command is issued by the corresponding relay control unit (RCNT) based on a write request or read request. A shutdown command is issued by the memory control unit (200) based on a request sent to the memory circuit 100 via the system bus (SBUS). A sleep command is issued by the corresponding relay control unit (RCNT) when switching the memory cell MU from active mode (ACT) to sleep mode (SLP). Alternatively, a sleep command can be issued by the memory control unit (200) based on a request sent to the memory circuit 100 via the system bus (SBUS).

[0187] In step S14, if a read request is issued, the relay control unit (RCNT) executes step S200 (read operation); if no read request is issued, it executes step S16. An example of step S200 is shown below. Figure 19 and Figure 20As shown. In step S16, if a write request is issued, the relay control unit (RCNT) executes step S300 (write operation); if no write request is issued, it returns to step S10. An example of step S300 is shown below. Figure 21 As shown.

[0188] In step S100, the relay control unit (RCNT) executes... Figure 18 The state transition process is shown, and the process returns to step S10. In step S200, the relay control unit RCNT executes... Figure 19 and Figure 20 The read process is shown, and the process returns to step S10. In step S300, the relay control unit RCNT executes... Figure 21 The write process is shown, and the process returns to step S10.

[0189] Figure 18 Show Figure 17 An example of step S100 (state transition processing). First, in step S102, the relay control unit RCNT determines whether the address signal A received along with the state transition instruction represents its own memory group MG. The own memory group MG refers to the memory group MG that the memory group control unit MCNT is accessing when performing a write or read operation. If the address signal A represents its own memory group MG, the relay control unit RCNT executes step S104; if the address signal A does not represent its own memory group MG, it executes step S116.

[0190] In step S104, if the state transition command is an activation command or a sleep deactivation command, the relay control unit RCNT executes step S106. If the state transition command is not an activation command or a sleep deactivation command, the relay control unit RCNT executes step S108.

[0191] In step S106, the relay control unit RCNT outputs a low-level (L) sleep signal SLP and a low-level power-off signal SD to the memory unit MU of the active target represented by the address signal A. As a result, the memory unit MU of the active target is switched to the active mode ACT. After step S106, step S114 is executed.

[0192] In step S108, the relay control unit RCNT executes step S110 if the state transition instruction is a sleep instruction, and executes step S112 if the state transition instruction is not a sleep instruction.

[0193] In step S110, the relay control unit RCNT outputs a high-level (H) sleep signal SLP and a low-level power-off signal SD to the memory unit MU of the active object (the object to be converted to active mode ACT) represented by address signal A. As a result, the memory unit MU of the active object is converted to sleep mode SLP. After step S110, step S114 is executed.

[0194] In step S112, the relay control unit RCNT outputs a low-level sleep signal SLP and a high-level power-off signal SD to the memory unit MU of the active target represented by address signal A. As a result, the memory unit MU of the active target is switched to the power-off mode SD. After step S112, step S114 is executed.

[0195] In step S114, the relay control unit RCNT sets the mask circuit MSKC to mask mode, suppressing the transmission of control signal CMD and address signal A to the downstream memory bank control unit MCNT, thus ending the process. Figure 18 The process is shown. On the other hand, in step S116, the relay control unit RCNT sets the mask circuit MSKC to the mask-off state, allowing the control signal CMD and the address signal A to be transmitted to the downstream memory bank control unit MCNT, thus ending the process. Figure 18 The processing shown.

[0196] Figure 19 Show Figure 17 An example of step S200 (read operation). First, in step S202, the relay control unit RCNT determines whether the address signal A received along with the read request signal indicating a read request represents its own memory group MG. If the address signal A represents its own memory group MG, the relay control unit RCNT executes step S204; if the address signal A does not represent its own memory group MG, it executes step S210.

[0197] In step S204, the relay control unit RCNT outputs a low-level chip enable signal CEB to the memory cell MU represented by address signal A as the read target. The relay control unit RCNT also outputs a high-level chip enable signal CEB to the memory cell MU that is not being read.

[0198] Next, in step S206, the relay control unit RCNT outputs a high-level write enable signal WEB and a high-level bit write enable signal BWEB to its own memory group MG. The relay control unit RCNT also outputs the address signal A, which it receives along with the control signal CMD, to its own memory group MG.

[0199] Next, in step S208, the object relay control unit RCNT corresponding to the memory group MG to be read outputs a high-level read data enable signal RDEN. The object relay control unit RCNT causes the selector SELQ to select an invalid read data signal Q from the front-end memory group control unit MCNT. Here, the relay control unit RCNT can also cause the selector SELQ to select an invalid read data signal Q from the front-end memory group MG. After step S208, step S220 is executed.

[0200] In step S210, the relay control unit RCNT outputs a high-level chip enable signal CEB, a high-level write enable signal WEB, and a high-level bit write enable signal BWEB to each memory cell MU. The relay control unit RCNT also outputs a low-level address signal A to each memory cell MU. By preventing changes in the logic level of the address signal A, power consumption during read operations can be reduced.

[0201] In step S212, the relay control unit RCNT determines whether the address signal A received along with the read request signal represents the memory group MG on the front end (front end or before the front end). If the address signal A represents the memory group MG on the front end, the relay control unit RCNT executes step S214; if the address signal A does not represent the memory group MG on the front end, the relay control unit RCNT executes step S216.

[0202] In step S214, the relay control unit RCNT outputs a low-level read data enable signal RDEN. Furthermore, the relay control unit RCNT causes the selector SELQ to select either the read data signal Q from the front-end memory group MG or the read data signal Q from the front-end memory group control unit MCNT. This allows the read data signal Q read from any one of the memory cells MU of the front-end memory group MG to be transmitted to the back-end. Additionally, the relay control unit RCNT receives the high-level read data enable signal RDEN output from the front-end memory group control unit MCNT via the OR circuit OR and transmits it to the back-end memory group control unit MCNT. After step S214, step S220 is executed.

[0203] In step S216, the relay control unit RCNT outputs a low-level read enable signal RDEN. Additionally, the relay control unit RCNT causes the selector SELQ to select an invalid read data signal Q from the front-end memory group control unit MCNT. Furthermore, the relay control unit RCNT can also cause the selector SELQ to select an invalid read data signal Q from the front-end memory group MG. After step S216, step S220 is executed.

[0204] In step S220, the relay control unit RCNT sets the mask state of the mask circuits MSKC and MSKR, and then ends the process. Figure 12 The actions shown.

[0205] Figure 20 Show Figure 19 An example of step S220. First, in step S222, the relay control unit RCNT sets the mask circuit MSKC to the mask de-mask state, allowing the control signal CMD and the address signal A to be transmitted to the downstream memory bank control unit MCNT.

[0206] Next, in step S224, the relay control unit RCNT determines whether the front-end memory group MG has performed the read operation based on the address signal A received along with the read request signal. If the front-end memory group MG performs the read operation, step S226 is executed. If the front-end memory group MG does not perform the read operation, step S228 is executed.

[0207] In step S226, the relay control unit RCNT sets the mask circuit MSKR to the mask-off state, so that the read data signal Q from the front-end memory group MG or the read data signal Q from the front-end memory group control unit MCNT can be transmitted to the back-end. After step S226, step S230 is executed.

[0208] In step S228, the relay control unit RCNT sets the mask circuit MSKR to mask state because the read data signal Q from the front-end memory group MG or the read data signal Q from the front-end memory group control unit MCNT is not transmitted. By suppressing the transmission of invalid read data signals Q, power consumption during the read operation can be reduced. After step S228, step S230 is executed.

[0209] In step S230, the relay control unit RCNT sets the mask circuits MSKW1 and MSKW2 to mask state, and the process ends. Figure 20 The operation. By suppressing the transmission of invalid write data signal D and invalid write data signal D', power consumption can be reduced.

[0210] Figure 21 Show Figure 17 Here is an example of step S300 (write operation). First, in step S302, the relay control unit RCNT determines whether the address signal A received along with the write request signal represents its own memory group MG. If the address signal A represents its own memory group MG, the relay control unit RCNT executes step S304; if the address signal A does not represent its own memory group MG, it executes step S312.

[0211] In step S304, the relay control unit RCNT outputs a low-level chip enable signal CEB and a low-level write enable signal WEB to the memory cell MU represented by the address signal A, indicating the target to be written. The relay control unit RCNT outputs a high-level chip enable signal CEB and a high-level write enable signal WEB to the memory cell MU that is not being written to.

[0212] Secondly, in step S306, the relay control unit RCNT outputs the address signal A, which is received together with the bit write enable signal BWEB contained in the control signal CMD and the control signal CMD, to its own memory group MG.

[0213] Next, in step S308, the relay control unit RCNT outputs a low-level read enable signal RDEN. The relay control unit RCNT causes the selector SELQ to select an invalid read data signal Q from the front-end memory group control unit MCNT. Alternatively, the relay control unit RCNT can also cause the selector SELQ to select an invalid read data signal Q from the front-end memory group MG.

[0214] Next, in step S310, the relay control unit RCNT sets the mask circuits MSKC and MSKW1 to the mask state and sets the mask circuit MSKW2 to the mask de-masking state, thus ending the process. Figure 21 The operation involves several steps. By setting the mask circuit MSKC to mask mode, the transmission of the back-end control signal CMD and address signal A, which are unrelated to the write operation, can be suppressed, thus reducing power consumption during the write operation. Similarly, by setting the mask circuit MSKW1 to mask mode, the transmission of the write data signal D to subsequent memory cells can be suppressed, thereby reducing power consumption during the write operation. Finally, by setting the mask circuit MSK2 to mask-off mode, the write data signal D can be transmitted to the memory cell MU to be written to.

[0215] In step S312, the relay control unit RCNT outputs a high-level chip enable signal CEB, a high-level write enable signal WEB, and a high-level bit write enable signal BWEB to each memory cell MU. The relay control unit RCNT outputs a low-level address signal A to each memory cell MU. Thus, with... Figure 19 Similarly, step S210 can reduce power consumption during write operations.

[0216] Next, in step S314, the relay control unit RCNT outputs a low-level read enable signal RDEN. The relay control unit RCNT causes the selector SELQ to select an invalid read data signal Q from the front-end memory group control unit MCNT. Additionally, the relay control unit RCNT can also cause the selector SELQ to select an invalid read data signal Q from the front-end memory group MG.

[0217] Next, in step S316, the relay control unit RCNT sets the mask state or mask de-masking state of the mask circuits MSKC, MSKR, MSKW1, and MSKW2. First, the relay control unit RCNT sets the mask circuit MSCR to the mask state. Second, the relay control unit RCNT determines whether the front-end memory group MG should perform a write operation based on the address signal A received along with the write request signal.

[0218] When the front-end memory group MG performs a write operation, the relay control unit RCNT sets the mask circuits MSKC, MSKW1, and MSKW2 to the masked state. When the front-end memory group MG does not perform a write operation, the relay control unit RCNT sets the mask circuits MSKC and MSKW1 to the mask-off state and sets the mask circuit MSKW2 to the masked state. Then, the relay control unit RCNT terminates. Figure 21 The operation. Without transmitting access request signals and write data signals D to the back end, by setting the mask circuits MSKC and MSKW1 to mask state, the power consumption during the write operation can be reduced.

[0219] Figure 22 Show Figure 1 An example of the action used in the memory circuit 100 to convert the memory cell MU into the active mode ACT. Figure 22 The description explains the actions taken when the memory cell MU shown by the halftone lines within memory group MG2 is switched to active mode. The memory cell MU shown by the halftone lines within memory group MG2 is also called the object memory cell MU (described as the active object MU in the diagram). Figure 22 The diagram only shows the signals used when switching to Active Mode (ACT).

[0220] When the memory control unit 200 receives an access request signal (write request signal or read request signal) in power-off mode SD, it outputs a state transition request to switch the accessed memory cell MU from power-off mode SD to active mode ACT. Additionally, when the memory control unit 200 receives an access request signal in sleep mode SLP, it outputs a state transition request to switch the accessed memory cell MU from sleep mode SLP to active mode ACT.

[0221] The memory group control unit MCNT, according to the instructions from the memory control unit 200, outputs a low-level power-off signal SD and a low-level sleep signal SLP to the corresponding memory cell MU if it is a memory state transition request for the memory cell MU in its own memory group MG.

[0222] The memory control unit 200 outputs a state transition request to the initial memory group control unit MCNT1 to set the target memory unit MU to an active state. Based on the address signal A included in the state transition request, the memory group control unit MCNT1 determines that the memory unit MU in its own memory group MG1 is not the target memory unit MU. Therefore, the memory group control unit MCNT1 transmits the state transition request to the subsequent memory group control unit MCNT2.

[0223] Based on the address signal A included in the state transition request, the memory group control unit MCNT2 determines that the memory cell MU contained in its own memory group MG2 is the target memory cell MU. Then, the memory group control unit MCNT2 outputs a low-level sleep signal SLP and a low-level power-off signal SD to the target memory cell MU of the memory group MG2. Furthermore, since the memory group control unit MCNT2 determines that the memory cell MU in its own memory group MG2 contains the target memory cell MU, it does not transmit the state transition request to the subsequent memory group control units MCNT3 and MCNT4.

[0224] Figure 23 and Figure 24 Show conversion Figure 22 An example of the timing of signals during the ACT (Activity Activity) mode. Figure 23 and Figure 24 In the middle, it is shown that... Figure 22 The diagram illustrates the timing waveforms of various signals corresponding to the actions described. Figure 23 , Figure 24 In the timing diagrams described later, the symbol (i) at the end of a signal indicates an input signal to the target circuit, and the symbol (o) at the end of a signal indicates an output signal from the target circuit. Hereinafter, symbols will sometimes be used to describe signals instead of their names. Figure 23 The signal names shown in the waveforms of subsequent timing diagrams may sometimes differ from those described above. For example, the symbol ID represents instruction signals for various instructions, ADR represents address signal A, and ETC represents other control signals. In the attached diagram, AWID(i), AWetc(i), and AWVLD(i) represent the request signal REQ from the system bus SBUS. The symbol AWA(i) represents the address signal ADR from the system bus SBUS. The symbol AWRDY(o) represents the acknowledgment signal for the system bus SBUS.

[0225] Figure 2The system bus input control unit 202 detects the validity of the AWID, AWA, and AWetc signals provided by the system bus SBUS, which are examples of the request signal REQ and address signal ADR, based on the high-level AWVLD signal (an example of the request signal REQ and address signal ADR) input from the system bus SBUS. The AWID signal contains information for identifying the state transition request, the AWA signal indicates the address used in the state transition request, and the AWetc signal indicates additional information used in the state transition request.

[0226] The system bus input control unit 202 stores (pushes) the CAWD signal (data) containing the control signal CMD and address A in buffer 204. The control signal CMD is a control signal containing additional information converted from the AWID, AWA, and AWetc signals received during the high level of the AWVLD signal. Address A is a 512-bit information unit used as an access unit for a memory region. After confirming the empty state of buffer 204 based on the low-level CAFULL signal, the system bus input control unit 202 outputs a high-level AWRDY signal (acknowledgment signal) indicating acceptance of a state transition request to the system bus SBUS. When there is no empty space in buffer 204, the CAFULL signal is set to high. The CAPUSH signal indicates the timing of storage in buffer 204.

[0227] The input interface control unit 214 confirms the information held in the buffer 204 and detects the memory unit MU to which the state transition is to occur based on the address information. The input interface control unit 214 receives the MST signal of the state of the memory unit MU to which the state transition is to occur from the memory state management unit 212.

[0228] For example, suppose the MST signal is in the power-off state (SD) or the sleep state (SLP). In this case, the input interface control unit 214 outputs a change command to the active state and information indicating the memory cell MU to be activated to the initial memory group control unit MCNT1. The change command to the active state and the information indicating the memory cell MU to be activated are output to the memory group control unit MCNT1 as a CAWD signal, synchronized with the high level of the CAEN signal.

[0229] A change command to the active state is also output to the memory state management unit 212. In the next clock cycle after receiving the change command, the memory state management unit 212 changes the MST signal from the power-off state SD to the transition state TOACT for changing to the active mode ACT. Furthermore, after time T1 has elapsed, the memory state management unit 212 sets the MST signal to the active state ACT.

[0230] exist Figure 24 In the text, the symbol (A) represents... Figure 23 The timing of the symbol (A). The physical distance from the output of the input interface control unit 214 to the input of the memory group control unit MCNT1. Therefore, the signal output from the input interface control unit 214 arrives at the memory group control unit MCNT1 after time Td. In this example, the memory cell MU of the object of the state transition is included in the memory group MG at the end of the memory group control unit MCNT2 and is controlled by the memory group control unit MCNT2. Therefore, the memory group control unit MCNT1 transmits the CAWD signal to the memory group control unit MCNT2 as a CAWD signal one clock cycle after receiving the CAWD signal indicating that the received change command to the active state.

[0231] The memory bank control unit MCNT2 detects that the memory cell MU within its own memory bank MG is an active target based on the address contained in the received CAWD signal. Then, MCNT2 sets the power-off terminal SD of the active memory cell MU from high to low, thus switching it to an active state. Furthermore, since the active memory cell MU is detected, MCNT2 masks the output of the CAWD(o) and CAEN(o) signals of the subsequent memory bank control unit MCNT3, preventing their transmission.

[0232] Figure 25 Show Figure 1 An example of a write operation in the memory circuit 100. Regarding... Figure 22 The same actions are described in detail, omitting further explanation. Figure 25 The operation of writing data to the memory cell MU of the object to be written, as shown in the net effect within the memory group MG2, will be explained.

[0233] The memory control unit 200, upon receiving a write request signal, such as Figure 2 As explained, the 512 bits of the set of up to 8 write data signals WD (e.g., 64 bits) received via the system bus SBUS, and the 1 bit of the LAST signal (described below, unless otherwise specified) are stored sequentially. Figure 2 In the buffer 206. Additionally, the memory control unit 200, when the memory cell MU containing the memory primitive MC containing the write target is in a power-off state, such as... Figure 22 As shown, after the object storage unit (MU) is switched to an active state, the following steps are implemented. Figure 25 The actions shown.

[0234] The memory control unit 200, for example, outputs a 512-bit write data signal D to the data conversion unit PSCNV, converting it into four 128-bit serially linked write data signals D. These four serially linked write data signals D, along with the control signal CMD and the address signal A, are provided to the initial memory group control unit MCNT1. Based on the received address signal A, the memory group control unit MCNT1 determines that its own memory group MG1 is not the target for writing. Therefore, the memory group control unit MCNT1 transmits the control signal CMD, the address signal A, and the write data signals D to the subsequent memory group control unit MCNT2.

[0235] The memory bank control unit MCNT2 determines that its own memory bank MG2 is the target memory bank based on the received address signal A. Then, MCNT2 outputs a control signal CMD and an address signal A to the target memory cell MU. Additionally, MCNT2 sequentially outputs four 128-bit write data signals D to the target memory cell MU. Finally, it writes data to the target memory cell MC.

[0236] like Figure 25 As shown, since the address signal received along with the write request signal represents its own memory group MG, the memory group control unit MCNT2 masks the transmission of the control signal CMD, address signal A, and write data signal D of the subsequent memory group control unit MCNT3. Each memory group control unit MCNT transmits the write request signal and address signal to the subsequent memory group control unit MCNT when the address signal received along with the write request signal does not represent its own memory group MG.

[0237] Therefore, for example, compared to the case where the control signal CMD, address signal A, and write data signal D are jointly supplied to each memory bank MG, the charging and discharging currents of the control line CMD, address line A, and write data line D can be suppressed. As a result, the increase in access time of the memory circuit 100 can be suppressed while the increase in dynamic power can be suppressed.

[0238] Figure 26 and Figure 27 Show Figure 25 An example of the timing of the signal during a write operation. Regarding... Figure 23 and Figure 24 The same actions are omitted in detail. Figure 26 and Figure 27 The middle shows with Figure 25 The timing waveforms of various signals corresponding to the write operation are described in the text.

[0239] Figure 2The system bus input control unit 202 detects whether a valid WDATA signal (data) is provided based on a high-level WVLD signal. The WDATA signal includes data written to the memory cell MC via a write operation and the write address, etc.

[0240] The system bus input control unit 202 pre-stores the DWATA signal received during the high level of the WVLD signal internally, and aggregates up to 8 data signals into 512 bits and stores (push) them into buffers 204 and 206. After confirming that there is space in buffers 204 and 206 based on the low level of the WFULL signal, the system bus input control unit 202 outputs a high level WRDY signal (acknowledgment signal) indicating that a write request has been accepted to the system bus SBUS.

[0241] The WPUSH signal indicates the timing of data writes, such as data signals, being stored in buffers 204 and 206. In this embodiment, whenever eight 64-bit data signals are received from the system bus SBUS, a total of 512 bits of data signals are stored in buffer 206. At this time, the WLAST signal from the system bus SBUS, indicating that the data signal is the last one, is stored in buffer 204. The "not-last" in the data write signal D indicates that the data is not the final data, while "last" indicates that the data is the final data.

[0242] When the input interface control unit 214 detects a write request from the information held in buffer 204, it reads the control signal CMD, the address signal A, and the write data signal D from buffers 204 and 206. The input interface control unit 214 determines whether this is the final write data signal D based on the last and not-last values ​​in WDRD. In this example, the case where two 512-bit write data signals D are obtained from buffer 206 is shown.

[0243] The input interface control unit 214 generates CAWD, CAEN, D, and WDEN signals based on the control signal CMD, address signal A, and write data signal D read from buffers 204 and 206. The input interface control unit 214 outputs the CAWD, CAEN, and WDEN signals to the initial memory group control unit MCNT1, and outputs the write data signal D to the data conversion unit PSCNV.

[0244] exist Figure 27 In the text, the symbol (B) represents... Figure 26The timing of symbol (B). The memory bank control unit MCNT1 receives the signal output from the input interface control unit 214 after time Td. Based on the received control signal CMD and address signal A, the memory bank control unit MCNT1 determines that the memory bank MG is not a write access target. Therefore, the memory bank control unit MCNT1 transmits the signal received from the input interface control unit 214 to the subsequent memory bank control unit MCNT2.

[0245] The memory group control unit MCNT1, synchronized with the memory clock signal MCLKxN, receives four write data signals D output from the input interface control unit 214 in 128-bit units. Synchronously with the memory clock signal MCLKxN, the memory group control unit MCNT1 transmits the received four write data signals D to the memory group control unit MCNT2. The symbols D1-D8 representing the write data signals D indicate that... Figure 2 The system bus input control unit 202 sequentially receives eight write data signals WD. That is, each of the four 128-bit write data signals D contains the data of two write data signals WD.

[0246] The memory group control unit MCNT2 detects that the memory cell MU within its own memory group MG is the target for writing based on the received control signal CMD and address signal A. Furthermore, the memory group control unit MCNT2 sets the CEB and WEB terminals of the target memory cell MU to low level. In addition, the memory group control unit MCNT2 receives four write data signals D sequentially, synchronously with the memory clock signal MCLKxN.

[0247] The memory group control unit MCNT2 outputs address A and bit write enable signal BWEB to the A and BWEB terminals of the memory cell MU to be written to, and synchronously with the memory clock signal MCLKxN, outputs four write data signals D sequentially to the D terminal of the memory cell MU to be written to. Therefore, data is written to the memory cell MC of the memory cell MU to be written to. Since the address signal A received along with the write request signal represents its own memory group MG, the memory group control unit MCNT2 masks the transmission of the subsequent memory group control unit MCNT3 signals CAWD(o), CAEN(o), D(o), and WDEN(o).

[0248] Figure 28 Show Figure 1 An example of a read operation of the memory circuit 100. Regarding... Figure 22 and Figure 25 The same actions are described in detail, omitting further explanation. Figure 28The section explains the operation of reading data from the storage unit MU of the object to be read, as shown by the inner net shadow of the memory group MG2.

[0249] The memory control unit 200, upon receiving a read request, performs the same actions as when a write request is received, except when the write data signal D is not received. Furthermore, when the memory cell MU containing the memory element MC to be read is in a powered-off state, such as... Figure 22 As shown, after the memory control unit 200 converts the object storage unit MU (shown as the active object MU in the figure) to an active state, it performs... Figure 28 The actions shown.

[0250] The memory control unit 200 (output side) outputs the control signal CMD and the address signal A to the initial memory group control unit MCNT1. Based on the received address signal A, the memory group control unit MCNT1 determines that its own memory group MG1 is not the target memory. Therefore, the memory group control unit MCNT1 transmits the control signal CMD and the address signal A to the subsequent memory group control unit MCNT2.

[0251] The memory bank control unit MCNT2 determines that its own memory bank MG2 is the target memory bank based on the received address signal A. MCNT2 then outputs the control signal CMD and the address signal A to each memory cell MU of the target memory bank. Next, it reads the read data signal Q from the memory cell MC of the target memory bank and outputs it to the subsequent memory bank control unit MCNT3.

[0252] The memory group control unit MCNT3 transmits the received control signal CMD, address signal A, and read data signal Q to the subsequent memory group control unit MCNT4. The memory group control unit MCNT4 then transmits the received control signal CMD, address signal A, and read data signal Q to the subsequent memory group control unit MCNT5. Based on the received control signal CMD and address signal A, the memory group control unit MCNT5 outputs the received read data signal Q to the memory control unit 200 (output side) via the data conversion unit SPCNV.

[0253] The data conversion unit SPCNV converts the four sequentially received 128-bit read data signals Q into 512-bit read data signals Q and outputs them to the memory control unit 200. The memory control unit 200 then divides the received 512-bit read data signals Q into multiple serial read data signals DT (e.g., 64 bits) and outputs them.

[0254] The read data lines for transmitting the read data signal Q are wired for each memory group MG and are sequentially electrically connected via the memory group control unit MCNT. Therefore, when memory group MG2 performs a read operation, the read data signal Q is not transmitted to the read data lines of memory group MG1, which is located further forward than memory group MG2. This reduces the dynamic power of memory block MBLK during read operations compared to a situation where all memory groups MG share a common read data line.

[0255] During a read operation, the memory block MBLK receives an access request signal from the memory control unit 200 (input side) and outputs a read data signal Q to the memory control unit 200 (output side). Therefore, regardless of the access location, the sum of the lengths of the signal lines transmitting the access request signal from the memory control unit 200 to the memory group MG to be read and the lengths of the signal lines transmitting the read data signal Q to the memory control unit 200 can be kept approximately constant. As a result, the phenomenon of read access time varying with the location of the memory group MG performing the read operation can be suppressed.

[0256] Each memory bank control unit (MCNT) outputs a read request signal to its own memory bank (MG) when the address signal A included in the read request signal represents its own memory bank (MG). If the address signal included in the read request signal represents a memory bank other than its own MG, the MCNT transmits the read request signal to the subsequent memory bank control unit (MCNT).

[0257] Figures 29 to 32 Show Figure 28 An example of the timing of the signal during a read operation. Regarding... Figure 23 , Figure 24 , Figure 26 and Figure 27 The same actions are omitted in detail. Figures 29 to 32 In the middle, it is shown that... Figure 28 The diagram illustrates the timing waveforms of various signals corresponding to the read operation. The symbols ARID(i), ARetc(i), and ARVLD(i) represent the request signal REQ from the system bus SBUS. The symbol ARAD(i) represents the address signal ADR from the system bus SBUS. The symbol ARRDY(o) represents the acknowledgment signal for the system bus SBUS.

[0258] exist Figure 29 middle, Figure 2The system bus input control unit 202 stores (pushes) the CAWD signal (data) containing the control signal CMD and address A in the buffer. The control signal CMD is a control signal containing additional information, derived from the request signal REQ received from the system bus SBUS during the high level of the ARVLD signal (an example of the request signal REQ and address signal ADR) input from the system bus SBUS, and the ARID signal (instruction), ARAD signal (address), and ARetc signal (other signals), which are examples of the address signal ADR. Address A indicates a storage purpose of 512 bits (four 128-bit units) as the access unit for the memory region. After confirming that the buffer 204 is empty based on the low-level CAFULL signal input from the system bus SBUS, the system bus input control unit 202 outputs a high-level ARRDY signal (acknowledgment signal) indicating that a read request has been received to the system bus SBUS. The CAPUSH signal indicates the storage timing when the read request signal and other information contained in the read request are stored in the buffer 204.

[0259] When an input interface control unit 214 detects a read request from the information held in buffer 204, it reads control signals CMD and address signals A from buffer 204. Based on the control signals CMD and address signals A read from buffer 204, the input interface control unit 214 outputs information for read access to the initial memory group control unit MCNT1. For example, the signals output for use during read access are CAWD, CAEN, and WDEN. Furthermore, the write data line D is not used during the read operation.

[0260] Read requests are categorized into two cases: one where the burst length of the number of outputs of the read data signal RD is relatively large compared to a single read request, and another where a single access to the memory unit MU cannot be completed. In this case, the input interface control unit 214 generates a second or subsequent read request. "Not-last" in CAWD indicates that the read request is not the final request, and "last" indicates the final request. Furthermore, it is assumed that four 128-bit read data signals Q are read through a single burst operation.

[0261] exist Figure 30 In the text, the symbol (A) represents... Figure 29 The timing of symbol (A) in the code. The memory bank control unit MCNT1 receives the signal output from the input interface control unit 214 after time Td. Based on the received control signal CMD and address signal A, the memory bank control unit MCNT1 determines that the memory bank MG is not a read access target. Therefore, the memory bank control unit MCNT1 transmits the signal received from the input interface control unit 214 to the subsequent memory bank control unit MCNT2.

[0262] The memory bank control unit MCNT2 detects that the memory cell MU within its own memory bank MG is the target for reading based on the received control signal CMD and address signal A. Furthermore, the memory bank control unit MCNT2 sets the CEB terminal of the target memory cell MU to a low level and the WEB terminal to a high level. Additionally, the memory bank control unit MCNT2 outputs address A to the A terminal of the target memory cell MU. Therefore, four 128-bit data bytes are sequentially read from the memory cell MC of the target memory cell MU.

[0263] In order to transmit the read data signal Q to the subsequent memory group control unit MCNT2, the memory group control unit MCNT2 generates a read data enable signal IRDEN. Figure 14 The read data enable signal IRDEN is output to the memory group control unit MCNT3 as the read data enable signal RDEN.

[0264] Additionally, the memory group control unit MCNT2 sequentially transmits four 128-bit read data signals Q, read from memory cell MU, to the memory group control unit MCNT3 synchronously with the memory clock signal MCLKxN. The symbols Q1-Q8 marked on the Q terminals of the read target MU indicate... Figure 2 The system bus output control unit 226 sequentially outputs eight read data signals RD. That is, each of the four 128-bit read data signals Q contains the data of two read data signals RD.

[0265] When the burst length is 8, two pulses of the read data enable signal RDEN are generated, and the memory group control unit MCNT2 transmits four 128-bit read data signals Q to the memory group control unit MCNT3 in sequence for each pulse of the read data enable signal RDEN.

[0266] During the read operation, the read data signal Q read from the memory cell MU is converted from series to parallel by the system bus output control unit 226 and output as the read data signal RD to the system bus SBUS. Therefore, the memory group control unit MCNT2 outputs the received control signal CMD and address signal A together with the read data signal Q to the memory group control unit MCNT3.

[0267] exist Figure 31 In the text, the symbols (B), (C), and (D) represent... Figure 30The timing of symbols (B), (C), and (D) in the diagram. The memory group control unit MCNT3 receives the signal output from the memory group control unit MCNT2 after time Td. The memory group control unit MCNT3 transmits the received control signal CMD, address signal A, and read data signal Q to the memory group control unit MCNT4. The memory group control unit MCNT4 transmits the received control signal CMD, address signal A, and read data signal Q to the memory group control unit MCNT5. The memory group control unit MCNT5 outputs the received control signal CMD and address signal A to the memory control unit 200, and sequentially outputs the received read data signal Q to the data conversion unit SPCNV.

[0268] exist Figure 32 In the text, the symbols (E) and (F) represent... Figure 31 The timing of symbols (E) and (F) in the data conversion unit SPCNV. During each burst operation, the data conversion unit SPCNV sequentially adds the four 128-bit read data signals Q received to form a 512-bit read data signal Q, which is then output to the memory control unit 200. The output interface control unit 220 of the memory control unit 200 stores (push) the received control signal CMD and address signal A into buffer 222, and stores (push) the read data signal Q received from the data conversion unit SPCNV into buffer 224.

[0269] The system bus output control unit 226 of the memory control unit 200 waits for buffers 222 and 224 to become readable (active) by referring to the CRAVLD signal output from buffer 222 and the RDVLD signal output from buffer 224. When buffers 222 and 224 become readable and the system bus SBUS is in a ready state (RRDY=H), the system bus output control unit 226 generates RID and RDATA signals for output to the system bus SBUS. The RID and RDATA signals are generated using the control signal CMD and address signal A held in buffer 222, and the read data signal Q held in buffer 224, to generate a read data signal RDATE (an example of the read data signal RD) and additional information RID and RLAST for the system bus side.

[0270] Additionally, the system bus output control unit 226 sets the RVLD signal, indicating that the output signal to the system bus SBUS is valid, to an active level (RVLD=H). Compared to the data signal read from the memory block MBLK, which is in 512-bit units, the read data signal on the system bus SBUS side is in 64-bit units. Therefore, the read data signal is output to the system bus SBUS in a maximum of 8 parts. When the CRAPOP and RDPOP signals are set to active level (H), the next control signal CMD, address signal A, and read data signal Q are output to buffers 222 and 224.

[0271] exist Figure 32 In the example shown, the system bus output control unit 226 sequentially selects 512-bit read data signals Q read from the memory block MBLK in a manner matching the 64-bit data bus width on the system bus SBUS side. Data signals Q1.1 to Q1.8, from the initial 64-bit data signals, are output to the system bus SBUS over eight clock cycles. Similarly, for the next 512-bit read data signal Q from the memory block MBLK, data signals Q2.1 to Q2.8 are also output to the system bus SBUS over eight clock cycles. Furthermore, when outputting the final read data signal Q2.8, the system bus output control unit 226 sets RLAST to an active level (e.g., high level) to complete the read operation.

[0272] Figures 33 to 36 Show Figure 1 Another example of the timing of the signal during the read operation of the memory circuit 100. Figures 33 to 36 This illustrates an example of issuing a read request to a memory cell MU in memory group MG1 after a read request has been issued to a memory cell MU in memory group MG4.

[0273] Figures 33 to 36 The actions of each circuit element, besides issuing two read requests sequentially, are related to... Figures 29 to 32 The circuit elements shown operate in the same way. In other words, Figures 33 to 36 In the middle, the actions for each read request are related to... Figures 29 to 32 The actions shown are the same.

[0274] In this embodiment, access request signals, write data signals D, and read data signals Q can be transmitted between memory group control units (MCNTs) via pipelines. Therefore, for example, before outputting a read data signal Q in response to a read request from memory block MBLK, other read requests can be sequentially provided to memory block MBLK. Thus, as... Figures 33 to 36 As shown, in the next clock cycle after a read access to memory group MG4, a read access to memory group MG1 can be performed.

[0275] In the first embodiment, the data conversion unit PSCNV converts the 512-bit write data signal D into four 128-bit write data signals D and supplies them to the memory block MBLK. Therefore, compared to the case where the data conversion unit PSCNV is not used, the number of write data lines D that are routed within the memory block MBLK can be reduced to one-quarter.

[0276] Similarly, the data conversion unit SPCNV converts the four 128-bit read data signals Q output from the memory block MBLK into 512-bit read data signals Q. Therefore, compared to the case where the data conversion unit SPCNV is not used, the number of read data lines Q routed within the memory block MBLK can be reduced to one-quarter.

[0277] Control line CMD, address line A, and write data line D are configured in each memory group MG and electrically connected sequentially via the memory group control unit MCNT. The control signal CMD, address signal A, and write data signal D are not transmitted to memory groups MG further downstream than the memory group MG to which write data signal D is to be written. Therefore, compared to the case where the control line CMD, address signal A, and write data signal D are jointly routed in each memory group MG to provide the control line CMD, address signal A, and write data signal D to each memory group MG, the charging and discharging current of the control line CMD, address line A, and write data line D can be suppressed. As a result, the increase in access time of the memory circuit 100 can be suppressed while reducing power consumption during write operations.

[0278] The read data line for transmitting the read data signal Q is wired in each memory group MG and sequentially electrically connected via the memory group control unit MCNT. Therefore, the read data signal Q is not transmitted to the read data lines of memory groups MG that are further upstream than the memory group MG performing the read operation. Thus, compared to the case where all memory groups MG share a common read data line, the power consumption of the memory block MBLK during read operations can be reduced.

[0279] Each memory module (MEM) has 512 memory cells (MCs) connected to word lines (WL). Data signals are simultaneously read from the memory cells (MCs) on the word line (WL) selected according to a single read instruction (RCMD). Data reading is controlled in four units and can be output sequentially as read data signals Q, with 128 bits output each time over four clock cycles. Furthermore, according to a single write instruction (WCMD) recognized by the control signal (CMD), write data signals D received sequentially over four clock cycles can be simultaneously written to all memory cells (MCs).

[0280] Each memory group control unit (MCNT) sets the memory cell MU used for writing or reading operations to active mode (ACT), and sets other memory cell MUs to power-off mode (SD) or sleep mode (SLP). This reduces the power consumption of the memory circuit 100. Furthermore, each memory group control unit (MCNT) can further reduce the power consumption of the memory circuit 100 by switching memory cell MUs that do not perform writing or reading operations during a specified period from active mode (ACT) to sleep mode (SLP).

[0281] The memory bank control unit MCNT operates synchronously with the memory clock signal MCLK, and the memory bank MG operates synchronously with the memory clock signal MCLKxN, which is amplified by four times the memory clock signal MCLK. Therefore, even when the 512-bit write data signal D is converted into four 128-bit write data signals D by the data conversion unit PSCNV and written to the memory cell MU, the same write rate can be achieved as when the 512-bit write data signal D is written to the memory cell MU synchronously with the memory clock signal MCLK.

[0282] Furthermore, even when the four 128-bit read data signals Q read from the memory cell MU are converted into 512-bit read data signals Q by the data conversion unit SPCNV, the same read rate as when reading 512-bit read data signals Q synchronously from the memory cell MU with the memory clock signal MCLK can be achieved.

[0283] The memory control unit 200 and the data conversion unit PSCNV convert eight write data signals WD received sequentially from the system bus SBUS into four write data signals D, and then sequentially output the four converted write data signals D to the memory block MBLK. Additionally, the memory control unit 200 and the data conversion unit PSCNV convert four read data signals Q sequentially read from the memory block MBLK into eight read data signals RD, and then sequentially output them to the system bus SBUS. This allows the operating frequency of the memory block MBLK to be lower than the operating frequency of the system bus SBUS, thereby reducing the power consumption of the memory block MBLK. Because the operating frequency of the memory block MBLK can be reduced, the operation of the memory group control unit MCNT and the memory group MG can have sufficient margin, thus simplifying circuit timing design.

[0284] The memory circuit 100 includes a memory group control unit MCNT and a memory group MG, alternately arranged between the memory control unit 200 (input side) and the memory control unit 200 (output side). During a read operation, the memory block MBLK receives an access request signal from the memory control unit 200 (input side) and outputs a read data signal Q to the memory control unit 200 (output side). Therefore, regardless of the access status, the sum of the lengths of the signal lines used to transmit the access request signal from the memory control unit 200 to the memory group MG to be read and the lengths of the signal lines used to transmit the read data signal Q to the memory control unit 200 can be kept approximately constant. As a result, the problem of read access time varying with the position of the memory group MG performing the read operation can be suppressed.

[0285] The control line CMD for transmitting the access request signal and the address line A for transmitting the address signal A are routed in each memory group MG and are sequentially electrically connected via the memory group control unit MCNT. Thus, each memory group control unit MCNT can control access for each memory group MG. Since the control line CMD and the address line A do not span multiple memory groups MG, the increase in wiring load can be suppressed. As a result, the increase in access time of the memory circuit 100 can be suppressed while power consumption can be reduced.

[0286] The number of clock cycles (e.g., the number of clock cycles in MCLKxN) required for the transmission of the access request signal, write data signal D, and read data signal Q between a pair of memory group control units (MCNTs) configured on both sides of the memory group MG are set to the same value. Therefore, timing design can be easily performed even when redesigning other memory circuits with different memory capacities by increasing or decreasing the number of memory groups MG.

[0287] Figure 37 An example of the structure of the memory circuit according to the second embodiment is shown. Regarding... Figure 1 Detailed descriptions of identical elements are omitted. Figure 37 In the memory circuit 102 shown, the memory block MBLK includes nine memory group control units MCNT1-MCNT9 and eight memory groups MG1-MG8 respectively arranged between adjacent memory group control units MCNT. The structure of each memory group control unit MCNT is similar to... Figure 14 The structure of the memory group control unit (MCNT) shown is the same. The structure of each memory group (MG) is the same. Figure 4 The memory group MG shown has the same structure. Therefore, the memory circuit 102 has a structure equivalent to Figure 3 The memory circuit 100 shown has twice the storage capacity of 32M bits (256k words × 128 bits).

[0288] In this embodiment, the control line CMD, address line ADR, write data line D, and read data line Q are reversed at memory group control unit MCNT5, which is located in the middle of the nine memory group control units MCNT1-MCNT9. This allows for... Figure 3 The input-side memory control unit 200 and the output-side memory control unit 200 shown are configured as a single unit. The structure of the memory control unit 200 is similar to... Figure 2 The memory control unit 200 shown has the same structure.

[0289] Furthermore, the 512-bit write data signal D output from the memory control unit 200 is converted into four 128-bit write data signals D and output to the memory group control unit MCNT1 via the data conversion unit PSCNV. The four 128-bit read data signals Q output from the memory group control unit MCNT9 are converted into 512-bit read data signals Q and output to the memory control unit 200 via the data conversion unit SPCNV.

[0290] As described above, the second embodiment also achieves the same effects as the first embodiment. For example, compared to the case where the data conversion unit PSCNV is not used, the number of write data lines D routed within the memory block MBLK can be reduced to one-quarter. Similarly, compared to the case where the data conversion unit SPCNV is not used, the number of read data lines Q routed within the memory block MBLK can be reduced to one-quarter. As a result, compared to the case where 512-bit data signals are input and output to the memory block MBLK, the power consumption during read operations can be reduced.

[0291] Compared to the case where the control line CMD, address line A, and write data line D are shared in multiple memory groups MG, and the control line CMD, address signal A, and write data signal D are provided to each memory group MG together, the charging and discharging currents of the control line CMD, address line A, and write data line D can be suppressed. As a result, the increase in access time of memory circuit 100 can be suppressed, while the power consumption during write operations can be reduced.

[0292] The memory bank control unit MCNT operates synchronously with the memory clock signal MCLK, and the memory bank MG operates synchronously with the memory clock signal MCLKxN, which is amplified by four times the memory clock signal MCLK. Therefore, even when the 512-bit write data signal D is converted into four 128-bit write data signals D by the data conversion unit PSCNV and written to the memory cell MU, the same write rate as when the 512-bit write data signal D is written to the memory cell MU synchronously with the memory clock signal MCLK can be achieved.

[0293] Furthermore, even when the four 128-bit read data signals Q read from the memory cell MU are converted into 512-bit read data signals Q by the data conversion unit SPCNV, the same read rate as when the 512-bit read data signals Q are read from the memory cell MU in sync with the memory clock signal MCLK can be achieved. As a result, the charging and discharging current of the data lines and the dynamic power of the memory circuit can be reduced without compromising access efficiency.

[0294] Furthermore, in the second embodiment, by reversing the column arrangement of the memory group control unit MCNT and the memory cell MU, the input-side memory control unit 200 and the output-side memory control unit 200 can be configured as one unit. As a result, for example, even when the storage capacity is... Figure 1 Even with twice the size of the memory circuit 100, the memory circuit 102 can still be configured compactly.

[0295] Figure 38 Showing the installation of Figure 1 This is an example of the structure of a system 300 with memory circuitry 100. Additionally, within system 300, a memory circuitry 100 can be installed... Figure 37 The memory circuit 100 is replaced by a memory circuit 102. For example, the system 300 is a head-mounted device such as AR / VR glasses, a digital camera, or a game console capable of processing animated images. Alternatively, the system 300 may also be an image processing system installed in a vehicle. Furthermore, the system with the memory circuit 100 is not limited to the structure of the system 300.

[0296] System 300 includes a controller 310, a camera device 320, a display device 330, and an external memory 340. The controller 310 includes a CPU 311, an image processing unit 312, a display processing unit 313, an encoder / decoder 314, an external memory control unit 315, and other components interconnected via a system bus SBUS. Figure 1 The memory circuit 100 is shown. For example, the controller 310 can be designed as a system LSI.

[0297] CPU 311 controls the entire system 300. Image processing unit 312 processes the image data acquired by camera device 320, converts the processed image data into frame image data that can be displayed on display device 330, and stores the frame image data in memory circuit 100. Display processing unit 313 reads the frame image data from memory circuit 100 and displays the image on display device 330. Encoder / decoder 314 encodes the image data before storing it in memory circuit 100 and combines the compressed image data read from memory circuit 100. External memory control unit 315 idles access to external memory 340 such as DRAM (Dynamic Random Access Memory).

[0298] For example, the resolution of the animation images processed by system 300 may be VGA (Video Graphics Array), Full Hi-Vision, or 4K. The memory circuit 100 of system 300 is equipped with a number of memory groups MG (not shown) corresponding to the resolution of the animation images. As described above, even if the number of memory groups MG increases or decreases, the clock cycle required for signal transmission between memory group control units MCNT remains unchanged. Therefore, timing can be easily set, thereby suppressing increases in access time.

[0299] The present invention has been described above according to various embodiments, but the present invention is not limited to the elements shown in the above embodiments. In this regard, modifications can be made without departing from the spirit of the present invention, and can be appropriately determined according to its application.

[0300] Symbol Explanation

[0301] 100, 102, 110 memory circuits

[0302] 200 Memory Control Unit

[0303] 202 System Bus Input Control Unit

[0304] 204, 206 buffers

[0305] 208 Peripheral Bus Control Unit

[0306] 210 Overall Management Department

[0307] 212 Memory Status Management Department

[0308] 214 Input Interface Control Unit

[0309] 220 Output Interface Control Unit

[0310] 222, 224 buffers

[0311] 226 System Bus Output Control Unit

[0312] 300 system

[0313] 310 Controller

[0314] 311 CPU

[0315] 312 Image Processing Department

[0316] 313 Display Processing Unit

[0317] 314 Encoder / Decoder

[0318] 315 External Memory Control Unit

[0319] 320 camera device

[0320] 330 display device

[0321] 340 External Memory

[0322] A address signal

[0323] ACT Activity Mode

[0324] ARY storage primitive array

[0325] ATRNS Activity Transition Mode

[0326] BL, BLB bit line pairs

[0327] BUF, BUF1, BUF2, BUF3 buffers

[0328] CMD control signal

[0329] CNTL control signals

[0330] COL_R column read signal

[0331] COL_W column write signal

[0332] D Write Data Signal

[0333] D-FF trigger circuit

[0334] I / O data input / output circuit

[0335] MBLK, MBLK120 storage blocks

[0336] MC storage primitive

[0337] MCLK, MCLKxN memory clock signals

[0338] MCLK_EN clock enable signal

[0339] MCNT Memory Group Control Unit

[0340] MEM and MEMb memory

[0341] MG, MGb memory groups

[0342] MSKC, MSKR, MSKW1, MSKW2 mask circuits

[0343] MU and MUb storage units

[0344] MEMCNT memory array control circuit

[0345] MUX multiplexer

[0346] PRE precharge circuit

[0347] Q read data signal

[0348] RCNT Relay Control Department

[0349] RD read data signal

[0350] RDEC line decoder

[0351] RLT Read Latch

[0352] RSW Read Switch

[0353] SA Sensing Amplifier

[0354] SBUS System Bus

[0355] SCLK system clock signal

[0356] SD power-off mode

[0357] SEL, SELQ selectors

[0358] SLP Sleep Mode

[0359] SubMEM (Sub-MEM)

[0360] WBUF write buffer

[0361] WD and WDD write data signals

[0362] WL lettering

[0363] WLT Write Latch

[0364] WSEL Write Selector

Claims

1. A memory circuit comprising: Multiple memory groups, each containing multiple memories with multiple memory cells, perform write or read operations according to request signals; Multiple memory group control units, each corresponding to one of the multiple memory groups; The first memory control unit outputs the request signal received from the outside to the adjacent memory group control unit; and The first data conversion unit divides the first write data signal received from the first memory control unit into n second write data signals, and outputs the second write data signals sequentially to the adjacent memory group control unit, where n is an integer greater than or equal to 2. When the write address signal included in the request signal received from the first memory control unit or the memory group control unit at the front end indicates the corresponding memory group, the plurality of memory group control units sequentially write the divided n second write data signals into any one of the memories of the corresponding memory group; when the write address signal does not indicate the corresponding memory group, the request signal and the n second write data signals are transmitted to the memory group control unit at the back end.

2. The memory circuit according to claim 1, wherein, Each of the plurality of memory groups has a write data line, and the write data lines sequentially transmit the write data signals via the memory group control unit in the subsequent section. A mask is provided for the transmission of the write data signal on the write data line of a memory group further downstream than the memory group on which the write data signal is written.

3. The memory circuit according to claim 1 or 2, further comprising: The second data conversion unit combines n first read data signals sequentially read from any one of the plurality of memory groups via at least one of the memory group control units into a second read data signal; and The second memory control unit outputs the second read data signal, which is integrated by the second data conversion unit. The plurality of memory group control units, when the read address signal included in the request signal received from the first memory control unit or the front-end memory group control unit indicates the corresponding memory group, sequentially read the data stored in any one of the memories of the corresponding memory group; when the read address signal does not indicate the corresponding memory group, they transmit the request signal to the back-end memory group control unit.

4. The memory circuit according to claim 3, wherein, Each of the plurality of memory groups has a read data line, and the read data lines sequentially transmit the read data signals via the subsequent memory group control unit. The read data line of the memory group that is further forward than the memory group that reads the read data signal does not transmit the read data signal.

5. The memory circuit according to claim 3, wherein, In each of the plurality of memory groups, The number of data terminals receiving the second write data signal is one-nth of the number of data terminals of the first memory control unit that outputs the first write data signal. The number of data terminals that output the first read data signal is one-nth of the number of data terminals of the second memory control unit that receives the second read data signal.

6. The memory circuit according to claim 3, wherein, The plurality of memories each include: m storage cells are connected to multiple word lines; m bit line pairs are respectively connected to columns of m memory cells arranged along a second direction that intersects a first direction extending from the word line; m pre-charge circuits and m sensing amplifiers are respectively connected to m bit line pairs; and m read latches and m read switches are sequentially connected to each of the m sense amplifiers. The precharge circuit, the sense amplifier, the read latch, and the read switch are connected to each of the m bit line pairs. It also includes m / n buffers, each connected to one of the n read switches.

7. The memory circuit according to claim 6, wherein, Each of the plurality of memories has a memory array control circuit. The memory array control circuit generates any one of the n column read signals for selecting m / n read switches based on the read address signal contained in the request signal.

8. The memory circuit according to claim 7, wherein, The one memory, Based on the request signal and the read address signal, any one of the plurality of word lines is selected, and data is read from the m memory cells connected to the selected word line and stored in the m read latches. Based on the n column read signals, each m / n data stored in the m read latches is read sequentially via the read switch, and the first read data signal containing m / n data is output n times.

9. The memory circuit according to claim 3, wherein, The plurality of memories each include: m storage cells are connected to multiple word lines; m bit line pairs are respectively connected to columns of m memory cells arranged along a second direction that intersects a first direction extending from the word line; m precharge circuits and m write buffers are respectively connected to the m bit line pairs; and m write latches and m write selectors are sequentially connected to each of the m write buffers. The precharge circuit, the write buffer, the write latch, and the write selector are connected to each of the m bit line pairs. It also has m / n trigger circuits, each connected to one of the n write selectors.

10. The memory circuit according to claim 9, wherein, Each of the plurality of memories has a memory array control circuit. The memory array control circuit generates any one of the n column write signals for selecting m / n write selectors based on the write address signal contained in the request signal.

11. The memory circuit according to claim 10, wherein, The one memory, Based on the request signal and the write address signal, m / n write selectors are selected sequentially using n column write signals, and the second write data signal containing m / n data is sequentially stored in m / n write latches. According to the write address signal, any one of the plurality of word lines is selected, and n second write data signals containing m data stored in m write latches are written into the m storage cells connected to the selected word line.

12. The memory circuit according to claim 3, wherein, The plurality of memory groups have a plurality of memory cells, each including the plurality of memories. The plurality of memories each have a plurality of memory cells that are respectively connected to a plurality of word lines. The one memory, Based on the write address signal included in the request signal, any one of the plurality of word lines is selected, and the n second write data signals are sequentially written into the plurality of memory cells connected to the selected word line. Based on the read address signal contained in the request signal, select any one of the plurality of word lines, and sequentially read the n data from the plurality of storage primitives connected to the selected word line.

13. The memory circuit according to claim 12, wherein, The plurality of memories each include: Multiple bit line pairs are respectively connected to columns of the memory primitives arranged along a second direction that intersects a first direction extending from the word line; Multiple data latches are respectively connected to the multiple bit line pairs; Data line, transmitting the second write data signal or the first read data signal; and The data selection unit connects the data line to any one of the plurality of data latches according to the second write address signal or the first read address signal.

14. The memory circuit according to claim 12, wherein, The plurality of storage units each have a low-power mode and an active mode. In the low-power mode, data is preserved while no write or read operations are performed. In the active mode, both write and read operations can be performed. The memory group control unit, corresponding to each of the plurality of memory groups, sets the memory cell used to perform the write operation or the read operation to an active mode, and sets the memory cell that does not perform the write operation or the read operation during a specified period to a low-power mode.

15. The memory circuit according to claim 3, wherein, The first memory control unit operates synchronously with the received first clock signal, outputting the first clock signal and a second clock signal (whose frequency is multiplied by n) to the adjacent memory group control unit. The control units of the multiple memory groups operate synchronously with the first clock signal. The multiple memory groups operate synchronously with the second clock signal. The second memory control unit operates synchronously with the first clock signal.

16. The memory circuit according to claim 15, wherein, The first data conversion unit converts the first write data signal, which is received from the first memory control unit in sync with the first clock signal, into the n second write data signals in sync with the second clock signal, and outputs them sequentially to the adjacent memory group control units. The plurality of memory group control units respectively output the first clock signal received from the first memory control unit or the front-end memory group control unit to the rear-end memory group control unit or the second memory control unit, and output the second clock signal received from the first memory control unit or the front-end memory group control unit to the corresponding memory group and the rear-end memory group control unit. The second data conversion unit converts the n first read data signals, which are received sequentially in sync with the second clock signal, into second read data signals in sync with the first clock signal, and outputs them to the second memory control unit.

17. The memory circuit according to claim 3, wherein, The first memory control unit converts a-bit b third write data signals received sequentially from the outside into a×b-bit first write data signals, and outputs them to the first data conversion unit, where a is an integer greater than or equal to 1, and b is an integer greater than or equal to 2. The second memory control unit converts the a×b bit second read data signal received from the second data conversion unit into a bit b third read data signals, and outputs them to the outside in sequence.

18. The memory circuit according to claim 1 or 2, wherein, The plurality of memories are SRAM.

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