Memory device with support for multiple sequence presence detect settings
By pre-storing multiple sets of parameters in the sequence presence detection module of the memory device and introducing a selection mechanism, the problems of performance degradation and insufficient compatibility of the memory module in multiprocessor platforms are solved, achieving efficient automatic adaptation and reducing deployment and maintenance costs.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- TEAM GRP
- Filing Date
- 2024-12-26
- Publication Date
- 2026-06-26
AI Technical Summary
Existing memory module sequence presence detection technologies are typically optimized for single-processor vendor architectures, leading to performance degradation, insufficient compatibility, and increased deployment and maintenance costs in multi-processor platform applications.
Multiple sets of optimized parameters are pre-stored in the sequence presence detection module of the memory device, and a selection mechanism is introduced to automatically adapt to different processor architectures. The sequence presence detection module automatically selects the appropriate parameters for configuration.
It achieves high performance and high compatibility of the memory module in a multi-platform environment, reduces the need for manual adjustment, lowers deployment and maintenance costs, and is suitable for large-scale multi-platform application scenarios.
Smart Images
Figure CN122290670A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to a memory device that supports multiple sequence presence detection settings, and is a memory device that supports processors with different arithmetic processing circuits. Background Technology
[0002] Memory typically employs Serial Presence Detection (SPD), a technology that provides a standardized framework for parameter setting between the memory module and the processor. SPD works by embedding non-volatile memory (such as EEPROM) within the memory module to store memory settings (such as timing, bandwidth, voltage, etc.). During system startup, the processor communicates with the processor via a communication bus (such as I / O). 2 The system reads parameters from the SPD using either C or SMBus and uses these parameters to set the operating environment of the memory to ensure stable system startup.
[0003] In current practices, the parameter design of SPD technology is usually optimized for the architectural requirements of a single processor manufacturer. For example, the parameter configuration within an SPD may be specifically tuned for a particular brand of processor to ensure optimal performance on that brand's processor. However, when the memory module is applied to processors from other manufacturers, these parameters may not match the hardware characteristics of the new processor, leading to performance degradation or even failure to function properly. This limitation significantly reduces the versatility and cross-platform compatibility of memory modules, resulting in performance degradation and insufficient compatibility. Furthermore, the lack of flexibility increases the deployment and maintenance costs of the memory.
[0004] Therefore, these limitations of conventional SPD technology are particularly evident in multiprocessor platform applications, failing to meet the needs of modern data centers, cloud computing environments, or other application scenarios requiring flexible adaptability.
[0005] In view of the problems of the prior art, the present invention proposes a novel design based on Sequence Presence Detection (SPD), which pre-stores multiple sets of optimized parameters for processor architectures from multiple vendors within the SPD and introduces a selection mechanism to achieve automatic adaptation. Summary of the Invention
[0006] One object of the present invention is to provide a memory device that supports multiple sequence presence detection settings, wherein multiple memory setting data are stored in the storage element of the sequence presence detection module, and different memory setting data support different processing units, so that the device can automatically adapt to the processing unit when connected to the processing unit.
[0007] To achieve the aforementioned objectives and effects, the present invention provides a memory device supporting multiple sequence presence detection settings, comprising: a substrate, a plurality of memory cells, and a sequence presence detection module. The memory cells are disposed on the substrate, and the sequence presence detection module is disposed on the substrate and electrically connected to the memory cells. The sequence presence detection module is electrically connected to a storage element, which stores at least a first memory setting data and a second memory setting data. The first memory setting data and the second memory setting data respectively support a first processing unit and a second processing unit, which are different processing circuits. When the sequence presence detection module is electrically connected to the first processing unit, the sequence presence detection module reads the first memory setting data into the first processing unit; when the sequence presence detection module is electrically connected to the second processing unit, the sequence presence detection module reads the second memory setting data into the second processing unit. Thus, the memory device supports different processor architectures.
[0008] In one embodiment of the present invention, the sequence presence detection module further includes preset memory setting data, which supports the first processing unit and the second processing unit. When the sequence presence detection module is electrically connected to the first processing unit, the sequence presence detection module reads the first memory setting data or the preset memory setting data into the first processing unit. When the sequence presence detection module is electrically connected to the second processing unit, the sequence presence detection module reads the second memory setting data or the preset memory setting data into the second processing unit.
[0009] In one embodiment of the present invention, the first processing unit is an Intel central processing unit or an AMD central processing unit.
[0010] In one embodiment of the present invention, the second processing unit is an Intel central processing unit or an AMD central processing unit.
[0011] In one embodiment of the present invention, the substrate and the memory cells are DDR5 memory. Attached Figure Description
[0012] Figure 1A This is a schematic diagram of a memory structure according to an embodiment of the present invention; Figures 1B to 1C This is a schematic diagram of the electrical connection according to an embodiment of the present invention; and Figure 2 This is a schematic diagram of the electrical connection of another embodiment of the present invention. [Figure Number Reference Guide] 10:Substrate 20: Memory Unit 30: Sequence Presence Detection Module 32: Storage element 322: First memory setting data 324: Second memory setting data 326: Preset memory settings data 40: Motherboard CPU1: First Processing Unit CPU2: Second Processing Unit CPU3: Processing Unit Detailed Implementation
[0013] To provide a better understanding of the structural features and effects achieved by the present invention, preferred embodiments and detailed descriptions are provided below:
[0014] Please see Figure 1A The figure shows a schematic diagram of a memory structure according to an embodiment of the present invention. This embodiment is the first embodiment and is a memory device that supports multiple sequence presence detection settings. It includes: a substrate 10, a plurality of memory cells 20 and a sequence presence detection module 30.
[0015] See again Figure 1A And see also 1B to Figure 1C , Figures 1B to 1C The figure shows an electrical connection diagram according to an embodiment of the present invention. In this embodiment, the memory units 20 are disposed on the substrate 10, the sequence presence detection module 30 is disposed on the substrate 10, and the sequence presence detection module 30 is electrically connected to the memory units 20. The sequence presence detection module 30 is also electrically connected to a storage element 32. The storage element 32 stores at least a first memory setting data 322 and a second memory setting data 324. The first memory setting data 322 and the second memory setting data 324 respectively support a first processing unit CPU1 and a second processing unit CPU2. That is, the first memory setting data 322 supports the first processing unit CPU1, and the second memory setting data 324 supports the second processing unit CPU2. The first processing unit CPU1 and the second processing unit CPU2 are different processing circuits.
[0016] Continuing from the above, as shown in the figure, when the sequence presence detection module 30 is electrically connected to the first processing unit CPU1, the sequence presence detection module 30 reads the first memory setting data 322 to the first processing unit CPU1 to adapt to the setting value of the first processing unit CPU1. Similarly, when the sequence presence detection module 30 is electrically connected to the second processing unit CPU2, the sequence presence detection module 30 reads the second memory setting data 324 to the second processing unit CPU2 to adapt to the setting value of the second processing unit CPU2.
[0017] In one embodiment, the first processing unit CPU1 is disposed on a motherboard 40, and similarly the second processing unit CPU2 is disposed on another motherboard 40.
[0018] In one embodiment, the first processing unit is an Intel CPU or an AMD CPU, and similarly the second processing unit is an Intel CPU or an AMD CPU. The first processing unit CPU1 and the second processing unit CPU2 are different arithmetic processing circuits, but this is not a limitation.
[0019] In one embodiment, the substrate and the memory cells are DDR5 memory.
[0020] The serial presence detection module 30 of this system is a serial presence detection (SPD) for memory. When the host is powered on, the serial presence detection performs a power-on self-test (POST). This process includes setting the current central processing unit (CPU) and the timing to be used to access memory. The serial presence detection module 30 can access BIOS parameters to view and change the setting parameters, namely the first memory setting data 322 or the second memory setting data 324, according to different processing units, in order to obtain the corresponding optimal memory timing, such as overclocking memory corresponding to the central processing unit of different manufacturers.
[0021] Continuing from the above, sequence presence detection is a standardized technique used to access data in memory modules about their configuration, capacity, speed, and other relevant information. The core purpose of sequence presence detection is to allow the host to quickly understand the characteristics of memory modules during system startup or runtime, thereby correctly configuring and using memory resources. The emergence and development of this technology stems from the increasing demands of modern computing systems for memory module compatibility and performance.
[0022] In early memory module designs, the Parallel Presence Detect (PPD) method was used. This method provides 5 bits of parallel data through five pins in the module to convey basic information about the module. However, with the development of memory technology, especially the continuous improvement in capacity and speed, 5 bits of data alone can no longer meet the needs of storing more complex module configuration information.
[0023] The introduction of sequential presence detection technology solved this limitation. As parallel presence detection was replaced by sequential presence detection, it used a small, non-volatile memory (such as EEPROM) to store detailed parameters of the memory module in a sequential manner. These parameters included module capacity, clock speed, latency, voltage requirements, and other critical configuration data affecting system performance and stability. During system startup, the motherboard or memory controller communicates with the system via I / O. 2 The C (Inter-Integrated Circuit) interface accesses the sequential presence detection memory, reading these parameters one by one. This sequential data transmission method is a significant improvement over parallel presence detection, allowing for the storage of more complex configuration information.
[0024] The use of sequence presence detection not only simplifies the design of memory modules, but also greatly improves the system's ability to identify and configure memory. In modern systems, the BIOS or UEFI reads the sequence presence detection information during the boot process to ensure the correct cooperation between the memory module and the motherboard, and automatically adjusts the clock frequency and delay parameters based on the data provided by the sequence presence detection. This adaptive capability not only improves system stability, but also eliminates the need for users to manually configure complex memory parameters.
[0025] Please see Figure 2 The figure shows an electrical connection diagram of another embodiment of the present invention. As shown, this embodiment is based on the first embodiment described above. The sequence presence detection module 30 of this embodiment further includes a preset memory setting data 326. The preset memory setting data 326 simultaneously supports the first processing unit CPU1, the second processing unit CPU2, and other processing units CPU3. When the sequence presence detection module 30 is electrically connected to the first processing unit CPU1, the sequence presence detection module 30 reads the first memory setting data 322 or the preset memory setting data 326 to the first processing unit CPU1. When the sequence presence detection module 30 is electrically connected to the second processing unit CPU2, the sequence presence detection module 30 reads the second memory setting data 324 or the preset memory setting data 326 to the second processing unit CPU2.
[0026] Continuing from the above, in this embodiment, when the sequence presence detection module 30 is electrically connected to other processing unit CPU 3 not supported by the first memory setting data 322 or the second memory setting data 324, the sequence presence detection module 30 reads the preset memory setting data 326 and adapts to other processing unit CPU 3 with priority given to operability.
[0027] In summary, this invention proposes a novel design based on sequence presence detection to address the existing problem. It pre-stores multiple sets of optimized parameters for various processor architectures within the storage element of the sequence presence detection module and introduces a selection mechanism for automatic adaptation. This invention pre-stores multiple sets of parameters for different processor manufacturers and architectures in the sequence presence detection process, classifying and managing them according to their type and applicable scope. This ensures that the memory module is compatible with the architectures of multiple processor manufacturers, and the sequence presence detection module can automatically select the optimal configuration from the pre-stored parameters based on the identification signal provided by the processor during startup. This achieves plug-and-play high-efficiency adaptation and optimized design, ensuring that the memory module achieves high performance and high compatibility in multi-platform applications.
[0028] Continuing from the above, this approach further reduces manual intervention, avoids the tedious process of manually adjusting sequence presence detection parameters, and significantly reduces deployment and maintenance costs. It is particularly suitable for large-scale, multi-platform applications. The multiple parameters in the sequence presence detection module enable the memory module to be universalized in the design, production, and testing stages, reducing the need for independent design for a single vendor's architecture, thereby reducing overall costs. It also addresses the issue that when conventional memory is used in processors from other vendors, these parameters may not match the hardware characteristics of the new processor, leading to performance degradation or even failure to operate normally. This limitation significantly reduces the universality and cross-platform compatibility of the memory module, resulting in performance degradation and insufficient compatibility. Furthermore, it solves the problem of increased deployment and maintenance costs for memory due to a lack of flexibility.
[0029] The above description is merely a preferred embodiment of the present invention and is not intended to limit the scope of the present invention. All equivalent variations and modifications made in accordance with the shape, structure, features and spirit described in the claims of the present invention should be included within the scope of the claims of the present invention.
Claims
1. A memory device with support for multiple sequence presence detection settings, characterized in that, It comprises: a substrate; a plurality of memory units disposed on the substrate; and a sequence presence detection module disposed on the substrate and electrically connected to the memory units, the sequence presence detection module being electrically connected to a storage element, the storage element storing at least a first memory setting data and a second memory setting data, the first memory setting data and the second memory setting data supporting a first processing unit and a second processing unit respectively, the first processing unit and the second processing unit being different operation processing circuits; wherein when the sequence presence detection module is electrically connected to the first processing unit, the sequence presence detection module reads the first memory setting data to the first processing unit, and when the sequence presence detection module is electrically connected to the second processing unit, the sequence presence detection module reads the second memory setting data to the second processing unit.
2. The memory device with support for multiple sequence presence detection settings of claim 1, wherein, wherein the sequence presence detection module further comprises a preset memory setting data, the preset memory setting data supporting the first processing unit and the second processing unit, wherein when the sequence presence detection module is electrically connected to the first processing unit, the sequence presence detection module reads the first memory setting data or the preset memory setting data to the first processing unit, and when the sequence presence detection module is electrically connected to the second processing unit, the sequence presence detection module reads the second memory setting data or the preset memory setting data to the second processing unit.
3. The memory device with support for multiple sequence presence detection settings of claim 1, wherein, wherein the first processing unit is an Intel central processing unit or an AMD central processing unit.
4. The memory device with support for multiple sequence presence detection settings of claim 1, wherein, wherein the second processing unit is an Intel central processing unit or an AMD central processing unit.
5. The memory device with support for multiple sequence presence detection settings of claim 1, wherein, wherein the substrate and the memory units are DDR5 memory.