Loss balancing method and system for anpc type three-level inverter based on double modulation wave

Abstract

This invention discloses a loss balancing method and system for ANPC-type three-level inverters based on dual modulation waves. The method includes: establishing two different zero-level path paths, obtaining the power device loss situation when switching between the two zero-level paths and P and N states, and then designing two modulation modes under one modulation wave cycle; the two modulation modes include PWM1 mode and PWM2 mode; based on the real-time loss of the power devices and combined with the Foster thermal model, calculating the average junction temperature of the power devices under the two modulation modes, and then calculating the junction temperature imbalance; based on the junction temperature imbalance, calculating the optimal allocation ratio of the two modes per M carrier cycles; based on the optimal allocation ratio, using the minimum maximum adjacent method to allocate the switching of the two modes to achieve loss balancing of the ANPC-type three-level inverter. This invention can achieve midpoint potential balance through a dual modulation wave strategy, and simultaneously achieve dynamic loss balancing of devices under dual modulation waves.

Description

Technical Field

[0001] This invention relates to the field of power electronics technology, and in particular to a loss balancing method and system for ANPC-type three-level inverters based on dual modulation waves. Background Technology

[0002] With the development of modern power electronics technology, power electronic devices are increasingly being used in high-voltage, high-power applications. Traditional two-level inverters are limited by the voltage levels of power devices, making them less suitable for high-voltage, high-power applications. However, a three-level topology can increase the overall voltage level of the inverter while maintaining the same device voltage levels. Compared to three-level NPC inverters, three-level ANPC inverters, by replacing clamping diodes with power devices that can be turned on and off, increase the zero-level path, allowing for more strategies to balance device losses.

[0003] Existing loss balancing technologies for ANPC-type three-level inverters mainly include replacing traditional Si-based power devices with third-generation semiconductors GaN / SiC, which have lower switching and conduction losses, but this significantly increases costs and reduces economic efficiency; or employing a fixed-ratio hybrid modulation strategy, but lacking a dynamic adjustment process. Furthermore, neither of these methods considers coordinating power device loss balancing with a midpoint potential balancing strategy. Therefore, it is highly significant to explore how to achieve loss balancing in ANPC-type three-level inverters by combining midpoint potential balancing with modulation strategy algorithms. Summary of the Invention

[0004] To address the shortcomings of the prior art, this invention provides a loss balancing method and system for ANPC-type three-level inverters based on dual modulation waves. The method achieves midpoint potential balance through a dual modulation wave strategy, and simultaneously realizes dynamic loss balancing of devices under dual modulation waves.

[0005] The first objective of this invention is to provide a loss equalization method for ANPC-type three-level inverters based on dual-modulation waves.

[0006] The second objective of this invention is to provide a loss balancing system for an ANPC-type three-level inverter based on dual modulation waves.

[0007] The first objective of this invention can be achieved by adopting the following technical solution:

[0008] A loss balancing method for an ANPC-type three-level inverter based on dual-modulation waves, wherein power devices S1, S5, S6, and S4 in the ANPC-type three-level inverter are sequentially connected between the positive and negative terminals of the power supply, and capacitors C1 and C2 are sequentially connected between the positive and negative terminals of the power supply; power devices S2 and S3 are sequentially connected between S1 and S4 and in parallel with the series-connected S5 and S6; the common terminal of S5 and S6 is connected to the common terminal of capacitors C1 and C2; and the common terminal of S2 and S3 serves as the output terminal of the inverter. The method includes:

[0009] Two different zero-level path paths were established, and the power device losses during the switching between the two zero-level paths and the P and N states were obtained.

[0010] Based on the power device losses during switching between two zero-level paths and P and N states, two modulation modes are designed under one modulation wave cycle; the two modulation modes include PWM1 mode and PWM2 mode.

[0011] Based on the real-time losses of power devices and combined with the Foster thermal model, the average junction temperature of power devices under two modulation modes is calculated; based on the average junction temperature of power devices under two modulation modes, the junction temperature imbalance is calculated; based on the junction temperature imbalance, the optimal allocation ratio of the two modes is calculated for every M carrier cycles; M is a positive integer greater than or equal to 1.

[0012] Based on the optimal allocation ratio, the minimum maximum adjacency method is used to allocate the switching between the two modes in order to achieve loss balance of the ANPC type three-level inverter.

[0013] Preferably, the two different zero-level path paths are:

[0014] Path 1: When the voltage output is in state 0, power devices S2, S4 and S5 are turned on;

[0015] Path 2: When the voltage output is in state 0, power devices S1, S3 and S6 are turned on.

[0016] Preferably, the PWM1 mode is as follows: when the positive modulation wave is greater than zero and the negative modulation wave is equal to zero, the P state and path 1 switch between each other; when the positive modulation wave is greater than zero and the negative modulation wave is less than zero, the P state, path 1, and N state switch between each other; when the positive modulation wave is equal to zero and the negative modulation wave is less than zero, the N state and path 2 switch between each other; in the PWM1 mode, the switching losses are concentrated in S1, S4, S5, and S6, and the conduction losses are concentrated in S2 and S3;

[0017] In PWM2 mode: when the positive modulation wave is greater than zero and the negative modulation wave is equal to zero, the P state and path 2 switch to each other; when the positive modulation wave is greater than zero and the negative modulation wave is less than zero, the P state, path 2, and N state switch to each other; when the positive modulation wave is equal to zero and the negative modulation wave is less than zero, the N state and path 1 switch to each other. In PWM2 mode, switching losses are concentrated in S2 and S3, and conduction losses are concentrated in S1, S4, S5, and S6.

[0018] Preferably, the step of calculating the optimal allocation ratio of the two modes per M carrier cycles based on junction temperature imbalance includes:

[0019] Let n1 be the number of times PWM1 mode occurs in M ​​modulation wave periods, n2 be the number of times PWM2 mode occurs in M ​​modulation wave periods, and r[k] be the proportion of the k-th sampling period, then:

[0020] ;

[0021] The ratio r[k] of the kth sampling period is adjusted as follows:

[0022] ;

[0023] In the formula, r[k-1] is the proportion of the (k-1)th sampling period, Δ[k] is the junction temperature imbalance of the kth sampling period, K is the proportional gain, and r min and r max These are the minimum and maximum ratios set, respectively; clip is for limiting the amplitude.

[0024] The optimal allocation ratio of the two modes per M carrier cycles is:

[0025] ;

[0026] In the formula, round is the rounding function.

[0027] Preferably, the junction temperature imbalance is calculated based on the average junction temperature of the power devices under the two modulation modes as follows:

[0028] ;

[0029] In the formula, Δ[k]∈(-1,1) represents the junction temperature imbalance over k sampling periods; G A [k] represents the average junction temperature of the power device in PWM1 mode during the kth sampling period, G B [k] represents the average junction temperature of the power device in PWM2 mode during the kth sampling period.

[0030] Preferably, the calculation of the average junction temperature of the power device under the two modulation modes based on the real-time loss of the power device and combined with the Foster thermal model includes:

[0031] The step thermal resistance of the Foster thermal model at time t is:

[0032] ;

[0033] In the formula, n is the number of thermally independent branches in the Foster model, and R i C i These are the thermal resistance and thermal capacity parameters of the i-th branch, respectively, τ i =R i C i Let i be the time constant of the i-th branch;

[0034] The total temperature rise ΔT(t) of the power device at time t is:

[0035] ;

[0036] ;

[0037] In the formula, τ represents any value between 0 and t, and P(τ) is the total power loss of the power device at time τ. The impact response at time t-τ;

[0038] Let the state variable of each branch at time t be s. i (t), then:

[0039] ;

[0040] The overall equivalent temperature rise of a single power device at time t is:

[0041] ;

[0042] With sampling time T s For s i Discretize (t) and ΔT(t):

[0043] ;

[0044] In the formula, s i [k], ΔT[k] and P[k] correspond to the state variables of the i-th branch, the total equivalent temperature rise of the power device in the i-th branch, and the total loss of the power device, respectively, during the k-th sampling period;

[0045] The real-time junction temperature of the power device is obtained by summing the temperature rise ΔT[k] obtained in each sampling period and the initial junction temperature of the power device.

[0046] Based on the real-time junction temperature of the power device, the average junction temperature of the power device under two modulation modes is calculated.

[0047] Preferably, since the conduction loss of IGBT devices is much greater than the switching loss, the power devices that lose power in PWM1 mode are S2 and S3; and the power devices that lose power in PWM2 mode are S1, S4, S5 and S6.

[0048] Preferably, the switching between the two modes based on the optimal allocation ratio and using the minimum-maximum neighbor method includes:

[0049] Based on the optimal allocation ratio, the minimum maximum neighbor method is used to minimize the length difference of consecutive identical patterns, thus determining the number of the majority and minority patterns, respectively, n. max and n min ;

[0050] Divide the majority pattern into n min +1 paragraph:

[0051] ;

[0052] In the formula, To round down;

[0053] If there exists a remainder a=n max mod (n min If +1), then an additional majority pattern will be allocated in the first a segment;

[0054] Insert a few patterns between each segment to obtain the final sequence.

[0055] Preferably, during the sequence arrangement process, patterns with a smaller current quantity are inserted first to separate patterns with a larger quantity.

[0056] The second objective of this invention can be achieved by adopting the following technical solution:

[0057] A loss balancing system for ANPC-type three-level inverters based on dual modulation waves is provided, the system being used to implement the aforementioned loss balancing method for ANPC-type three-level inverters.

[0058] The present invention has the following advantages over the prior art:

[0059] (1) The present invention takes into account the midpoint potential balance and adopts a dual modulation wave modulation method, which is equivalent to virtual space vector synthesis. By reconstructing the small vector and the medium vector, the injection current at the midpoint is 0, which reduces the midpoint potential imbalance.

[0060] (2) This invention calculates the junction temperature imbalance of two sets of power devices by real-time loss calculation, combined with Foster thermal model and superposition convolution algorithm, and calculates the optimal ratio of PWM1 mode and PWM2 mode based on this imbalance, thereby improving dynamic response capability.

[0061] (3) After obtaining the optimal allocation ratio, the present invention uses the minimum maximum adjacent method to achieve the balance of the time distribution of the two PWM modes (PWM1 mode and PWM2 mode). This sequence arrangement effectively avoids the concentration of power device losses caused by the concentrated use of a certain PWM mode. Attached Figure Description

[0062] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on the structures shown in these drawings without creative effort.

[0063] Figure 1 This is a topology diagram of an ANPC-type three-level inverter according to an embodiment of the present invention;

[0064] Figure 2 This is a simplified flowchart of a loss balancing method for an ANPC-type three-level inverter based on dual modulation waves, according to an embodiment of the present invention.

[0065] Figure 3 This is a detailed flowchart of a loss equalization method for an ANPC-type three-level inverter based on dual modulation waves, according to an embodiment of the present invention.

[0066] Figure 4 P is an embodiment of the present invention. OU 245 Pathway diagram;

[0067] Figure 5 P is an embodiment of the present invention. OL 136 Pathway diagram;

[0068] Figure 6 N is an embodiment of the present invention. OU 245 Pathway diagram;

[0069] Figure 7 N is an embodiment of the present invention. OL 136 Pathway diagram;

[0070] Figure 8 This is a diagram showing the voltage levels of the upper and lower bus capacitors in an embodiment of the present invention.

[0071] Figure 9 This is the PWM1 mode dual modulation wave modulation strategy of this invention embodiment;

[0072] Figure 10 This is a dual-modulation wave modulation strategy for PWM2 mode according to an embodiment of the present invention;

[0073] Figure 11 This is a Foster thermal model of a single power device according to an embodiment of the present invention;

[0074] Figure 12 This is a diagram showing the power loss distribution of a single-phase bridge arm power device according to an embodiment of the present invention. Detailed Implementation

[0075] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention. It should be understood that the specific embodiments described are merely used to explain this application and are not intended to limit this application.

[0076] Example 1:

[0077] like Figure 1 As shown, the ANPC three-level inverter consists of six power devices, corresponding anti-parallel diodes, and upper and lower bridge arm bus capacitors. Power devices S1, S5, S6, and S4 are connected sequentially between the positive and negative terminals of the power supply, and capacitors C1 and C2 are also connected sequentially between the positive and negative terminals. Power devices S2 and S3 are connected sequentially between S1 and S4 and in parallel with the series-connected S5 and S6. The common terminal of S5 and S6 is connected to the common terminal of capacitors C1 and C2. The common terminal of S2 and S3 serves as the inverter's output terminal. Using the midpoint between two capacitors as the reference voltage neutral point, the inverter can output three voltage levels (P, O, N) depending on the device conduction status. When the power devices are on, the voltage level is P. x =1, power device turns off S x =0, the switch status is shown in Table 1:

[0078] Table 1 Switching Status of ANPC Type Inverter

[0079]

[0080] like Figure 2 , 3 As shown in the figure, the loss equalization method for ANPC type three-level inverter based on dual modulation wave proposed in this embodiment includes the following steps:

[0081] S201. Establish two different zero-level path paths and obtain the power device loss situation when switching between the two zero-level paths and the P state and N state.

[0082] The two zero-level path paths are as follows:

[0083] Path 1 (OU) 245 When the voltage output is in the 0 state, select power devices S2, S4 and S5 are turned on;

[0084] Path 2 (OL) 136 When the voltage output is in the 0 state, select power devices S1, S3 and S6 are turned on.

[0085] Different loss distributions occur when P and N states switch with different O states:

[0086] like Figure 4 As shown, when P OU 245 During switching, switching losses are mainly concentrated in S1, S4, S5, and S6, while conduction losses are mainly concentrated in S2; for example Figure 5 As shown, when P OL 136 During switching, switching losses are mainly concentrated in S2 and S3, while conduction losses are mainly concentrated in S1 and S6; for example Figure 6 As shown, when N OU 245 During switching, switching losses are mainly concentrated in S2 and S3, while conduction losses are mainly concentrated in S4 and S5; for example Figure 7 As shown, when N OL 136 During switching, the switching losses are mainly concentrated in S1, S4, S5, and S6, while the conduction losses are mainly concentrated in S3.

[0087] In order to fully consider the control of midpoint potential balance while achieving loss balance, a dual-modulation wave modulation method based on virtual space vector generation is adopted. By reconstructing the small vector and the medium vector, the injection current at the midpoint is reduced to zero, thereby reducing the midpoint potential imbalance.

[0088] S202. Based on the power device loss situation when switching between two zero-level paths and P and N states, two PWM modulation modes under one modulation wave period are proposed.

[0089] refer to Figure 8The voltage fluctuations of both capacitors were effectively limited to between 89.4V and 90.4V, and the midpoint potential was effectively balanced. Based on the power device loss distribution during the switching between the P and N states and the two zero-level paths, two PWM modulation strategies were proposed: PWM1 mode and PWM2 mode.

[0090] refer to Figure 9 The specific implementation steps of PWM1 mode include: when the positive modulation wave is greater than zero and the negative modulation wave is equal to zero, P... OU 245 The states switch between each other; when the positive modulation wave is greater than zero and the negative modulation wave is less than zero, P OU 245 N states switch between each other; when the positive modulation wave is equal to zero and the negative modulation wave is less than zero, N... OL 136 The states switch between each other. In PWM1 mode, the switching losses are concentrated in S1, S4, S5, and S6, while the conduction losses are concentrated in S2 and S3.

[0091] refer to Figure 10 The specific implementation steps of PWM2 mode include: when the positive modulation wave is greater than zero and the negative modulation wave is equal to zero, P... OL 136 The states switch between each other; when the positive modulation wave is greater than zero and the negative modulation wave is less than zero, P OL 136 N states switch between each other; when the positive modulation wave is equal to zero and the negative modulation wave is less than zero, N... OU 245 The states switch between each other. In PWM2 mode, the switching losses are concentrated in S2 and S3, and the conduction losses are concentrated in S1, S4, S5 and S6.

[0092] S203. Calculate the optimal allocation ratio of the two PWM modes per M carrier cycles.

[0093] To obtain the optimal allocation ratio between PWM1 mode and PWM2 mode, the total loss of each power device needs to be calculated:

[0094] (1)

[0095] in:

[0096] , ,

[0097] , ,

[0098] In the formula, P(t) represents the total power loss of the power device at time t; P I (t) represents the total loss of the IGBT at time t; P D (t) represents the total loss of the anti-parallel diode at time t; P I,c (t) represents the conduction loss of the IGBT at time t; P I,sw (t) represents the switching loss of the IGBT at time t; P D,c (t) represents the conduction loss of the anti-parallel diode at time t; P D,rec (t) represents the reverse recovery loss of the anti-parallel diode at time t; V ce_on I is the on-state voltage drop of the IGBT at time t; c (t) represents the collector current of the IGBT at time t; r I V is the on-resistance of the IGBT at time t; D (t) represents the forward voltage drop of the anti-parallel diode at time t; I D (t) represents the instantaneous current of the anti-parallel diode at time t; r D f is the on-resistance of the anti-parallel diode at time t; sw E is the switching frequency. sw (t) represents the energy required for one switching operation of the IGBT at time t; E D,rec (t) represents the energy of the anti-parallel diode during one turn-off at time t.

[0099] refer to Figure 11 The thermal resistance parameters can be obtained from the datasheet of the corresponding device. The step thermal resistance of the Foster network at time t is:

[0100]

[0101] Where n is the number of thermally independent branches in the Foster model, R i C i These are the thermal resistance and thermal capacity parameters of the i-th branch, respectively, τ i =R i C i Let be the time constant of the i-th branch.

[0102] The overall temperature rise ΔT(t) of the power device at time t is the convolution of the total power loss P(t) and the impact response h(t):

[0103]

[0104] Where τ represents any value between 0 and t, for:

[0105]

[0106] Define the state variable of each branch at time t as s. i (t) represents the cumulative power density of the i-th branch after exponential decay weighting:

[0107]

[0108] Then the total equivalent temperature rise of a single power device at time t is obtained as:

[0109]

[0110] With sampling time T s For s i Discretize (t) and ΔT(t):

[0111]

[0112] Where k represents the sampling time index of the kth sampling period, s i [k], ΔT[k], and P[k] correspond to the kth sampling period s, respectively. i The discretized expressions for (t), ΔT(t), and P(t).

[0113] The junction temperature of a single power device can be obtained by summing the temperature rise ΔT[k] obtained in each sampling period and the initial device junction temperature T0.

[0114] Since the conduction loss of IGBT devices is much greater than the switching loss, the main loss-generating devices in PWM1 mode are S2 and S3, defined as group A; the main loss-generating devices in PWM2 mode are S1, S4, S5, and S6, defined as group B.

[0115]

[0116] In the formula, T x [k] represents the junction temperature of the power device in the kth sampling period calculated by the Foster thermal model, G A [k] represents the average junction temperature of group A devices in the kth sampling period, G B [k] represents the average junction temperature of group B devices in the kth sampling period.

[0117] The junction temperature imbalance index is defined as follows:

[0118]

[0119] Where Δ[k]∈(-1,1), when Δ[k]>0 it means that the loss of group A is greater than that of group B in the kth sampling period, and vice versa.

[0120] Let n1 be the number of times PWM1 mode occurs in M ​​modulation wave cycles, and n2 be the number of times PWM2 mode occurs in M ​​modulation wave cycles, where M is a positive integer greater than or equal to 1. Define the ratio r[k] as follows:

[0121]

[0122] The ratio r[k] of the kth sampling period is adjusted as follows:

[0123]

[0124] Where r[k-1] is the final selected ratio for the (k-1)th sampling period; Δ[k] is the junction temperature imbalance for the kth sampling period; K is the proportional gain, typically set to 0.1~0.3; r min and r max These are the minimum and maximum allowed proportions, respectively, with r as the value. min =1 / M, r max =(M-1) / M, corresponding to a maximum ratio of (M-1):1; clip is a clipping operation.

[0125] Combining equations (10) and (11), the final ratio is quantified as follows:

[0126]

[0127] In the formula, round is a rounding function, which finally determines the ratio of PWM1 mode and PWM2 mode in M ​​modulation wave cycles.

[0128] S204. Based on the optimal allocation ratio, the minimum maximum adjacent method is used to allocate the switching between the two PWM modes in order to achieve loss balance of the ANPC type three-level inverter.

[0129] After determining the optimal ratio, to avoid uneven losses over a period of time caused by continuously applying the same PWM mode, the minimum-maximum adjacency method is used to minimize the length difference of consecutive identical modes, thus determining the majority and minority modes, with a corresponding number of n. max and n min .

[0130] The majority pattern is divided into (n min +1) Section:

[0131]

[0132] Where d is obtained by rounding down, representing the basic length of each segment.

[0133] If there exists a remainder a=n max mod (n min If +1), then an additional majority pattern will be allocated in the first a segment.

[0134] Insert a few patterns between each segment to obtain the final sequence.

[0135] With M=10, the resulting sequence is shown in Table 2:

[0136] Table 2. PWM Sequence Allocation Table for 10 Modulation Wave Cycles

[0137]

[0138] While ensuring the optimal ratio remains unchanged, we try to avoid the continuous occurrence of PWM1 or PWM2 modes for a long time. During the arrangement process, we prioritize inserting modes with a smaller number of modes to separate modes with a larger number of modes. The goal is to minimize the maximum continuous length of adjacent similar modes, which effectively achieves loss balance in timing.

[0139] refer to Figure 12 The loss distribution of the six power devices under DC bus voltage of 180V and load current of 50A shows that the method provided in this embodiment has good loss balancing performance, verifying the feasibility of the method.

[0140] This embodiment provides a loss balancing method for ANPC-type three-level inverters based on dual modulation waves. By calculating the power device losses and junction temperature in real time, the optimal allocation ratio is obtained for each M carrier cycles. The method combines the minimum and maximum adjacent method to allocate two PWM mode sequences to achieve power device loss balancing. This method takes into account the midpoint potential balance problem and modulates by calculating device losses online, thus having good dynamic adjustment capability.

[0141] Those skilled in the art will understand that all or part of the steps in the methods of the above embodiments can be implemented by a program instructing related hardware, and the corresponding program can be stored in a computer-readable storage medium.

[0142] It should be noted that although the method operations of the above embodiments are described in a specific order in the accompanying drawings, this does not require or imply that these operations must be performed in that specific order, or that all the operations shown must be performed to achieve the desired result. On the contrary, the order of execution of the described steps may be changed. Additionally or alternatively, certain steps may be omitted, multiple steps may be combined into one step, and / or one step may be broken down into multiple steps.

[0143] This embodiment also provides a loss balancing system for ANPC-type three-level inverters based on dual modulation waves, used to implement the above-mentioned loss balancing method for ANPC-type three-level inverters.

[0144] The above description is merely a preferred embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any equivalent substitutions or modifications made by those skilled in the art within the scope disclosed in the present invention, based on the technical solution and inventive concept of the present invention, shall fall within the scope of protection of the present invention.

Claims

1. A loss balancing method for an ANPC-type three-level inverter based on dual-modulation waves, wherein power devices S1, S5, S6, and S4 in the ANPC-type three-level inverter are sequentially connected between the positive and negative terminals of the power supply, and capacitors C1 and C2 are sequentially connected between the positive and negative terminals of the power supply; power devices S2 and S3 are sequentially connected between S1 and S4 and in parallel with the series-connected S5 and S6, the common terminal of S5 and S6 is connected to the common terminal of capacitors C1 and C2, and the common terminal of S2 and S3 serves as the output terminal of the inverter, characterized in that... The method includes: Two different zero-level path paths were established, and the power device losses during the switching between the two zero-level paths and the P and N states were obtained. Based on the power device losses during switching between two zero-level paths and P and N states, two modulation modes are designed under one modulation wave cycle; the two modulation modes include PWM1 mode and PWM2 mode. Based on the real-time losses of power devices and combined with the Foster thermal model, the average junction temperature of power devices under two modulation modes is calculated; based on the average junction temperature of power devices under two modulation modes, the junction temperature imbalance is calculated; based on the junction temperature imbalance, the optimal allocation ratio of the two modes is calculated for every M carrier cycles; M is a positive integer greater than or equal to 1. Based on the optimal allocation ratio, the minimum maximum adjacency method is used to allocate the switching between the two modes in order to achieve loss balance of the ANPC type three-level inverter.

2. The loss balancing method for ANPC-type three-level inverters according to claim 1, characterized in that, The two different zero-level path paths are as follows: Path 1: When the voltage output is in state 0, power devices S2, S4 and S5 are turned on; Path 2: When the voltage output is in state 0, power devices S1, S3 and S6 are turned on.

3. The loss balancing method for an ANPC-type three-level inverter according to claim 2, characterized in that, The PWM1 mode is as follows: when the positive modulation wave is greater than zero and the negative modulation wave is equal to zero, the P state and path 1 switch between each other; when the positive modulation wave is greater than zero and the negative modulation wave is less than zero, the P state, path 1, and N state switch between each other. When the positive modulation wave is equal to zero and the negative modulation wave is less than zero, state N and path 2 switch to each other. In PWM1 mode, switching losses are concentrated in S1, S4, S5, and S6, while conduction losses are concentrated in S2 and S3. PWM2 mode is as follows: when the positive modulation wave is greater than zero and the negative modulation wave is equal to zero, the P state and path 2 switch to each other. When the positive modulation wave is greater than zero and the negative modulation wave is less than zero, the P state, path 2, and N state switch to each other. When the positive modulation wave is equal to zero and the negative modulation wave is less than zero, state N and path 1 switch to each other. In PWM2 mode, switching losses are concentrated in S2 and S3, while conduction losses are concentrated in S1, S4, S5, and S6.

4. The loss balancing method for an ANPC-type three-level inverter according to claim 1, characterized in that, The calculation of the optimal allocation ratio of the two modes per M carrier cycles based on junction temperature imbalance includes: Let n1 be the number of times PWM1 mode occurs in M ​​modulation wave periods, n2 be the number of times PWM2 mode occurs in M ​​modulation wave periods, and r[k] be the proportion of the k-th sampling period, then: ； The ratio r[k] of the kth sampling period is adjusted as follows: ； In the formula, r[k-1] is the proportion of the (k-1)th sampling period, Δ[k] is the junction temperature imbalance of the kth sampling period, K is the proportional gain, and r min and r max These are the minimum and maximum ratios set, respectively; clip is for limiting the amplitude. The optimal allocation ratio of the two modes per M carrier cycles is: ； In the formula, round is the rounding function.

5. The loss balancing method for an ANPC-type three-level inverter according to claim 1, characterized in that, The junction temperature imbalance is calculated based on the average junction temperature of the power devices under the two modulation modes: ； In the formula, Δ[k]∈(-1,1) represents the junction temperature imbalance over k sampling periods; G A [k] represents the average junction temperature of the power device in PWM1 mode during the kth sampling period, G B [k] represents the average junction temperature of the power device in PWM2 mode during the kth sampling period.

6. The loss balancing method for an ANPC-type three-level inverter according to any one of claims 1 to 5, characterized in that, The calculation of the average junction temperature of the power device under two modulation modes, based on the real-time loss of the power device and combined with the Foster thermal model, includes: The step thermal resistance of the Foster thermal model at time t is: ； In the formula, n is the number of thermally independent branches in the Foster model, and R i C i These are the thermal resistance and thermal capacity parameters of the i-th branch, respectively, τ i =R i C i Let i be the time constant of the i-th branch; The total temperature rise ΔT(t) of the power device at time t is: ； ； In the formula, τ represents any value between 0 and t, and P(τ) is the total power loss of the power device at time τ. The impact response at time t-τ; Let the state variable of each branch at time t be s. i (t), then: ； The overall equivalent temperature rise of a single power device at time t is: ； With sampling time T s For s i Discretize (t) and ΔT(t): ； In the formula, s i [k], ΔT[k] and P[k] correspond to the state variables of the i-th branch, the total equivalent temperature rise of the power device in the i-th branch, and the total loss of the power device, respectively, during the k-th sampling period; The real-time junction temperature of the power device is obtained by summing the temperature rise ΔT[k] obtained in each sampling period and the initial junction temperature of the power device. Based on the real-time junction temperature of the power device, the average junction temperature of the power device under two modulation modes is calculated.

7. The loss balancing method for an ANPC-type three-level inverter according to claim 6, characterized in that, Since the conduction loss of IGBT devices is much greater than the switching loss, the power devices that lose power in PWM1 mode are S2 and S3; the power devices that lose power in PWM2 mode are S1, S4, S5 and S6.

8. The loss balancing method for an ANPC-type three-level inverter according to any one of claims 1 to 5, characterized in that, The switching between the two modes based on the optimal allocation ratio and using the minimum maximum neighbor method includes: Based on the optimal allocation ratio, the minimum maximum neighbor method is used to minimize the length difference of consecutive identical patterns, thus determining the number of the majority and minority patterns, respectively, n. max and n min ; Divide the majority pattern into n min +1 paragraph: ； In the formula, To round down; If there exists a remainder a=n max mod (n min If +1), then an additional majority pattern will be allocated in the first a segment; Insert a few patterns between each segment to obtain the final sequence.

9. The loss balancing method for an ANPC-type three-level inverter according to claim 8, characterized in that, During the sequence arrangement process, patterns with fewer occurrences are inserted first to separate patterns with more occurrences.

10. A loss balancing system for an ANPC-type three-level inverter based on dual-modulation waves, characterized in that, The system is used to implement the loss balancing method for ANPC type three-level inverters as described in any one of claims 1 to 9.

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