Semiconductor device and method of manufacturing the same

Abstract

This application relates to a semiconductor device and its fabrication method. The semiconductor device fabrication method involves forming a deep well region with a different conductivity type than the substrate on the side of the trench emitter structure away from the trench gate structure. This deep well region extends below the trench emitter structure, which can adjust the electric field distribution in the bottom region of the trench emitter structure, reduce the peak electric field, decrease the electric field strength of the semiconductor device in the gate-off state, increase the short-circuit withstand time of the device, extend the lifespan of the semiconductor device, and enhance the long-term reliability of the semiconductor device during operation.

Description

Technical Field

[0001] This application relates to the field of power semiconductor device technology, and in particular to a semiconductor device and a method for manufacturing the same. Background Technology

[0002] Insulated-gate bipolar transistors (IGBTs) are characterized by high input impedance, low on-state voltage drop, fast switching speed, and low losses, making them widely used in new energy, transportation, power grids, and industry. As end-use applications move towards higher voltages, larger currents, and higher power densities, there are increasingly higher requirements for IGBT voltage ratings, high withstand voltage ratings, and long-term operational reliability. Summary of the Invention

[0003] Therefore, it is necessary to provide a semiconductor device and its fabrication method to address the problems in the prior art.

[0004] In a first aspect, this application provides a method for fabricating a semiconductor device, comprising the following steps:

[0005] A substrate is provided, the substrate having a first conductivity type;

[0006] Multiple trench structures are formed on the front side of the substrate, the trench structures extend from the front side of the substrate to the back side, and the multiple trench structures include at least one trench emitter structure and at least one trench gate structure, the trench emitter structure and the trench gate structure are spaced apart in the horizontal direction;

[0007] High-energy ions of a second conductivity type are implanted into the substrate through the front side of the substrate to form a deep well region. The deep well region is located on the side of at least one trench emitter structure away from the trench gate structure and extends from the front side of the substrate to below the trench emitter structure.

[0008] In one embodiment, the implantation of high-energy ions of a second conductivity type into the substrate through the front side of the substrate includes:

[0009] A protective layer and a photoresist layer are sequentially formed on the front side of the substrate, the protective layer and the photoresist layer covering at least the plurality of trench structures;

[0010] Using the protective layer and the photoresist layer as masks, high-energy ions are implanted into the side of the trench emitter structure away from the trench gate structure.

[0011] In one embodiment, the high-energy ion implantation is greater than or equal to 2500 keV, and the implantation dose is 5 × 10⁻⁶. 12 cm-2 Up to 5×10 13 cm -2 .

[0012] In one embodiment, forming a plurality of trench structures on the front side of the substrate includes:

[0013] The substrate is etched from the front side to the back side to form at least one first trench and at least one second trench spaced apart.

[0014] A first oxide layer is formed, a gate dielectric layer is formed in the first trench, and an emitter dielectric layer is formed in the second trench;

[0015] A conductive layer is formed, a gate conductive layer is formed in the first trench, and an emitter conductive layer is formed in the second trench;

[0016] The gate dielectric layer and the gate conductive layer in the first trench together constitute the trench gate structure; the emitter dielectric layer and the emitter conductive layer in the second trench together constitute the trench emitter structure.

[0017] In one embodiment, after forming the plurality of trench structures on the front side of the substrate, the method further includes:

[0018] The substrate between the trench emitter structure and the trench gate structure is doped with ions of a second conductivity type to form a bulk region;

[0019] Doping of the trench emitter structure and the trench gate structure with dopant ions of a first conductivity type forms a source region on the body region;

[0020] The substrate is etched to form contact holes extending into the body region;

[0021] A metal emitter is formed, covering the front side of the substrate and filling the contact hole.

[0022] In one embodiment, after forming the deep well region, the method further includes:

[0023] Doping the back side of the substrate with dopant ions of a first conductivity type forms a field cutoff layer;

[0024] A second conductivity type of dopant ions are doped onto the back side of the substrate to form a collector layer on the side of the field stop layer opposite to the bulk region;

[0025] A metal current collector is formed on the side of the current collector layer opposite to the field cutoff layer.

[0026] In one embodiment, the formation of a plurality of trench structures on the front side of the substrate includes two first trenches spaced apart in a horizontal direction, and two second trenches located on both sides of the two first trenches in a horizontal direction.

[0027] The trench gate structure is formed in the first trench, and the trench emitter structure is formed in the second trench, forming a first trench emitter structure, a first trench gate structure, a second trench gate structure, and a second trench emitter structure arranged sequentially in the horizontal direction.

[0028] In one embodiment, forming the deep well region includes:

[0029] High-energy particles are injected into the substrate on the side of the first trench emitter structure away from the first trench gate structure to form a first deep well region extending from the front side of the substrate to below the first trench emitter structure.

[0030] High-energy particles are injected into the substrate on the side of the second trench emitter structure away from the second trench gate structure to form a second deep well region extending from the front side of the substrate to below the second trench emitter structure.

[0031] Secondly, this application provides a semiconductor device, comprising:

[0032] The substrate includes a drift region having a first conductivity type;

[0033] The body region, located on the front side of the drift region near the substrate, has a second conductivity type;

[0034] Multiple trench structures are located on the front side of the semiconductor substrate. The multiple trench structures extend through the body region into the drift region. The multiple trench structures include at least one trench emitter structure and at least one trench gate structure. The trench emitter structure and the trench gate structure are spaced apart in the horizontal direction.

[0035] A deep well region, located horizontally on the side of at least one of the trench emitter structures away from the trench gate structure, extends from the front side of the substrate below the trench emitter structure, and the deep well region has a second conductivity type.

[0036] In one embodiment, the deep well region includes:

[0037] A first extension extends from the front side of the substrate to the back side of the substrate; and,

[0038] The second extension is connected to the bottom of the first extension and extends horizontally to the bottom of the trench emitter structure.

[0039] In one embodiment, the deep well region is formed by ion implantation, wherein the implantation dose of the deep well region is 5×10¹² cm⁻² to 5×10¹² cm⁻².

[0040] In one embodiment, it further includes:

[0041] The source region is located on the front side of the body region near the substrate and between the trench emitter structure and the trench gate structure, and the source region has a first conductivity type.

[0042] A contact hole is provided on the front side of the substrate, passes through the source region and extends to the body region;

[0043] A metal emitter covers the front side of the substrate and fills the contact hole;

[0044] A field-stop layer, located on the side of the drift region away from the body region, has a first conductivity type;

[0045] The collector layer, located on the side of the field cutoff layer away from the drift region, has a second conductivity type;

[0046] A metal current collector covers the back side of the substrate and the current collector layer.

[0047] In one embodiment, the plurality of trench structures sequentially include, along the horizontal direction: a first trench emitter structure, a first trench gate structure, a second trench gate structure, and a second trench emitter structure; the semiconductor device includes:

[0048] The first deep well region is located horizontally on the side of the first trench emitter structure away from the first trench gate structure, extending from the front side of the substrate to below the first trench emitter structure.

[0049] The second deep well region is located horizontally on the side of the second trench emitter structure away from the second trench gate structure, extending from the front side of the substrate to below the second trench emitter structure.

[0050] The semiconductor device and its fabrication method disclosed in this application form a deep well region with a different conductivity type than the substrate on the side of the trench emitter structure away from the trench gate structure. The deep well region extends below the trench emitter structure, which can adjust the electric field distribution in the bottom region of the trench emitter structure, reduce the peak electric field, reduce the electric field strength of the semiconductor device in the gate-off state, increase the short-circuit withstand time of the device, extend the service life of the semiconductor device, and enhance the long-term reliability of the semiconductor device during operation. Attached Figure Description

[0051] To more clearly illustrate the technical solutions in the embodiments of this application or the conventional technology, the drawings used in the description of the embodiments or the conventional technology will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0052] Figure 1 This is a process flow diagram of a method for fabricating a semiconductor device provided in one embodiment;

[0053] Figure 2 This is a schematic diagram of the structure of a substrate provided in one embodiment;

[0054] Figure 3 This is a schematic diagram of the structure after the carrier storage layer is formed in one embodiment;

[0055] Figure 4 This is a schematic diagram of the structure after spaced trenches are formed on the front side of the substrate in one embodiment;

[0056] Figure 5 This is a schematic diagram of the structure after the gate dielectric layer and emitter dielectric layer are formed in one embodiment;

[0057] Figure 6 This is a schematic diagram of the structure after the trench gate structure and trench emitter structure are formed in one embodiment;

[0058] Figure 7 This is a schematic diagram of the structure after the deep well region is formed in one embodiment;

[0059] Figure 8 This is a schematic diagram of the structure after the body region, source region, and contact hole are formed in one embodiment;

[0060] Figure 9 This is a schematic diagram of the structure after a metal emitter is formed on the front side of the substrate in one embodiment;

[0061] Figure 10 This is a schematic diagram of the structure after forming a field cutoff layer, a collector layer, and a metal collector on the back side of a substrate in one embodiment.

[0062] Explanation of reference numerals in the attached figures:

[0063] 1. Source region; 2. Body region; 3. Carrier storage layer; 4. Trench emitter structure; 4a. First trench emitter structure; 4b. Second trench emitter structure; 41. Emitter dielectric layer; 42. Emitter conductive layer; 5. Trench gate structure; 5a. First trench gate structure; 5b. Second trench gate structure; 51. Gate dielectric layer; 52. Gate conductive layer; 4-1. First trench; 5-1. Second trench; 6. Deep well region; 6a. First deep well region; 6b. Second deep well region; 7. Substrate; 7a. Drift region; 8. Field cutoff layer; 9. Collector layer; 10. Metal emitter; 11. Contact hole; 12. Metal collector; 13. First oxide layer; 14. Conductive layer. Detailed Implementation

[0064] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings, which illustrate preferred embodiments of the application. However, this application may be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that the disclosure of this application will be thorough and complete.

[0065] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

[0066] As end-user applications demand higher voltage withstand levels from IGBTs, they are required not only to maintain normal operation and high reliability under prolonged high voltage (e.g., 1200V, 1700V), but also to exhibit good robustness under special operating conditions (e.g., short circuits, high voltage / high current).

[0067] To achieve better performance, advanced IGBT structures combining field stop and trench gate are commonly used in related technologies. While this structure effectively reduces conduction losses, when the device is in the off state and subjected to high voltage, electric field distortion concentration easily occurs at the bottom of the trench gate, becoming the peak point of the electric field intensity, which may trigger avalanche breakdown. At the same time, during short circuits, the higher the voltage, the worse the short circuit robustness.

[0068] According to an exemplary embodiment, this embodiment provides a method for fabricating a semiconductor device. The semiconductor device in this embodiment can be an insulated gate bipolar transistor (IGBT), such as... Figure 1 As shown, the method for fabricating a semiconductor device includes the following steps:

[0069] Step S101: Provide a substrate 7, which has a first conductivity type. In this embodiment, the first conductivity type is N-type, and the substrate 7 is an N-type substrate. The doping concentration of N-type conductive ions in the substrate 7 is 1×10⁻⁶. 13 cm -3 Up to 1×10 14 cm -3 Magnitude.

[0070] Reference Figure 2 The substrate 7 can be a semiconductor substrate, and the material of the substrate 7 can be silicon (Si), germanium (Ge), silicon-germanium (GeSi), silicon carbide (SiC); it can also be silicon-on-insulator (SOI), germanium-on-insulator (GOI); or it can be other materials, such as gallium arsenide and other III-V compounds.

[0071] In this embodiment, the substrate 7 is an N-type doped single-crystal silicon wafer. The N-type doped single-crystal silicon wafer can be fabricated by the following method: epitaxially growing N-type doped silicon on the single-crystal silicon wafer, and then reverse etching away the excess silicon on the surface to form an N-type doped drift region 7a, thereby obtaining the N-type doped substrate 7.

[0072] Step S102: A plurality of trench structures are formed on the front side of the substrate 7. The trench structures extend from the front side of the substrate 7 to the back side. The plurality of trench structures include at least one trench emitter structure 4 and at least one trench gate structure 5. The trench emitter structure 4 and the trench gate structure 5 are spaced apart in the horizontal direction.

[0073] In this embodiment, refer to Figure 4 , Figure 5 , Figure 6 The substrate 7 is etched to form at least two trenches spaced apart on the front side of the substrate 7. A trench emitter structure 4 is formed in at least one of the trenches, and a trench gate structure 5 is formed in at least one of the trenches.

[0074] Step S103: High-energy ions of a second conductivity type are implanted into the substrate 7 through the front side of the substrate 7 to form a deep well region 6. The deep well region 6 is located on the side of at least one trench emitter structure 4 away from the trench gate structure 5 in the horizontal direction and extends from the front side of the substrate 7 to below the trench emitter structure 4.

[0075] In this embodiment, refer to Figure 7 On the front side of the substrate 7 after the formation of multiple trench structures, a protective layer (not shown in the figure) is formed to protect the trench gate structure 5 and its surrounding area, exposing a portion of the substrate 7 on the side of the trench emitter structure 4 away from the trench gate structure 5. High-energy ions of a second conductivity type are implanted into the exposed area of ​​the substrate 7. In this embodiment, the second conductivity type is P-type, and the high-energy ions can be, for example, boron (B+) ions.

[0076] High-energy ions are implanted into the substrate 7 by controlling the implantation energy and implantation angle. After implantation, the substrate 7 undergoes a high-temperature annealing process. This process repairs lattice damage caused by ion implantation and activates the implanted high-energy ions, promoting their diffusion below the trench emitter structure 4 to form a deep well region 6 that at least partially overlaps with the trench emitter structure 4 in the vertical direction. In this embodiment, the shape and dopant ion concentration of the deep well region 6 can be adjusted by controlling the annealing temperature and time, resulting in a higher concentration of high-energy ions below the trench emitter structure 4 in the deep well region 6. This enhances the ability of the deep well region 6 to regulate the electric field distribution in the bottom region of the trench emitter structure 4.

[0077] The above-mentioned semiconductor device fabrication method forms a deep well region 6 on the side of the trench emitter structure 4 away from the trench gate structure 5, which has a different conductivity type than the substrate 7. The deep well region 6 extends below the trench emitter structure 4, which can adjust the electric field distribution in the bottom region of the trench emitter structure 4, reduce the electric field peak, reduce the electric field strength of the semiconductor device in the gate-off state, increase the short-circuit withstand time of the device, extend the service life of the semiconductor device, and enhance the long-term reliability of the semiconductor device during operation.

[0078] In some embodiments, step S103 involves implanting high-energy ions of a second conductivity type into the substrate 7 through the front side of the substrate 7, including:

[0079] Step S1031: A protective layer and a photoresist layer are sequentially formed on the front side of the substrate 7, and the protective layer and the photoresist layer cover at least a plurality of trench structures.

[0080] In this embodiment, a full-layer protective layer can be formed on the front side of the substrate 7 after multiple trench structures are formed using chemical vapor deposition (CVD) or atomic layer deposition (ALD) processes. The protective layer is used to protect the substrate 7 and prevent high-energy ions from damaging the substrate 7 or the trench emitter structure 4 and trench gate structure 5.

[0081] A photoresist layer is formed by coating a photoresist material onto a protective layer. The photoresist layer is then patterned using a photolithography-exposure process to define the injection regions for high-energy particles. The protective layer is then etched based on the patterned photoresist layer to expose the injection regions for high-energy particles.

[0082] Step S1032: Using the protective layer and photoresist layer as masks, high-energy ions are injected into the side of the trench emitter structure 4 away from the trench gate structure 5.

[0083] Reference Figure 7Using a protective layer and a photoresist layer as masks, high-energy ions are implanted into the exposed implantation region of the substrate 7. In this embodiment, the high-energy ions can be boron ions, which have good implantation depth control and electroactivation characteristics.

[0084] In some embodiments, the high-energy ion implantation is greater than or equal to 2500 keV. The implantation energy is greater than or equal to 2500 keV, thereby implanting high-energy ions relatively deeply. Implanting high-energy ions from the front side to the back side of the substrate 7 (vertical direction) can implant a large number of high-energy ions to a position below the bottom surface of the trench emitter structure 4, forming a local high-dose region. After thermal annealing, the high-energy ions in the local high-dose region can diffuse laterally along the horizontal direction below the trench emitter structure 4, and the formed deep well region 6 can effectively modulate the electric field at the bottom of the trench emitter structure 4.

[0085] If the implantation dose of high-energy ions is too low, it will not be sufficient to form an effective electric field modulation; if the dose is too high, it may affect the conduction characteristics of the device. In this embodiment, the implantation dose of high-energy ions is 5 × 10⁻⁶. 12 cm -2 Up to 5×10 13 cm -2 .

[0086] In some embodiments, step S102 forms a plurality of trench structures on the front side of the substrate 7, including the following steps:

[0087] Step S1021: Etch the substrate 7 from the front side to the back side to form at least one first trench 4-1 and at least one second trench 5-1 spaced apart.

[0088] In this embodiment, refer to Figure 4 A hard mask layer can be formed on the front side of the substrate 7, and a pattern of multiple trenches can be defined on the hard mask layer by photolithography and etching. The substrate 7 is etched from the front side to the back side according to the hard mask layer to form at least one first trench 4-1 and at least one second trench 5-1 arranged at intervals along the horizontal direction.

[0089] For example, refer to Figure 4 This forms two first grooves 4-1 and two second grooves 5-1. Along the horizontal direction, the two first grooves 4-1 and the two second grooves 5-1 are arranged in the following manner: one second groove 5-1, two spaced first grooves 4-1, and another second groove 5-1.

[0090] For example, trenches can be formed using dry etching processes, such as reactive ion etching.

[0091] Step S1022: Form a first oxide layer 13, form a gate dielectric layer 51 in the first trench 4-1, and form an emitter dielectric layer 41 in the second trench 5-1.

[0092] Reference Figure 5 The first oxide layer 13 can be formed using atomic layer deposition or thermal growth processes. The first oxide layer 13 covers the trench walls of the first trench 4-1, the trench walls of the second trench 5-1, and the front side of the substrate 7. The first oxide layer 13 in the first trench 4-1 serves as the gate dielectric layer 51, and the first oxide layer 13 in the second trench 5-1 serves as the emitter dielectric layer 41. The material of the first oxide layer 13 may include silicon oxide.

[0093] Step S1023: Form conductive layer 14, form gate conductive layer 52 in first trench 4-1, and form emitter conductive layer 42 in second trench 5-1.

[0094] Reference Figure 6 A conductive layer 14 can be formed using a chemical vapor deposition process. The conductive layer 14 covers the first oxide layer 13 and completely fills the unfilled areas of the first trench 4-1 and the second trench 5-1. The conductive layer 14 located in the first trench 4-1 serves as the gate conductive layer 52; the conductive layer 14 located in the second trench 5-1 serves as the emitter conductive layer 42. The gate dielectric layer 51 and the gate conductive layer 52 in the first trench 4-1 together constitute the trench gate structure 5; the emitter dielectric layer 41 and the emitter conductive layer 42 in the second trench 5-1 together constitute the trench emitter structure 4.

[0095] For example, the material of the gate conductive layer 52 may include polysilicon, and the electrical properties of the gate conductive layer 52 may be adjusted by in-situ doping of conductive ions into the polysilicon during the deposition process.

[0096] In this embodiment, after the conductive layer 14 is formed, the conductive layer 14 and the first oxide layer 13 on the front side of the substrate 7 are removed. For example, chemical mechanical polishing (CMP) can be used to remove the conductive layer 14 and the first oxide layer 13 on the front side.

[0097] In some embodiments, after forming at least one first trench 4-1 and at least one second trench 5-1 spaced apart in step S1021 and before forming the first oxide layer 13 in step S1022, the following steps are also performed:

[0098] Step S102-1: A sacrificial oxide layer (not shown in the figure) is grown on the surface of the first trench 4-1 and the second trench 5-1. Then the sacrificial oxide layer is removed to expose the trench wall of the first trench 4-1 and the trench wall of the second trench 5-1.

[0099] In this embodiment, after etching to form the first trench 4-1 and the second trench 5-1, a sacrificial oxide layer, such as a silicon oxide layer, can be formed on the surface of the first trench 4-1 and the second trench 5-1 using thermal oxidation or deposition processes. The growth process of the sacrificial oxide layer can induce lattice rearrangement of the substrate 7 exposed by the first trench 4-1 and the second trench 5-1, repairing the defects caused by etching on the surface of the substrate 7. After removing the sacrificial oxide layer, the newly formed first oxide layer 13 is more dense.

[0100] For example, the sacrificial oxide layer can be removed by wet etching.

[0101] In some embodiments, after forming a plurality of trench structures on the front side of the substrate 7 in step S102 and before forming the deep well region 6 in step S103, the following steps are also performed:

[0102] Step S104: Doping the substrate 7 between the trench emitter structure 4 and the trench gate structure 5 with ions of a second conductivity type to form a body region 2.

[0103] In this embodiment, a mask layer can be formed on the front side of the substrate 7, exposing the substrate 7 between the trench emitter structure 4 and the trench gate structure 5. Ions of a second conductivity type, namely P-type doped ions, are injected into the substrate 7 between the trench emitter structure 4 and the trench gate structure 5 to form a body region 2. The bottom surface of the body region 2 is higher than the bottom surface of the trench emitter structure 4 and the trench gate structure 5.

[0104] Alternatively, P-type doped ions can be implanted into the entire front side of substrate 7 to form body region 2.

[0105] Step S105: Doping with dopant ions of a first conductivity type between the trench emitter structure 4 and the trench gate structure 5 to form a source region 1 on the body region 2.

[0106] In this embodiment, refer to Figure 8 Doped ions of the first conductivity type can be injected into the front side of the substrate 7 to form a source region 1 of the first conductivity type, i.e., an N-type source region 1, in the area near the front side.

[0107] Step S106: Etch substrate 7 to form contact hole 11 extending into body region 2.

[0108] In this embodiment, refer to Figure 8 First, a full-length second oxide layer (not shown in the figure) is deposited on the front side of substrate 7. Then, a photoresist mask is formed on the second oxide layer, exposing a portion of the area above source region 1. The second oxide layer and source region 1 are etched according to the photoresist mask until body region 2 is exposed. Then, body region 2 is etched to form contact hole 11. By controlling the etching depth, the bottom surface of contact hole 11 is made close to drift region 7a, but located within body region 2.

[0109] In this embodiment, after forming the contact hole 11, a large number of ions of the second conductivity type are injected into the body region 2 below the contact hole 11 to form a heavily doped contact region. In this embodiment, the heavily doped contact region has a P-type conductivity type. The P-type heavily doped contact region is used to prevent latch-up of the semiconductor device during operation.

[0110] Step S108: Form a metal emitter 10, covering the front side of the substrate 7, and fill the contact hole 11.

[0111] In this embodiment, refer to Figure 9 Metal materials can be deposited using physical vapor deposition or sputtering processes. The metal material covers the front side of the substrate 7 and fills the contact holes 11 to form a metal emitter 10. The metal emitter 10 forms a good ohmic contact between the bottom of the contact holes 11 and the metal emitter, which can effectively suppress the latch-up effect of parasitic thyristors.

[0112] The material of the metal emitter 10 may include at least one of aluminum or titanium and their alloys.

[0113] In some embodiments, after forming the metal emitter 10 in step S108, the following steps are also performed:

[0114] Step S109: Doping the back side of the substrate 7 with dopant ions of a first conductivity type to form a field cutoff layer 8.

[0115] In this embodiment, after forming the metal emitter 10, the substrate 7, which has already undergone front-side processing, is thinned on the back side. For example, a combination of mechanical grinding and chemical mechanical polishing (CMP) or wet etching is used to thin the substrate 7 from its original thickness to a target thickness to reduce the bulk resistance of the drift region 7a, thereby reducing the on-state voltage drop of the device.

[0116] After thinning, refer to Figure 10 Ion implantation of a first conductivity type (N-type in this embodiment) is performed on the back side of substrate 7. The implanted ions can be phosphorus (P) or arsenic (As) ions. An N-type field stop layer 8 (FS layer) is formed on the back side of the thinned substrate 7. The doping concentration of the field stop layer 8 is higher than that of the N-type drift region 7a.

[0117] Reference Figure 10 The field cutoff layer 8 is used to terminate the electric field distribution when the device is in the off state, preventing the electric field from penetrating to the collector layer 9, thereby enabling the device to achieve a higher breakdown voltage with a thinner drift region 7a thickness.

[0118] Step S110: Doping the back side of the substrate 7 with dopant ions of the second conductivity type, forming a collector layer 9 on one side of the field stop layer 8 away from the body region 2.

[0119] Reference Figure 10 Ion implantation of a second conductivity type (P-type in this embodiment) is performed on the back side of substrate 7. The implanted ions can be boron ions, to form a heavily doped P-type collector layer 9 on the back side of field stop layer 8. When the device is turned on, the P-type collector layer 9 injects minority carriers (holes) into drift region 7a, enhancing the conductivity modulation effect and thus obtaining a low on-state voltage drop.

[0120] Step S111: A metal collector 12 is formed on the side of the collector layer 9 away from the field cutoff layer 8.

[0121] Reference Figure 10 On the back side of the substrate 7 after back-side ion implantation, one or more layers of metal are deposited by electron beam evaporation or sputtering to form a metal collector 12.

[0122] The material of the metal current collector 12 may include at least one of titanium, nickel (Ni), silver (Ag), aluminum, or alloys of these metals.

[0123] In some embodiments, step S102 forms a plurality of trench structures on the front side of the substrate 7, including two first trenches 4-1 spaced apart in the horizontal direction, and two second trenches 5-1 located on both sides of the two first trenches 4-1 in the horizontal direction.

[0124] Reference Figure 10 A trench gate structure 5 is formed in the first trench 4-1, and a trench emitter structure 4 is formed in the second trench 5-1. A first trench emitter structure 4a, a first trench gate structure 5a, a second trench gate structure 5b, and a second trench emitter structure 4b are formed sequentially along the horizontal direction.

[0125] The semiconductor device formed in this embodiment is an insulated gate bipolar transistor. When trenches are etched on the front side of the substrate 7, four trenches are formed at horizontal intervals. The arrangement of these four trenches is as follows: two first trenches 4-1 are located in the middle, and two second trenches 5-1 are located on the outer sides of these two first trenches 4-1. In other words, the trench arrangement sequence is: one second trench 5-1, one first trench 4-1, another first trench 4-1, and another second trench 5-1.

[0126] Subsequently, referring to Figure 10Following the aforementioned steps S1022 to S1024 (depositing a dielectric layer, filling with conductive material, and covering with a top dielectric layer), trench gate structures 5 are formed in the two middle first trenches 4-1. For ease of distinction, the one closer to the first second trench 5-1 is defined as the first trench gate structure 5a, and the one closer to the second second trench 5-1 is defined as the second trench gate structure 5b. Trench emitter structures 420 are formed in the two outer second trenches 5-1. Similarly, the one on the left is defined as the first trench emitter structure 4a, and the one on the right is defined as the second trench emitter structure 4b.

[0127] Therefore, the following cell units are formed sequentially along the horizontal direction on the front side of the substrate 7: first trench emitter structure 4a, first trench gate structure 5a, second trench gate structure 5b, and second trench emitter structure 4b.

[0128] In some embodiments, refer to Figure 7 Step S103 forms the deep trap region 6, including:

[0129] Step S1031: High-energy particles are injected into the substrate 7 on the side of the first trench emitter structure 4a away from the first trench gate structure 5a to form a first deep well region 6a extending from the front side of the substrate 7 to the bottom of the first trench emitter structure 4a.

[0130] Step S1032: High-energy particles are injected into the substrate 7 on the side of the second trench emitter structure 4b away from the second trench gate structure 5b to form a second deep well region 6b extending from the front side of the substrate 7 to the bottom of the second trench emitter structure 4b.

[0131] In this embodiment, a protective layer and a photoresist layer are sequentially formed on the front side of the substrate 7, and the protective layer and photoresist layer are patterned to expose a portion of the front side of the first trench emitter structure 4a away from its adjacent first trench gate structure 5a, and a portion of the front side of the second trench emitter structure 4b away from its adjacent first trench gate structure 5a.

[0132] Reference Figure 7 A first deep well region 6a is formed by implantation on the side of the first trench emitter structure 4a away from its adjacent first trench gate structure 5a (i.e., its outer side), and a second deep well region 6b is formed by implantation on the side of the second trench emitter structure 4b away from its adjacent second trench gate structure 5b (i.e., its outer side). These two deep well regions 6 are symmetrically distributed, optimizing the electric field at the bottom of the two trench emitter structures 4 respectively, thereby improving the breakdown voltage and robustness of the entire cell while maintaining the symmetry and uniformity of the current distribution.

[0133] In one embodiment, this embodiment provides a method for fabricating a semiconductor device, including the following steps:

[0134] Step S201: Provide an N-type substrate 7, as shown in the figure. Figure 2 The N-type substrate 7 includes an N-type drift region 7a, in which N-type conductive ions are doped. The doping concentration of the N-type drift region 7a is 1 × 10⁻⁶. 13 cm -3 Up to 1×10 14 cm -3 Magnitude.

[0135] Step S202: A dielectric layer (not shown in the figure) is formed on the front side of the N-type substrate 7, and N-type conductive ions (such as phosphorus) are implanted into the dielectric layer to form the carrier storage layer 3. Wherein, refer to... Figure 3 The dielectric layer can be a silicon oxide layer. The doping concentration of the carrier storage layer 3 is greater than that of the N-type drift region 7a, and the doping depth of the carrier storage layer 3 should be less than that of the N-type drift region 7a, so that the formed device still has the N-type drift region 7a.

[0136] Step S203: Etch substrate 7 from the front side to the back side to form four trenches spaced horizontally, as shown in the figure. Figure 4 The four grooves are arranged as follows: one second groove 5-1, one first groove 4-1, another first groove 4-1, and another second groove 5-1.

[0137] Step S204: A sacrificial oxide layer (not shown in the figure) is formed on the surfaces of the first trench 4-1 and the second trench 5-1, and then the sacrificial oxide layer is removed. In this embodiment, the sacrificial oxide layer can be formed by thermal oxidation. The growth process of the sacrificial oxide layer can induce the lattice rearrangement of the substrate 7 exposed by the first trench 4-1 and the second trench 5-1, repairing the defects caused by etching on the surface of the substrate 7. In this embodiment, the sacrificial oxide layer can be removed by wet etching.

[0138] Step S205: Refer to Figure 5 A first oxide layer 13 is formed, a gate dielectric layer 51 is formed in the first trench 4-1, and an emitter dielectric layer 41 is formed in the second trench 5-1. In this embodiment, the first oxide layer 13 can be formed using atomic layer deposition or thermal growth processes.

[0139] Step S206: Forming a conductive layer 14, forming a gate conductive layer 52 in the first trench 4-1, and forming an emitter conductive layer 42 in the second trench 5-1. In this embodiment, refer to... Figure 6A conductive layer 14 can be formed by chemical vapor deposition. The conductive layer 14 covers the first oxide layer 13 and completely fills the unfilled areas of the first trench 4-1 and the second trench 5-1. The conductive layer 14 located in the first trench 4-1 serves as the gate conductive layer 52; the conductive layer 14 located in the second trench 5-1 serves as the emitter conductive layer 42. For example, the material of the gate conductive layer 52 may include polysilicon. The gate dielectric layer 51 and the gate conductive layer 52 in the first trench 4-1 together constitute the trench gate structure 5; the emitter dielectric layer 41 and the emitter conductive layer 42 in the second trench 5-1 together constitute the trench emitter structure 4. Thus, a first trench emitter structure 4a, a first trench gate structure 5a, a second trench gate structure 5b, and a second trench emitter structure 4b are formed and arranged sequentially at intervals along the horizontal direction.

[0140] Step S207: A protective layer (not shown in the figure) and a photoresist layer (not shown in the figure) are sequentially formed on the front side of the substrate 7, using the protective layer and the photoresist layer as masks, referring to... Figure 7 High-energy ions are injected into the side of the first trench emitter structure 4a away from the first trench gate structure 5a to form a first deep well region 6a, and high-energy ions are injected into the side of the second trench emitter structure 4b away from the second trench gate structure 5b to form a second deep well region 6b. In this embodiment, the high-energy ions can be boron ions, and the high-energy ion injection is greater than or equal to 2500 keV. After thermal annealing, the high-energy ions in the first deep well region 6a can diffuse laterally in the horizontal direction to the bottom of the first trench emitter structure 4a, and the high-energy ions in the second deep well region 6b can diffuse laterally in the horizontal direction to the bottom of the second trench emitter structure 4b. The first deep well region 6a and the second deep well region 6b can effectively modulate the electric field at the bottom of the trench emitter structure 4.

[0141] Step S208: Refer to Figure 8 P-type conductive ions are doped into the substrate 7 between the trench emitter structure 4 and the trench gate structure 5 to form a P-type body region 2. In this embodiment, the P-type conductive ions can be boron ions.

[0142] Step S209: Refer to Figure 8 N-type conductive ions are doped between the trench emitter structure 4 and the trench gate structure 5 to form an N-type source region 1 on the body region 2.

[0143] Step S210: Refer to Figure 8 The medium layer and source region 1 are etched until the body region 2 is exposed. Then the body region 2 is etched to form contact hole 11. By controlling the etching depth, the bottom surface of contact hole 11 is made close to drift region 7a, but located in body region 2.

[0144] Step S211: P-type conductive ions are injected into the body region 2 below the contact hole 11 to form a heavily doped contact region. The heavily doped P-type contact region is used to prevent latch-up of the semiconductor device during operation.

[0145] Step S212: Refer to Figure 9 A metal emitter 10 is formed, covering the front side of the substrate 7 and filling the contact hole 11. In this embodiment, a physical vapor deposition or sputtering process can be used to deposit the metal material. The material of the metal emitter 10 may include titanium, nickel, silver (Ag), aluminum, etc. The metal emitter 10 forms a good ohmic contact between the bottom of the contact hole 11 and the metal emitter, which can effectively suppress the latch-up effect of the parasitic thyristor.

[0146] Step S213: Flip the substrate 7 and use a thinning process to reduce the thickness of the substrate 7 to a preset thickness.

[0147] Step S214: Refer to Figure 10 N-type conductive ions are doped onto the back side of substrate 7 to form an N-type field-stop layer 8. The doping ions can be phosphorus (P) or arsenic (As) ions, and the doping concentration of the field-stop layer 8 is higher than that of the N-type drift region 7a. The field-stop layer 8 is used to terminate the electric field distribution when the device is in the off state, preventing the electric field from penetrating to the collector, thereby enabling the device to achieve a higher breakdown voltage with a relatively thin drift region 7a.

[0148] Step S215: Refer to Figure 10 P-type conductive ions are doped onto the back side of the substrate 7 to form a collector layer 9 on the side of the field stop layer 8 away from the body region 2. The doping ions can be boron ions to form a heavily doped P-type collector layer 9 on the back side of the field stop layer 8. When the device is turned on, the P-type collector layer 9 injects minority carriers (holes) into the drift region 7a, enhancing the conductivity modulation effect and thus obtaining a low on-state voltage drop.

[0149] Step S216: Refer to Figure 10 A metal current collector 12 is formed on the side of the current collector layer 9 facing away from the field cutoff layer 8. One or more layers of metal are deposited on the back side of the substrate 7 after back-side ion implantation to form the metal current collector 12. The material of the metal current collector 12 may include at least one of titanium, nickel (Ni), silver (Ag), aluminum, or alloys of these metals.

[0150] According to an exemplary embodiment, this embodiment provides a semiconductor device, with reference to... Figure 10 It includes a substrate 7, a body region 2, multiple trench structures, and a deep well region 6.

[0151] Reference Figure 10 The substrate 7 has a drift region 7a of a first conductivity type (N-type in this embodiment), and the doping concentration of the drift region 7a is, for example, 1 × 10⁻⁶.13 cm -3 Up to 1×10 14 cm -2 The thickness of the drift region 7a is determined based on the device's rated blocking voltage (such as 1200V, 1700V, etc.) and is designed to withstand high voltage.

[0152] Reference Figure 10 The body region 2 is located on the front side of the drift region 7a near the substrate 7 and has a second conductivity type. In this embodiment, the body region 2 is a P-type body region 2. The bottom surface of the body region 2 is higher than the bottom surface of the trench structure. The body region 2 defines the channel region of the device. The body region 2 is located in multiple trench structures and is penetrated and separated by multiple trench structures.

[0153] Reference Figure 10 Combined with reference Figure 4 , Figure 6 , Figure 6 Multiple trench structures are located on the front side of the semiconductor substrate 7, extending through the body region 2 into the drift region 7a. Each trench structure includes at least one trench emitter structure 4 and at least one trench gate structure 5, spaced horizontally. The trench emitter structure 4 and trench gate structure 5 are located in the first trench 4-1, and include a gate dielectric layer 51 and a gate conductive layer 52. The gate dielectric layer 51 covers the trench wall of the first trench 4-1, and the gate conductive layer 52 is disposed inside the gate dielectric layer 51 and fills the first trench 4-1. The sidewall region adjacent to the P-type body region 2 forms an inversion channel when a voltage is applied. The trench emitter structure 4 is located in the second trench 5-1 and includes an emitter dielectric layer 41 and an emitter conductive layer 42. The emitter dielectric layer 41 covers the trench wall of the second trench 5-1, and the emitter conductive layer 42 is disposed inside the emitter dielectric layer 41 and fills the second trench 5-1. The trench emitter structure 4 serves as an electrical connection electrode and does not form a conductive channel.

[0154] Reference Figure 10 The deep well region 6 is located horizontally on the side of at least one trench emitter structure 4 away from the trench gate structure 5, extending from the front side of the substrate 7 to below the trench emitter structure 4. The deep well region 6 has a second conductivity type; in this embodiment, the deep well region 6 is P-type. In this embodiment, by setting the deep well region 6 to adjust the electric field distribution in the bottom region of the trench emitter structure 4, the electric field strength of the semiconductor device in the gate-off state can be reduced, while effectively suppressing the electric field spike at the bottom of the trench emitter structure 4, improving the avalanche breakdown voltage, increasing the short-circuit withstand time of the device, extending the lifespan of the semiconductor device, and enhancing the long-term reliability of the semiconductor device.

[0155] In some embodiments, refer to Figure 10The deep well region 6 includes a first extension extending from the front side of the substrate 7 to the back side of the substrate 7, and a second extension connected to the bottom of the first extension, the second extension extending horizontally to below the trench emitter structure 4.

[0156] In this embodiment, during the formation of the deep well region 6 through doping, the implantation angle and energy of high-energy ions are adjusted so that the peak doping concentration of the deep well region 6 is located directly below the bottom of the trench emitter structure 4. This effectively alleviates the electric field concentration at the bottom of the trench emitter structure 4 and reduces the electric field strength of the semiconductor device in the gate-off state. The deep well region 6 is formed by ion implantation, and the implantation dose of the deep well region 6 is 5 × 10⁻⁶. 12 cm -2 Up to 5×10 12 cm -2 .

[0157] In some embodiments, refer to Figure 10 The peak doping concentration of the deep well region 6 is located below the trench emitter structure 4. That is, the projection area of ​​the deep well region 6 on the substrate 7 does not overlap with the projection area of ​​any trench gate structure 5, so as to avoid affecting the gate control characteristics of the trench gate structure 5.

[0158] In some embodiments, refer to Figure 10 Combined with reference Figure 4 , Figure 5 , Figure 6 Multiple trench structures are sequentially arranged horizontally, including a first trench emitter structure 4a, a first trench gate structure 5a, a second trench gate structure 5b, and a second trench emitter structure 4b, which together form a symmetrical IGBT cell. The first trench gate structure 5a and the second trench gate structure 5b are located in the center of the cell and are adjacent to each other, while the first trench emitter structure 4a and the second trench emitter structure 4b are located on the two sides of the cell, respectively. The semiconductor device includes a first deep well region 6a and a second deep well region 6b, which are located on both sides of the IGBT cell, respectively optimizing the electric field distribution at the bottom of the trench emitters on both sides, while maintaining the symmetry of the cell structure.

[0159] Among them, reference Figure 10 The first deep well region 6a is located horizontally on the side of the first trench emitter structure 4a away from the first trench gate structure 5a, extending from the front of the substrate 7 to below the first trench emitter structure 4a; the second deep well region 6b is located horizontally on the side of the second trench emitter structure 4b away from the second trench gate structure 5b, extending from the front of the substrate 7 to below the second trench emitter structure 4b.

[0160] In this embodiment, the first deep well region 6a and the second deep well region 6b are located on both sides of the IGBT cell, maintaining the symmetry of the cell structure and avoiding the defects of one side having an excessively strong electric field and the other side having a weak electric field due to structural asymmetry. When the device is turned on, the current flow path on both sides of the cell is also basically symmetrical, thereby avoiding local current concentration and helping to improve the overall reliability of the device.

[0161] In some embodiments, refer to Figure 10 The semiconductor device also includes a source region 1 disposed on the front side of the body region 2 near the substrate 7, and the source region 1 is located between the trench emitter structure 4 and the trench gate structure 5. The source region 1 has a first conductivity type. In this embodiment, the source region 1 is N-type heavily doped (such as arsenic or phosphorus). The source region 1 forms a PN junction with the body region 2 and is adjacent to the sidewall of the trench gate structure 5.

[0162] Reference Figure 10 The semiconductor device also includes a contact hole 11 disposed on the front side of the substrate 7, the contact hole 11 passing through the source region 1 and extending to the body region 2, and a metal emitter 10 covering the front side of the substrate 7 and filling the contact hole 11; in some embodiments, a locally heavily doped contact region is also disposed at the bottom of the contact hole 11, the heavily doped contact region being connected to the body region 2, for reducing contact resistance and effectively suppressing the latch-up effect of the parasitic thyristor. The metal emitter 10 covers most of the front side area and fills the contact hole 11, thereby forming an electrical connection with both the source region 1 and the heavily doped contact region.

[0163] Reference Figure 10 The semiconductor device further includes a field cutoff layer 8, a collector layer 9, and a metal collector 12, sequentially located on one side of the drift region 7a away from the body region 2. The field cutoff layer 8 has a first conductivity type, which in this embodiment is N-type (e.g., a phosphorus-doped layer). The doping concentration of the field cutoff layer 8 is higher than that of the drift region 7a but lower than that of the collector layer 9. The field cutoff layer 8 is used to terminate the electric field propagation when the device is turned off, thereby reducing the on-state voltage drop. The collector layer 9 has a second conductivity type, which in this embodiment is a heavily doped P-type layer (e.g., a boron-doped layer). It is used to inject holes into the drift region 7a when the device is turned on, inducing a conductivity modulation effect and reducing the on-resistance. The metal collector 12 is used for external connections of the device.

[0164] In some embodiments, refer to Figure 10 A carrier storage layer 3 is further disposed between the body region 2 and the drift region 7a, and the carrier storage layer 3 has a first conductivity type. In this embodiment, the carrier storage layer 3 has an N-type conductivity type, and the doping concentration of the carrier storage layer 3 is higher than that of the drift region 7a, which is used to further increase the carrier concentration near the body region 2 and optimize the on-state voltage drop and switching characteristics of the device.

[0165] In one embodiment, this embodiment provides a semiconductor device, such as... Figure 10As shown, in conjunction with reference Figure 4 , Figure 5 , Figure 6 The semiconductor device in this embodiment is an insulated-gate bipolar transistor (IGBT) structure with high voltage withstand reliability. The semiconductor device includes a substrate 7 having a first conductivity type (N-type) drift region 7a, an IGBT cell structure located on the front side of the substrate 7, and a collector region structure located on the back side of the substrate 7. The IGBT cell structure includes a P-type body region 2, multiple trench structures extending through the body region 2 into the drift region 7a, a first deep well region 6a and a second deep well region 6b located on both sides of the IGBT cell structure, a source region 1 formed within the body region 2, and a metal emitter 10 located on the front side. The collector region structure includes an N-type field-stop layer 8, a P-type collector layer 9, and a back metal collector 12 stacked sequentially.

[0166] The doping concentration of the N-type drift region 7a in substrate 7 is 1×10⁻⁶. 13 cm -3 Up to 1×10 14 cm -2 The thickness of the drift region 7a is defined according to the rated blocking voltage of the device and is used to withstand high voltage when the device is turned off. In this embodiment, the substrate 7 is a silicon substrate. The P-type body region 2 extends from the front side to the back side of the substrate 7. The extension depth is less than the depth of the trench structure. The doping concentration of the body region 2 is higher than that of the drift region 7a. The body region 2 defines the channel region of the device and is penetrated and separated by multiple trench structures.

[0167] In this embodiment, as Figure 10 As shown, in conjunction with reference Figure 4 , Figure 5 , Figure 6 The multiple trench structures, arranged horizontally, include: a first trench emitter structure 4a, a first trench gate structure 5a, a second trench gate structure 5b, and a second trench emitter structure 4b. A first deep well region 6a is located on the side of the first trench emitter structure 4a away from the first trench gate structure 5a. The first deep well region 6a extends downward from the front side of the substrate 7, reaching the area below the bottom of the first trench emitter structure 4a. The projection of the first deep well region 6a onto the substrate 7 is the same as the projection of the first trench emitter structure 4a onto the substrate 7. There is an overlapping region, but there is no overlapping region with the projection of the first trench gate structure 5a on the substrate 7; the second deep well region 6b is located on the side of the second trench emitter structure 4b away from the second trench gate structure 5b. The second deep well region 6b extends downward from the front side of the substrate 7 to the area below the bottom of the second trench emitter structure 4b. The projection of the second deep well region 6b on the substrate 7 overlaps with the projection of the second trench emitter structure 4b on the substrate 7, but there is no overlapping region with the projection of the second trench gate structure 5b on the substrate 7.

[0168] like Figure 10As shown, source region 1 is located on top of the P-type body region 2 between the trench emitter structure 4 and the trench gate structure 5. It is formed by selective N-type heavy doping. Source region 1 forms a PN junction with body region 2 and is adjacent to the sidewall of trench gate structure 530, serving as the source region 1 of the IGBT. Contact hole 11 extends through source region 1 into the interior of the lower P-type body region 2. Contact hole 11 has a locally heavily doped P-type contact region (not shown in the figure) to form a low-resistance ohmic contact with the P-type body region 2 and effectively suppress the latch-up effect of parasitic thyristors. Metal emitter 10 covers most of the front area and fills contact hole 11.

[0169] In this embodiment, as Figure 10 As shown, an N-type carrier storage layer 3 is also provided between the body region 2 and the drift region 7a. The doping concentration of the carrier storage layer 3 is higher than that of the drift region 7a, which is used to further increase the carrier concentration near the body region 2.

[0170] The semiconductor device in this embodiment, such as Figure 10 As shown, by setting a first deep well region 6a on the side of the first trench emitter structure 4a away from the first trench gate structure 5a, the peak electric field at the bottom of the first trench gate structure 5a is reduced. By setting a second deep well region 6b on the side of the second trench emitter structure 4b away from the second trench gate structure 5b, the peak electric field at the bottom of the second trench gate structure 5b is reduced. In both the on and short-circuit states, the first deep well region 6a and the second deep well region 6b suppress parasitic transistor effects and extend the short-circuit withstand time, thereby improving the avalanche breakdown voltage and long-term withstand voltage reliability of the device.

[0171] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features of the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0172] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

Claims

1. A method for fabricating a semiconductor device, characterized in that, Includes the following steps: A substrate is provided, the substrate having a first conductivity type; Multiple trench structures are formed on the front side of the substrate, the trench structures extend from the front side of the substrate to the back side, and the multiple trench structures include at least one trench emitter structure and at least one trench gate structure, the trench emitter structure and the trench gate structure are spaced apart in the horizontal direction; High-energy ions of a second conductivity type are implanted into the substrate through the front side of the substrate to form a deep well region. The deep well region is located on the side of at least one trench emitter structure away from the trench gate structure and extends from the front side of the substrate to below the trench emitter structure.

2. The method for fabricating a semiconductor device according to claim 1, characterized in that, The implantation of high-energy ions of a second conductivity type into the substrate through the front side of the substrate includes: A protective layer and a photoresist layer are sequentially formed on the front side of the substrate, the protective layer and the photoresist layer covering at least the plurality of trench structures; Using the protective layer and the photoresist layer as masks, high-energy ions are implanted into the side of the trench emitter structure away from the trench gate structure.

3. The method for fabricating a semiconductor device according to claim 2, characterized in that, The high-energy ion implantation is greater than or equal to 2500 keV, and the implantation dose is 5 × 10⁻⁶. 12 cm -2 Up to 5×10 13 cm -2 .

4. The method for fabricating a semiconductor device according to claim 2, characterized in that, The formation of multiple trench structures on the front side of the substrate includes: The substrate is etched from the front side to the back side to form at least one first trench and at least one second trench spaced apart. A first oxide layer is formed, a gate dielectric layer is formed in the first trench, and an emitter dielectric layer is formed in the second trench; A conductive layer is formed, a gate conductive layer is formed in the first trench, and an emitter conductive layer is formed in the second trench; The gate dielectric layer and the gate conductive layer in the first trench together constitute the trench gate structure; the emitter dielectric layer and the emitter conductive layer in the second trench together constitute the trench emitter structure.

5. The method for fabricating a semiconductor device according to claim 4, characterized in that, After forming multiple trench structures on the front side of the substrate, the method further includes: The substrate between the trench emitter structure and the trench gate structure is doped with ions of a second conductivity type to form a bulk region; Doping of the trench emitter structure and the trench gate structure with dopant ions of a first conductivity type forms a source region on the body region; The substrate is etched to form contact holes extending into the body region; A metal emitter is formed, covering the front side of the substrate and filling the contact hole.

6. The method for fabricating a semiconductor device according to claim 1, characterized in that, After forming the deep well region, the process further includes: Doping the back side of the substrate with dopant ions of a first conductivity type forms a field cutoff layer; A second conductivity type of dopant ions are doped onto the back side of the substrate to form a collector layer on the side of the field stop layer opposite to the bulk region; A metal current collector is formed on the side of the current collector layer opposite to the field cutoff layer.

7. The method for fabricating a semiconductor device according to any one of claims 1-6, characterized in that, The formation of multiple trench structures on the front side of the substrate includes two first trenches spaced apart in the horizontal direction, and two second trenches located on both sides of the two first trenches in the horizontal direction. The trench gate structure is formed in the first trench, and the trench emitter structure is formed in the second trench, forming a first trench emitter structure, a first trench gate structure, a second trench gate structure, and a second trench emitter structure arranged sequentially in the horizontal direction.

8. The method for fabricating a semiconductor device according to claim 7, characterized in that, The formation of the deep well region includes: High-energy particles are injected into the substrate on the side of the first trench emitter structure away from the first trench gate structure to form a first deep well region extending from the front side of the substrate to below the first trench emitter structure. High-energy particles are injected into the substrate on the side of the second trench emitter structure away from the second trench gate structure to form a second deep well region extending from the front side of the substrate to below the second trench emitter structure.

9. A semiconductor device, characterized in that, include: The substrate includes a drift region having a first conductivity type; The body region, located on the front side of the drift region near the substrate, has a second conductivity type; Multiple trench structures are located on the front side of the semiconductor substrate. The multiple trench structures extend through the body region into the drift region. The multiple trench structures include at least one trench emitter structure and at least one trench gate structure. The trench emitter structure and the trench gate structure are spaced apart in the horizontal direction. A deep well region, located horizontally on the side of at least one of the trench emitter structures away from the trench gate structure, extends from the front side of the substrate below the trench emitter structure, and the deep well region has a second conductivity type.

10. The semiconductor device according to claim 9, characterized in that, The deep well region includes: A first extension extends from the front side of the substrate to the back side of the substrate; and, The second extension is connected to the bottom of the first extension and extends horizontally to the bottom of the trench emitter structure.

11. The semiconductor device according to claim 10, characterized in that, The deep well region is formed by ion implantation, and the implantation dose of the deep well region is 5 × 10⁻⁶. 12 cm -2 Up to 5×10 12 cm -2 .

12. The semiconductor device according to claim 9, characterized in that, Also includes: The source region is located on the front side of the body region near the substrate and between the trench emitter structure and the trench gate structure, and the source region has a first conductivity type. A contact hole is provided on the front side of the substrate, passes through the source region and extends to the body region; A metal emitter covers the front side of the substrate and fills the contact hole; A field-stop layer, located on the side of the drift region away from the body region, has a first conductivity type; The collector layer, located on the side of the field cutoff layer away from the drift region, has a second conductivity type; A metal current collector covers the back side of the substrate and the current collector layer.

13. The semiconductor device according to claim 9, characterized in that, The plurality of trench structures, arranged horizontally, sequentially include: a first trench emitter structure, a first trench gate structure, a second trench gate structure, and a second trench emitter structure; the semiconductor device includes: The first deep well region is located horizontally on the side of the first trench emitter structure away from the first trench gate structure, extending from the front side of the substrate to below the first trench emitter structure. The second deep well region is located horizontally on the side of the second trench emitter structure away from the second trench gate structure, extending from the front side of the substrate to below the second trench emitter structure.

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