Semiconductor device and method of manufacturing the same

Abstract

This application relates to semiconductor devices and methods for manufacturing the same. A semiconductor device includes a substrate, a channel region formed in a portion of the substrate, a source region and a drain region spaced apart from each other, penetrating the substrate and connected to the channel region, a gate insulating layer located on the portion of the substrate in a first direction, a gate electrode disposed on the gate insulating layer, a gate contact connected to the gate electrode, and a source contact and a drain contact located below the substrate in a second direction opposite to the first direction and respectively connected to the source region and drain region.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2024-0190937, filed on December 19, 2024, the entire contents of which are incorporated herein by reference. Technical Field

[0003] Embodiments of this disclosure relate to semiconductor devices and methods of manufacturing the same. Background Technology

[0004] Semiconductor devices are gaining significant attention as a crucial component of the electronics industry due to their miniaturization, multifunctionality, and / or low manufacturing costs. With the development of the electronics industry, the integration level of semiconductor devices is increasing. For these highly integrated semiconductor devices, the width of the lines within the device is gradually decreasing, making the formation of transistors within the device more challenging. Summary of the Invention

[0005] Embodiments of this disclosure provide semiconductor devices that can be highly integrated without degrading transistor performance, and methods for manufacturing the same.

[0006] The embodiments disclosed herein are not limited to those set forth herein, and other unmentioned embodiments will be apparent to those skilled in the art from the following description.

[0007] Embodiments of this disclosure may provide a semiconductor device comprising: a substrate; a channel region formed in a portion of the substrate; a source region and a drain region spaced apart from each other that penetrate the substrate and are connected to the channel region; a gate insulating layer on the portion of the substrate along a first direction; a gate electrode disposed on the gate insulating layer; a gate contact connected to the gate electrode; and a source contact and a drain contact located below the substrate and connected to the source region and the drain region respectively along a second direction opposite to the first direction.

[0008] Embodiments of this disclosure provide a semiconductor device comprising: a first semiconductor structure and a second semiconductor structure bonded to each other. The first semiconductor structure includes a first bonding insulating layer, a first substrate disposed on the first bonding insulating layer, a channel region formed in a portion of the first substrate, a first source region and a first drain region spaced apart from each other and connected to the channel region through the first substrate and the first bonding insulating layer, a gate electrode located on the first substrate, and a gate contact connected to the gate electrode. The second semiconductor structure includes: a second bonding insulating layer connected to the lower surface of the first bonding insulating layer; a second substrate disposed below the second bonding insulating layer; a second source region and a second drain region that penetrate the second substrate and the second bonding insulating layer and are respectively connected to the first source region and the first drain region; and a source contact and a drain contact respectively connected to the second source region and the second drain region.

[0009] Embodiments of this disclosure provide a method for manufacturing a semiconductor device, comprising: preparing a first substrate having an upper surface; forming a channel region on the upper surface and a first semiconductor region and a second semiconductor region connected to the channel region; forming a gate electrode and a gate contact connected to the gate electrode on the upper surface of the first substrate, exposing the lower surfaces of the first semiconductor region and the second semiconductor region; and forming a source contact and a drain contact respectively connected to the first semiconductor region and the second semiconductor region.

[0010] According to embodiments of this disclosure, a high degree of integration of semiconductor devices can be achieved without reducing transistor performance.

[0011] The advantages of the embodiments disclosed herein are not limited to those foregoing, and other advantages will become apparent to those skilled in the art from the following detailed description. Attached Figure Description

[0012] The embodiments of this disclosure will be more fully understood through the following detailed description and accompanying drawings; however, these detailed descriptions and drawings are for illustrative purposes only and are not intended to limit the embodiments.

[0013] Figure 1 A view illustrating a semiconductor device according to an embodiment of this disclosure.

[0014] Figure 2 and Figure 3 A view illustrating another semiconductor device according to an embodiment of this disclosure.

[0015] Figures 4 to 8 A view illustrating a method for manufacturing a semiconductor device according to an embodiment of the present disclosure.

[0016] Figures 9 to 19 A view illustrating a method of manufacturing another semiconductor device according to an embodiment of this disclosure. Detailed Implementation

[0017] Embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. When assigning reference numerals to components in each figure, the same reference numerals may be assigned even if the same component appears in different figures. Details of known techniques or functions may be omitted if the subject matter of this disclosure is determined to be unclear. As described herein, when a component “comprises” another component, that component may include other components unless the word “only” is used with “comprises, has, or consists of”. As described herein, the singular forms “a,” “an,” and “the” also include the plural forms unless the context clearly indicates otherwise.

[0018] Labels such as "first" and "second" may be used to describe components of this disclosure. These labels are only used to distinguish components, and the nature, order, or number of components is not limited by the labels.

[0019] When describing the positional relationship between components, when two or more components are described as "connected" or "coupled," these two or more components may be directly "connected" or "coupled," or another component may be inserted into them. Here, the other component may be included in one or more of the two or more components that are "connected" or "coupled" to each other.

[0020] When describing the temporal relationship between components, operating methods, or manufacturing methods, discontinuous situations may be included unless “directly” or “immediately following” is used.

[0021] When a value or its corresponding information (e.g., level) of a component is mentioned, it can be interpreted, even if not explicitly stated, as including a range of errors that may be caused by various factors (e.g., process factors, internal or external shocks, noise, etc.).

[0022] The embodiments of this disclosure will now be described in detail with reference to the accompanying drawings.

[0023] Figure 1 This is a view illustrating a semiconductor device according to an embodiment of the present disclosure.

[0024] refer to Figure 1 The semiconductor device includes a substrate 100, a transistor TR, a spacer 105, a gate capping layer 106, a gate contact 114, a gate line 124, a source contact 111, a source line 121, a drain contact 112, a drain line 122, a first insulating layer 130, a second insulating layer 140, and a third insulating layer 150.

[0025] The transistor TR includes a source region 101, a drain region 102, a gate insulating layer 103, a gate electrode 104, and a channel region 107.

[0026] Semiconductor devices include memories, processors, or combinations thereof. For example, semiconductor devices include dynamic random access memory (DRAM), static random access memory (SRAM), flash memory, magnetoresistive random access memory (MRAM), phase-change random access memory (PRAM), ferroelectric random access memory (FRAM), resistive random access memory (RRAM), or combinations thereof. However, semiconductor devices are not limited to the memories described above.

[0027] A transistor TR can be any transistor contained within a semiconductor device. For example, when the semiconductor device is DRAM, the transistor TR can be any transistor contained within the peripheral circuitry of the DRAM.

[0028] Substrate 100 includes a semiconductor substrate, such as a silicon wafer or a silicon-on-insulator (SOI) wafer. Substrate 100 includes a III-V group semiconductor substrate, such as a compound semiconductor substrate like GaAs. Substrate 100 includes monocrystalline silicon, polycrystalline silicon, amorphous silicon, monocrystalline silicon-germanium, polycrystalline silicon-germanium, carbon-doped silicon, or combinations thereof.

[0029] The substrate 100 includes a first surface 100a and a second surface 100b that are opposite to each other. The first surface 100a may be referred to as the front side of the substrate 100, and the second surface 100b may be referred to as the back side of the substrate 100.

[0030] In one embodiment, the thickness of the substrate 100 may be greater than or equal to 50 nm and less than or equal to 500 nm.

[0031] Channel region 107, source region 101, and drain region 102 are disposed in substrate 100. Source region 101 and drain region 102 are located on two opposite sides of channel region 107. Source region 101 and drain region 102 can be connected to channel region 107 on two opposite sides of channel region 107, respectively.

[0032] The source region 101 and the drain region 102 may extend through the substrate 100. For example, the upper surfaces of the source region 101 and the drain region 102 may form substantially the same plane as the first surface 100a of the substrate 100. The lower surfaces of the source region 101 and the drain region 102 may form substantially the same plane as the second surface 100b of the substrate 100.

[0033] In one embodiment, the widths of the source region 101 and the drain region 102 located on the second surface 100b of the substrate 100 may be smaller than the widths of the source region 101 and the drain region 102 located on the first surface 100a, respectively.

[0034] In one embodiment, channel region 107 comprises single-crystal silicon doped with P-type impurities. P-type impurities include boron (B), boron fluoride (BF), boron difluoride (BF2), or combinations thereof. In one embodiment, source region 101 and drain region 102 may be epitaxially grown layers. Depending on the type of transistor TR (e.g., N-type or P-type), source region 101 and drain region 102 comprise silicon doped with carbon, phosphorus, or arsenic, silicon-germanium, or boron-doped silicon-germanium.

[0035] On the first surface 100a of the substrate 100, a gate insulating layer 103 is disposed in a region overlapping with the channel region 107. The gate insulating layer 103 includes silicon oxide, silicon nitride, silicon oxynitride, a high-k dielectric, or a combination thereof.

[0036] Gate electrode 104 and gate capping layer 106 are sequentially disposed on gate insulating layer 103. Spacer 105 is disposed on the side of gate insulating layer 103, gate electrode 104 and gate capping layer 106. Spacer 105 and gate capping layer 106 both comprise silicon oxide, silicon nitride, silicon oxynitride, high-k dielectric layer or combinations thereof.

[0037] A second insulating layer 140 may be disposed on the gate capping layer 106 and the spacer 105. The second insulating layer 140 comprises silicon oxide, silicon nitride, silicon oxynitride, high-k dielectric, or a combination thereof.

[0038] One side of the gate contact 114 extends through the gate capping layer 106 and is connected to the upper surface of the gate electrode 104. The other side of the gate contact 114 is connected to the gate line 124. The gate contact 114 and the gate line 124 include metal, metal silicide, metal nitride, metal oxide, polysilicon, conductive carbon, or a combination thereof. Figure 1 A gate contact 114 and a gate line 124 connected thereto are shown, but the number of gate contacts 114 and gate lines 124 is not limited thereto.

[0039] A first insulating layer 130 is located below the source region 101 and the drain region 102. One side of the source contact 111 extends through the first insulating layer 130 and is connected to the lower surface of the source region 101. In one embodiment, one side of the source contact 111 may be connected to the second surface 100b of the substrate 100. A third insulating layer 150 is disposed below the first insulating layer 130. The source line 121 and the drain line 122 extend through the third insulating layer 150. The other side of the source contact 111 is connected to the source line 121. One side of the drain contact 112 is connected to the lower surface of the drain region 102. In one embodiment, one side of the drain contact 112 may be connected to the second surface 100b of the substrate 100. The other side of the drain contact 112 is connected to the drain line 122.

[0040] The source contact 111, drain contact 112, source line 121 and drain line 122 all contain metal, metal silicide, metal nitride, metal oxide, polysilicon, conductive carbon or a combination thereof. Figure 1 A source contact 111 and a drain contact 112, and a source line 121 and a drain line 122 connected thereto, are shown, but the number of source contacts 111 and 112, and source lines 121 and 122, is not limited thereto. Both the first insulating layer 130 and the third insulating layer 150 comprise silicon oxide, silicon nitride, silicon oxynitride, a high-k dielectric, or a combination thereof.

[0041] Figure 2 and Figure 3 This is a view illustrating another semiconductor device according to an embodiment of the present disclosure.

[0042] refer to Figure 2 The semiconductor device includes a first semiconductor structure S1 and a second semiconductor structure S2. The first semiconductor structure S1 and the second semiconductor structure S2 may be bonded to each other. In one embodiment, the first semiconductor structure S1 and the second semiconductor structure S2 may be different wafers.

[0043] The first semiconductor structure S1 includes a first substrate 200, a first bonding insulating layer 251, a first source region 201, a first drain region 202, a channel region 207, a gate insulating layer 203, a gate electrode 204, a gate capping layer 206, a spacer 205, a gate contact 214, a gate line 224, and a second insulating layer 240.

[0044] The second semiconductor structure S2 includes a second substrate 300, a second bonding insulating layer 252, a second source region 301, a second drain region 302, a first insulating layer 330, a source contact 311, a drain contact 312, a source line 321, a drain line 322, and a third insulating layer 350.

[0045] The first source region 201, the first drain region 202, the second source region 301, the second drain region 302, the channel region 207, the gate insulating layer 203, and the gate electrode 204 can constitute a transistor TR. The first source region 201 and the second source region 301 can constitute the source region of the transistor TR. The first drain region 202 and the second drain region 302 can constitute the drain region of the transistor TR. The bonding insulating layer 250 includes a first bonding insulating layer 251 and a second bonding insulating layer 252.

[0046] The first substrate 200 may be referenced Figure 1 The substrates 100 described are substantially the same. The first substrate 200 includes a first surface 200a and a second surface 200b that are opposite each other.

[0047] A channel region 207, a first source region 201, and a first drain region 202 are disposed in a first substrate 200. The first source region 201 and the first drain region 202 respectively include a reference [region / area]. Figure 1 The source region 101 and drain region 102 are made of the same material.

[0048] The first source region 201 and the first drain region 202 can penetrate the first substrate 200 and the first bonding insulating layer 251. For example, the upper surfaces of the first source region 201 and the first drain region 202 can be substantially coplanar with the first surface 200a of the first substrate 200. The lower surfaces of the first source region 201 and the first drain region 202 can be substantially coplanar with the lower surface 251a of the first bonding insulating layer 251.

[0049] In one embodiment, the widths of the first source region 201 and the first drain region 202 on the first surface 200a of the first substrate 200 may be substantially the same as the widths of the first source region 201 and the first drain region 202 on the lower surface 251a of the first bonding insulating layer 251, respectively. In another embodiment, the widths of the first source region 201 and the first drain region 202 on the first surface 200a of the first substrate 200 may be substantially the same as the widths of the first source region 201 and the first drain region 202 on the second surface 200b of the first substrate 200, respectively.

[0050] A gate insulating layer 203, a gate electrode 204, and a gate capping layer 206 are sequentially stacked on the first substrate 200 in the region overlapping with the channel region 207. A spacer 205 is disposed on the side of the gate insulating layer 203, the gate electrode 204, and the gate capping layer 206. The gate insulating layer 203, the gate electrode 204, the gate capping layer 206, and the spacer 205 can be respectively positioned with reference... Figure 1 The gate insulating layer 103, gate electrode 104, gate capping layer 106, and spacer 105 described are substantially the same.

[0051] One side of the gate contact 214 penetrates the gate capping layer 206 and connects to the upper surface of the gate electrode 204. The other side of the gate contact 214 connects to the gate line 224. A second insulating layer 240 may be disposed on the gate contact 214, the gate line 224, and the spacer 205. The gate contact 214, the gate line 224, and the second insulating layer 240 may be respectively connected to a reference... Figure 1 The gate contact 114, gate line 124 and second insulating layer 140 described are substantially the same.

[0052] The second bonding insulating layer 252 is disposed below the first bonding insulating layer 251. The upper surface 252a of the second bonding insulating layer 252 is connected to the lower surface 251a of the first bonding insulating layer 251. The upper surface 252a of the second bonding insulating layer 252 and the lower surface 251a of the first bonding insulating layer 251 may be located in the same plane. Both the first bonding insulating layer 251 and the second bonding insulating layer 252 contain silicon oxide, silicon nitride, silicon carbide, or a combination thereof. Both the first bonding insulating layer 251 and the second bonding insulating layer 252 contain SiO2, SiOC, SiOCN, SiBN, SiBCN, SiN, or a combination thereof.

[0053] The second substrate 300 is located below the second bonding insulating layer 252. The second substrate 300 is spaced apart from the first substrate 200. The second substrate 300 includes a semiconductor substrate, such as a silicon wafer or a silicon-on-insulator (SOI) wafer. The second substrate 300 includes a III-V group semiconductor substrate, such as a compound semiconductor substrate, such as GaAs. The second substrate 300 includes monocrystalline silicon, polycrystalline silicon, amorphous silicon, monocrystalline silicon-germanium, polycrystalline silicon-germanium, carbon-doped silicon, or a combination thereof. In one embodiment, the second substrate 300 comprises the same material as the first substrate 200.

[0054] The second substrate 300 includes a first surface 300a and a second surface 300b that are opposite to each other.

[0055] The second source region 301 and the second drain region 302 can penetrate the second substrate 300 and the second bonding insulating layer 252. For example, the lower surfaces of the second source region 301 and the second drain region 302 can be substantially coplanar with the second surface 300b of the second substrate 300. The upper surfaces of the second source region 301 and the second drain region 302 can be substantially coplanar with the upper surface 252a of the second bonding insulating layer 252.

[0056] In one embodiment, the widths of the second source region 301 and the second drain region 302 on the first surface 300a of the second substrate 300 may be substantially the same as the widths of the second source region 301 and the second drain region 302 on the upper surface 252a of the second bonding insulating layer 252. In another embodiment, the widths of the second source region 301 and the second drain region 302 on the first surface 300a of the second substrate 300 may be substantially the same as the widths of the second source region 301 and the second drain region 302 on the second surface 300b of the second substrate 300.

[0057] The upper surface of the second source region 301 is connected to the lower surface of the first source region 201, and the upper surface of the second drain region 302 is connected to the lower surface of the first drain region 202. In one embodiment, the width of the second source region 301 may be substantially the same as the width of the first source region 201. In one embodiment, the width of the second drain region 302 may be substantially the same as the width of the first drain region 202.

[0058] A first insulating layer 330 is disposed below the second source region 301 and the second drain region 302. One side of the source contact 311 penetrates the first insulating layer 330 and connects to the second source region 301. The upper surface of the source contact 311 is connected to the second source region 301. A third insulating layer 350 is disposed below the first insulating layer 330. The source line 321 and the drain line 322 penetrate the third insulating layer 350. The other side of the source contact 311 is connected to the source line 321. Similarly, one side of the drain contact 312 is connected to the second drain region 302. The upper surface of the drain contact 312 is connected to the second drain region 302. The other side of the drain contact 312 is connected to the drain line 322.

[0059] The first insulating layer 330 is disposed on the side of the source contact 311 and the drain contact 312, the source line 321 and the drain line 322.

[0060] refer to Figure 3 The semiconductor device includes a first semiconductor structure S1 and a second semiconductor structure S2. The first semiconductor structure S1 and the second semiconductor structure S2 may be bonded to each other. In one embodiment, the first semiconductor structure S1 and the second semiconductor structure S2 may be different wafers.

[0061] The first semiconductor structure S1 includes a first substrate 200, a first bonding insulating layer 251, a first source region 401, a first drain region 402, a channel region 207, a gate insulating layer 203, a gate electrode 204, a gate capping layer 206, a spacer 205, a gate contact 214, a gate line 224, and a second insulating layer 240.

[0062] The second semiconductor structure S2 includes a second substrate 300, a second bonding insulating layer 252, a second source region 301, a second drain region 302, a first insulating layer 330, a source contact 311, a drain contact 312, a source line 321, a drain line 322, and a third insulating layer 350.

[0063] The first source region 401, the first drain region 402, the second source region 301, the second drain region 302, the channel region 207, the gate insulating layer 203, and the gate electrode 204 can constitute a transistor TR. The first source region 401 and the second source region 301 can constitute the source region of the transistor TR. The first drain region 402 and the second drain region 302 can constitute the drain region of the transistor TR. The bonding insulating layer 250 includes a first bonding insulating layer 251 and a second bonding insulating layer 252.

[0064] A channel region 207, a first source region 401, and a first drain region 402 are disposed in a first substrate 200. The first source region 401 and the first drain region 402 respectively include a reference... Figure 2 The first source region 201 and the first drain region 202 are made of the same material.

[0065] The first source region 401 and the first drain region 402 can penetrate the first substrate 200 and the first bonding insulating layer 251. For example, the upper surfaces of the first source region 401 and the first drain region 402 can be substantially coplanar with the first surface 200a of the first substrate 200. The lower surfaces of the first source region 401 and the first drain region 402 can be substantially coplanar with the lower surface 251a of the first bonding insulating layer 251.

[0066] In one embodiment, the widths of the first source region 401 and the first drain region 402 on the first surface 200a of the first substrate 200 may be greater than the widths of the first source region 401 and the first drain region 402 on the second surface 200b of the first substrate 200, respectively. In another embodiment, the widths of the first source region 401 and the first drain region 402 on the second surface 200b of the first substrate 200 may be smaller than the widths of the first source region 401 and the first drain region 402 on the lower surface 251a of the first bonding insulating layer 251, respectively.

[0067] Figures 4 to 8 A view illustrating a method for manufacturing a semiconductor device according to an embodiment of the present disclosure.

[0068] refer to Figure 4 A substrate 100 having a channel region 107 is prepared, and a first semiconductor region 501 and a second semiconductor region 502 connected to the channel region 107 are formed on the first surface 100a.

[0069] The first semiconductor region 501 and the second semiconductor region 502 may be epitaxial growth layers. Depending on the type of transistor TR (e.g., N-type or P-type), both the first semiconductor region 501 and the second semiconductor region 502 contain silicon doped with carbon, phosphorus, or arsenic, silicon germanium, or boron doped silicon germanium.

[0070] A gate insulating layer 103, a gate electrode 104, and a gate capping layer 106 are sequentially formed in the region of the substrate 100 that overlaps with the channel region 107. Spacers 105 are formed on the side surfaces of the gate insulating layer 103, the gate electrode 104, and the gate capping layer 106.

[0071] A gate contact 114 is formed to penetrate the gate capping layer 106 and connect to the upper surface of the gate electrode 104. A gate line 124 is formed on the gate contact 114.

[0072] refer to Figure 5 ,Will Figure 4 The semiconductor device in the middle flips. (Reference) Figure 4 and Figure 5 The lower portion of substrate 100 is removed to expose the first semiconductor region 501 and the second semiconductor region 502. The process for removing the lower portion of substrate 100 includes chemical mechanical polishing (CMP) or grinding.

[0073] As the lower portion of substrate 100 is removed, at least a portion of the first semiconductor region 501 and the second semiconductor region 502 can be removed together, thereby forming source region 101 and drain region 102, respectively. In one embodiment, a surface (e.g., the upper surface) of source region 101 and a surface (e.g., the upper surface) of drain region 102 can be substantially coplanar with the second surface 100b of substrate 100. In one embodiment, the widths of source region 101 and drain region 102 on the second surface 100b of substrate 100 can be smaller than the widths of source region 101 and drain region 102 on the first surface 100a of substrate 100, respectively.

[0074] refer to Figure 6 and Figure 7 A first insulating layer 130 is formed on the substrate 100. After forming the first insulating layer 130, at least one first via 700 is formed through the first insulating layer 130. The process of forming the first via 700 includes an etching process. The first via 700 may expose one surface (e.g., the upper surface) of the source region 101 and the drain region 102. In one embodiment, the first via 700 may expose a second surface 100b of the substrate 100 (where the source region 101 or the drain region 102 is not disposed).

[0075] refer to Figure 7 and Figure 8 A source contact 111 and a drain contact 112 are formed in the first through-hole 700. A third insulating layer 150 is formed on the source contact 111 and the drain contact 112. A source line 121 and a drain line 122 are formed on the source contact 111 and the drain contact 112 respectively through the third insulating layer 150.

[0076] Figures 9 to 19A view illustrating a method of manufacturing another semiconductor device according to an embodiment of this disclosure.

[0077] refer to Figure 9 A second substrate 300 having a third semiconductor region 901 and a fourth semiconductor region 902 is prepared.

[0078] The third semiconductor region 901 and the fourth semiconductor region 902 may be epitaxial growth layers. Depending on the type of transistor TR (e.g., N-type or P-type), both the third semiconductor region 901 and the fourth semiconductor region 902 contain silicon doped with carbon, phosphorus, or arsenic, silicon germanium, or boron doped silicon germanium.

[0079] A first insulating layer 330 is formed on the second substrate 300. After forming the first insulating layer 330, at least one second via 900 is formed through the first insulating layer 330. The process of forming the second via 900 includes an etching process. The second via 900 may expose one surface (e.g., the upper surface) of the third semiconductor region 901 and the fourth semiconductor region 902.

[0080] refer to Figure 9 and Figure 10 Source contact 311 and drain contact 312 are formed in the second through hole 900. A third insulating layer 350 is formed on source contact 311 and drain contact 312. Source line 321 and drain line 322 are formed on source contact 311 and drain contact 312 respectively through the third insulating layer 350.

[0081] refer to Figure 11 ,Will Figure 10 The semiconductor devices in the substrate are flipped. The lower portion of the second substrate 300 is removed to expose the third semiconductor region 901 and the fourth semiconductor region 902. The process for removing the lower portion of the second substrate 300 includes a chemical mechanical polishing (CMP) process or a grinding process.

[0082] In one embodiment, the upper surfaces of the third semiconductor region 901 and the fourth semiconductor region 902 may form substantially the same plane with a surface (e.g., the upper surface) of the second substrate 300. In one embodiment, the widths of the third semiconductor region 901 and the fourth semiconductor region 902 on a surface (e.g., the upper surface) of the second substrate 300 may be the same as the widths of the third semiconductor region 901 and the fourth semiconductor region 902 on a surface (e.g., the lower surface) of the second substrate 300, respectively.

[0083] refer to Figure 12A and Figure 12BA first substrate 200 is fabricated having a channel region 207 and a first semiconductor region 1201 and a second semiconductor region 1202 connected to the channel region 207. A gate insulating layer 203, a gate electrode 204, a gate capping layer 206, a spacer 205, a gate contact 214, and a gate line 224 formed on the first substrate 200 can be respectively connected to a reference... Figure 2 The gate insulating layer 203, gate electrode 204, gate capping layer 206, spacer 205, gate contact 214 and gate line 224 of the semiconductor device described are the same.

[0084] A first bonding insulating layer 251 is formed on one surface (e.g., the upper surface) of the first substrate 200. A second bonding insulating layer 252 is formed on one surface (e.g., the upper surface) of the second substrate 300.

[0085] refer to Figure 13A and 13B At least one third via 1301 is formed through the first bonding insulating layer 251. The process of forming the third via 1301 includes an etching process. The third via 1301 may expose one surface (e.g., the upper surface) of the first semiconductor region 1201 and the second semiconductor region 1202.

[0086] At least one fourth via 1302 is formed through the second bonding insulating layer 252. The process of forming the fourth via 1302 includes an etching process. The fourth via 1302 may expose one surface (e.g., the upper surface) of the third semiconductor region 901 and the fourth semiconductor region 902.

[0087] refer to Figure 13A , Figure 13B , Figure 14A and Figure 14B A first source region 201, a first drain region 202, a second source region 301, and a second drain region 302 can be formed by epitaxially growing a first semiconductor region 1201, a second semiconductor region 1202, a third semiconductor region 901, and a fourth semiconductor region 902. The first source region 201 and the first drain region 202 can fill the interior of the third via 1301. The second source region 301 and the second drain region 302 can fill the interior of the fourth via 1302.

[0088] In one embodiment, a surface (e.g., the upper surface) of the first source region 201 and the first drain region 202 may form substantially the same plane as a surface (e.g., the upper surface) of the first bonding insulating layer 251. In one embodiment, a surface (e.g., the upper surface) of the second source region 301 and the second drain region 302 may form substantially the same plane as a surface (e.g., the upper surface) of the second bonding insulating layer 252.

[0089] refer to Figure 15,Will Figure 14A The semiconductor device in the process is flipped. A first semiconductor structure S1 is bonded to a second semiconductor structure S2. For example, the lower surface of the first bonding insulating layer 251 is bonded to the upper surface of the second bonding insulating layer 252. The lower surface of the first source region 201 is connected to the upper surface of the second source region 301. The lower surface of the first drain region 202 is connected to the upper surface of the second drain region 302.

[0090] refer to Figure 16A and Figure 16B A first substrate 200 is fabricated having a channel region 207 and a first semiconductor region 1601 and a second semiconductor region 1602 connected to the channel region 207. A gate insulating layer 203, a gate electrode 204, a gate capping layer 206, a spacer 205, a gate contact 214, and a gate line 224 formed on the first substrate 200 can be respectively connected to a reference... Figure 3 The gate insulating layer 203, gate electrode 204, gate capping layer 206, spacer 205, gate contact 214 and gate line 224 of the semiconductor device described are the same.

[0091] In one embodiment, the widths of the first semiconductor region 1601 and the second semiconductor region 1602 on a surface (e.g., the upper surface) of the first substrate 200 may be smaller than the widths of the first semiconductor region 1601 and the second semiconductor region 1602 on a surface (e.g., the lower surface) of the first substrate 200, respectively.

[0092] Figure 16A The thickness of the first substrate 200 shown can be greater than Figure 12A The thickness of the first substrate 200 shown. Figure 16A The thicknesses of the first semiconductor region 1601 and the second semiconductor region 1602 shown can be greater than [amount missing]. Figure 12A The thickness of the first semiconductor region 1201 and the second semiconductor region 1202 shown.

[0093] A first bonding insulating layer 251 is formed on a first substrate 200, a first semiconductor region 1601, and a second semiconductor region 1602. A second bonding insulating layer 252 is formed on a second substrate 300, a third semiconductor region 901, and a fourth semiconductor region 902. The second bonding insulating layers 252 on the second substrate 300, the third semiconductor region 901, and the fourth semiconductor region 902 can be respectively bonded to a reference... Figure 12B The second bonding insulating layer 252 on the second substrate 300, the third semiconductor region 901 and the fourth semiconductor region 902 described are the same.

[0094] refer to Figure 17A and 17BAt least one fifth via 1701 is formed penetrating the first bonding insulating layer 251. The process of forming the fifth via 1701 includes an etching process. The fifth via 1701 may expose one surface (e.g., the upper surface) of the first semiconductor region 1601 and the second semiconductor region 1602. In one embodiment, the fifth via 1701 may expose at least a portion of one surface (e.g., the upper surface) of the first substrate 200.

[0095] At least one sixth via 1702 is formed penetrating the second bonding insulating layer 252. The process for forming the sixth via 1702 includes an etching process. The sixth via 1702 may expose one surface (e.g., the upper surface) of the third semiconductor region 901 and the fourth semiconductor region 902.

[0096] refer to Figure 18A and 18B Through epitaxial growth Figure 17A and Figure 17B The first semiconductor region 1601, the second semiconductor region 1602, the third semiconductor region 901, and the fourth semiconductor region 902 can form a first source region 401, a first drain region 402, a second source region 301, and a second drain region 302. The first source region 401 and the first drain region 402 can fill the interior of the fifth via 1701. The second source region 301 and the second drain region 302 can fill the interior of the sixth via 1702.

[0097] In one embodiment, one surface (e.g., the upper surface) of the first source region 401 and the first drain region 402 may form substantially the same plane as one surface (e.g., the upper surface) of the first bonding insulating layer 251. In one embodiment, one surface (e.g., the upper surface) of the second source region 301 and the second drain region 302 may form substantially the same plane as one surface (e.g., the upper surface) of the second bonding insulating layer 252. In one embodiment, the widths of the first source region 401 and the first drain region 402 on one surface (e.g., the upper surface) of the first substrate 200 may be smaller than the widths of the first source region 401 and the first drain region 402 on one surface (e.g., the lower surface) of the first substrate 200, respectively.

[0098] refer to Figure 19 ,Will Figure 18A The semiconductor device in the process is flipped. A first semiconductor structure S1 is bonded to a second semiconductor structure S2. For example, the lower surface of the first bonding insulating layer 251 is bonded to the upper surface of the second bonding insulating layer 252. The lower surface of the first source region 401 is connected to the upper surface of the second source region 301. The lower surface of the first drain region 402 is connected to the upper surface of the second drain region 302.

[0099] Refer again Figure 1The gate contact 114 is connected to the upper surface of the gate electrode 104 located on the first surface 100a of the substrate 100. The source contact 111 and the drain contact 112 are connected to the lower surfaces of the source region 101 and the drain region 102, and form the same plane with the second surface 100b of the substrate 100.

[0100] According to embodiments of this disclosure, the gate contact 114 may be positioned relative to the substrate 100 in a direction opposite to that of the source contact 111 and the drain contact 112. Therefore, the distance between the gate contact 114 and the source contact 111, or the distance between the gate contact 114 and the drain contact 112, is greater than the distance between the gate contact 114 and the source contact 111, or the distance between the gate contact 114 and the drain contact 112, when the gate contact 114, source contact 111, and drain contact 112 are positioned in the same direction relative to the substrate. Therefore, interference between the gate contact 114 and the source contact 111, and interference between the gate contact 114 and the drain contact 112, can be minimized. Thus, even with reduced transistor size due to high integration, transistor performance degradation due to interference between contacts can be avoided. Furthermore, since interference between the gate contact 114 and the source contact 111, as well as interference between the gate contact 114 and the drain contact 112, is minimized, the width of each contact does not decrease even if the size of the transistor TR is reduced. Therefore, the semiconductor device according to embodiments of this disclosure is advantageous for achieving high integration.

[0101] The above embodiments are for reference only, and those skilled in the art should understand that various modifications can be made to them without departing from the scope of this disclosure. Therefore, the embodiments described herein are for illustrative purposes only and are not intended to limit the scope of this disclosure. Furthermore, these embodiments can be combined to form other embodiments.

Claims

1. A semiconductor device, comprising: Substrate; A channel region, which is formed in a portion of the substrate; The source and drain regions are spaced apart from each other, penetrate the substrate, and are connected to the channel region. A gate insulating layer located on said portion of the substrate in a first direction; A gate electrode is disposed on the gate insulating layer; A gate contact, which is connected to the gate electrode; as well as Source and drain contacts are connected to the source and drain regions respectively under the substrate in a second direction opposite to the first direction.

2. The semiconductor device according to claim 1, wherein, The substrate includes a first surface and a second surface that are opposite to each other, and The upper surfaces of the source region and the drain region are coplanar with the first surface of the substrate, and the lower surfaces of the source region and the drain region are coplanar with or substantially coplanar with the second surface of the substrate.

3. The semiconductor device according to claim 2, wherein, The gate contact is connected to the upper surface of the gate electrode, and the source contact and the drain contact are respectively connected to the lower surface of the source region and the lower surface of the drain region.

4. The semiconductor device according to claim 2, wherein, The source contact and the drain contact are connected to the second surface of the substrate in the second direction.

5. The semiconductor device according to claim 1, wherein, The substrate includes a first substrate having the channel region and a second substrate located below the first substrate, and The first substrate and the second substrate are spaced apart from each other.

6. The semiconductor device of claim 5, further comprising a bonding insulating layer between the first substrate and the second substrate, in, The source region and the drain region penetrate the first substrate, the bonding insulating layer, and the second substrate.

7. The semiconductor device according to claim 5, wherein, The source contact and the drain contact are disposed below the second substrate.

8. A semiconductor device, comprising: The first semiconductor structure and the second semiconductor structure are bonded together. The first semiconductor structure includes: First bonded insulating layer; A first substrate is disposed on the first bonding insulating layer; A channel region is formed in a portion of the first substrate; A first source region and a first drain region are spaced apart from each other, penetrate the first substrate and the first bonding insulating layer, and are connected to the channel region; The gate electrode is located on the first substrate; and A gate contact, which is connected to the gate electrode, and The second semiconductor structure includes: A second bonding insulating layer is connected to the lower surface of the first bonding insulating layer; A second substrate is disposed below the second bonding insulating layer; The second source region and the second drain region penetrate the second substrate and the second bonding insulating layer, and are respectively connected to the first source region and the first drain region; and Source contacts and drain contacts are connected to the source region and the drain region, respectively.

9. The semiconductor device according to claim 8, wherein, The lower surface of the first bonding insulating layer forms a plane or substantially forms a plane with the lower surface of the first source region and the lower surface of the first drain region, and the upper surface of the second bonding insulating layer forms a plane or substantially forms a plane with the upper surface of the second source region and the upper surface of the second drain region.

10. The semiconductor device according to claim 8, wherein, The upper surface of the first substrate forms a plane or substantially forms a plane with the upper surface of the first source region and the upper surface of the first drain region, and the lower surface of the second substrate forms a plane or substantially forms a plane with the lower surface of the second source region and the lower surface of the second drain region.

11. The semiconductor device according to claim 8, wherein, The lower surfaces of the first source region and the first drain region are respectively connected to the upper surfaces of the second source region and the second drain region.

12. The semiconductor device according to claim 8, wherein, The second source region comprises the same material as the first source region, and the second drain region comprises the same material as the second source region.

13. The semiconductor device according to claim 8, wherein, The first source region, the first drain region, the second source region, and the second drain region are epitaxial growth layers.

14. A method for manufacturing a semiconductor device, the method comprising: A first substrate is prepared, the first substrate having an upper surface, on which a channel region and a first semiconductor region and a second semiconductor region connected to the channel region are formed; A gate electrode and a gate contact connected to the gate electrode are formed on the upper surface of the first substrate; Expose the lower surfaces of the first semiconductor region and the second semiconductor region; as well as Source contacts and drain contacts are formed that are respectively connected to the first semiconductor region and the second semiconductor region.

15. The method according to claim 14, wherein, The gate contact is located in the opposite direction to the source contact and the drain contact relative to the first substrate.

16. The method of claim 14, wherein, The lower surfaces of the first semiconductor region and the second semiconductor region are exposed by removing the lower portion of the first substrate, and the lower surfaces of the first semiconductor region and the second semiconductor region form the same plane as the lower surface of the first substrate.

17. The method of claim 14, further comprising: A second substrate is prepared, the second substrate having an upper surface on which a third semiconductor region and a fourth semiconductor region are formed; Expose the lower surfaces of the third semiconductor region and the fourth semiconductor region; A first bonding insulating layer is formed on the lower surface of the first semiconductor region and the lower surface of the second semiconductor region; A second bonding insulating layer is formed on the lower surface of the third semiconductor region and the lower surface of the fourth semiconductor region; as well as The first bonding insulating layer and the second bonding insulating layer are bonded together.

18. The method of claim 17, further comprising: Between the formation of the first bonding insulating layer and the bonding of the first bonding insulating layer and the second bonding insulating layer, the first source region and the first drain region are formed by epitaxial growth of the first semiconductor region and the second semiconductor region; as well as Between the formation of the second bonding insulating layer and the bonding of the first and second bonding insulating layers, the third semiconductor region and the fourth semiconductor region are epitaxially grown to form the second source region and the second drain region.

19. The method according to claim 18, wherein, The first source region and the first drain region are respectively connected to the second source region and the second drain region. Wherein, the source contact and the drain contact are respectively connected to the second source region and the second drain region, and The source contact and the drain contact are respectively connected to the first source region and the first drain region through the second source region and the second drain region.

20. The method of claim 14, wherein, The lower surface of the first semiconductor region and the lower surface of the second semiconductor region are exposed by removing the lower portion of the first substrate.

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