High voltage semiconductor device

Abstract

A high-voltage semiconductor device includes: a substrate; a well region of a first conductivity type within the substrate; a first drift region and a second drift region of a second conductivity type within the well region; a gate trench including: a bottom between the first drift region and the second drift region, the bottom partially defining the well region; and first and second sidewalls facing each other, the first and second sidewalls respectively partially defining the first drift region and the second drift region; a gate insulating film covering the bottom of the gate trench, the first sidewall, and the second sidewall; a gate electrode buried in a lower region of the gate trench; and a field distribution structure disposed on the gate electrode in an upper region of the gate trench and extending above the upper surfaces of the first drift region and the second drift region.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2024-0197453, filed on December 26, 2024, with the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference for all purposes. Technical Field

[0003] The exemplary embodiments of the present invention relate to high-voltage semiconductor devices. Background Technology

[0004] High-voltage semiconductor devices are typically used in a wide range of integrated circuits, such as non-volatile memory or display driver ICs (DDIs). For example, high-voltage semiconductor devices may include high-voltage transistors with recessed trench channels and may be used with transistors that may have different operating voltages and / or functions (e.g., transistors with flat channels).

[0005] Specifically, methods have been investigated for ensuring electrical characteristics such as high breakdown voltage and / or low gate-induced drain leakage (GIDL) in the impurity regions of the source / drain of high-voltage transistors with recessed channels. Summary of the Invention

[0006] Some example embodiments provide a high-voltage semiconductor device with improved electrical characteristics.

[0007] According to some example embodiments, a high-voltage semiconductor device includes: a substrate; a well region of a first conductivity type within the substrate; a first drift region and a second drift region of a second conductivity type within the well region; a gate trench including: a bottom between the first drift region and the second drift region, the bottom partially defining the well region; and first and second sidewalls facing each other, the first and second sidewalls respectively partially defining the first drift region and the second drift region; a gate insulating film covering the bottom of the gate trench, the first sidewall, and the second sidewall; a gate electrode buried in a lower region of the gate trench; and a field distribution structure disposed on the gate electrode in an upper region of the gate trench and extending above the upper surfaces of the first drift region and the second drift region.

[0008] According to some example embodiments, a high-voltage semiconductor device includes: a substrate; a well region of a first conductivity type within the substrate; a first drift region and a second drift region of a second conductivity type disposed in the well region in a first direction; a gate trench extending in a second direction between the first drift region and the second drift region, the second direction intersecting the first direction, and the gate trench including a bottom partially defining the well region, and a first sidewall and a second sidewall facing each other, the first sidewall and the second sidewall respectively partially defining the first drift region and the second drift region; a gate insulating film covering the bottom of the gate trench, the first sidewall and the second sidewall; a gate electrode buried in the lower region of the gate trench and extending in the second direction; an interlayer insulating layer on the substrate and covering the first drift region, the second drift region and the gate electrode; a first contact plug and a second contact plug penetrating the interlayer insulating layer and respectively connected to the first drift region and the second drift region; and a field distribution structure penetrating the interlayer insulating layer and extending in the second direction on the gate electrode, the field distribution structure comprising the same material as the first contact plug and the second contact plug.

[0009] According to some example embodiments, a high-voltage semiconductor device includes: a substrate; a well region of a first conductivity type within the substrate; a first drift region and a second drift region of a second conductivity type disposed in the well region in a first direction; a gate trench extending in a second direction between the first drift region and the second drift region, the second direction intersecting the first direction, and the gate trench including a bottom partially defining the well region, and a first sidewall and a second sidewall facing each other, the first sidewall and the second sidewall respectively partially defining the first drift region and the second drift region; a gate insulating film covering the bottom of the gate trench, the first sidewall and the second sidewall; a gate electrode buried in the lower region of the gate trench and extending in the second direction; a field distribution structure extending in the second direction on the gate electrode, and the upper surface of the field distribution structure being higher than the upper surfaces of the first drift region and the second drift region, the field distribution structure comprising the same material as the gate electrode; an interlayer insulating layer on the substrate and covering the first drift region, the second drift region, the gate electrode and the field distribution structure; and a first contact plug and a second contact plug penetrating the interlayer insulating layer and respectively connected to the first drift region and the second drift region.

[0010] According to some example embodiments, a method of manufacturing a high-voltage semiconductor device includes: forming a well region on a first region and a second region of a semiconductor substrate, the well region including a first conductivity type; forming a device isolation region in the well region, the device isolation region defining an active region; forming a first drift region and a second drift region in the first region and the second region, respectively; forming a gate trench in the first region using a first photoresist pattern; forming a channel region below the gate trench in the first region using an ion implantation process; removing the first photoresist pattern; and forming a gate insulating film in the first region and the second region, the gate insulating film covering the gate trench. The device includes an inner surface, a device isolation region, a well region, a first drift region, and a second drift region; a conductive material layer is formed on a gate insulating film, the conductive material layer at least partially filling a gate trench; a second photoresist pattern is formed on the conductive material layer in a second region; an etch-back process is performed to form a first gate electrode and a second gate electrode in the first region and the second region, respectively; gate spacers are formed on the sidewalls of the second gate electrode in the second region and on the inner sidewalls of the gate trench in the first region; and an interlayer insulating layer is formed covering the device isolation region, the well region, the first drift region, the second drift region, and the first and second gate electrodes.

[0011] According to some example embodiments, a method of manufacturing a high-voltage semiconductor device further includes: forming contact holes in an interlayer insulating layer in a first region and a second region, the contact holes exposing a first drift region, a second drift region, a first gate electrode and a second gate electrode, forming a field distribution structure in contact with the first gate electrode and the second gate electrode, and forming a first contact plug and a second contact plug in contact with the first drift region and the second drift region, respectively. Attached Figure Description

[0012] The above and other aspects, features, and advantages of the present invention will become more clearly understood from the following detailed description, taken in conjunction with the accompanying drawings, in which:

[0013] Figure 1 This is a plan view of a high-voltage semiconductor device according to some example embodiments;

[0014] Figure 2 It is along Figure 1 A side view of the cross section taken along line I-I' of the high-voltage semiconductor device shown;

[0015] Figure 3 It shows Figure 2 A partial enlarged view of part A1 of the high-voltage semiconductor device shown;

[0016] Figures 4A to 4C This is a schematic diagram illustrating impact ionization in high-voltage semiconductor devices having various gate structures (Comparative Example 1, Comparative Example 2, and Exemplary Embodiments);

[0017] Figures 5A to 5C This is a schematic diagram showing the interband generation distribution of charge carriers in high-voltage semiconductor devices having various gate structures (Comparative Example 1, Comparative Example 2, and Exemplary Embodiments);

[0018] Figure 6 IV curves of high-voltage semiconductor devices according to Comparative Example 1, Comparative Example 2 and Example Embodiment are shown;

[0019] Figures 7A to 7I This is a cross-sectional view of the main process, illustrating a method for manufacturing a high-voltage semiconductor device according to some example embodiments;

[0020] Figure 8 and Figure 9 These are plan views and side cross-sectional views of a high-voltage semiconductor device according to some example embodiments;

[0021] Figure 10 and Figure 11 These are plan views and side cross-sectional views of a high-voltage semiconductor device according to some example embodiments;

[0022] Figure 12 It shows Figure 11 A partial enlarged view of part A2 of the high-voltage semiconductor device shown; and

[0023] Figures 13A to 13D This is a cross-sectional view of the main process, illustrating a method for manufacturing a high-voltage semiconductor device according to some example embodiments. Detailed Implementation

[0024] In the following description, some exemplary embodiments will be illustrated with reference to the accompanying drawings.

[0025] Figure 1 This is a plan view illustrating a high-voltage semiconductor device according to some example embodiments, and Figure 2 It is along Figure 1 The image shows a cross-sectional side view of the high-voltage semiconductor device taken along line I-I'. In this case... Figure 1 This can be understood as a planar diagram of a high-voltage semiconductor device, excluding... Figure 2 Interlayer insulation layer 150.

[0026] refer to Figure 1 and Figure 2 According to some example embodiments, a high-voltage semiconductor device 100 may include: a substrate 101; a well region 102 of a first conductivity type within the substrate 101; a first drift region 105A and a second drift region 105B of a second conductivity type, facing each other in the well region 102 along a first direction D1; and a buried gate electrode 130 between the first drift region 105A and the second drift region 105B.

[0027] Substrate 101 may include, for example, a semiconductor such as Si or Ge, or a compound semiconductor such as SiGe, SiC, GaAs, InAs, or InP. In another example, substrate 101 may have a silicon-on-insulator (SOI) structure. However, the example embodiments are not limited thereto. Substrate 101 may include a first conductivity type impurity, and therefore may have a first conductivity type. In some example embodiments, the first conductivity type may be, for example, P-type, and the first conductivity type impurity may be, for example, a P-type impurity, such as aluminum (Al). In some example embodiments, the first conductivity type may be, for example, N-type, and the first conductivity type impurity may be, for example, an N-type impurity, such as nitrogen (N) and / or phosphorus (P). However, the example embodiments are not limited thereto.

[0028] A device isolation region 110 can be formed in the substrate 101 to define the active region of the high-voltage semiconductor device 100. A first drift region 105A and a second drift region 105B can be respectively disposed on opposite sides of the active region defined by the device isolation region 110. Figure 1 As shown, the device isolation region 110 may extend along a second direction D2 intersecting the first direction D1. The device isolation region 110 may include one or more insulating materials, such as silicon oxide, silicon nitride, or silicon oxynitride, filling trenches formed in the well region 102. However, the example embodiment is not limited thereto. For example, the device isolation region 110 is also referred to as shallow trench isolation (STI).

[0029] Well region 102 includes a first conductivity type impurity and therefore may have a first conductivity type. Well region 102 may also be referred to as a "high-voltage well region". In some example embodiments, the first conductivity type may be, for example, P-type, and the first conductivity type impurity may be, for example, a P-type impurity, such as aluminum (Al). In some example embodiments, the first conductivity type may be, for example, N-type, and the first conductivity type impurity may be, for example, an N-type impurity, such as nitrogen (N) and / or phosphorus (P). In some example embodiments, well region 102 may be formed by implanting the first conductivity type impurity into substrate 101 using a mask such as a photoresist pattern.

[0030] The first drift region 105A and the second drift region 105B include impurities of a second conductivity type, and therefore can have a second conductivity type. The first drift region 105A and the second drift region 105B can be formed to expose the upper surface of the substrate 101. For example... Figure 1As shown, the first drift region 105A and the second drift region 105B can extend along the second direction D2. In some example embodiments, the second conductivity type can be, for example, N-type, and the second conductivity type impurity can be, for example, an N-type impurity, such as nitrogen (N) and / or phosphorus (P). In some example embodiments, the second conductivity type can be, for example, P-type, and the second conductivity type impurity can be, for example, a P-type impurity, such as aluminum (Al). However, the example embodiments are not limited thereto. In some example embodiments, the first drift region 105A and the second drift region 105B can be formed by injecting the second conductivity type impurity into both sides of the well region 102 using a mask such as a photoresist pattern.

[0031] In some example embodiments, the buried gate electrode 130 may be formed in a gate trench GT between the first drift region 105A and the second drift region 105B. The gate trench GT may be formed by an etching process using photolithography. In some example embodiments, the gate trench GT may be formed after the first drift region 105A and the second drift region 105B are formed. The bottom of the gate trench GT may be provided by the well region 102, and the two sidewalls of the gate trench GT may be provided by the first drift region 105A and the second drift region 105B. The sidewalls of the gate trench GT may be provided by the first drift region 105A and the second drift region 105B over almost the entire area.

[0032] The high-concentration impurity region 104 for the channel region can be formed in the well region 102 exposed at the bottom of the gate trench GT. In some example embodiments, the high-concentration impurity region 104 can be obtained by an ion implantation process using the mask for forming the gate trench GT as is, without the need for an additional mask (see [link to example]). Figure 7D The high-concentration impurity region 104 can be additionally implanted with impurities to control the threshold voltage. For example, the impurity concentration in the high-concentration impurity region 104 can be higher than the impurity concentration in the region of the well region 102 defined as the bottom of the gate trench GT in the well region 102.

[0033] Figure 3 It shows Figure 2 A partial enlarged view of part A1 of the high-voltage semiconductor device shown.

[0034] refer to Figure 3 and Figure 2 The sidewalls of the gate trench GT are shown as having a plane that is almost perpendicular to the bottom of the gate trench GT (or the upper surface of the substrate 101), but the example embodiments are not limited to this, and in some example embodiments, the sidewalls of the gate trench GT may be inclined relative to the bottom of the gate trench GT.

[0035] In some example embodiments, the gate trench GT may be formed such that at least a portion of the two corners TC at its bottom are covered by the first drift region 105A and the second drift region 105B. In some example embodiments, the bottom of the gate trench GT may be formed such that it is substantially the same as or higher than the lower surfaces of the first drift region 105A and the second drift region 105B. Therefore, the bottom of the gate electrode 130 in the gate trench GT may have a level equal to (or substantially equal to) or higher than the lower surfaces of the first drift region 105A and the second drift region 105B. In some example embodiments, the bottom of the gate electrode 130 may be higher than the lower surfaces of the first drift region 105A and the second drift region 105B by an amount represented by "D". For example, the depth d of the gate trench GT may be from 0.3µm to 0.6µm, and the width S of the gate trench GT may be from 0.4µm to 0.8µm.

[0036] The gate insulating film 120 may be conformally formed to cover the inner surface of the gate trench GT, such as the bottom and two sidewalls. In some example embodiments, the gate insulating film 120 may extend to the upper end of the sidewalls of the gate trench GT. The gate insulating film 120 may include, for example, silicon oxide, silicon oxynitride, a high-k dielectric, a combination thereof, or a laminate thereof. However, the example embodiments are not limited thereto. High-k dielectrics may include HfO2, ZrO2, Al2O3, Ta2O5, hafnium silicate, zirconium silicate, or a combination thereof. However, the example embodiments are not limited thereto. When the gate insulating film 120 is silicon oxide, the silicon oxide may be formed by an oxidation process (e.g., a thermal oxidation process), but the example embodiments are not limited thereto, and the gate insulating film 120 may be formed by chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD), or a combination thereof. For example, the thickness of the gate insulating film 120 may be from 100 Å to 500 Å.

[0037] The gate electrode 130 is buried in the lower region of the gate trench GT and may be disposed on the gate insulating film 120. For example, the gate electrode 130 may comprise polysilicon. The polysilicon may be doped with N-type or P-type impurities. In some example embodiments, the gate electrode 130 may comprise a metal, such as tungsten.

[0038] The gate electrode 130 can be deposited by chemical vapor deposition (CVD) or physical vapor deposition (PVD). In some example embodiments, the gate electrode 130 used can be obtained by a etch-back process after the material of the gate electrode 130 is deposited, without the need for an additional mask (see [link to documentation]). Figure 7G ).like Figure 2 and Figure 3 As shown, the gate electrode 130 may have an upper surface 130T on which a concave valley is formed. The valley may extend in a second direction D2 in which the gate electrode 130 extends.

[0039] The upper end of the gate electrode 130 (the portion in contact with the gate insulating film 120) can be at a level that is 50% or more of the total depth d of the gate trench GT. In some example embodiments, the upper end of the gate electrode 130 can be at a level that is 70% or more of the total depth d. Thus, the gate electrode in contact with the gate insulating film 120 may not be present in the upper region of the gate trench GT (the region indicated by "d2"). In the off state, the gate electrode 130 does not extend to the upper region of the first drift region 105A or the second drift region 105B, which is beneficial for improving breakdown voltage characteristics, but may reduce GIDL characteristics.

[0040] To improve GIDL characteristics while maintaining improved breakdown voltage characteristics, the high-voltage semiconductor device 100 according to some example embodiments may include a field distribution structure FD disposed on the gate electrode 130 in the upper region of the gate trench GT. The field distribution structure FD may extend above the upper surfaces of the first drift region 105A and the second drift region 105B.

[0041] like Figure 3 As shown, the two side surfaces of the field distribution structure FD can be spaced apart from the gate insulating film 120. The field distribution structure FD can be spaced apart from the sidewalls of the gate trench GT by a gap G, which is larger than the gap between the gate electrode 130 and the sidewalls of the gate trench GT.

[0042] Specifically, the gaps between the gate electrode 130 and the first drift region 105A and the gate electrode 130 and the second drift region 105B are defined by the gate insulating film 120, while the gaps G between the field distribution structure FD and the first drift region 105A and the field distribution structure FD and the second drift region 105B can be greater than the thickness of the gate insulating film 120. In some example embodiments, a portion 150E extending from the interlayer insulating layer 150 and residual spacer material 140D can be located in the gap between the field distribution structure FD and the gate insulating film 120. The residual spacer material 140D can be located on the two sidewalls of the gate trench on the gate electrode 130. The residual spacer material 140D can be spacer material left over from the formation of the gate spacer of the MOSFET device in another region of the substrate 101 (see [link to documentation]). Figure 7H For example, the residual spacer material 140D may include silicon nitride or silicon oxynitride. However, the example embodiments are not limited thereto.

[0043] refer to Figure 1The gate electrode 130 extends along a second direction D2 between the first drift region 105A and the second drift region 105B, and the field distribution structure FD can be spaced apart from the upper regions of the first drift region 105A and the second drift region 105B by a certain distance, and can extend along the second direction D2. In some example embodiments, in a plan view, the field distribution structure FD can have a strip shape extending in the second direction D2.

[0044] In this way, the field distribution structure FD can maintain the improved breakdown voltage characteristics through the lower gate electrode 130 by separating it from the upper regions of the first drift region 105A and the second drift region 105B, and can further improve the GIDL characteristics by extending from the upper regions of the first drift region 105A and the second drift region 105B along the second direction D2 to disperse the electric field concentrated on the upper end of the gate electrode 130.

[0045] refer to Figure 1 and Figure 2 Source / drain regions 107A and 107B can be respectively disposed in the first drift region 105A and the second drift region 105B. The impurity concentration of source / drain regions 107A and 107B can be higher than the impurity concentration of the first drift region 105A and the second drift region 105B. Multiple source / drain regions 107A and 107B have the same second conductivity type as the first drift region 105A and the second drift region 105B. Multiple source / drain regions 107A and 107B can be arranged along a second direction D2 in the first drift region 105A and the second drift region 105B. Multiple source / drain regions 107A and 107B can be formed by implanting impurities of the second conductivity type into the first drift region 105A and the second drift region 105B using a mask (e.g., a photoresist pattern). In some example embodiments, multiple source / drain regions 107A and 107B may be connected to each other in the first drift region 105A and the second drift region 105B and configured as a line.

[0046] Multiple source / drain regions 107A and 107B are formed from the surfaces of the first drift region 105A and the second drift region 105B, and may have a thickness thinner than the first drift region 105A and the second drift region 105B. Compared to the first drift region 105A and the second drift region 105B, the source / drain regions 107A and 107B may be further spaced from the gate trench GT. This arrangement of source / drain regions 107A and 107B can improve breakdown voltage characteristics.

[0047] refer to Figure 2According to some example embodiments, the high-voltage semiconductor device 100 may further include: an interlayer insulating layer 150 covering a first drift region 105A and a second drift region 105B and a gate electrode 130 on a substrate 101; and a plurality of first contact plugs 180A and a plurality of second contact plugs 180B penetrating the interlayer insulating layer 150 and electrically connected to the first drift region 105A and the second drift region 105B, respectively. For example, the plurality of first contact plugs 180A and the plurality of second contact plugs 180B may include at least one of nickel (Ni), aluminum (Al), titanium (Ti), silver (Ag), vanadium (V), tungsten (W), cobalt (Co), molybdenum (Mo), copper (Cu), and ruthenium (Ru). However, the example embodiments are not limited thereto. In some example embodiments, the source / drain regions in contact with the plurality of first contact plugs 180A and the plurality of second contact plugs 180B may include a metal semiconductor compound layer (not shown) to reduce contact resistance. For example, the metal-semiconductor compound layer may include at least one of TiSi, CoSi, MoSi, LaSi, NiSi, TaSi, or WSi. However, the example embodiments are not limited thereto.

[0048] refer to Figure 1 Multiple first contact plugs 180A and multiple second contact plugs 180B can be arranged along the second direction D2. The multiple first contact plugs 180A and multiple second contact plugs 180B can be connected to the source / drain regions 107A and 107B respectively, and can be electrically connected to the first drift region 105A and the second drift region 105B through the source / drain regions 107A and 107B.

[0049] In some example embodiments, the field distribution structure FD may include a different conductive material than the gate electrode 130. For example, the field distribution structure FD may include at least one of nickel (Ni), aluminum (Al), titanium (Ti), silver (Ag), vanadium (V), tungsten (W), cobalt (Co), molybdenum (Mo), copper (Cu), and ruthenium (Ru). However, the example embodiments are not limited thereto. The field distribution structure FD may include the same material as the first contact plug 180A and the second contact plug 180B. As described above, in the plan view, the field distribution structure FD is a strip shape extending in the second direction D2, but similar to the first contact plug 180A and the second contact plug 180B, it can be used as a third contact plug 180C connected to the gate electrode 130. The first interconnect pattern to the third interconnect pattern 190A, 190B and 190C are disposed on the interlayer insulating layer 150, and the first interconnect pattern to the third interconnect pattern 190A, 190B and 190C can be connected to the first contact plug to the third contact plug 180A, 180B and 180C respectively.

[0050] refer to Figure 2Taking into account the gap between the first drift region 105A and the second drift region 105B, a field distribution structure FD is formed within the gate trench GT. Therefore, the field distribution structure FD can have a width Wc that is different from the width Wa of the first contact plug 180A and the width Wb of the second contact plug 180B. In some example embodiments, the width Wc of the field distribution structure FD can be greater than the width Wa of the first contact plug 180A and the width Wb of the second contact plug 180B. The upper surface of the field distribution structure FD can be at the same level as the upper surfaces of the first contact plug 180A and the second contact plug 180B. After forming holes for the first contact plug 180A and the second contact plug 180B and trenches for the field distribution structure FD in the interlayer insulating layer 150, conductive material can be filled into the holes and trenches. Chemical mechanical polishing (CMP) can then be applied until the upper surface of the interlayer insulating layer 150 is exposed to remove any residual conductive material on the interlayer insulating layer 150.

[0051] According to some example embodiments, the breakdown voltage characteristics can be improved by reducing the gate electrode 130 in the gate trench. Furthermore, by separating the field distribution structure FD on the gate electrode 130 from the upper regions of the first drift region 105A and the second drift region 105B, improved breakdown voltage characteristics can be maintained while dispersing the electric field concentrated on the upper end of the gate electrode 130, thereby improving GIDL characteristics.

[0052] To verify the effects of some example embodiments, the electrical characteristics of high-voltage semiconductor devices (Comparative Example 1, Comparative Example 2 and Example Embodiments) with various gate structures were compared.

[0053] It is understood that the high-voltage semiconductor devices according to Comparative Example 1, Comparative Example 2 and the exemplary embodiment have the same specifications, except that they differ only in the shape of the gate electrode and the presence or absence of the field distribution structure.

[0054] First of all, Figure 4A and Figure 5A In the high-voltage semiconductor device (Comparative Example 1), the gate electrode 130A is configured to almost fill the entire region of the gate trench GT; while Figure 4B and Figure 5B In the high-voltage semiconductor device shown (Comparative Example 2), the gate electrode 130B can be configured to fill the lower region of the gate trench GT (approximately 80% of the total depth). In Comparative Examples 1 and 2, the third contact plug (not shown) connected to the gate electrodes 130A and 130B can be connected to any point on the gate electrodes 130A and 130B extending in one direction from a planar perspective.

[0055] In comparison, Figure 4C and Figure 5CThe high-voltage semiconductor device (example embodiment) is similar to Comparative Example 2 in that the gate electrode 130 fills the lower region of the gate trench GT (approximately 80% of the total depth). Figure 4C and Figure 5C In the high-voltage semiconductor device, the field distribution structure FD is disposed on the gate electrode 130, and the field distribution structure FD has a strip shape extending along the extension direction of the gate electrode 130.

[0056] Figures 4A to 4C This is a schematic diagram illustrating impact ionization in high-voltage semiconductor devices having various gate structures (Comparative Example 1, Comparative Example 2, and Exemplary Embodiment); and Figures 5A to 5C This is a schematic diagram illustrating the interband generation distribution in high-voltage semiconductor devices having various gate structures (Comparative Example 1, Comparative Example 2, and Example Embodiment). Furthermore, Figure 6 The IV curves of the high-voltage semiconductor devices according to Comparative Example 1, Comparative Example 2 and Example Embodiment are shown, and the results measured in the drain region in the gate-off state are shown in detail.

[0057] refer to Figure 4A , Figure 4B and Figure 6 By reducing the gate electrode (130A→130B) within the gate trench GT, the distance between the gate electrode and the drain region increases, thereby delaying or improving avalanche breakdown at the surface of the first drift region 105A. In this way, Comparative Example 2 can have improved breakdown voltage characteristics compared to Comparative Example 1.

[0058] On the other hand, reference Figure 5A , Figure 5B and Figure 6 Because of the increased interband carrier generation (B2B) in the sidewalls of the gate trench adjacent to the upper end of the gate electrode (e.g., the first drift region 105A), Comparative Example 2 may have worse GIDL characteristics compared to Comparative Example 1.

[0059] refer to Figure 4C and Figure 6 In some example embodiments, by providing a field distribution structure FD on the gate electrode while separating the field distribution structure FD from the upper regions of the first drift region 105A and the second drift region 105B, improved breakdown voltage characteristics similar to those of the gate electrode 130B in Comparative Example 2 can be maintained. Furthermore, refer to... Figure 5C and Figure 6 In some example embodiments, the GIDL characteristics can be further improved by using a field distribution structure FD extending along the extension direction of the gate electrode 130 between the first drift region 105A and the second drift region 105B to disperse the electric field concentrated on the upper end of the gate electrode 130.

[0060] Thus, the high-voltage semiconductor device 100 according to some example embodiments can significantly improve its electrical characteristics in the off state by forming a gate electrode 130 in the lower region of the gate trench GT and providing a field distribution structure FD extending along the gate electrode on the gate electrode 130.

[0061] Figures 7A to 7I These are cross-sectional views of the main processes, illustrating methods for manufacturing high-voltage semiconductor devices according to some example embodiments. The processes according to some example embodiments can be understood as simultaneously forming in a first region I and a second region II of a substrate 101. Figures 1 to 3 The process of high-voltage semiconductor device 100 and another planar MOSFET element.

[0062] refer to Figure 7A A first conductivity type well region 102 can be formed on the first region I and the second region II of the substrate 101, and a device isolation region 110 defining the active region can be formed.

[0063] In some example embodiments, the substrate 101 may include, for example, a semiconductor such as Si or Ge, or a compound semiconductor such as SiGe, SiC, GaAs, InAs, or InP. In another example, the substrate 101 may have a silicon-on-insulator (SOI) structure. However, the example embodiments are not limited thereto. The substrate 101 may be a first conductivity type substrate including impurities of a first conductivity type (e.g., P-type). Next, a first conductivity type well region 102 may be formed by implanting the first conductivity type impurities into a first region I and a second region II of the substrate 101 using a mask (e.g., a photoresist pattern). In the second region II, when forming a low-voltage MOSFET or a MOSFET of another conductivity type, an additional mask may be used to form a well region with different impurity concentrations or a well region with different conductivity type impurity concentrations in the second region II.

[0064] Device isolation regions 110 may be formed in each of the first region I and the second region II of substrate 101 to define an active region for forming a device (e.g., a MOSFET). The device isolation region 110 may extend along a second direction D2 intersecting the first direction D1. In this way, an active region extending in the second direction D2 may be provided in each of the first region I and the second region II of substrate 101. In some example embodiments, the device isolation region 110 may be formed from different planar perspectives to form semiconductor devices with different layouts (e.g., see...). Figure 8 ).

[0065] Next, refer to Figure 7BA first drift region 105A and a second drift region 105B, as well as a first drift region 105A' and a second drift region 105B', can be formed in the first region I and the second region II of the substrate 101, respectively.

[0066] In this process, a first drift region 105A and a second drift region 105B, as well as a first drift region 105A' and a second drift region 105B', can be formed by implanting impurities of a second conductivity type into both sides of the active region (e.g., well region 102) of each of the first region I and the second region II of the substrate 101 using a mask (e.g., a photoresist pattern). In the first region I of the substrate 101, as... Figure 1 As shown, the first drift region 105A and the second drift region 105B can extend along the second direction D2. Similarly, in the second region II of the substrate 101, the first drift region 105A' and the second drift region 105B' can extend along the second direction D2.

[0067] The inventive concept is not limited thereto, and in some exemplary embodiments, as described above, the first drift region 105A and the second drift region 105B, as well as the first drift region 105A' and the second drift region 105B', may have different layouts depending on the pattern of the active region defined by the device isolation region 110.

[0068] Next, refer to Figure 7C A gate trench GT can be formed in a first region I of substrate 101 using a first photoresist pattern PR1.

[0069] The first photoresist pattern PR1 has an opening defining a gate trench GT in a first region I of the substrate 101, and can be formed to completely cover a second region II of the substrate 101. The gate trench GT can be formed by an etching process using the first photoresist pattern PR1.

[0070] The gate trench GT can be formed after the formation of the first drift region 105A and the second drift region 105B. In some example embodiments, the gate trench GT can extend in the second direction D2. By controlling the position and width of the gate trench GT, the first drift region 105A and the second drift region 105B can be formed such that they are open on both sidewalls of the gate trench GT.

[0071] Furthermore, the gate trench GT can be formed such that the well region 102 is open at the bottom of the gate trench GT. In some example embodiments, the bottom of the gate trench GT may be at a level substantially the same as or higher than the lower surfaces of the first drift region 105A and the second drift region 105B. For example, the lower corner of the gate trench GT may be at least partially covered by the first drift region 105A and the second drift region 105B.

[0072] In some example embodiments, the sidewalls of the gate trench GT are typically shown to have a surface that is substantially perpendicular to the upper surface of the substrate 101, but the example embodiments are not limited thereto, and in some example embodiments, the sidewalls of the gate trench GT may have a slightly inclined surface.

[0073] Next, refer to Figure 7D An ion implantation process can be performed on the bottom of the gate trench GT using the first photoresist pattern PR1.

[0074] This ion implantation process can be introduced as a process for controlling the threshold voltage of the channel region 104. For example, a first conductivity type impurity can be additionally implanted in this process. The first photoresist pattern PR1 for forming the gate trench GT can be used as is in this ion implantation process. The channel region 104 with an adjusted threshold voltage can be formed at the bottom of the gate trench GT. In some example embodiments, even if the sidewalls of the gate trench GT are slightly tilted, it will not have a significant impact on the regions adjacent to the sidewalls of the first drift region 105A and the second drift region 105B, which have relatively high concentrations of impurities to be ion implanted, because the impurities to be ion implanted are relatively small.

[0075] Next, refer to Figure 7E After removing the first photoresist pattern PR1, a gate insulating film 120L can be formed in the first region I and the second region II of the substrate 101.

[0076] In the first region I of the substrate 101, a gate insulating film 120L may be conformally formed to cover the inner surface of the gate trench GT, such as the bottom and the two sidewalls. For example, the gate insulating film 120L may comprise silicon oxide, silicon oxynitride, a high-k dielectric, a combination thereof, or a laminate thereof. However, the exemplary embodiments are not limited thereto. High-k dielectrics may comprise HfO2, ZrO2, Al2O3, Ta2O5, hafnium silicate, zirconium silicate, or a combination thereof. However, the exemplary embodiments are not limited thereto.

[0077] In some example embodiments, the same gate insulating film 120L is formed in both the first region I and the second region II of the substrate 101, but a different gate insulating film than the gate insulating film in the first region I can be formed in the second region II. For example, when a low-voltage MOSFET is formed in the second region II of the substrate 101, an additional mask can be used to form a gate insulating film of a different material and / or a different number of layers in the second region II.

[0078] Next, refer to Figure 7F A conductive material layer 130L for the gate electrode can be formed on the first region I and the second region II of the substrate 101.

[0079] The conductive material layer 130L may fill the gate trench GT in the first region I of the substrate 101. The conductive material layer 130L may include polysilicon. The polysilicon may be doped with N-type or P-type impurities. In some example embodiments, the conductive material layer 130L may include a metal, such as tungsten. The conductive material layer 130L may be deposited by chemical vapor deposition (CVD) or physical vapor deposition (PVD).

[0080] Next, a second photoresist pattern PR2 can be formed on a portion of the conductive material layer 130L located in the second region II of the substrate 101. The second photoresist pattern PR2 can define a portion of the conductive material layer 130L corresponding to the gate electrode.

[0081] Next, refer to Figure 7G An etch-back process can be performed on the conductive material layer 130L in the first region I and the second region II of the substrate 101 to form gate electrodes 130 and 130' and gate insulating films 120 and 120'.

[0082] In this process, in the first region I of the substrate 101, the gate electrode 130 can be retained in the lower region of the gate trench GT by performing an etch-back process across the entire surface (without an additional mask), and in the second region II, the gate electrode 130' defined by the second photoresist pattern PR2 can be formed. During or after the etch-back process, the exposed gate insulating film portions can be removed by means of a separate etching process, and gate insulating films 120 and 120' can be formed in the first region I and the second region II of the substrate 101, respectively.

[0083] Next, refer to Figure 7H and Figure 7I Gate spacers 140S can be formed on the sidewall of the gate electrode 130' in the second region II of the substrate 101.

[0084] The process of forming the gate spacer 140S can be performed by forming a spacer material layer over a first region I and a second region II of the substrate 101 and applying anisotropic etching to remove a portion of the spacer material layer from a surface parallel to the upper surface of the substrate 101.

[0085] In the process of forming the gate spacer 140S, a residual spacer material 140D can be formed in the first region I of the substrate 101 on the inner sidewall portion of the gate trench GT located on the gate electrode 130.

[0086] Additionally, source / drain regions 107A and 107B, and source / drain regions 107A' and 107B', can be formed in the first drift region 105A and the second drift region 105B, and in the first drift region 105A' and the second drift region 105B', respectively, in the first region I and the second region II of the substrate 101. The impurity concentrations of the source / drain regions 107A, 107B, 107A', and 107B' can be higher than the impurity concentrations of the first drift region 105A and the second drift region 105B, and in the first drift region 105A' and the second drift region 105B'.

[0087] Next, refer to Figure 7I An interlayer insulating layer 150 is formed on a first region I and a second region II of the substrate 101. Contact holes CH1a, CH1b, CH2a, and CH2b, connecting to the source / drain regions 107A, 107B, 107A', and 107B', and a trench TR for the field distribution structure FD can be formed in the interlayer insulating layer 150. In a plan view, unlike the contact holes CH1a, CH1b, CH2a, and CH2b, the trench TR can have a shape extending along the gate electrode 130 in the second direction D2.

[0088] In subsequent processes, contact holes CH1a, CH1b, CH2a, and CH2b, as well as trench TR, are filled with conductive material, followed by chemical mechanical polishing (CMP) until the upper surface of the interlayer insulating layer 150 is exposed to remove any residual conductive material on the interlayer insulating layer 150. Therefore, a conductive material is formed in the first region I of the substrate 101 as described above. Figures 1 to 3 The high-voltage semiconductor device 100 (or high-voltage MOSFET) shown can be formed in the second region II of the substrate 101, and the MOSFET 200 can be formed in a planar structure.

[0089] Figure 8 and Figure 9 These are plan views and side cross-sectional views of a high-voltage semiconductor device according to some example embodiments.

[0090] refer to Figure 8 and Figure 9The high-voltage semiconductor device 100A according to some example embodiments can be understood as being similar to... Figures 1 to 3 The high-voltage semiconductor device 100 shown is similar, except that it has a ring structure in the plan view and a ring field distribution structure FD1 corresponding to the gate electrode 130. Furthermore, unless otherwise specifically described, it can be understood by referring to... Figures 1 to 3 The description of the same or similar components of the high-voltage semiconductor device 100 shown is used to understand the components of some example embodiments.

[0091] Unlike the high-voltage semiconductor device 100 according to the previous example embodiment, the high-voltage semiconductor device 100A according to some example embodiments has a quadrilateral ring structure in a plan view.

[0092] refer to Figure 8 The device isolation region 110 is formed in a quadrilateral annular shape, and a quadrilateral active region can be defined within the device isolation region 110. A first drift region 105A with a constant width can be formed along the inner side of the device isolation region 110. A second drift region 105B in a quadrilateral shape can be formed at the center of the quadrilateral active region.

[0093] refer to Figure 9 and Figure 8 A gate trench GT is formed between a first drift region 105A and a second drift region 105B, for example, on the inner side of the first drift region 105A and the outer side of the second drift region 105B, and in a plan view, the gate trench GT may have a quadrilateral annular shape. A gate insulating film 120 may be conformally formed to cover the inner surface of the gate trench GT, for example, the bottom and the two sidewalls.

[0094] A gate electrode 130 is disposed on the gate insulating film 120 to be buried in the lower region of the gate trench GT, and in a plan view, the gate electrode 130 may have a quadrilateral annular shape. The upper end of the gate electrode 130 may be located at a level that is 50% or more (e.g., 70% or more) of the total depth of the gate trench GT. The gate electrode in contact with the gate insulating film 120 may not be present in the upper region of the gate trench GT.

[0095] According to some example embodiments, a high-voltage semiconductor device 100A may include a field distribution structure FD1 disposed on a gate electrode 130 in the upper region of a gate trench GT. The field distribution structure FD1 may extend above the upper surfaces of the first drift region 105A and the second drift region 105B.

[0096] Furthermore, the two side surfaces of the field distribution structure FD1 can be spaced apart from the sidewalls of the gate trench GT by a gap larger than the gap between the gate electrode 130 and the sidewalls of the gate trench GT. This field distribution structure FD1 can improve GIDL characteristics while maintaining improved breakdown voltage characteristics by reducing the gate electrode 130.

[0097] In some example embodiments, portions extending from the interlayer insulating layer 150, as well as the first residual spacer material 140D1 and the second residual spacer material 140D2, may be located in the space between the field distribution structure FD1 and the gate insulating film 120. The first residual spacer material 140D1 may be located near the first drift region 105A, and the second residual spacer material 140D2 may be located near the second drift region 105B.

[0098] refer to Figure 9 Multiple drain regions 107A are shown arranged in a first drift region 105A, and a source region 107B is shown arranged at the center of a second drift region 105B, but the inventive concept is not limited thereto. In some exemplary embodiments, multiple source regions 107B may also be arranged. Multiple first contact plugs 180A and second contact plugs 180B may be connected to multiple drain regions 107A and source regions 107B, respectively, and may be electrically connected to the first drift region 105A and the second drift region 105B.

[0099] In some example embodiments, the field distribution structure FD1 may include a different conductive material than the gate electrode 130. For example, the field distribution structure FD1 may include the same material as the first contact plug 180A and the second contact plug 180B. As described above, in a plan view, the field distribution structure FD1 may be extended into an annular shape, which is a quadrilateral shape, according to the gate electrode 130.

[0100] In some example embodiments, the ring-shaped layout is described using a quadrilateral shape as an example, but the inventive concept is not limited thereto. In some example embodiments, the ring-shaped layout may have a circular shape or other polygonal shapes, and in some other embodiments, even if it has a quadrilateral shape, it may be provided with a shape having rounded corners.

[0101] Figure 10 and Figure 11 These are plan views and side cross-sectional views of a high-voltage semiconductor device according to some example embodiments.

[0102] refer to Figure 10 and Figure 11 The high-voltage semiconductor device 100B according to some example embodiments can be understood as being similar to... Figures 1 to 3The high-voltage semiconductor device 100 shown is similar, except that the field distribution structure FD2 includes the same material as the gate electrode 130 and is integrated with the gate electrode 130, a valley is formed on the upper surface of the field distribution structure FD2, and residual spacer material 140D is disposed on both side surfaces of the field distribution structure FD2. Furthermore, unless otherwise specifically stated, it can be understood by referring to... Figures 1 to 3 The description of the same or similar components of the high-voltage semiconductor device 100 shown is used to understand the components of some example embodiments.

[0103] In some example embodiments, the field distribution structure FD2 employs the same material as the gate electrode 130 and may include an electrode structure 160 integrated with the gate electrode 130. The field distribution structure FD2 may extend along the extension direction of the gate electrode 130 (e.g., D2). In some example embodiments, the field distribution structure FD may have an upper surface 160T in which a concave valley is formed. This valley may extend in a second direction D2 in which the field distribution structure FD2 extends.

[0104] Figure 12 It shows Figure 11 A partial enlarged view of part A2 of the high-voltage semiconductor device shown.

[0105] refer to Figure 12 and Figure 11 The field distribution structure FD2 is an electrode structure 160 integrated with the gate electrode 130, but the gate electrode 130 is in contact with the gate insulating film 120. At the same time, the two side surfaces of the field distribution structure FD2 can be spaced apart from the sidewalls of the gate trench GT by a constant gap G'. In this way, the width W2 of the field distribution structure FD2 in the first direction D1 can be smaller than the width W1 of the gate electrode 130 in the first direction D1.

[0106] In some example embodiments, the field distribution structure FD2 may include residual spacer material 140D' disposed on the side surfaces facing the first drift region 105A and the second drift region 105B, respectively. The residual spacer material 140D' may also extend into the space between the field distribution structure FD2 and the gate insulating film 120.

[0107] like Figure 12 As shown, the gate trench GT can be formed such that at least a portion of the two corners TC at its bottom are covered by the first drift region 105A and the second drift region 105B. In some example embodiments, the bottom of the gate trench GT can be formed at a level substantially the same as or lower than the lower surfaces of the first drift region 105A and the second drift region 105B. The bottom of the gate electrode 130 can be higher than the lower surfaces of the first drift region 105A and the second drift region 105B by an amount represented by "D".

[0108] In some example embodiments, the field distribution structure FD2 differs in that it is integrated with the gate electrode, but the two side surfaces of the field distribution structure FD2 can be spaced apart from the sidewalls of the gate trench GT by a gap larger than the gap between the gate electrode 130 and the sidewalls of the gate trench GT. This field distribution structure FD2 can improve GIDL characteristics while maintaining improved breakdown voltage characteristics by reducing the gate electrode 130.

[0109] Figures 13A to 13D This is a cross-sectional view of the main process, illustrating a method for manufacturing a high-voltage semiconductor device according to some example embodiments. The process according to some example embodiments can be understood as simultaneously forming in a first region I and a second region II of a substrate 101. Figures 10 to 12 The process of high-voltage semiconductor device 100B and another planar MOSFET device.

[0110] Figure 13A The process can be understood as the manufacturing process according to the previous example embodiment in which Figure 7E The process performed after the previous process.

[0111] refer to Figure 13A A conductive material layer 130L for a gate electrode is formed on a first region I and a second region II of the substrate 101. Then, second photoresist patterns PR2a and PR2b can be formed in some regions of the conductive material layer 130L in the first region I and the second region II of the substrate 101.

[0112] First, a conductive material layer 130L may fill the gate trench GT in the first region I of the substrate 101. The conductive material layer 130L may include polysilicon. The polysilicon may be doped with N-type or P-type impurities. In some example embodiments, the conductive material layer 130L may also include a metal, such as tungsten. The conductive material layer 130L may be deposited by chemical vapor deposition (CVD) or physical vapor deposition (PVD). Then, second photoresist patterns PR2a and PR2b may define the portion of the conductive material layer 130L corresponding to the gate electrode.

[0113] In some example embodiments, the second photoresist pattern PR2a disposed in the first region I of the substrate 101 can be configured to not only define the gate electrode 130, but also form a field distribution structure FD2. The second photoresist pattern PR2a can be formed such that the width W2 of the field distribution structure FD2 is smaller than the width of the gate trench GT, such as... Figure 12 As stated above.

[0114] Next, refer to Figure 13BThe conductive material layer 130L in the first region I and the second region II of the substrate 101 can be etched using the second photoresist patterns PR2a and PR2b, thereby forming gate electrodes 130 and 130' and gate insulating films 120 and 120'.

[0115] In this process, gate electrodes 130 and 130' and gate insulating films 120 and 120' can be formed in the first region I and the second region II of the substrate 101, respectively. Specifically, in the first region I of the substrate 101, a field distribution structure FD2 can be formed by selectively etching the conductive material layer 130L using a second photoresist pattern PR2a, such that its two side surfaces are spaced apart from the sidewalls of the gate trench GT. On the other hand, by appropriately controlling the etching process conditions (e.g., time and / or process gas flow rate), a relatively small width ( Figure 12 The field distribution structure FD2 ("W2") is used, but the portion of the conductive material layer 130L located below the field distribution structure FD2 can remain unchanged. The remaining portion of the conductive material layer 130L can be configured as the gate electrode 130, and the width of the gate electrode 130 ( Figure 12 The “W1” in the figure is defined by the width of the gate trench GT. In the second region II of substrate 101, it can be as follows: Figure 7G As described, the gate electrode 130' is formed using a second photoresist pattern PR2b.

[0116] Additionally, during or after the main etching process, gate insulating films 120 and 120' can be formed in the first region I and the second region II of the substrate 101 by removing the exposed gate insulating film portions using an additional etching process.

[0117] Next, refer to Figure 13C and Figure 13D Gate spacers 140S can be formed on the sidewall of the gate electrode 130' in the second region II of the substrate 101.

[0118] The process of forming the gate spacer 140S can be performed by forming a spacer material layer over a first region I and a second region II of the substrate 101 and applying anisotropic etching to remove a portion of the spacer material layer from a surface parallel to the upper surface of the substrate 101.

[0119] In the process of forming the gate spacer 140S, residual spacer material 140D' can be formed on the two side surfaces of the field distribution structure FD2 protruding on the gate electrode 130 in the first region I of the substrate 101.

[0120] Additionally, source / drain regions 107A and 107B, and source / drain regions 107A' and 107B', can be formed in the first drift region 105A and the second drift region 105B, and in the first drift region 105A' and the second drift region 105B', respectively, in the first region I and the second region II of the substrate 101. The impurity concentrations of the source / drain regions 107A, 107B, 107A', and 107B' can be higher than the impurity concentrations of the first drift region 105A and the second drift region 105B, and in the first drift region 105A' and the second drift region 105B'.

[0121] Next, refer to Figure 13D An interlayer insulating layer 150 is formed on a first region I and a second region II of the substrate 101, and in the process described in the previous example embodiment. Figure 7I As described in the process, first contact holes connected to source / drain regions 107A, 107B and 107A', 107B' and second contact holes for the field distribution structure FD2 can be formed in the interlayer insulating layer 150. In some example embodiments, the second contact holes can be connected to a portion of the field distribution structure FD2 in a similar manner to the first contact holes in the plan view, and a drive voltage can be applied to the gate electrode 130 through the field distribution structure FD2.

[0122] In subsequent processes, conductive material can be filled into the first and second contact holes, and then the remaining conductive material on the interlayer insulating layer 150 can be removed by chemical mechanical polishing (CMP) until the upper surface of the interlayer insulating layer 150 is exposed. Therefore, a conductive material can be provided in the first region I of the substrate 101 as described above. Figures 10 to 12 The high-voltage semiconductor device 100B (or high-voltage MOSFET) shown can be formed in the second region II of the substrate 101, and the MOSFET 200 can be formed in a planar structure.

[0123] As described above, according to some of the example embodiments, by introducing buried gate electrodes and field distribution structures within the trench of a high-voltage semiconductor device, not only can the breakdown voltage characteristics be improved, but also the gate-induced drain leakage (GIDL) characteristics can be improved.

[0124] While exemplary embodiments have been shown and described above, it will be apparent to those skilled in the art that modifications and alterations may be made without departing from the scope of the inventive concept as defined by the appended claims.

Claims

1. A high-voltage semiconductor device, comprising: Substrate; A well region of the first conductivity type is located within the substrate; The first and second drift regions of the second conductivity type are located in the well region; Gate trench, including: At the bottom between the first drift region and the second drift region, the bottom partially defines the trap region; and A first sidewall and a second sidewall facing each other, the first sidewall and the second sidewall respectively partially defining the first drift region and the second drift region; A gate insulating film covers the bottom, the first sidewall, and the second sidewall of the gate trench; The gate electrode is buried in the lower region of the gate trench; and The field distribution structure is located in the upper region of the gate trench and on the gate electrode, and extends above the upper surfaces of the first drift region and the second drift region.

2. The high-voltage semiconductor device according to claim 1, wherein, The gate electrode is spaced apart from the first sidewall of the gate trench by a first gap. The field distribution structure is spaced apart from the first sidewall of the gate trench by a second gap, and The second gap is larger than the first gap.

3. The high-voltage semiconductor device according to claim 1, wherein, In the plan view, the gate electrode extends in a first direction between the first drift region and the second drift region, and the field distribution structure extends in a second direction, which is the extension direction of the gate electrode.

4. The high-voltage semiconductor device according to claim 3, wherein, In a planar view, the field distribution structure has a strip shape or a ring shape.

5. The high-voltage semiconductor device according to claim 1, further comprising: An interlayer insulating layer is provided on the substrate and covers the first drift region, the second drift region, and the gate electrode; as well as The first contact plug and the second contact plug penetrate the interlayer insulation layer and are respectively connected to the first drift region and the second drift region.

6. The high-voltage semiconductor device according to claim 5, wherein, The field distribution structure includes a material different from that of the gate electrode.

7. The high-voltage semiconductor device according to claim 6, wherein, The field distribution structure comprises the same material as the material of the first contact plug and the material of the second contact plug.

8. The high-voltage semiconductor device according to claim 6, wherein, The width of the field distribution structure is greater than the width of the first contact plug and the width of the second contact plug.

9. The high-voltage semiconductor device according to claim 5, wherein, The field distribution structure comprises the same material as the gate electrode.

10. The high-voltage semiconductor device according to claim 9, wherein, The upper surface of the field distribution structure is lower than the upper surface of the first contact plug and the upper surface of the second contact plug.

11. The high-voltage semiconductor device according to claim 1, wherein, The bottom level of the gate electrode is equal to or higher than the level of the lower surface of the first drift region and the level of the lower surface of the second drift region.

12. The high-voltage semiconductor device according to claim 1, wherein, The first drift region and the second drift region cover at least a portion of the two corners of the bottom of the gate trench.

13. The high-voltage semiconductor device according to claim 1, further comprising: Ditch area, The channel region in the well region is partially defined by the bottom portion of the gate trench, and The impurity concentration in the channel region is higher than that in the trap region.

14. The high-voltage semiconductor device according to claim 1, further comprising: The first source / drain region and the second source / drain region are located in the first drift region and the second drift region, respectively, and The impurity concentrations in the first source / drain region and the second source / drain region are higher than the impurity concentrations in the first drift region and the second drift region, respectively.

15. A high-voltage semiconductor device, comprising: Substrate; A well region of the first conductivity type is located within the substrate; The first and second drift regions of the second conductivity type are arranged in the well region in the first direction; A gate trench extends in a second direction between the first drift region and the second drift region, the second direction intersecting the first direction, and the gate trench includes a bottom that partially defines the well region, and a first sidewall and a second sidewall facing each other, the first sidewall and the second sidewall respectively partially defining the first drift region and the second drift region; A gate insulating film covers the bottom, the first sidewall, and the second sidewall of the gate trench; The gate electrode is buried in the lower region of the gate trench and extends in the second direction; An interlayer insulating layer is provided on the substrate and covers the first drift region, the second drift region, and the gate electrode; The first contact plug and the second contact plug penetrate the interlayer insulation layer and are respectively connected to the first drift region and the second drift region; as well as A field distribution structure penetrates the interlayer insulation layer and extends in the second direction on the gate electrode, the field distribution structure comprising the same material as the material of the first contact plug and the material of the second contact plug.

16. The high-voltage semiconductor device according to claim 15, wherein, The upper surface of the gate electrode includes a valley extending in the second direction.

17. The high-voltage semiconductor device according to claim 15, wherein, The first and second sides of the field distribution structure are spaced apart from the gate insulating film, and The interlayer insulating layer has a portion in the upper region of the gate trench that fills the space between the first and second sides of the field distribution structure and the gate insulating film.

18. The high-voltage semiconductor device according to claim 15, wherein, The upper surface of the field distribution structure is at the same level as the upper surface of the first contact plug and the upper surface of the second contact plug, and the width of the field distribution structure is greater than the width of the first contact plug and the width of the second contact plug.

19. A high-voltage semiconductor device, comprising: Substrate; A well region of the first conductivity type is located within the substrate; The first and second drift regions of the second conductivity type are arranged in the well region in the first direction; A gate trench extends in a second direction between the first drift region and the second drift region, the second direction intersecting the first direction, and the gate trench includes a bottom that partially defines the well region, and a first sidewall and a second sidewall facing each other, the first sidewall and the second sidewall respectively partially defining the first drift region and the second drift region; A gate insulating film covers the bottom, the first sidewall, and the second sidewall of the gate trench; The gate electrode is buried in the lower region of the gate trench and extends in the second direction; A field distribution structure extends on the gate electrode in the second direction, and the upper surface of the field distribution structure is higher than the upper surface of the first drift region and the upper surface of the second drift region, the field distribution structure comprising the same material as the gate electrode; An interlayer insulating layer is provided on the substrate and covers the first drift region, the second drift region, the gate electrode, and the field distribution structure. as well as The first contact plug and the second contact plug penetrate the interlayer insulation layer and are respectively connected to the first drift region and the second drift region.

20. The high-voltage semiconductor device according to claim 19, wherein, The first and second sides of the field distribution structure are spaced apart from the gate insulating film, and The upper surface of the field distribution structure includes valleys extending in the second direction.

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