High voltage semiconductor device

Abstract

A high-voltage semiconductor device includes: a substrate; a well region of a first conductivity type in the substrate; a first drift region and a second drift region, both of a second conductivity type, in the well region; and a gate trench between the first drift region and the second drift region. The gate trench has a bottom defined by the well region and two sidewalls defined by the first drift region and the second drift region, respectively. Each of the two sidewalls has a step. The high-voltage semiconductor device further includes: a gate insulating film covering the bottom and the two sidewalls of the gate trench; and a gate electrode in the gate trench.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2024-0197454, filed with the Korean Intellectual Property Office on December 26, 2024, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The example embodiments relate to high-voltage semiconductor devices. Background Technology

[0004] High-voltage semiconductor devices are used in a variety of integrated circuits, such as non-volatile memory or display driver ICs (DDI). For example, high-voltage semiconductor devices include high-voltage transistors with recessed trench channels and can be used with transistors that have different operating voltages or functions (e.g., transistors with flat channels).

[0005] For high-voltage semiconductor devices (such as high-voltage transistors), improved electrical characteristics (e.g., high breakdown voltage of the impurity regions forming the source / drain of a high-voltage transistor with a recessed channel) are advantageous. Summary of the Invention

[0006] The example embodiment relates to a high-voltage semiconductor device with improved electrical characteristics.

[0007] According to some example embodiments, a high-voltage semiconductor device includes: a substrate; a well region of a first conductivity type in the substrate; a first drift region and a second drift region, both of a second conductivity type, in the well region; and a gate trench between the first drift region and the second drift region. The gate trench has a bottom defined by the well region and two sidewalls defined by the first drift region and the second drift region, respectively. Each of the two sidewalls has a step. The high-voltage semiconductor device further includes: a gate insulating film covering the bottom and the two sidewalls of the gate trench; and a gate electrode in the gate trench.

[0008] According to some example embodiments, a high-voltage semiconductor device includes: a substrate; a well region of a first conductivity type in the substrate; a first drift region and a second drift region of a second conductivity type in the well region; and a gate trench between the first drift region and the second drift region. The gate trench has a bottom defined by the well region and two sloping sidewalls defined by the first drift region and the second drift region, respectively. The bottom of the gate trench has a corner structure formed by two steps. The high-voltage semiconductor device further includes: a gate insulating film covering the bottom of the gate trench and the two sloping sidewalls; a gate electrode in the gate trench; an interlayer insulating layer on the substrate and covering the first drift region, the second drift region, and the gate electrode; and a first contact plug and a second contact plug penetrating the interlayer insulating layer and respectively connected to the first drift region and the second drift region.

[0009] According to some example embodiments, a high-voltage semiconductor device includes: a substrate; a well region of a first conductivity type in the substrate; a first drift region and a second drift region of a second conductivity type in the well region; and a gate trench between the first drift region and the second drift region, having a bottom at least partially defined by the well region, and two sidewalls defined by the first drift region and the second drift region, respectively. Each of the two sidewalls has a step and an upper sidewall and a lower sidewall separated by the step. The high-voltage semiconductor device further includes: a gate insulating film covering the bottom and the two sidewalls of the gate trench; a gate electrode in the gate trench and on the first drift region and the second drift region adjacent to the gate trench; an interlayer insulating layer on the substrate and covering the first drift region, the second drift region, and the gate electrode; and a first contact plug and a second contact plug penetrating the interlayer insulating layer and connected to the first drift region and the second drift region, respectively.

[0010] According to some example embodiments, a method of manufacturing a high-voltage semiconductor device includes: forming a well region of a first conductivity type in a substrate; forming a first drift region and a second drift region, both of a second conductivity type, in the well region; and forming a gate trench between the first drift region and the second drift region. The gate trench has a bottom defined by the well region and two sidewalls defined by the first drift region and the second drift region, respectively. Each of the two sidewalls has a step. The method further includes: forming a gate insulating film on the bottom of the gate trench and the two sidewalls, and forming a gate electrode in the gate trench. According to some example embodiments, the step defines an upper sidewall and a lower sidewall of each of the two sidewalls of the gate trench, and the height of the upper sidewall is greater than the height of the lower sidewall. According to some example embodiments, the upper and lower sidewalls are inclined. According to some example embodiments, the gate trench has a lower corner connecting the lower sidewall and the bottom, and an upper corner located at the lower end of the upper sidewall, and the lower corner is rounded. According to some example embodiments, the first drift region and the second drift region each cover at least a portion of the lower corner of the gate trench. According to some example embodiments, the upper corner is rounded. Attached Figure Description

[0011] The above and other aspects, features, and advantages of the present invention will become more clearly understood from the following detailed description, taken in conjunction with the accompanying drawings, in which:

[0012] Figure 1 This is a plan view of a high-voltage semiconductor device according to some example embodiments.

[0013] Figure 2 It is along Figure 1 The side view of the high-voltage semiconductor device shown is a cross-sectional view taken along line I-I'.

[0014] Figure 3 It shows Figure 2 A partial enlarged view of part A1 of the high-voltage semiconductor device shown.

[0015] Figure 4A and Figure 4B as well as Figure 5A and Figure 5B Impact ionization in high-voltage semiconductor devices with different gate structures (comparative examples and exemplary embodiments) is illustrated.

[0016] Figure 6A and Figure 6B IV curves of high-voltage semiconductor devices according to comparative and exemplary embodiments are shown respectively.

[0017] Figure 7A , Figure 7B , Figure 7C , Figure 7D , Figure 7E and Figure 7F This is a cross-sectional view of some processes of a method for manufacturing a high-voltage semiconductor device according to some example embodiments.

[0018] Figure 8A , Figure 8B , Figure 8C , Figure 8D and Figure 8E This is a cross-sectional view of some processes of a method for manufacturing a high-voltage semiconductor device according to some example embodiments.

[0019] Figure 9 This is a cross-sectional view of a high-voltage semiconductor device according to some example embodiments.

[0020] Figure 10A and Figure 10B The degree of impact ionization in high-voltage semiconductor devices with different gate structures (Example 1 and Example 2) is shown.

[0021] Figure 11 The IV curves of the high-voltage semiconductor devices according to Examples 1 and 2 are shown. Detailed Implementation

[0022] In the following description, exemplary embodiments will be illustrated with reference to the accompanying drawings.

[0023] In the accompanying drawings, the thickness of layers, films, panels, areas, etc., has been enlarged for clarity.

[0024] In the accompanying drawings, for clarity, parts irrelevant to the description have been omitted, and the same or similar reference numerals are used throughout the specification to denote the same or similar components.

[0025] It will be understood that when an element such as a layer, film, region, or substrate is referred to as being “on” another element, it may be directly on the other element or there may be intermediate elements present. In contrast, when an element is referred to as being “directly” on another element, there are no intermediate elements present. It will also be understood that when an element is referred to as being “on” another element, the element may be above or below the other element, or adjacent to the other element (e.g., horizontally adjacent).

[0026] When the terms “about” or “substantially” are used in conjunction with numerical values ​​in this specification, the numerical values ​​to be associated are intended to include manufacturing or operational tolerances (e.g., ±10%) near said numerical values. Furthermore, when the terms “about” and “substantially” are used in conjunction with geometry, it is intended not to require precision of the geometry, but rather tolerance for the shape within the scope of this disclosure. Moreover, regardless of whether a numerical value or shape is modified to “about” or “substantially,” it will be understood that these values ​​and shapes should be interpreted as including manufacturing or operational tolerances (e.g., ±10%) near said numerical value or shape. When a range is specified, the range includes all values ​​within that range, such as increments of 0.1%.

[0027] Figure 1 This is a plan view illustrating a high-voltage semiconductor device according to some example embodiments, and Figure 2 It is along Figure 1 The image shows a cross-sectional view of the high-voltage semiconductor device taken along line I-I'. Figure 1 For clarity, the following can be omitted. Figure 2 Interlayer insulation layer 150.

[0028] refer to Figure 1 and Figure 2 According to some example embodiments, a high-voltage semiconductor device 100 may include: a substrate 101; a well region 102 of a first conductivity type in the substrate 101; a first drift region 105A and a second drift region 105B of a second conductivity type facing each other in the well region 102 along a first direction D1; and a buried gate electrode 130 between the first drift region 105A and the second drift region 105B.

[0029] Substrate 101 may include, for example, a semiconductor such as Si or Ge, or a compound semiconductor such as SiGe, SiC, GaAs, InAs, or InP. In some example embodiments, substrate 101 may have a silicon-on-insulator (SOI) structure. Substrate 101 may include a first conductivity type impurity, and therefore may have a first conductivity type. In some example embodiments, the first conductivity type may be, for example, P-type, and the first conductivity type impurity may be, for example, a P-type impurity, such as aluminum (Al). In some example embodiments, the first conductivity type may be, for example, N-type, and the first conductivity type impurity may be, for example, an N-type impurity, such as nitrogen (N) and / or phosphorus (P).

[0030] A device isolation region 110 can be formed in the substrate 101 to define the active region of the high-voltage semiconductor device 100. A first drift region 105A and a second drift region 105B can be respectively disposed on opposite sides of the active region defined by the device isolation region 110. Figure 1 As shown, the component isolation region 110 may extend in a second direction D2 intersecting the first direction D1. The component isolation region 110 may include silicon oxide or a silicon oxide-based insulating material filling trenches formed in the well region 102. For example, the component isolation region 110 may also be referred to as shallow trench isolation (STI).

[0031] Well region 102 may include a first conductivity type impurity and therefore may have a first conductivity type. Well region 102 may also be referred to as a "high-voltage well region". In some example embodiments, the first conductivity type may be, for example, P-type, and the first conductivity type impurity may be, for example, a P-type impurity, such as aluminum (Al). In some example embodiments, the first conductivity type may be, for example, N-type, and the first conductivity type impurity may be, for example, an N-type impurity, such as nitrogen (N) and / or phosphorus (P). In some example embodiments, well region 102 may be formed by implanting the first conductivity type impurity into substrate 101 using a mask such as a photoresist pattern.

[0032] The first drift region 105A and the second drift region 105B include impurities of a second conductivity type, and therefore can have a second conductivity type. The first drift region 105A and the second drift region 105B can be exposed from the upper surface of the substrate 101 (or, alternatively, from the upper surface of the well region 102). Figure 1As shown, the first drift region 105A and the second drift region 105B can extend in the second direction D2. In some example embodiments, the second conductivity type can be, for example, N-type, and the second conductivity type impurity can be, for example, an N-type impurity, such as nitrogen (N) and / or phosphorus (P). In some example embodiments, the second conductivity type can be, for example, P-type, and the second conductivity type impurity can be, for example, a P-type impurity, such as aluminum (Al). In some example embodiments, the first drift region 105A and the second drift region 105B can be formed by injecting the second conductivity type impurity into both sides of the well region 102 using a mask such as a photoresist pattern.

[0033] A buried gate electrode 130 may be formed in a gate trench GT between a first drift region 105A and a second drift region 105B. The gate trench GT may be formed by an etching process using photolithography. In some example embodiments, the gate trench GT may be formed after the first drift region 105A and the second drift region 105B are formed. The bottom of the gate trench GT may be provided or defined by a well region 102, and the two sidewalls of the gate trench GT may be provided or defined by the first drift region 105A and the second drift region 105B. The sidewalls of the gate trench GT may be provided or defined by the first drift region 105A and the second drift region 105B over nearly the entire area.

[0034] In some example embodiments, the two sidewalls of the gate trench GT may have steps ST (or step features). Figure 3 It shows Figure 2 A partial enlarged view of part A1 of the high-voltage semiconductor device 100 shown.

[0035] refer to Figure 3 and Figure 2 The sidewalls of the gate trench GT may have a sloping surface based on (or referencing) the bottom of the gate trench GT (or the upper surface of the substrate 101). The sloping sidewalls of the gate trench GT may be divided into an upper sidewall SW1 and a lower sidewall SW2 by a step ST. The height H1 of the upper sidewall SW1 may be greater than the height H2 of the lower sidewall SW2. For example, the height H1 of the upper sidewall SW1 may be in the range of 0.2µm (or about 0.2µm) to 0.5µm (or about 0.5µm), and the height H2 of the lower sidewall SW2 may be in the range of 0.05µm (or about 0.05µm) to 0.2µm (or about 0.2µm). The height H2 of the lower sidewall SW2 may be 30% or less of the total depth H of the gate trench GT. In some example embodiments, the height H2 of the lower sidewall SW2 may be 20% or less of the total depth H of the gate trench GT.

[0036] Due to the step ST, the bottom corner of the gate trench GT can be a two-step corner structure. In some example embodiments, by forming the bottom corner of the gate trench GT (where current and electric field are relatively concentrated) into a two-step structure, the concentrated current and electric field can be dispersed. This two-step corner structure can not only reduce the breakdown voltage in the ON state, but also reduce the injection of hot carriers.

[0037] In some example embodiments, the two-step corner structure of the gate trench GT may include: a lower corner TC2 adjacent to the bottom of the gate trench GT; and an upper corner TC1 on the lower corner TC2. The lower corner TC2 connects the lower sidewall SW2 of the gate trench GT to the bottom, and the upper corner TC1 may be located at the lower end of the upper sidewall SW1. As described above, the sidewalls of the gate trench GT have inclined surfaces, and the width W2 between the lower corners TC2 in the first direction D1 may be smaller than the width W1 between the upper corners TC1 in the first direction D1. The lower sidewall SW2 may have a generally inclined surface similar to the upper sidewall SW1.

[0038] In some example embodiments, the lower corner TC2 may have a rounded structure (or a curved structure), such as... Figure 3 As shown. If the lower corner TC2 is angled (e.g., defined as a corner or edge, rather than curvature), the drain current may be reduced because electron mobility may be decreased in the adjacent drift regions 105A and 105B. The rounded lower corner TC2 according to some example embodiments does not reduce the drain current. In some example embodiments, the upper corner TC1 may also have a similar rounded structure.

[0039] At least a portion of the upper corner TC1 may be formed to be covered by the first drift region 105A and the second drift region 105B. In some example embodiments, the upper corner TC1 may be covered by the first drift region 105A and the second drift region 105B, and at least a portion of the lower corner TC2 may be covered by the first drift region 105A and the second drift region 105B.

[0040] In some example embodiments, the bottom of the gate trench GT may be substantially at the level of the lower surfaces of the first drift region 105A and the second drift region 105B, or it may be at a level higher than the lower surfaces of the first drift region 105A and the second drift region 105B. Therefore, the bottom of the gate electrode 130 in the gate trench GT may have the same (or equal) level as or higher than the lower surfaces of the first drift region 105A and the second drift region 105B. In some example embodiments, the bottom of the gate electrode 130 may be higher than the lower surfaces of the first drift region 105A and the second drift region 105B by an amount represented by "D". For example, the depth H of the gate trench GT may be from 0.3µm to 0.6µm, and the width S of the gate trench GT may be from 0.4µm to 0.8µm.

[0041] A high-concentration channel region 104 can be formed in the well region 102 at the bottom of the gate trench GT. The high-concentration channel region 104 can be defined as the region between the lower corners TC2. In some example embodiments, the high-concentration channel region 104 can be obtained by an ion implantation process using a mask for forming the gate trench GT, without the need for an additional mask (see [link to example]). Figure 7F The high-concentration channel region 104 can be additionally implanted with impurities to control the threshold voltage. For example, the impurity concentration in the high-concentration channel region 104 can be higher than the impurity concentration in the region of the well region 102 defined by the bottom of the gate trench GT.

[0042] The gate insulating film 120 may be conformally formed to cover the inner surface of the gate trench GT, such as the bottom and two sidewalls. In some example embodiments, the gate insulating film 120 may extend to the upper end of the sidewalls of the gate trench GT. The gate insulating film 120 may include, for example, silicon oxide, silicon oxynitride, a high-k dielectric, a combination thereof, or a laminate thereof. The high-k dielectric may include HfO2, ZrO2, Al2O3, Ta2O5, hafnium silicate, zirconium silicate, or a combination thereof. When the gate insulating film 120 is silicon oxide, the silicon oxide may be formed by an oxidation process (e.g., a thermal oxidation process), but is not limited thereto, and the gate insulating film 120 may also be formed by chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD), or a combination thereof. For example, the thickness of the gate insulating film 120 may be from 100 Å to 500 Å.

[0043] The gate electrode 130 may be buried in the gate trench GT and may be disposed on the gate insulating film 120. For example, the gate electrode 130 may comprise polysilicon. The polysilicon may be doped with N-type or P-type impurities. In some example embodiments, the gate electrode 130 may comprise a metal, such as tungsten. The gate electrode 130 may be deposited by chemical vapor deposition (CVD) or physical vapor deposition (PVD).

[0044] In the gate electrode 130 according to some example embodiments, in a plan view, the gate electrode extends along a second direction D2 between a first drift region 105A and a second drift region 105B, and the upper surface of the gate electrode 130 may define a valley (e.g., a groove or recess in the gate electrode 130) extending in the second direction D2. The gate electrode 130 may have extensions 130P extending into the first drift region 105A and the second drift region 105B adjacent to the gate trench GT. For example, the width of each of the extensions 130P of the gate electrode 130 may be 0.2 μm or less. In some example embodiments, the gate electrode 130 may be formed only in the gate trench GT.

[0045] The first residual spacer material 140D1 and the second residual spacer material 140D2 can be formed around the gate electrode 130. The first residual spacer material 140D1 can be disposed on the sidewall of the extension 130P of the gate electrode 130, and the second residual spacer material 140D2 can be disposed on the sidewall along the valley of the gate electrode 130. The first residual spacer material 140D1 and the second residual spacer material 140D2 can be spacer materials left over from the process of forming the gate spacer of the MOSFET element in another region of the substrate 101 (see [link]). Figure 8D For example, the first residual spacer material 140D1 and the second residual spacer material 140D2 may include silicon nitride or silicon oxynitride.

[0046] refer to Figure 1 and Figure 2 Source / drain regions 107A and 107B can be respectively disposed on the first drift region 105A and the second drift region 105B. The impurity concentration of source / drain regions 107A and 107B can be higher than the impurity concentration of the first drift region 105A and the second drift region 105B. Multiple source / drain regions 107A and 107B have the same second conductivity type as the first drift region 105A and the second drift region 105B. Multiple source / drain regions 107A and 107B can be arranged along a second direction D2 in the first drift region 105A and the second drift region 105B. Multiple source / drain regions 107A and 107B can be formed by implanting impurities of the second conductivity type into the first drift region 105A and the second drift region 105B using a mask (e.g., a photoresist pattern). In some example embodiments, multiple source / drain regions 107A and 107B may be connected to each other at the first drift region 105A and the second drift region 105B and configured as a line.

[0047] Multiple source / drain regions 107A and 107B are formed from the surfaces of the first drift region 105A and the second drift region 105B, and may have a thickness thinner than that of the first drift region 105A and the second drift region 105B. For example... Figure 2 As shown, source / drain regions 107A and 107B can be formed to be spaced apart from the extension 130P of the gate electrode 130 by a desired or given distance X1. The arrangement of source / drain regions 107A and 107B can improve breakdown voltage characteristics. For example, the distance X1 between source / drain regions 107A and 107B and the extension 130P can be 0.2µm to 1µm.

[0048] refer to Figure 2 According to some example embodiments, the high-voltage semiconductor device 100 may further include: an interlayer insulating layer 150 covering a first drift region 105A and a second drift region 105B and a gate electrode 130 on a substrate 101; and a plurality of first contact plugs 180A and a plurality of second contact plugs 180B penetrating the interlayer insulating layer 150 and electrically connected to the first drift region 105A and the second drift region 105B, respectively. For example, the plurality of first contact plugs 180A and the plurality of second contact plugs 180B may include at least one of nickel (Ni), aluminum (Al), titanium (Ti), silver (Ag), vanadium (V), tungsten (W), cobalt (Co), molybdenum (Mo), copper (Cu), and ruthenium (Ru). In some example embodiments, the source / drain regions in contact with the plurality of first contact plugs 180A and the plurality of second contact plugs 180B may include a metal semiconductor compound layer (not shown) to reduce contact resistance. For example, the metal semiconductor compound layer may include at least one of TiSi, CoSi, MoSi, LaSi, NiSi, TaSi, or WSi.

[0049] refer to Figure 1 Multiple first contact plugs 180A and multiple second contact plugs 180B can be arranged in the second direction D2. The multiple first contact plugs 180A and multiple second contact plugs 180B are respectively connected to source / drain regions 107A and 107B, and can be electrically connected to the first drift region 105A and the second drift region 105B through the source / drain regions 107A and 107B. Similar to the first contact plugs 180A and the second contact plugs 180B, a third contact plug 180C can be connected to the gate electrode 130 at any desired location on the gate electrode 130 by penetrating the interlayer insulating layer 150.

[0050] The technical effects of some example embodiments can be observed based on the electrical characteristics caused by different gate structures of the high-voltage semiconductor devices of comparative examples and some example embodiments.

[0051] It is understood that the high-voltage semiconductor devices according to the comparative examples and exemplary embodiments have the same or similar specifications, and the shape of the gate trench and the gate structure according to the gate trench may be different.

[0052] Figure 4A and Figure 4B as well as Figure 5A and Figure 5B Impact ionization in high-voltage semiconductor devices with different gate structures (comparative examples and some example embodiments) is shown, and Figure 6A and Figure 6B IV curves of high-voltage semiconductor devices according to comparative and exemplary embodiments are shown for different operating voltage conditions (e.g., on-state).

[0053] first, Figure 4A and Figure 5A The high-voltage semiconductor device (comparative example) has a gate electrode 130A, and the gate trench GT of the gate electrode 130A has a skewed or inclined sidewall without steps. Figure 4B and Figure 5B The high-voltage semiconductor device (example embodiment) has a skewed or tilted sidewall of a gate trench GT, which has a step. Figure 4B and Figure 5B The gate trench GT in the middle has a two-step bottom corner structure including an upper corner TC1 and a lower corner TC2.

[0054] Figure 4A and Figure 4B as well as Figure 5A and Figure 5B The degree of collisional ionization of the corresponding components in the on state is shown respectively. Figure 4A and Figure 4B The degree of impact ionization in the high-voltage semiconductor devices according to the comparative example and the exemplary embodiment is shown respectively when a gate voltage Vg of 13.5V is applied. Figure 5A and Figure 5B The degree of impact ionization in the high-voltage semiconductor devices according to the comparative example and the exemplary embodiment is shown when a gate voltage Vg and a drain voltage Vd of 13.5V are applied simultaneously.

[0055] In the on-state, in the high-voltage semiconductor device according to the comparative example (see...) Figure 4A and Figure 5A Impact ionization occurs relatively strongly at the bottom corner of the gate trench GT where current density and electric field are concentrated, whereas in high-voltage semiconductor devices according to some example embodiments (see...) Figure 4B and Figure 5B The electric field and current density can be dispersed by introducing two steps at the bottom corners.

[0056] refer to Figure 6AThe diagram illustrates how the drain current Id of a high-voltage semiconductor device varies with the drain voltage Vd according to some example embodiments and comparative examples when a gate voltage Vg is applied. The results varying with the threshold voltage Vt are shown in the example embodiments and comparative examples, respectively. The results for the example embodiments and comparative examples at high threshold voltages are shown as EH and CH, respectively, and the results for the example embodiments and comparative examples at low threshold voltages are shown as E(L) and C(L), respectively.

[0057] refer to Figure 6A As indicated by the arrows, compared to the high-voltage semiconductor device according to the comparative example, the high-voltage semiconductor device according to some exemplary embodiments can improve the breakdown voltage characteristics in the conduction state. This technical effect can be achieved by the high-voltage semiconductor device according to some exemplary embodiments by introducing two stepped bottom corners to disperse the electric field and current density to the upper and lower corners.

[0058] refer to Figure 6B When the drain voltage Vd and the gate voltage Vg are applied together, the substrate current Isub of the high-voltage semiconductor device according to the example embodiment and the comparative example is shown based on the gate voltage Vg, and the results varying with the magnitude of the threshold voltage Vt are shown in the example embodiment and the comparative example, respectively. The results of the example embodiment and the comparative example at high threshold voltage are shown as EH and CH, respectively, and the results of the example embodiment and the comparative example at low threshold voltage are shown as E(L) and C(L), respectively.

[0059] refer to Figure 6B As indicated by the arrows, it can be observed that the substrate current Isub of the high-voltage semiconductor device according to the example embodiment is reduced compared to the high-voltage semiconductor device according to the comparative example. This technical effect may be due to the high-voltage semiconductor device according to the example embodiment reducing the number of carriers generated by impact ionization by introducing two step bottom corners, thereby reducing "hot carrier injection (HCI)".

[0060] Figures 7A to 7F This is a cross-sectional view of some processes for manufacturing high-voltage semiconductor devices according to some example embodiments. The processes according to some example embodiments can simultaneously form a first region I and a second region II in a (single) substrate 101. Figures 1 to 3 The high-voltage semiconductor device 100 and another planar MOSFET element.

[0061] refer to Figure 7A A first conductivity type well region 102 can be formed on a first region I and a second region II of the substrate 101, and a device isolation region 110 defining an active region can be formed in the first conductivity type well region 102.

[0062] In some example embodiments, the substrate 101 may include, for example, a semiconductor such as Si or Ge, or a compound semiconductor such as SiGe, SiC, GaAs, InAs, or InP. In some example embodiments, the substrate 101 may have a silicon-on-insulator (SOI) structure. The substrate 101 may be a first conductivity type substrate including impurities of a first conductivity type (e.g., P-type). A first conductivity type well region 102 may then be formed by implanting the first conductivity type impurities into a first region I and a second region II of the substrate 101 using a mask (e.g., a photoresist pattern). In the second region II, when forming a low-voltage MOSFET or a MOSFET of another conductivity type, an additional mask may be used to form a well region with different impurity concentrations or a well region with different conductivity type impurity concentrations in the second region II.

[0063] Device isolation regions 110 can be formed in a first region I and a second region II of substrate 101 to define active regions for forming devices (e.g., MOSFETs). The device isolation regions 110 can extend along a second direction D2 intersecting a first direction D1. Therefore, an active region extending in the second direction D2 can be provided in each of the first region I and the second region II of substrate 101. In some example embodiments, the device isolation regions 110 can be formed differently in a plan view to form semiconductor devices with different layouts.

[0064] Next, refer to Figure 7B A first drift region 105A and a second drift region 105B, as well as a first drift region 105A' and a second drift region 105B', can be formed in the first region I and the second region II of the substrate 101, respectively.

[0065] The first drift region 105A and the second drift region 105B, as well as the first drift region 105A' and the second drift region 105B', can be formed by implanting impurities of a second conductivity type into the respective active regions (e.g., well regions 102) of the first region I and the second region II of the substrate 101 using a mask (e.g., a photoresist pattern). In the first region I of the substrate 101, the first drift region 105A and the second drift region 105B can extend along the second direction D2, such as... Figure 1 As shown. Similarly, in the second region II of the substrate 101, the first drift region 105A' and the second drift region 105B' may extend along the second direction D2.

[0066] In some example embodiments, as described above, the first drift region 105A and the second drift region 105B, as well as the first drift region 105A' and the second drift region 105B', can have different layouts depending on the pattern of the active region defined by the element isolation region 110.

[0067] refer to Figure 7C A first gate trench GT' can be formed in a first region I of substrate 101 using a first photoresist pattern PR1.

[0068] The first photoresist pattern PR1 may have an opening defining a first gate trench GT' in a first region I of the substrate 101, and may be formed to completely cover a second region II of the substrate 101. The first gate trench GT' may be formed by an etching process using the first photoresist pattern PR1.

[0069] The first gate trench GT' can be formed after the formation of the first drift region 105A and the second drift region 105B. In some example embodiments, the first gate trench GT' can extend in the second direction D2. By controlling the position and width of the first gate trench GT', the first drift region 105A and the second drift region 105B can form the two sidewalls of the first gate trench GT'.

[0070] In some example embodiments, the first gate trench GT' may be formed with a depth that is a portion of the final depth of the desired gate trench (e.g., 70% to 90%). The bottom of the first gate trench GT' may be sufficiently higher than the lower surfaces of the first drift region 105A and the second drift region 105B. In some example embodiments, the sidewalls of the first gate trench GT' may have sloping surfaces.

[0071] Next, refer to Figure 7D After removing the first photoresist pattern PR1, a second photoresist pattern PR2 can be formed to form the final gate trench GT with steps.

[0072] Similar to the first photoresist pattern PR1, the second photoresist pattern PR2 may have an opening TR in the first region I of the substrate 101, and may be formed to completely cover the second region II of the substrate 101. The opening TR of the second photoresist pattern PR2 may be formed to have a width in the first direction D1 that is narrower than the width of the first gate trench GT'. Furthermore, the opening TR of the second photoresist pattern PR2 is formed such that a portion of the bottom region of the first gate trench GT' is open.

[0073] Next, refer to Figure 7E A gate trench GT can be formed in the first region I of the substrate 101 using a second photoresist pattern PR2.

[0074] This process can be performed using a wet etching process on the bottom region of the first gate trench GT' exposed by the opening TR. As shown in the enlarged view indicated by the arrow, the exposed bottom region is etched almost isotropically, which not only increases the depth of the first gate trench GT', but also allows for partial etching below the second photoresist pattern PR2. This wet etching process forms a gate trench GT with a two-step corner structure, having an upper corner TC1 and a lower corner TC2. The lower corner TC2 can be formed into a rounded structure using a wet etching process.

[0075] The well region 102, which can be configured as a channel region, may be open at the bottom of the gate trench GT obtained by this process. In some example embodiments, the bottom of the gate trench GT may be at approximately the same level as the lower surfaces of the first drift region 105A and the second drift region 105B, or at a level higher than the lower surfaces of the first drift region 105A and the second drift region 105B. For example, the lower corner TC2 of the gate trench GT may be at least partially covered by the first drift region 105A and the second drift region 105B.

[0076] In some example embodiments, the two-step corner structure is formed using a wet etching process, but the example embodiments are not limited to this, and in some example embodiments, the two-step corner structure can be obtained using a dry etching process. However, in this case, the lower corner may have a relatively sharper angle (or edge) (see...). Figure 9 ).

[0077] Next, refer to Figure 7F An ion implantation process can be performed on the bottom of the gate trench GT using a second photoresist pattern PR2.

[0078] This ion implantation process allows control over the threshold voltage of the channel region 104. For example, a first conductivity type impurity can be additionally implanted during this process. The second photoresist pattern PR2 used to form the final gate trench GT can be used as is in this ion implantation process. A channel region 104 with a controlled threshold voltage can be formed at the bottom of the gate trench GT.

[0079] Figures 8A to 8E This is a cross-sectional view of a process for manufacturing a high-voltage semiconductor device according to some example embodiments.

[0080] refer to Figure 8A After removing the second photoresist pattern PR2 ( Figure 7F After that, a gate insulating film 120L can be formed in the first region I and the second region II of the substrate 101.

[0081] In the first region I of the substrate 101, a gate insulating film 120L may be conformally formed to cover the inner surface of the gate trench GT, such as the bottom and the two sidewalls. For example, the gate insulating film 120L may include silicon oxide, silicon oxynitride, a high-k dielectric, a combination thereof, or a laminate thereof. The high-k dielectric may include HfO2, ZrO2, Al2O3, Ta2O5, hafnium silicate, zirconium silicate, or a combination thereof.

[0082] In some example embodiments, the same gate insulating film 120L is formed in both the first region I and the second region II of the substrate 101, but a different gate insulating film than the gate insulating film in the first region I may be formed in the second region II. For example, in the case of forming a low-voltage MOSFET in the second region II of the substrate 101, an additional mask may be used to form a gate insulating film of a different material and / or a different number of layers in the second region II.

[0083] Next, refer to Figure 8B A conductive material layer 130L for a gate electrode can be formed on a first region I and a second region II of the substrate 101. Then, third photoresist patterns PR3a and PR3b can be formed in some regions of the conductive material layer 130L in the first region I and the second region II of the substrate 101.

[0084] First, a conductive material layer 130L may fill the gate trench GT in the first region I of the substrate 101. The conductive material layer 130L may comprise polysilicon. The polysilicon may be doped with N-type or P-type impurities. In some example embodiments, the conductive material layer 130L may comprise a metal, such as tungsten. The conductive material layer 130L may be deposited by chemical vapor deposition (CVD) or physical vapor deposition (PVD). Then, third photoresist patterns PR3a and PR3b may define the portion of the conductive material layer 130L corresponding to the gate electrode.

[0085] A third photoresist pattern PR3a defining the gate electrode 130 can be formed on a portion of the conductive material layer 130L in the first region I of the substrate 101. A third photoresist pattern PR3b defining the gate electrode 130' can be formed on a portion of the conductive material layer 130L in the second region II of the substrate 101.

[0086] Next, refer to Figure 8C By etching the conductive material layer 130L in the first region I and the second region II of the substrate 101 using the third photoresist patterns PR3a and PR3b, gate electrodes 130 and 130' and gate insulating films 120 and 120' can be formed.

[0087] In this process, gate electrodes 130 and 130' and gate insulating films 120 and 120' can be formed in the first region I and the second region II of the substrate 101, respectively. In the first region I of the substrate 101, the gate electrode 130 can be formed by selectively etching the conductive material layer 130L using a third photoresist pattern PR3a. Similarly, in the second region II of the substrate 101, the gate electrode 130' can be formed using a third photoresist pattern PR3b.

[0088] Additionally, during the main etching process or after performing the back etching process, the exposed gate insulating film portions can be removed by means of an additional etching process, thereby forming gate insulating films 120 and 120' in the first region I and the second region II of the substrate 101, respectively.

[0089] Next, refer to Figure 8D and Figure 8E Gate spacers 140S can be formed on the sidewall of the gate electrode 130' in the second region II of the substrate 101.

[0090] The process of forming the gate spacer 140S can be performed by forming a spacer material layer over a first region I and a second region II of the substrate 101 and applying anisotropic etching to remove a portion of the spacer material layer from a surface parallel to the upper surface of the substrate 101.

[0091] In the process of forming the gate spacer 140S, a first residual spacer material 140D1 and a second residual spacer material 140D2 can be formed on the sidewall of the gate electrode 130 in the first region I of the substrate 101.

[0092] Additionally, source / drain regions 107A and 107B, and source / drain regions 107A' and 107B', can be formed in the first drift region 105A and the second drift region 105B, and in the first drift region 105A' and the second drift region 105B', respectively, in the first region I and the second region II of the substrate 101. The impurity concentrations of the source / drain regions 107A, 107B, 107A', and 107B' can be higher than the impurity concentrations of the first drift region 105A and the second drift region 105B, and in the first drift region 105A' and the second drift region 105B'.

[0093] Next, an interlayer insulating layer 150 is formed on the first region I and the second region II of the substrate 101 (see Figure 8ENext, contact holes connecting to source / drain regions 107A, 107B, 107A', and 107B' can be formed in the interlayer insulating layer 150. In a subsequent process, conductive material is filled into the contact holes, and then chemical mechanical polishing (CMP) is applied until the upper surface of the interlayer insulating layer 150 is exposed to remove any conductive material remaining on the interlayer insulating layer 150. Therefore, a first region I of the substrate 101 is formed as shown... Figures 1 to 3 The high-voltage semiconductor device 100 (or high-voltage MOSFET) shown can be formed in the second region II of the substrate 101, and the MOSFET 200 can be formed in a planar structure.

[0094] Figure 9 This is a cross-sectional side view of a high-voltage semiconductor device according to some example embodiments.

[0095] refer to Figure 9 According to some example embodiments, the high-voltage semiconductor device 100A can be used with Figures 1 to 3 The high-voltage semiconductor device 100 shown is identical or similar in some respects. In the high-voltage semiconductor device 100A, the lower corner may include an angled (or edged, angular) structure. Reference can be made to... Figures 1 to 3 The description of the high-voltage semiconductor device 100 shown is best understood. Figure 9 The high-voltage semiconductor device 100A, wherein the same reference numerals denote the same elements, and will not be described in detail.

[0096] In some example embodiments, the lower corner TC2' may have an angled (or angular, or edged) structure. The angled lower corner TC2' also reduces the drain current because the electron mobility in the adjacent drift regions 105A and 105B is reduced, and the breakdown voltage characteristics and hot carrier injection characteristics in the conduction state can be improved by dispersing the current and electric field with the help of the lower and upper corners.

[0097] exist Figure 7C In the etching process, an angled lower corner TC2' can be obtained by performing dry etching instead of wet etching. When performing dry etching, Figure 7D The opening TR of the second photoresist pattern PR2 introduced in the process can be formed to have a relatively large width.

[0098] Figure 10A and Figure 10B The degree of impact ionization in high-voltage semiconductor devices with different gate structures (Example 1 and Example 2) is shown.

[0099] The high-voltage semiconductor devices according to both Examples 1 and 2 include a gate trench with a two-step corner structure, but the high-voltage semiconductor device according to Example 1 has the same... Figure 9The high-voltage semiconductor device 100A shown has an angled lower corner structure, while the high-voltage semiconductor device according to Example 2 has a similar structure. Figure 2 The high-voltage semiconductor device 100 shown has a similar rounded lower corner structure. This difference in the lower corner can be determined according to... Figure 7E The type of etching process introduced in the process determines this.

[0100] refer to Figure 10A and Figure 11 In the two-step corner structure, the lower corner TC2 leads to a lower electron mobility in the adjacent drift region, thus reducing the drain current. On the other hand, the reference... Figure 10B and Figure 11 According to Example 2, the high-voltage semiconductor device has a rounded lower corner structure, so it can maintain a higher drain current than Example 1 without reducing electron mobility.

[0101] In this way, through a second etching process used to form the lower corner ( Figure 7E The process uses wet etching, which can form a rounded structure at the bottom corner and achieve a relatively high drain current around the bottom corner.

[0102] As described above, according to some of the example embodiments, by introducing a corner structure in a high-voltage semiconductor device in which the corner adjacent to the bottom of the gate trench consists of two steps, not only can the breakdown voltage characteristics in the on-state be improved, but the hot carrier injection effect can also be reduced, thereby improving reliability.

[0103] While several embodiments have been provided in this disclosure, it should be understood that the disclosed systems and methods may be embodied in many other specific forms without departing from the spirit or scope of this disclosure. These examples should be considered illustrative rather than restrictive and are not intended to be limited to the details given herein. For example, various elements or components may be combined or integrated into another system, or certain features may be omitted or not implemented.

Claims

1. A high-voltage semiconductor device, comprising: Substrate; A well region of the first conductivity type is located in the substrate; Both are first and second drift regions of the second conductivity type, located in the well region; A gate trench, located between a first drift region and a second drift region, having a bottom defined by the well region and two sidewalls defined by the first drift region and the second drift region, each of the two sidewalls having a step. A gate insulating film covers the bottom and the two sidewalls of the gate trench; as well as The gate electrode is located in the gate trench.

2. The high-voltage semiconductor device according to claim 1, wherein, The step defines an upper sidewall and a lower sidewall for each of the two sidewalls of the gate trench, and the height of the upper sidewall is greater than the height of the lower sidewall.

3. The high-voltage semiconductor device according to claim 2, wherein, The height of the upper sidewall is in the range of 0.2µm to 0.5µm, and The height of the lower sidewall is in the range of 0.05µm to 0.2µm.

4. The high-voltage semiconductor device according to claim 2, wherein, The depth from the step of the lower sidewall of each of the two sidewalls to the bottom of the gate trench is 30% or less of the total depth of the gate trench.

5. The high-voltage semiconductor device according to claim 2, wherein, The upper sidewall and the lower sidewall are inclined.

6. The high-voltage semiconductor device according to claim 2, wherein, The gate trench has a lower corner connecting the lower sidewall and the bottom, and an upper corner located at the lower end of the upper sidewall. The lower corner is rounded.

7. The high-voltage semiconductor device according to claim 6, wherein, The first drift region and the second drift region respectively cover at least a portion of the lower corner of the gate trench.

8. The high-voltage semiconductor device according to claim 6, wherein, The upper corner is rounded.

9. The high-voltage semiconductor device according to claim 1, wherein, The bottom of the gate electrode is at a level equal to or higher than the lower surfaces of the first drift region and the second drift region.

10. The high-voltage semiconductor device according to claim 1, wherein, The well region has a channel region at least partially defined by the bottom of the gate trench, and The impurity concentration in the channel region is higher than that in the trap region.

11. The high-voltage semiconductor device according to claim 1, wherein, In the plan view, the gate electrode extends in a first direction between the first drift region and the second drift region, and the upper surface of the gate electrode defines a valley extending in the first direction.

12. The high-voltage semiconductor device according to claim 1, wherein, The gate electrode includes extensions on the first drift region and the second drift region adjacent to the gate trench.

13. The high-voltage semiconductor device according to claim 12, wherein, The width of each of the extensions of the gate electrode is 0.2 μm or less.

14. The high-voltage semiconductor device according to claim 12, wherein, The first drift region includes a first source / drain region, and the second drift region includes a second source / drain region. The impurity concentration in the first source / drain region is higher than the impurity concentration in the first drift region. The impurity concentration in the second source / drain region is higher than the impurity concentration in the second drift region, and The first source / drain region and the second source / drain region are spaced apart from the gate electrode.

15. A high-voltage semiconductor device, comprising: Substrate; A well region of the first conductivity type is located in the substrate; The first and second drift regions of the second conductivity type are located in the well region; A gate trench, located between a first drift region and a second drift region, has a bottom defined by the well region and two inclined sidewalls defined by the first drift region and the second drift region, respectively. The bottom of the gate trench has a corner structure formed by two steps. A gate insulating film covers the bottom of the gate trench and the two inclined sidewalls; The gate electrode is located in the gate trench. An interlayer insulating layer is provided on the substrate and covers the first drift region, the second drift region, and the gate electrode; as well as The first contact plug and the second contact plug penetrate the interlayer insulation layer and are respectively connected to the first drift region and the second drift region.

16. The high-voltage semiconductor device according to claim 15, wherein, The corner structure of the two steps of the gate trench includes a lower corner adjacent to the bottom and an upper corner on the lower corner, and The first drift region and the second drift region cover at least a portion of the lower corner.

17. The high-voltage semiconductor device according to claim 16, wherein, The lower corner is rounded.

18. The high-voltage semiconductor device according to claim 15, wherein, The channel region is defined in the well region at least partially by the bottom of the gate trench, and The impurity concentration in the channel region is higher than that in the trap region.

19. A high-voltage semiconductor device, comprising: Substrate; A well region of the first conductivity type is located in the substrate; The first and second drift regions of the second conductivity type are located in the well region; A gate trench is located between the first drift region and the second drift region, and the gate trench has a bottom at least partially defined by the well region, and two sidewalls defined by the first drift region and the second drift region, respectively, each of the two sidewalls having a step and an upper sidewall and a lower sidewall separated by the step; A gate insulating film covers the bottom and the two sidewalls of the gate trench; The gate electrode is located in the gate trench and on the first drift region and the second drift region adjacent to the gate trench. An interlayer insulating layer is provided on the substrate and covers the first drift region, the second drift region, and the gate electrode; as well as The first contact plug and the second contact plug each penetrate the interlayer insulation layer and are respectively connected to the first drift region and the second drift region.

20. The high-voltage semiconductor device according to claim 19, wherein, The lower corner where the lower sidewall and the bottom connect is rounded, and the first drift region and the second drift region respectively cover at least a portion of the lower corner of the gate trench.

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