Nldmos device and method of forming
By setting specific structures and isolation structures in NLDMOS devices, the leakage current problem was solved, and stable voltage output and efficiency improvement were achieved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- SHANGHAI HUAHONG GRACE SEMICON MFG CORP
- Filing Date
- 2026-04-20
- Publication Date
- 2026-06-26
AI Technical Summary
Partially symmetrical NLDMOS suffers from leakage current issues, leading to unstable output voltage and low efficiency.
An N-type buried layer and a P-type epitaxial layer are sequentially formed on a P-type substrate. First and second P-type well regions, N-type drift regions and P-type ion implantation regions are set to form source, drain and base terminals, which are separated by a shallow trench isolation structure to prevent the N-type drift region, P-type epitaxial layer and N-type buried layer from conducting.
It reduces leakage current, provides a stable output voltage, and improves device efficiency.
Smart Images
Figure CN122294543A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of semiconductor technology, and in particular to an NLDMOS device and its fabrication method. Background Technology
[0002] LDMOS (Lateral Diffused Metal Oxide Semiconductor) is widely used in power management circuits due to its advantages such as high voltage resistance, high current driving capability, extremely low power consumption, and integration with CMOS.
[0003] N-type LDMOS (NLDMOS) forms an inversion layer channel by applying a sufficiently high positive voltage to the gate (G). It operates at high voltages, efficiently conducting large currents while completely shutting off high-voltage power switches. The breakdown voltage and on-resistance of medium- and high-voltage NLDMOS devices are important electrical parameters. Symmetrical NLDMOS devices, because both their drain and source terminals can withstand high voltages, can meet the needs of many specific circuit applications.
[0004] However, partially symmetrical NLDMOS may have leakage current, which can lead to unstable output voltage and reduced efficiency. Summary of the Invention
[0005] The purpose of this invention is to provide an NLDMOS device and its fabrication method, which can reduce leakage current, thereby enabling stable voltage output and improving efficiency.
[0006] To achieve the above objectives, the present invention provides an NLDMOS device, comprising:
[0007] A P-type substrate, with an N-type buried layer and a P-type epitaxial layer sequentially located on the P-type substrate;
[0008] The gate is located on the surface of a portion of the P-type epitaxial layer;
[0009] A first P-type well region and a second P-type well region are disposed at intervals within the P-type epitaxial layer. The second P-type well region is symmetrically disposed on both sides of the first P-type well region. The first P-type well region is located below the gate.
[0010] The N-type drift region is symmetrically disposed in the P-type epitaxial layer on both sides of the first P-type well region, and the N-type drift region is located between the first P-type well region and the second P-type well region.
[0011] The P-type ion implantation region is located below the N-type drift region;
[0012] The P-type body region is located below the first P-type well region and the second P-type well region, and the P-type body region is adjacent to the P-type ion implantation region.
[0013] The gate has a source terminal, a drain terminal, and a base terminal, wherein the source terminal and the drain terminal are located in the N-type drift region, the source terminal and the drain terminal are located on both sides of the gate, and the base terminal is located in the second P-type well region.
[0014] Optionally, in the NLDMOS device, the N-type buried layer is connected to a high voltage.
[0015] Optionally, in the NLDMOS device, the base terminal and the source and drain terminals are separated by a shallow trench isolation structure.
[0016] Optionally, the NLDMOS device further includes a gate oxide layer located between the gate and the P-type epitaxial layer.
[0017] This invention provides a method for forming an NLDMOS device, comprising:
[0018] A P-type substrate is provided, on which an N-type buried layer and a P-type epitaxial layer are sequentially formed;
[0019] An N-type drift region is formed within the P-type epitaxial layer;
[0020] The epitaxial layer contains a P-type ion implantation region and a P-type body region, which are adjacent to the P-type ion implantation region and located below the N-type drift region.
[0021] A first P-type well region and a second P-type well region are formed at intervals within the P-type epitaxial layer. The second P-type well region is symmetrically arranged on both sides of the first P-type well region. The N-type drift region is symmetrically arranged on both sides of the first P-type well region. The N-type drift region is located between the first P-type well region and the second P-type well region. The P-type body region is located below the first P-type well region and the second P-type well region.
[0022] A gate is formed on the surface of a portion of the epitaxial layer, and the first P-type well region is located below the gate.
[0023] A source and a drain are formed in the N-type drift region, and a base is formed in the second P-type well region, with the source and drain located on opposite sides of the gate.
[0024] Optionally, in the method for forming the NLDMOS device, after sequentially forming an N-type buried layer and a P-type epitaxial layer on the P-type substrate, the method further includes:
[0025] A plurality of shallow trench isolation structures are formed in the epitaxial layer at intervals, and the base end and the source end, as well as the base end and the drain end, are separated by the shallow trench isolation structures.
[0026] Optionally, in the method for forming the NLDMOS device, before forming the gate on the surface of a portion of the epitaxial layer, the method further includes:
[0027] A gate oxide layer is formed on the surface of a portion of the epitaxial layer, the gate oxide layer being located between the gate and the P-type epitaxial layer.
[0028] Optionally, in the method for forming the NLDMOS device, N-type impurity ions are implanted to form an N-type drift region within the P-type epitaxial layer.
[0029] Optionally, in the method for forming the NLDMOS device, P-type impurity ions are implanted to form a P-type ion implantation region and a P-type body region within the epitaxial layer.
[0030] Optionally, in the method for forming the NLDMOS device, P-type impurity ions are implanted to form a first P-type well region and a second P-type well region spaced apart within the P-type epitaxial layer.
[0031] The NLDMOS device and its formation method provided by this invention include: a P-type substrate, an N-type buried layer and a P-type epitaxial layer sequentially located on the P-type substrate; a gate located on the surface of a portion of the P-type epitaxial layer; a first P-type well region and a second P-type well region, spaced apart within the P-type epitaxial layer, the second P-type well region being symmetrically disposed on both sides of the first P-type well region, the first P-type well region being located below the gate; an N-type drift region, symmetrically disposed within the P-type epitaxial layer on both sides of the first P-type well region, the N-type drift region being located between the first P-type well region and the second P-type well region; a P-type ion implantation region located below the N-type drift region; a P-type body region located below the first P-type well region and the second P-type well region, the P-type body region being adjacent to the P-type ion implantation region; a source terminal, a drain terminal, and a base terminal, the source terminal and the drain terminal being located within the N-type drift region, the source terminal and the drain terminal being located on both sides of the gate, and the base terminal being located within the second P-type well region. In this invention, a P-type body region is formed below both the first and second P-type well regions, and a P-type ion implantation region is formed below the N-type drift region. This invention prevents the conduction of the N-type drift region, the P-type epitaxial layer, and the N-type buried layer, thereby reducing leakage current, outputting a stable voltage, and improving efficiency. Attached Figure Description
[0032] Figure 1 This is a flowchart of a method for forming an NLDMOS device according to an embodiment of the present invention;
[0033] Figures 2 to 5 This is a schematic diagram of the formation process of the NLDMOS device according to an embodiment of the present invention;
[0034] In the figure: 101-P-type substrate, 102-N-type buried layer, 103-P-type epitaxial layer, 104-shallow trench isolation structure, 105-N-type drift region, 106-P-type body region, 107-first P-type well region, 108-second P-type well region, 109-P-type ion implantation region, 110-gate oxide layer, 111-gate, 114-base terminal, 112-source terminal, 113-drain terminal. Detailed Implementation
[0035] The specific embodiments of the present invention will now be described in more detail with reference to the accompanying drawings. The advantages and features of the present invention will become clearer from the following description. It should be noted that the drawings are all in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of the present invention.
[0036] In the following text, the terms “first,” “second,” etc., are used to distinguish between similar elements and are not necessarily used to describe a specific order or chronological sequence. It should be understood that these terms, as used herein, may be replaced where appropriate. Similarly, if the methods described herein comprise a series of steps, and the order of these steps presented herein is not necessarily the only possible order in which they can be performed, and some described steps may be omitted and / or other steps not described herein may be added to the method.
[0037] Furthermore, it should be understood that when a layer (or film), region, pattern, or structure is referred to as being "on" a substrate, layer (or film), region, and / or pattern, it can be located directly on another layer or substrate, and / or intercalation layers may also be present. Additionally, it should be understood that when a layer is referred to as being "under" another layer, it can be located directly under that layer, and / or one or more intercalation layers may also be present. Furthermore, references to "on" and "under" the layers may be made based on the accompanying drawings.
[0038] Please refer to Figure 5This invention provides an NLDMOS device, comprising: a P-type substrate 101, with an N-type buried layer 102 and a P-type epitaxial layer 103 sequentially located on the P-type substrate 101; a gate oxide layer 110 and a gate 111 sequentially located on a portion of the surface of the P-type epitaxial layer 103; a first P-type well region 107 and a second P-type well region 108, spaced apart within the P-type epitaxial layer 103, the second P-type well region 108 being symmetrically disposed on both sides of the first P-type well region 107, the first P-type well region 107 being located below the gate 111; and an N-type drift region 105, symmetrically disposed on both sides of the first P-type well region 107. Within the epitaxial layer 103, an N-type drift region 105 is located between a first P-type well region 107 and a second P-type well region 108; a P-type ion implantation region 109 is located below the N-type drift region 105; a P-type body region 106 is located below the first P-type well region 107 and the second P-type well region 108, and the P-type body region 106 is adjacent to the P-type ion implantation region 109; a source terminal 112, a drain terminal 113, and a base terminal 114 are located. The source terminal 112 and the drain terminal 113 are located within the N-type drift region 105, and are located on opposite sides of the gate 111, respectively. The base terminal 114 is located within the second P-type well region. The base terminal 114 is separated from the source terminal 112 and the drain terminal 113 by a shallow trench isolation structure 104.
[0039] Please refer to Figure 1 This invention provides a method for forming an NLDMOS device, comprising:
[0040] S11: Provide a P-type substrate, and sequentially form an N-type buried layer and a P-type epitaxial layer on the P-type substrate;
[0041] S12: An N-type drift region is formed within the P-type epitaxial layer;
[0042] S13: A P-type ion implantation region and a P-type body region are respectively in the epitaxial layer. The P-type body region is adjacent to the P-type ion implantation region. The P-type ion implantation region is located below the N-type drift region.
[0043] S14: A first P-type well region and a second P-type well region are formed in the P-type epitaxial layer. The second P-type well region is symmetrically arranged on both sides of the first P-type well region. The N-type drift region is symmetrically arranged on both sides of the first P-type well region. The N-type drift region is located between the first P-type well region and the second P-type well region. The P-type body region is located below the first P-type well region and the second P-type well region.
[0044] S15: A gate is formed on the surface of a portion of the epitaxial layer, with the first P-type well region located below the gate;
[0045] S16: The source and drain terminals are formed in the N-type drift region, and the base terminal is formed in the second P-type well region. The source and drain terminals are located on both sides of the gate, respectively.
[0046] Please refer to Figure 2 First, a substrate is provided. In this embodiment of the invention, the substrate is a P-type substrate 101 (P-sub). N-type impurities are implanted into the P-type substrate 101 near its surface to form an N-type buried layer 102 (NBL) on the remaining P-type substrate 101. A P-type epitaxial layer 103 is epitaxially grown on the N-type buried layer 102. The P-type epitaxial layer 103 is photolithographically formed using an active region and filled with oxide to form a plurality of shallow trench isolation structures 104 spaced apart within the P-type epitaxial layer 103.
[0047] Next, please refer to Figure 3 The well implantation region is opened by photolithography, and N-type impurity ions are implanted to form an N-type drift region 105. Then, P-type impurity ions are implanted to form a P-type body region 106, a first P-type well region 107, a second P-type well region 108, and a P-type ion implantation region 109. The first P-type well region 107 and the second P-type well region 108 are spaced apart within the P-type epitaxial layer 103. The N-type drift region 105 is located within the P-type epitaxial layer 103 on both sides of the first P-type well region 107. The P-type ion implantation region 109 is located below the N-type drift region 105. The P-type ion implantation region 109 and the N-type drift region 105 use the same layout, and the cross-sectional area of the P-type ion implantation region 109 and the N-type drift region 105 are the same. The P-type body region 106 is located below the first P-type well region 107 and the second P-type well region 108, that is, the P-type body region 106 is located below both the first P-type well region 107 and the second P-type well region 108. The P-type body region 106 is adjacent to the P-type ion implantation region 109.
[0048] Please refer to Figure 4 An oxide, which may be silicon dioxide, is grown on the surface of the P-type epitaxial layer 103, and a portion of the oxide is etched back to form a gate oxide layer 110. Next, polysilicon is deposited on the gate oxide layer 110 and etched back to form a gate 111. The gate 111 is located above the gate oxide layer 110, i.e., the gate oxide layer 110 is located between the gate 111 and the P-type epitaxial layer 103. A first P-type well region 107 is located below the gate 111, and a second P-type well region 108 is located on the side of the first P-type well region 107 away from the gate 111.
[0049] Please refer to Figure 5Selective source and drain ion implantation is performed to form N-type heavily doped regions and P-type heavily doped regions. The N-type heavily doped regions serve as source and drain terminals. In this embodiment, one N-type heavily doped region serves as source terminal 112, and the other as drain terminal 113. The P-type heavily doped region serves as base terminal 114. Source terminal 112 and drain terminal 113 are located in the P-type epitaxial layer 103 on both sides of gate 111, and base terminal 114 is located on the side of source terminal 112 and drain terminal 113 away from gate 111. Base terminal 114 is located in the second P-type well region 108.
[0050] In this embodiment of the invention, the N-type buried layer 102 is connected to a high voltage, which completely depletes the drain terminal 113 and the P-type substrate 101, thereby achieving a high breakdown voltage and meeting the requirements of medium and high voltage applications.
[0051] Below the N-type drift region 105 is the P-type ion implantation region 109, which achieves the effect of high breakdown voltage and low on-resistance, while suppressing the conduction of the N-type drift region 102, the P-type epitaxial layer 103 and the N-type buried layer 102.
[0052] A P-type body region 106 is added to the area outside the N-type drift region 105 to prevent the N-type drift region, P-type epitaxial layer and N-type buried layer from conducting on the side of the N-type drift region 105.
[0053] The first P-type well region 107 of the channel region below the gate 111 is led out through the second P-type well regions 108 on both sides via the P-type body region 106 and the bottom N-type drift region 105 of the N-type drift region 105;
[0054] The structure is symmetrical, and both the source end 112 and the drain end 113 can withstand high voltage.
[0055] In summary, the NLDMOS device and its formation method provided in this embodiment of the invention include: a P-type substrate, an N-type buried layer and a P-type epitaxial layer sequentially located on the P-type substrate; a gate located on the surface of a portion of the P-type epitaxial layer; a first P-type well region and a second P-type well region, spaced apart within the P-type epitaxial layer, the second P-type well region being symmetrically disposed on both sides of the first P-type well region, the first P-type well region being located below the gate; an N-type drift region, symmetrically disposed within the P-type epitaxial layer on both sides of the first P-type well region, the N-type drift region being located between the first P-type well region and the second P-type well region; a P-type ion implantation region located below the N-type drift region; a P-type body region located below the first P-type well region and the second P-type well region, the P-type body region being adjacent to the P-type ion implantation region; a source terminal, a drain terminal, and a base terminal, the source terminal and the drain terminal being located within the N-type drift region, the source terminal and the drain terminal being located on both sides of the gate, and the base terminal being located within the second P-type well region. In this embodiment of the invention, a P-type body region is formed below both the first and second P-type well regions, and a P-type ion implantation region is formed below the N-type drift region. This embodiment of the invention prevents the conduction of the N-type drift region, the P-type epitaxial layer, and the N-type buried layer, thereby reducing leakage current, outputting a stable voltage, and improving efficiency.
[0056] The above are merely preferred embodiments of the present invention and do not constitute any limitation on the present invention. Any equivalent substitutions or modifications made by those skilled in the art to the technical solutions and content disclosed in the present invention without departing from the scope of the present invention shall be deemed to have remained within the protection scope of the present invention.
Claims
1. An NLDMOS device, characterized by, include: A P-type substrate, with an N-type buried layer and a P-type epitaxial layer sequentially located on the P-type substrate; The gate is located on the surface of a portion of the P-type epitaxial layer; A first P-type well region and a second P-type well region are disposed at intervals within the P-type epitaxial layer. The second P-type well region is symmetrically disposed on both sides of the first P-type well region. The first P-type well region is located below the gate. The N-type drift region is symmetrically disposed in the P-type epitaxial layer on both sides of the first P-type well region, and the N-type drift region is located between the first P-type well region and the second P-type well region. The P-type ion implantation region is located below the N-type drift region; The P-type body region is located below the first P-type well region and the second P-type well region, and the P-type body region is adjacent to the P-type ion implantation region. The gate has a source terminal, a drain terminal, and a base terminal, wherein the source terminal and the drain terminal are located in the N-type drift region, the source terminal and the drain terminal are located on both sides of the gate, and the base terminal is located in the second P-type well region.
2. The NLDMOS device of claim 1, wherein, The N-type buried layer is connected to a high voltage.
3. The NLDMOS device of claim 1, wherein, The base terminal, the source terminal, and the drain terminal are separated by a shallow trench isolation structure.
4. The NLDMOS device of claim 1, wherein, It also includes a gate oxide layer located between the gate and the P-type epitaxial layer.
5. A method for forming an NLDMOS device as described in any one of claims 1 to 4, characterized in that, include: A P-type substrate is provided, on which an N-type buried layer and a P-type epitaxial layer are sequentially formed; An N-type drift region is formed within the P-type epitaxial layer; The epitaxial layer contains a P-type ion implantation region and a P-type body region, which are adjacent to the P-type ion implantation region and located below the N-type drift region. A first P-type well region and a second P-type well region are formed at intervals within the P-type epitaxial layer. The second P-type well region is symmetrically arranged on both sides of the first P-type well region. The N-type drift region is symmetrically arranged on both sides of the first P-type well region. The N-type drift region is located between the first P-type well region and the second P-type well region. The P-type body region is located below the first P-type well region and the second P-type well region. A gate is formed on the surface of a portion of the epitaxial layer, and the first P-type well region is located below the gate. A source and a drain are formed in the N-type drift region, and a base is formed in the second P-type well region, with the source and drain located on opposite sides of the gate.
6. The method for forming an NLDMOS device as described in claim 5, characterized in that, After sequentially forming an N-type buried layer and a P-type epitaxial layer on the P-type substrate, the method further includes: A plurality of shallow trench isolation structures are formed in the epitaxial layer at intervals, and the base end and the source end, as well as the base end and the drain end, are separated by the shallow trench isolation structures.
7. The method for forming an NLDMOS device as described in claim 5, characterized in that, Before forming a gate on the surface of a portion of the epitaxial layer, the method further includes: A gate oxide layer is formed on the surface of a portion of the epitaxial layer, the gate oxide layer being located between the gate and the P-type epitaxial layer.
8. The method for forming an NLDMOS device as described in claim 5, characterized in that, N-type impurity ions are implanted to form an N-type drift region within the P-type epitaxial layer.
9. The method for forming an NLDMOS device as described in claim 5, characterized in that, P-type impurity ions are implanted separately to form P-type ion implantation regions and P-type body regions within the epitaxial layer.
10. The method for forming an NLDMOS device as described in claim 5, characterized in that, P-type impurity ions are implanted to form a first P-type well region and a second P-type well region spaced apart within the P-type epitaxial layer.