Vertical double diffused metal-oxide-semiconductor field effect transistor and method of fabrication

Abstract

This application discloses a vertically double-diffused metal-oxide-semiconductor field-effect transistor and its fabrication method, relating to the field of semiconductor technology. The vertically double-diffused metal-oxide-semiconductor field-effect transistor includes a substrate, a gate layer, an isolation layer, a source layer, and a drain layer. The gate layer includes a connected cell gate and a gate bus. By providing at least one PN junction structure in at least one of the cell gate and the gate bus, a discharge path is provided for the gate-drain capacitor when the device is turned off, increasing the charge discharge speed of the gate-drain capacitor and thus shortening the overlap time between the drain voltage and drain current. This is beneficial for improving the device turn-off speed and reducing device turn-off losses.

Description

Technical Field

[0001] This application belongs to the field of semiconductor technology, and in particular relates to a vertically double-diffused metal-oxide-semiconductor field-effect transistor and its fabrication method. Background Technology

[0002] In the field of power semiconductors, vertically conductive metal-oxide-semiconductor field-effect transistors (MOSFETs) fabricated using a vertical double-diffused process are called vertical double-diffused metal-oxide-semiconductor field-effect transistors (VDMOS). VDMOS is widely used in power electronics due to its advantages such as fast switching speed, high input impedance, good frequency characteristics, and good thermal stability.

[0003] In related technologies, the presence of capacitance between the gate, source, and drain leads to a prolonged overlap time between the drain voltage and drain current, which in turn results in a prolonged turn-off time and increased turn-off losses. Summary of the Invention

[0004] This application provides a vertical double-diffused metal-oxide-semiconductor field-effect transistor and its fabrication method. By providing at least one PN junction structure in at least one of the gate and gate bus in the cell region, a discharge circuit is provided for the gate-drain capacitor when the device is turned off, which improves the charge discharge speed of the gate-drain capacitor and is beneficial to improving the device turn-off speed and reducing the device turn-off loss.

[0005] In a first aspect, embodiments of this application provide a vertically double-diffused metal-oxide-semiconductor field-effect transistor, comprising: Substrate; A gate layer located on one side of the substrate; the gate layer includes a cell gate and a gate bus, the cell gate is connected to the gate bus, and at least one of the cell gate and the gate bus includes at least one PN junction structure; The source layer is located on the side of the gate layer away from the substrate; An isolation layer is located between the gate layer and the source layer; The drain layer is located on the side of the substrate away from the gate layer.

[0006] According to any of the foregoing embodiments of the first aspect of this application, the PN junction structure located on the gate bus includes a plurality of parallel first PN junction structures, and the plurality of parallel first PN junction structures include a first P-type structure and a first N-type structure arranged alternately along the length direction of the gate bus. And / or, the PN junction structure located at the gate of the cell region includes multiple parallel second PN junction structures, and the multiple parallel second PN junction structures include alternating second P-type structures and second N-type structures along the length direction of the gate of the cell region.

[0007] According to any of the foregoing embodiments of the first aspect of this application, the size difference between the first P-type structure and the first N-type structure is less than or equal to a first threshold. The size difference between the second P-type structure and the second N-type structure is less than or equal to the second threshold.

[0008] According to any of the foregoing embodiments of the first aspect of this application, the first PN junction structure is located in a portion of the gate bus, and the non-PN junction structure region is located on at least one side of the first PN junction structure in a first direction, the first direction being perpendicular to the length direction of the gate bus. And / or, the second PN junction structure is located in a portion of the cell gate, and the non-PN junction structure region is located on at least one side of the second PN junction structure in the second direction, which is perpendicular to the length direction of the cell gate.

[0009] According to any of the foregoing embodiments of the first aspect of this application, the proportion of the PN junction structure in the gate bus and / or the gate of the cell region is greater than or equal to a first proportion, and the proportion of the PN junction structure in the gate bus and / or the gate of the cell region is less than or equal to a second proportion, wherein the first proportion is less than the second proportion.

[0010] According to any of the foregoing embodiments of the first aspect of this application, the non-PN junction structure regions located on both sides of the first PN junction structure are of equal size; And / or, the dimensions of the non-PN junction structure regions located on both sides of the second PN junction structure are equal.

[0011] According to any of the foregoing embodiments of the first aspect of this application, the non-PN junction structure region includes an N-type structure region.

[0012] According to any of the foregoing embodiments of the first aspect of this application, the vertically double-diffused metal-oxide-semiconductor field-effect transistor further includes: The epitaxial layer is located on the side of the gate layer closest to the substrate; The ring-shaped doped region is located around the periphery of the epitaxial layer, and the doping type of the ring-shaped doped region is different from that of the epitaxial layer.

[0013] Secondly, embodiments of this application provide a method for fabricating a vertically double-diffused metal-oxide-semiconductor field-effect transistor, the method comprising: A gate layer is formed on one side of the substrate; the gate layer includes a connected cell gate and a gate bus, at least one of the cell gate and the gate bus including at least one PN junction structure; An isolation layer is formed on the side of the gate layer away from the substrate; A source layer is formed on the side of the isolation layer away from the gate layer; A drain layer is formed on the side of the substrate away from the gate layer.

[0014] According to any of the foregoing embodiments of the second aspect of this application, the vertically double-diffused metal-oxide-semiconductor field-effect transistor further includes an epitaxial layer and a ring-shaped doped region; before forming a gate layer on one side of the substrate, the method further includes: An epitaxial layer is formed on one side of the substrate; A ring-shaped doped region is formed around the periphery of the epitaxial layer; the conductivity type of the ring-shaped doped region is different from that of the epitaxial layer.

[0015] The vertically double-diffused metal-oxide-semiconductor field-effect transistor and its fabrication method provided in this application embodiment include a substrate, a gate layer, an isolation layer, a source layer, and a drain layer. The gate layer includes a connected cell gate and a gate bus. By providing at least one PN junction structure in at least one of the cell gate and the gate bus, the gate-drain capacitance C is [value missing] when the device is turned off. GD Provides a discharge circuit, increasing the gate-drain capacitance C GD The charge discharge speed is increased, thereby shortening the overlap time between drain voltage and drain current, which is beneficial to improving device turn-off speed and reducing device turn-off loss. Attached Figure Description

[0016] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments of this application will be briefly introduced below. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0017] Figure 1 This is a schematic diagram of the gate charge versus gate-source voltage curve in related technologies; Figure 2 This is a schematic diagram of a typical capacitance variation curve with drain-source voltage in related technologies; Figure 3 This is a schematic diagram of the structure of a vertically double-diffused metal-oxide-semiconductor field-effect transistor provided in an embodiment of this application; Figure 4 This is a schematic diagram of another vertical double-diffused metal-oxide-semiconductor field-effect transistor provided in the embodiments of this application; Figure 5 This is a schematic diagram of another vertically double-diffused metal-oxide-semiconductor field-effect transistor provided in the embodiments of this application; Figure 6 for Figure 3 The vertical double-diffused metal-oxide-semiconductor field-effect transistor shown is located at position A-A'. Figure 4The vertically double-diffused metal-oxide-semiconductor field-effect transistor shown is located at C-C' and... Figure 5 The diagram shows the cross-sectional structure of a vertically double-diffused metal-oxide-semiconductor field-effect transistor along the E-E' line. Figure 7 for Figure 3 The vertical double-diffused metal-oxide-semiconductor field-effect transistor shown is located at position B-B' and Figure 4 The cross-sectional view of the vertically double-diffused metal-oxide-semiconductor field-effect transistor at position D-D' is shown. Figure 8 This is an equivalent circuit diagram of the vertical double-diffused metal-oxide-semiconductor field-effect transistor provided in the embodiments of this application; Figure 9 This is a schematic flowchart of the fabrication method of the vertical double-diffused metal-oxide-semiconductor field-effect transistor provided in the embodiments of this application. Detailed Implementation

[0018] The features and exemplary embodiments of various aspects of this application will be described in detail below. To make the objectives, technical solutions, and advantages of this application clearer, the application will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are only intended to explain this application and not to limit it. For those skilled in the art, this application can be implemented without some of these specific details. The following description of the embodiments is merely to provide a better understanding of this application by illustrating examples.

[0019] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising..." does not exclude the presence of additional identical elements in the process, method, article, or apparatus that includes said element.

[0020] In related technologies, the gate charge of VDMOS varies with the gate voltage V G The change curve is as follows Figure 1 As shown, during the device switching process, due to the parasitic gate-drain capacitance C GD and gate-source capacitance C GSThe Miller plateau voltage is generated by the competition between charging and discharging. The plateau voltage directly affects the overlap time of high voltage and high current during switching, which prolongs the turn-on and turn-off times and increases switching losses. In severe cases, it can also aggravate electromagnetic interference.

[0021] Figure 2 A schematic diagram of a typical capacitance versus drain-source voltage curve is shown. Figure 2 As shown, the capacitance decreases with increasing drain-source voltage, but the relationship is non-linear. Specifically, when the drain-source voltage V... DS In the low-voltage range, the capacitance is relatively large, and the capacitance increases with the drain-source voltage V. DS The drain-source voltage V decreases rapidly as the drain-source voltage increases. DS In the medium to high voltage range, the capacitance is relatively small, and the capacitance increases with the drain-source voltage V. DS It decreases slowly as it increases. During the turn-on process, the drain-source voltage V at the Miller plateau... DS In the medium to high voltage range, the capacitance is relatively small; during the turn-off process, at the Miller plateau, the drain-source voltage V DS In the low-voltage range, the capacitance is relatively large. Therefore, the turn-on time is usually shorter than the turn-off time.

[0022] Based on this, the present invention aims to reduce device turn-off losses.

[0023] This application provides a vertically double-diffused metal-oxide-semiconductor field-effect transistor (MOSFET) and its fabrication method. The MOSFET includes: a substrate; a gate layer located on one side of the substrate; the gate layer comprising a cell gate and a gate bus, the cell gate and the gate bus being connected, and at least one of the cell gate and the gate bus including at least one PN junction structure; a source layer located on the side of the gate layer away from the substrate; an isolation layer located between the gate layer and the source layer; and a drain layer located on the side of the substrate away from the gate layer. With this configuration, by providing at least one PN junction structure in at least one of the cell gate and the gate bus, the gate-drain capacitance C is [value missing] when the device is turned off. GD Provides a discharge circuit, increasing the gate-drain capacitance C GD The charge discharge speed is increased, thereby shortening the overlap time between drain voltage and drain current, which is beneficial to improving device turn-off speed and reducing device turn-off loss.

[0024] The vertically double-diffused metal-oxide-semiconductor field-effect transistor provided in the embodiments of this application will be described below.

[0025] Figure 3 This is a schematic diagram of the structure of a vertically double-diffused metal-oxide-semiconductor field-effect transistor provided in an embodiment of this application. Figure 4 This is a schematic diagram of another vertically double-diffused metal-oxide-semiconductor field-effect transistor provided in an embodiment of this application. Figure 5This is a schematic diagram of the structure of a vertically double-diffused metal-oxide-semiconductor field-effect transistor provided in an embodiment of this application. Figure 3 At position A-A' in the middle Figure 4 At the C-C' position and Figure 5 The cross-sectional structures at positions E-E' are the same, both as Figure 6 As shown, Figure 3 The position of B-B' in the middle and Figure 4 The cross-sectional structures at positions D-D' are the same, both as Figure 7 As shown.

[0026] Reference Figures 3-7 The vertically double-diffused metal-oxide-semiconductor field-effect transistor may include: a substrate 1, a gate layer 2, a source layer 3, an isolation layer 4, and a drain layer 5.

[0027] The substrate 1 serves as the basis for the growth of other film structures and may include all types of substrates known to those skilled in the art, such as silicon-based substrates or silicon carbide substrates, without limitation herein.

[0028] The gate layer 2 is located on one side of the substrate 1. This application embodiment limits the type of the gate layer 2; all types of gates known to those skilled in the art can be used, such as polysilicon gates.

[0029] The source layer 3 is located on the side of the gate layer 2 away from the substrate 1. As an example, the source layer 3 includes a source metal layer, which is the source of a vertically double-diffused metal-oxide-semiconductor field-effect transistor.

[0030] An isolation layer 4 is located between the gate layer 2 and the source layer 3. The isolation layer 4 is an insulating layer used to isolate the gate layer 2 and the source layer 3. The isolation layer 4 may include a silicon dioxide layer, and may also include a high dielectric constant material layer known to those skilled in the art, such as a zirconium oxide layer or a silicon nitride layer.

[0031] The drain layer 5 is located on the side of the substrate 1 away from the gate layer 2. As an example, the drain layer 5 includes a drain metal layer, which is the drain of a vertical double-diffused metal-oxide-semiconductor field-effect transistor.

[0032] The gate layer 2 is divided according to its function. The gate layer 2 may include a cell gate 210 and a gate bus 220, with the cell gate 210 and the gate bus 220 connected. The cell gate 210 and the gate bus 220 are a continuous structure formed by the same deposition and etching process.

[0033] As an example, gate layer 2 may include a bonding region gate, a cell region gate 210, and a gate bus 220, with the gate bus 220 connecting the bonding region gate and the cell region gate 210. The bonding region gate is used to receive the gate drive signal, and the gate bus 220 is used to transmit the gate drive signal to the cell region gate 210. The cell region gate 210 is located in the cell array and is the final execution terminal of the gate drive signal, directly controlling the channel to be turned on or off. The cell region gate 210 is the gate of the device.

[0034] At least one of the cell gate 210 and the gate bus 220 includes at least one PN junction structure 230.

[0035] For example, such as Figure 3 As shown, in this vertically double-diffused metal-oxide-semiconductor field-effect transistor, both the cell gate 210 and the gate bus 220 include at least one PN junction structure 230.

[0036] For example, such as Figure 4 As shown, in this vertically double-diffused metal-oxide-semiconductor field-effect transistor, the cell gate 210 includes at least one PN junction structure 230.

[0037] For example, such as Figure 5 As shown, in this vertically double-diffused metal-oxide-semiconductor field-effect transistor, the gate bus 220 includes at least one PN junction structure 230.

[0038] During the turn-off process of a vertically double-diffused metal-oxide-semiconductor field-effect transistor, the external driving circuit uses the gate resistor R G Extracting gate charge to make the gate-source voltage V GS It begins to decrease. When the gate-source voltage V GS Drop to platform voltage V GS(pl) (Its value is higher than the threshold voltage V) GS(th) Drain-source voltage V DS The voltage rises, through the gate-drain capacitance C GD A displacement current is generated and injected into the gate, reducing the gate-source voltage V. GS "Locked" at platform voltage V GS(pl) This forms the Miller plateau. The drain-source voltage V is to be determined. DS After the voltage rises to the bus voltage and stabilizes, the gate-drain capacitance C GD The displacement current disappears, and the gate-source voltage V GS It can continue to decrease from the plateau voltage, passing the threshold voltage V. GS(th) The channel is turned off until the device is completely turned off. During this process, the gate-drain capacitance C GD The size, discharge path, gate charge QG, drive resistance, drive voltage, and external circuit parasites determine the device's turn-off time.

[0039] like Figure 8 As shown, the vertical double-diffused metal-oxide-semiconductor field-effect transistor provided in this application, by providing at least one PN junction structure 230 in at least one of the cell region gate 210 and gate bus 220, is equivalent to adding a junction with the gate resistor R. G The parallel reverse diodes form an additional gate-drain capacitance C when the device is turned off. GD The discharge circuit increases the gate-drain capacitance C. GD The charge discharge speed is increased, thereby shortening the overlap time between drain voltage and drain current, which is beneficial to improving device turn-off speed and reducing device turn-off loss.

[0040] It should be noted that, Figure 3 , Figure 4 and Figure 5 The black arrow in the image indicates the current flow path when the vertically double-diffused metal-oxide-semiconductor field-effect transistor is turned off, which is equivalent to... Figure 8 The current flows from the gate GCELL in the cell region to the gate GPAD in the bonding region, indicated by a solid arrow. The direction of the drive current flowing from the gate GPAD in the bonding region during turn-on (indicated by a short arrow) is opposite to the direction of the current flowing during turn-off.

[0041] This application provides a vertically double-diffused metal-oxide-semiconductor field-effect transistor, including a substrate 1; a gate layer 2 located on one side of the substrate 1; the gate layer 2 includes a cell gate 210 and a gate bus 220, the cell gate 210 and the gate bus 220 being connected, and at least one of the cell gate 210 and the gate bus 220 including at least one PN junction structure 230; a source layer 3 located on the side of the gate layer 2 away from the substrate 1; an isolation layer 4 located between the gate layer 2 and the source layer 3; and a drain layer 5 located on the side of the substrate 1 away from the gate layer 2. With this configuration, by providing at least one PN junction structure 230 in at least one of the cell gate 210 and the gate bus 220, the gate-drain capacitance C is [value missing] when the device is turned off. GD Provides a discharge circuit, increasing the gate-drain capacitance C GD The charge discharge speed is increased, thereby shortening the overlap time between drain voltage and drain current, which is beneficial to improving device turn-off speed and reducing device turn-off loss.

[0042] In some embodiments, such as Figure 6 or Figure 7 As shown, the vertical double-diffused metal-oxide-semiconductor field-effect transistor may further include: an epitaxial layer 6, a well region 7, a source region 8, a gate dielectric layer 9, and a passivation layer 10.

[0043] In this configuration, epitaxial layer 6 is located on the side of gate layer 2 closest to substrate 1. Epitaxial layer 6 includes a silicon epitaxial layer. Gate dielectric layer 9 is located between epitaxial layer 6 and gate layer 2. Gate dielectric layer 9 is an insulating layer, such as a silicon dioxide layer. Well region 7 is located on the surface of epitaxial layer 6 closest to gate layer 2 and within epitaxial layer 6, and source region 8 is located within well region 7. Source layer 3 is connected to source region 8 and well region 7. Passivation layer 10 is located on the side of source layer 3 furthest from isolation layer 4.

[0044] It should be noted that, Figure 6 or Figure 7 The vertically double-diffused metal-oxide-semiconductor field-effect transistor (DDS-PFET) is shown as an N-type transistor only, and does not constitute a limitation on the DDS-PFET provided in the embodiments of this application. In other embodiments, the DDS-PFET may also be a P-type transistor, which is not limited here.

[0045] In some embodiments, the vertically double-diffused metal-oxide-semiconductor field-effect transistor further includes a ring-shaped doped region located around the periphery of the epitaxial layer, wherein the doping type of the ring-shaped doped region is different from that of the epitaxial layer.

[0046] In this configuration, if the epitaxial layer is an N-type epitaxial layer, the annular doped region is a P-type annular doped region; conversely, if the epitaxial layer is a P-type epitaxial layer, the annular doped region is an N-type doped region. The annular doped region surrounds the outer side of the epitaxial layer in the unit cell region, forming a PN junction. This PN junction can distribute the edge-concentrated electric field to the transition region between the annular doped region and the epitaxial layer through hole-electron charge compensation, thereby reducing the local electric field intensity. The annular doped region can also be used in conjunction with field plates and other terminating structures to further weaken the edge electric field, resulting in a more uniform electric field distribution.

[0047] In some embodiments, such as Figure 5 As shown, the PN junction structure 230 located on the gate bus 220 includes a plurality of parallel first PN junction structures 231, and the plurality of parallel first PN junction structures 231 include a first P-type structure 2311 and a first N-type structure 2312 arranged alternately along the length direction of the gate bus 220.

[0048] The extension direction of the gate bus 220 is the length direction of the gate bus 220. As an example, such as... Figure 5 As shown, the gate bus 220 extends along the second direction X, that is, the length direction of the gate bus 220 is parallel to the second direction X.

[0049] In this embodiment, the gate bus 220 is used to transmit the driving signal connected to the bonding region gate to the cell region gate 210. The driving signal is transmitted in the gate bus 220 along the length direction of the gate bus 220. By setting the first P-type structure 2311 and the first N-type structure 2312 to be arranged alternately along the length direction of the gate bus 220, the arrangement direction of the PN junction structure is consistent with the transmission direction of the driving signal.

[0050] In some embodiments, such as Figure 4 As shown, the PN junction structure 230 located in the cell gate 210 includes a plurality of parallel second PN junction structures 232, and the plurality of parallel second PN junction structures 232 include a second P-type structure 2321 and a second N-type structure 2322 alternately arranged along the length direction of the cell gate 210.

[0051] In this context, the extending direction of the cell gate 210 is the same as the length direction of the cell gate 210. As an example, such as... Figure 4 As shown, the cell gate 210 extends along the first direction Y, that is, the length direction of the cell gate 210 is parallel to the first direction Y.

[0052] In this embodiment, the driving signal is transmitted in the cell gate 210 along the length direction of the cell gate 210. By setting the second P-type structure 2321 and the second N-type structure 2322 to be alternately arranged along the length direction of the cell gate 210, the arrangement direction of the PN junction structure is consistent with the driving signal transmission direction.

[0053] In some embodiments, such as Figure 3 As shown, the PN junction structure 230 located on the gate bus 220 includes a plurality of parallel first PN junction structures 231, the plurality of parallel first PN junction structures 231 including a first P-type structure 2311 and a first N-type structure 2312 alternately arranged along the length direction of the gate bus 220; the PN junction structure 230 located on the cell gate 210 includes a plurality of parallel second PN junction structures 232, the plurality of parallel second PN junction structures 232 including a second P-type structure 2321 and a second N-type structure 2322 alternately arranged along the length direction of the cell gate 210.

[0054] In this embodiment, the gate bus 220 is used to transmit the driving signal connected to the bonding region gate to the cell region gate. The driving signal is transmitted along the length direction of the gate bus 220 and along the length direction of the cell region gate 210. By setting the first P-type structure 2311 and the first N-type structure 2312 to be alternately arranged along the length direction of the gate bus 220, and setting the second P-type structure 2321 and the second N-type structure 2322 to be alternately arranged along the length direction of the cell region gate 210, the arrangement direction of the PN junction structure is consistent with the driving signal transmission direction.

[0055] In some embodiments, such as Figure 3 or Figure 5 As shown, the size difference between the first P-type structure 2311 and the first N-type structure 2312 is less than or equal to the first threshold.

[0056] The first threshold is the maximum acceptable size difference between the first P-type structure 2311 and the first N-type structure 2312. As an example, the first threshold is equal to 0, that is, the size of the first P-type structure 2311 and the size of the first N-type structure 2312 are equal.

[0057] In this embodiment, the dimensions of the first P-type structure 2311 and the first N-type structure 2312 are as close as possible, and the difference between their dimensions is less than or equal to the first threshold value. This avoids gate layer resistance imbalance caused by size inhomogeneity and helps to improve the stability and reliability of device performance.

[0058] In some embodiments, such as Figure 3 or Figure 4 As shown, the size difference between the second P-type structure 2321 and the second N-type structure 2322 is less than or equal to the second threshold.

[0059] The second threshold is the maximum acceptable size difference between the second P-type structure 2321 and the second N-type structure 2322. As an example, the second threshold is equal to 0, meaning that the size of the second P-type structure 2321 and the size of the second N-type structure 2322 are equal.

[0060] In this embodiment, the dimensions of the second P-type structure 2321 and the second N-type structure 2322 are as close as possible, and the difference between their dimensions is less than or equal to the second threshold. This avoids gate layer resistance imbalance caused by size inhomogeneity and helps to improve the stability and reliability of device performance.

[0061] In some embodiments, such as Figure 3 or Figure 5 As shown, the first PN junction structure 231 is located in a portion of the gate bus 220, and the non-PN junction structure region 240 is located on at least one side of the first PN junction structure 230 in the first direction Y. The first direction Y is perpendicular to the length direction of the gate bus 220.

[0062] Non-PN junction structure regions 240 may be provided on one or both sides of the first PN junction structure 231. For example, such as... Figure 3 or Figure 5 As shown, the first PN junction structure 231 and the non-PN junction structure region 240 are arranged along the first direction Y and extend along the second direction X.

[0063] In some embodiments, such as Figure 3 or Figure 4 As shown, the second PN junction structure 232 is located in a portion of the cell gate 210, and the non-PN junction structure region 240 is located on at least one side of the second PN junction structure 232 in the second direction X, which is perpendicular to the length direction of the cell gate 210.

[0064] Non-PN junction structure regions 240 may be provided on one or both sides of the second PN junction structure 232. For example, such as... Figure 3 or Figure 4 As shown, the second PN junction structure 232 and the non-PN junction structure region 240 are arranged along the second direction X and extend along the first direction Y.

[0065] like Figure 8 As shown, the directions of the turn-on current and the turn-off current are opposite, requiring consideration of both switching and turn-off performance. If the first PN junction structure 231 occupies the entire area of ​​the gate bus 220, the unidirectional conduction characteristic of the diode will lead to an excessively large gate drive voltage, making it difficult to turn on.

[0066] In this embodiment, the first PN junction structure 231 occupies only a portion of the gate bus 220, and / or the second PN junction structure 232 occupies only a portion of the cell gate 210, with the remaining area being the non-PN junction structure region 240. With this configuration, during turn-off, the signal can pass through a smaller number of reverse-biased PN junction structures 230, then through a corresponding number of forward-biased PN junction structures 230, and then continue to be transmitted along the non-PN junction structure region 240 to the gate bonding region GPAD. Similarly, during turn-on, the gate drive signal can be transmitted along the non-PN junction structure region 240, requiring only a smaller number of PN junction structures, thus balancing turn-on and turn-off characteristics.

[0067] In some embodiments, such as Figure 3 or Figure 5 As shown, the non-PN junction structure regions 240 located on both sides of the first PN junction structure 231 have equal dimensions.

[0068] In some embodiments, such as Figure 3 or Figure 4 As shown, the non-PN junction structure regions 240 located on both sides of the second PN junction structure 232 have equal dimensions.

[0069] In this embodiment, along the first direction Y, the first PN junction structure 231 is located in the middle region of the gate bus 220, and the non-PN junction structure region 240 is symmetrically disposed on both sides of the first PN junction structure 231. Along the second direction X, the second PN junction structure 232 is located in the middle region of the cell gate 210, and the non-PN junction structure region 240 is symmetrically disposed on both sides of the second PN junction structure 232, which is beneficial to improving the stability and reliability of the device.

[0070] In some embodiments, such as Figure 3 , Figure 6 or Figure 7 As shown, the non-PN junction structure region 240 includes an N-type structure region.

[0071] Since electrons are the primary charge carriers in N-type semiconductors, their mobility is approximately 2 to 3 times that of holes at the same doping concentration. In this embodiment, the non-PN junction region 240 is configured as an N-type region, which helps to reduce the bulk resistivity of the gate layer.

[0072] In some embodiments, the proportion of the PN junction structure in the gate bus and / or the gate of the cell region is greater than or equal to a first proportion, and the proportion of the PN junction structure in the gate bus and / or the gate of the cell region is less than or equal to a second proportion, wherein the first proportion is less than the second proportion.

[0073] In this embodiment, the proportion of the PN junction structure in the gate bus, i.e., the proportion of the first PN junction structure in the gate bus, can be represented by a volume ratio or a projected area ratio. The proportion of the PN junction structure in the cell gate, i.e., the proportion of the second PN junction structure in the cell gate, can be represented by a volume ratio or a projected area ratio.

[0074] The proportion of the PN junction structure in the gate bus and / or cell gate directly affects the discharge performance and drive performance of the device, and can be determined based on the target turn-off loss of the device.

[0075] As an example, the first ratio ranges from 20% to 30%, and the second ratio ranges from 40% to 60%.

[0076] In this embodiment, the proportion of the PN junction structure in the gate bus and / or cell gate is controlled within a suitable range, while taking into account both the discharge performance and driving performance of the device.

[0077] Based on the vertically double-diffused metal-oxide-semiconductor field-effect transistor provided in the above embodiments, this application also provides a method for fabricating a vertically double-diffused metal-oxide-semiconductor field-effect transistor, which is used to fabricate any of the vertically double-diffused metal-oxide-semiconductor field-effect transistors provided in the above embodiments.

[0078] For example, such as Figure 9 As shown, the fabrication method of this vertical double-diffused metal-oxide-semiconductor field-effect transistor may include the following steps: S110~S140.

[0079] S110. A gate layer is formed on one side of the substrate. The gate layer includes a connected cell gate and a gate bus. At least one of the cell gate and the gate bus includes at least one PN junction structure.

[0080] In this step, any process known to those skilled in the art can be used to fabricate the gate layer, and there is no limitation herein. For example, first, an undoped polysilicon layer is deposited layer by layer, and a mask process is used to form a P-type structure and an N-type structure in a designated area of ​​the polysilicon layer (the area corresponding to at least one of the cell gate and the total gate line). Then, a patterned gate layer 2 is formed using a photolithography-etching process, thereby realizing the formation of a PN junction structure in at least one of the cell gate and the total gate line.

[0081] S120. An isolation layer is formed on the side of the gate layer away from the substrate.

[0082] S130. A source layer is formed on the side of the isolation layer away from the gate layer.

[0083] S140. A drain layer is formed on the side of the substrate away from the gate layer.

[0084] The isolation layer 4, source layer 3 and drain layer 5 are prepared using all processes known to those skilled in the art, which will not be described in detail here.

[0085] In some embodiments, the vertically double-diffused metal-oxide-semiconductor field-effect transistor further includes an epitaxial layer and a ring-shaped doped region.

[0086] Accordingly, before forming the gate layer on the substrate side, the method may further include the following steps: An epitaxial layer is formed on one side of the substrate; A ring-shaped doped region is formed around the periphery of the epitaxial layer.

[0087] In this embodiment, combined with Figure 4 or Figure 5 An epitaxial layer 6 is formed on one side of substrate 1, and then a ring-shaped doped region is formed around the periphery of the epitaxial layer. The conductivity type of the ring-shaped doped region is different from that of the epitaxial layer. If the epitaxial layer is an N-type epitaxial layer, the ring-shaped doped region is a P-type ring-shaped doped region; if the epitaxial layer is a P-type epitaxial layer, the ring-shaped doped region is an N-type doped region. The ring-shaped doped region and the epitaxial layer 6 form a PN junction, which can disperse the edge-concentrated electric field to the transition region between the ring-shaped doped region and the epitaxial layer, thereby reducing the local electric field intensity. The ring-shaped doped region can also be used in conjunction with field plates and other termination structures to further weaken the edge electric field and make the electric field distribution more uniform.

[0088] For example, the fabrication method of this vertically double-diffused metal-oxide-semiconductor field-effect transistor may include the following steps: Step a: An epitaxial layer of a first conductivity type is formed on one side of the substrate.

[0089] Step b: Form an oxide pad layer on the side of the epitaxial layer away from the substrate.

[0090] Step c: Prepare a voltage dividing ring in the circumferential region of the epitaxial layer to form a ring-shaped doped region of the second conductivity type.

[0091] Step d: The oxygen pad layer on the epitaxial layer is removed using a wet etching process.

[0092] Step e: A gate dielectric layer is formed on the side of the epitaxial layer away from the substrate using a thermal growth process.

[0093] Step f involves forming an undoped polysilicon gate layer on the side of the gate dielectric layer away from the epitaxial layer using a deposition process, and then forming a well region of the second conductivity type and a source region of the first conductivity type in the epitaxial layer using an ion implantation-high temperature diffusion process, and forming at least one PN junction structure at least at one location in the cell gate and the total gate line.

[0094] Step g involves using dry etching to etch the polysilicon gate layer, forming a patterned gate layer, which in turn forms the cell gate, gate bus, and bonding gate.

[0095] In this step, the well region, source region, and the P-type and N-type structure regions of the gate layer can be fabricated in separate steps. Alternatively, the gate layer can be selectively implanted using a mask while fabricating the well and source regions. Depending on the concentration requirements of the desired PN junction structure, if necessary, the gate layer can be implanted again after this step using a combination of the first and / or second conductivity types.

[0096] In step h, an isolation layer is formed on the side of the gate layer away from the epitaxial layer, and the isolation layer is selectively wet etched to form a contact hole that penetrates the isolation layer.

[0097] Step i: A source metal layer is formed on the side of the isolation layer away from the gate layer, and the source metal layer is selectively etched to form the source.

[0098] Step j: A passivation layer is formed on the side of the source metal layer away from the isolation layer, and the passivation layer is selectively etched.

[0099] Step k: A drain metal layer is formed on the side of the substrate away from the epitaxial layer to form a drain.

[0100] The aspects of this disclosure have been described above with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of this disclosure. It should be understood that each block in the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing apparatus to produce a machine such that these instructions, executable via the processor of the computer or other programmable data processing apparatus, enable the implementation of the functions / actions specified in one or more blocks of the flowchart illustrations and / or block diagrams. Such a processor can be, but is not limited to, a general-purpose processor, a special-purpose processor, a special application processor, or a field-programmable logic circuit. It is also understood that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, can also be implemented by special-purpose hardware performing the specified functions or actions, or can be implemented by a combination of special-purpose hardware and computer instructions.

[0101] The above description is merely a specific implementation of this application. Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working processes of the systems, modules, and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here. It should be understood that the protection scope of this application is not limited thereto. Any person skilled in the art can easily conceive of various equivalent modifications or substitutions within the technical scope disclosed in this application, and these modifications or substitutions should all be covered within the protection scope of this application.

Claims

1. A vertically double-diffused metal-oxide-semiconductor field-effect transistor, characterized in that, include: Substrate; Gate layer located on one side of the substrate; The gate layer includes a cell gate and a gate bus, the cell gate is connected to the gate bus, and at least one of the cell gate and the gate bus includes at least one PN junction structure. The source layer is located on the side of the gate layer away from the substrate; An isolation layer is located between the gate layer and the source layer; The drain layer is located on the side of the substrate away from the gate layer.

2. The vertically double-diffused metal-oxide-semiconductor field-effect transistor according to claim 1, characterized in that, The PN junction structure located on the gate bus includes multiple parallel first PN junction structures, wherein the multiple parallel first PN junction structures include first P-type structures and first N-type structures arranged alternately along the length direction of the gate bus; And / or, The PN junction structure located at the gate of the cell region includes a plurality of parallel second PN junction structures, wherein the plurality of parallel second PN junction structures include alternating arrangement of second P-type structures and second N-type structures along the length direction of the gate of the cell region.

3. The vertically double-diffused metal-oxide-semiconductor field-effect transistor according to claim 2, characterized in that, The size difference between the first P-type structure and the first N-type structure is less than or equal to a first threshold. The size difference between the second P-type structure and the second N-type structure is less than or equal to the second threshold.

4. The vertically double-diffused metal-oxide-semiconductor field-effect transistor according to claim 2, characterized in that, The first PN junction structure is located in a portion of the gate bus, and the non-PN junction structure region is located on at least one side of the first PN junction structure in a first direction, the first direction being perpendicular to the length direction of the gate bus; And / or, The second PN junction structure is located in a portion of the cell gate region, and the non-PN junction structure region is located on at least one side of the second PN junction structure in the second direction, which is perpendicular to the length direction of the cell gate region.

5. The vertically double-diffused metal-oxide-semiconductor field-effect transistor according to claim 4, characterized in that, The proportion of the PN junction structure in the gate bus and / or the cell gate is greater than or equal to a first proportion, and the proportion of the PN junction structure in the gate bus and / or the cell gate is less than or equal to a second proportion, wherein the first proportion is less than the second proportion.

6. The vertically double-diffused metal-oxide-semiconductor field-effect transistor according to claim 4, characterized in that, The non-PN junction structure regions located on both sides of the first PN junction structure are of equal size; And / or, The non-PN junction structure regions located on both sides of the second PN junction structure are of equal size.

7. The vertically double-diffused metal-oxide-semiconductor field-effect transistor according to claim 4, characterized in that, The non-PN junction structure region includes the N-type structure region.

8. The vertically double-diffused metal-oxide-semiconductor field-effect transistor according to any one of claims 1-7, characterized in that, Also includes: An epitaxial layer is located on the side of the gate layer closest to the substrate; A ring-shaped doped region is located around the periphery of the epitaxial layer, and the doping type of the ring-shaped doped region is different from the doping type of the epitaxial layer.

9. A method for fabricating a vertically double-diffused metal-oxide-semiconductor field-effect transistor, characterized in that, The method includes: A gate layer is formed on one side of the substrate; the gate layer includes a connected cell gate and a gate bus, and at least one of the cell gate and the gate bus includes at least one PN junction structure; An isolation layer is formed on the side of the gate layer away from the substrate; A source layer is formed on the side of the isolation layer away from the gate layer; A drain layer is formed on the side of the substrate away from the gate layer.

10. The method according to claim 9, characterized in that, The vertically double-diffused metal-oxide-semiconductor field-effect transistor further includes an epitaxial layer and a ring-shaped doped region. Before forming a gate layer on one side of the substrate, the method further includes: The epitaxial layer is formed on one side of the substrate; A ring-shaped doped region is formed around the periphery of the epitaxial layer; the conductivity type of the ring-shaped doped region is different from that of the epitaxial layer.

Images