Semiconductor device

Abstract

The object of the present invention is to provide a semiconductor device capable of improving moisture resistance or acid resistance. The semiconductor device according to this disclosure includes: a semiconductor substrate; wiring disposed on the semiconductor substrate; and a protective film covering at least a portion of the wiring. The wiring has: a first metal layer; and a second metal layer disposed on the first metal layer and comprising a metal with higher moisture resistance or acid resistance than the first metal layer. In the wiring, the contact portion between the first metal layer and the second metal layer is not exposed relative to a component disposed on the protective film.

Description

Technical Field

[0001] This disclosure relates to semiconductor devices. Background Technology

[0002] Patent Document 1 discloses a semiconductor device capable of improving insulation reliability. This semiconductor device includes a semiconductor substrate comprising a drift layer of a first conductivity type and a terminal well region formed on the surface of the drift layer, having a second conductivity type different from the first conductivity type. A surface electrode, primarily composed of aluminum, is formed on the surface of the semiconductor substrate, and its outer peripheral end face is electrically connected to the terminal well region by being located above and in contact with it. An insulating protective film covers the surface electrode end and the terminal well region of the surface electrode and extends to the outer peripheral side of the semiconductor substrate. An electrode protective film made of titanium is disposed between the surface electrode and the insulating protective film. Both the electrode protective film and the insulating protective film have openings that correspond to the electrode formation region of the surface electrode, exposing the surface electrode.

[0003] Patent Document 1: International Publication No. 2021 / 064944

[0004] Power devices, also known as electrical semiconductor devices, are switching elements used to control the power supply to motor loads and other applications. As electrical semiconductor devices, insulated-gate semiconductor devices such as MOSFETs (Metal Oxide Semiconductor Field-Effect Transistors) and IGBTs (Insulated-Gate Bipolar Transistors) are widely used. With the development of high current, high voltage, and low loss characteristics, power devices are used in various fields. Power devices are also frequently used in harsh environments such as high altitudes, high temperatures, and high humidity, thus requiring high reliability under temperature cycling and humidity conditions.

[0005] In the structure of Patent Document 1, a highly corrosion-resistant protective film such as Ti is used to cover the end of the surface electrode in the Schottky barrier diode where the electric field is strengthened. This prevents corrosion of the surface electrode, which is formed from easily corroded wiring material, namely aluminum. However, in the structure of Patent Document 1, since multiple metal materials are in contact with each other, corrosion of the electrode due to localized galvanic effects may occur in the presence of moisture. Summary of the Invention

[0006] This disclosure was made to solve the above-mentioned problems, and its purpose is to provide a semiconductor device that can improve moisture resistance or acid resistance.

[0007] The semiconductor device disclosed in the first disclosure includes: a semiconductor substrate; wiring disposed on the semiconductor substrate; and a protective film covering at least a portion of the wiring, wherein the wiring has: a first metal layer; and a second metal layer disposed on the first metal layer and comprising a metal with higher moisture resistance or acid resistance than the first metal layer, wherein the contact portion between the first metal layer and the second metal layer is not exposed relative to a component disposed on the protective film.

[0008] The semiconductor device disclosed in the second disclosure includes: a semiconductor substrate having an active region, a wiring region outside the active region, and a terminal region outside the wiring region; wiring disposed on the wiring region; and a protective film covering at least a portion of the wiring, wherein the wiring has: a first metal layer; and a second metal layer disposed on the first metal layer and comprising a metal having higher moisture resistance or acid resistance than the first metal layer, and the protective film being disposed from the upper surface of the second metal layer to the side surfaces of both sides of the first metal layer.

[0009] The semiconductor device disclosed in the third disclosure includes: a semiconductor substrate; a pad electrode disposed on the semiconductor substrate; and a protective film disposed on the pad electrode. The pad electrode has: a first metal layer; and a second metal layer disposed on the first metal layer and comprising a metal with higher moisture resistance or acid resistance than the first metal layer. A pad opening is formed on the pad electrode in which the first metal layer protrudes from the second metal layer. The contact portion between the first metal layer and the second metal layer facing the pad opening is covered by the protective film.

[0010] In the semiconductor device disclosed in the first disclosure, the contact portion between the first metal layer and the second metal layer is not exposed relative to the component disposed on the protective film. Therefore, it is possible to improve moisture resistance or acid resistance.

[0011] In the semiconductor device disclosed in the second disclosure, a protective film is disposed from the upper surface of the second metal layer to the sides of both sides of the first metal layer. Therefore, it is possible to improve moisture resistance or acid resistance.

[0012] In the semiconductor device disclosed in the third disclosure, the contact portion between the first metal layer and the second metal layer facing the pad opening is covered by a protective film. Therefore, moisture resistance or acid resistance can be improved. Attached Figure Description

[0013] Figure 1 This is a top view of the semiconductor device according to Embodiment 1.

[0014] Figure 2 This is an enlarged view of the active region involved in Implementation Method 1.

[0015] Figure 3 It is by... Figure 2 The sectional view obtained by cutting with the line A-B.

[0016] Figure 4 This is an enlarged view of the end region of the active region involved in Embodiment 1.

[0017] Figure 5 It is by... Figure 4 The sectional view obtained by cutting with a C-D straight line.

[0018] Figure 6 This is a cross-sectional view illustrating the manufacturing method of the semiconductor device according to Embodiment 1.

[0019] Figure 7 This is a cross-sectional view illustrating the manufacturing method of the semiconductor device according to Embodiment 1.

[0020] Figure 8 This is a cross-sectional view illustrating the manufacturing method of the semiconductor device according to Embodiment 1.

[0021] Figure 9 This is a cross-sectional view illustrating the manufacturing method of the semiconductor device according to Embodiment 1.

[0022] Figure 10 This is a cross-sectional view illustrating the manufacturing method of the semiconductor device according to Embodiment 1.

[0023] Figure 11 This is a cross-sectional view illustrating the manufacturing method of the semiconductor device according to Embodiment 1.

[0024] Figure 12 This is a cross-sectional view illustrating the manufacturing method of the semiconductor device according to Embodiment 1.

[0025] Figure 13 This is a cross-sectional view illustrating the manufacturing method of the semiconductor device according to Embodiment 1.

[0026] Figure 14 This is a cross-sectional view illustrating the manufacturing method of the semiconductor device according to Embodiment 1.

[0027] Figure 15 This is a cross-sectional view illustrating the manufacturing method of the semiconductor device according to Embodiment 1.

[0028] Figure 16 This is a cross-sectional view illustrating the manufacturing method of the semiconductor device according to Embodiment 1.

[0029] Figure 17 This is a cross-sectional view illustrating the manufacturing method of the semiconductor device according to Embodiment 1.

[0030] Figure 18 This is a cross-sectional view illustrating the manufacturing method of the semiconductor device according to Embodiment 1.

[0031] Figure 19 This is a cross-sectional view illustrating the manufacturing method of the semiconductor device according to Embodiment 1.

[0032] Figure 20 This is a cross-sectional view illustrating the manufacturing method of the semiconductor device according to Embodiment 1.

[0033] Figure 21 This is a cross-sectional view illustrating the manufacturing method of the semiconductor device according to Embodiment 1.

[0034] Figure 22 This is an enlarged view of the end region of the active region involved in Embodiment 2.

[0035] Figure 23 It is by... Figure 22 The sectional view obtained by cutting with a C-D straight line.

[0036] Figure 24 This is an enlarged view of the end region of the active region involved in Embodiment 3.

[0037] Figure 25 It is by... Figure 24 The sectional view obtained by cutting with a C-D straight line.

[0038] Figure 26 This is an enlarged view of the end region of the active region involved in Embodiment 4.

[0039] Figure 27 It is by... Figure 26 The sectional view obtained by cutting with a C-D straight line.

[0040] Figure 28 This is a top view of the semiconductor device according to Embodiment 5.

[0041] Figure 29 This is an enlarged view of the end region of the active region involved in Embodiment 5.

[0042] Figure 30 It is by... Figure 29 The sectional view obtained by cutting with the E-F line.

[0043] Explanation of reference numerals in the attached figures

[0044] 1...Semiconductor substrate; 2...Buffer layer; 3...Drift layer; 4...Well layer; 5...Source layer; 6...Contact layer; 7...JFET doped layer; 8...Gate insulating film; 9...Gate electrode layer; 10...Interlayer insulating film; 11...Ni silicide layer; 12...Barrier metal layer; 13...Metal layer; 14...Ni silicide layer; 15...Al electrode; 16...FLR layer; 17...Channel cutoff layer; 18...Field insulating film; 19...Protective film; 20...Protective film; 21...Gate electrode; 22...Resistor 23...Metal layer; 24...Metal layer; 25...Metal layer; 26...Ti film; 27...Resist; 28...Nitrogen film; 29, 30, 31...Contact holes; 32...Metal layer; 41...Pad electrode; 41a...Pad opening; 42...Gate wiring; 48...Source pad wiring; 100...Semiconductor device; 101...Active region; 102...Gate wiring region; 103...Gate pad; 104...Termination region; 105...Cut line region; 108...Source pad wiring region. Detailed Implementation

[0045] The semiconductor devices involved in each embodiment will be described with reference to the accompanying drawings. The same or corresponding components are labeled with the same reference numerals, and repeated descriptions are sometimes omitted.

[0046] Implementation Method 1

[0047] Figure 1 This is a top view of the semiconductor device 100 according to Embodiment 1. The semiconductor substrate of the semiconductor device 100 has an active region 101, a gate wiring region 102 outside the active region 101, and a terminal region 104 outside the gate wiring. A main electrode of the semiconductor device 100 is formed on the upper surface of the active region 101. The main electrode is, for example, a source electrode. The main electrode corresponds to the pad electrode 41 described later.

[0048] A gate wiring 42 electrically connected to a gate electrode serving as a control electrode is provided in a gate wiring region 102 surrounding the active region 101. The gate wiring 42 is connected to a gate pad 103. A termination region 104 for withstand voltage maintenance is formed to surround the active region 101, the gate wiring region 102, and the gate pad 103. A dicing line region 105 corresponding to the dicing line during chip cutting is provided in a manner that surrounds the termination region 104.

[0049] Figure 2 This is an enlarged view of the active region 101 involved in Embodiment 1. Figure 2 It is Figure 1The image shows a magnified view of region 106. Figure 3 It is by... Figure 2 A sectional view obtained by cutting along line A-B. For example... Figure 3 As shown, the semiconductor device 100 includes an n+ type semiconductor substrate 1. An n+ type buffer layer 2 is formed on the semiconductor substrate 1. An n- type drift layer 3 is formed on the upper surface of the buffer layer 2. A p- type well layer 4 is selectively formed on the upper surface of the drift layer 3. An n+ type source layer 5 and a p+ type contact layer 6 are formed on the upper surface of the well layer 4. An n-type JFET doped layer 7 is formed between the well layers 4.

[0050] A gate insulating film 8 is disposed on the upper surface of the semiconductor substrate 1, above the well layer 4, the source layer 5, and the JFET doped layer 7. A gate electrode layer 9 is disposed on the gate insulating film 8. The gate electrode layer 9 is formed, for example, of polysilicon. An interlayer insulating film 10 is formed on the gate electrode layer 9. A Ni silicide layer 11 is formed on the upper surface of the semiconductor substrate 1, above the source layer 5 and the contact layer 6. A barrier metal layer 12 is disposed on the Ni silicide layer 11 and the interlayer insulating film 10. The barrier metal layer 12 is formed, for example, of Ti / TiN. A metal layer 13 is formed on the barrier metal layer 12. The metal layer 13 is, for example, an Al electrode. The Ni silicide layer 11, the barrier metal layer 12, and the metal layer 13 may also be collectively referred to as the source electrode or the pad electrode 41.

[0051] A Ni silicide layer 14 is formed on the back side of the semiconductor substrate 1. An Al electrode 15 is formed on the back side of the Ni silicide layer 14. The Ni silicide layer 14 and the Al electrode 15 can also be collectively referred to as the drain electrode.

[0052] Figure 4 This is an enlarged view of region 107 at the end of the active region 101 involved in Embodiment 1. Figure 5 It is by... Figure 4 A sectional view obtained by cutting with a C-D line. For example... Figure 5 As shown, a p-type FLR (Field Limiting Ring) layer 16 and an n+ type channel cutoff layer 17 are formed on the upper surface side of the drift layer 3 in the terminal region 104. Thus, a voltage-holding structure, known as the FLR structure, is formed in the terminal region 104. A field insulating film 18 is formed on the upper surface of the semiconductor substrate 1 in the terminal region 104. A protective film 19, such as a nitride film, is formed on the field insulating film 18. A protective film 20, such as a polyimide film, is formed on the protective film 19. The protective film 19 is, for example, an inorganic protective film with excellent moisture resistance and moisture-proofing function. The protective film 20 is, for example, an organic protective film with stress-relieving function.

[0053] In the gate wiring region 102, a gate electrode 21 is formed on the field insulating film 18. The gate electrode 21 is a wiring layer connected to the gate electrode layer 9. The gate electrode 21 is formed of polysilicon. A barrier metal layer 22 is formed on the gate electrode 21. The barrier metal layer 22 is formed, for example, of Ti silicide / TiN. A metal layer 23 is formed on the barrier metal layer 22. The metal layer 23 is formed, for example, of Al. In the active region 101, a metal layer 24 is formed on the field insulating film 18, separated by the barrier metal layer 22. The metal layer 24 is formed, for example, of Al.

[0054] A metal layer 25, serving as an electrode protective film, is formed on top of metal layers 23 and 24. Metal layer 25 is formed, for example, of Ti. Barrier metal layers 22 and 23, and the metal layer 25 disposed on metal layer 23, constitute the gate wiring 42. Barrier metal layers 22 and 24, and the metal layer 25 disposed on metal layer 24, constitute the pad electrode 41. Protective films 19 and 20 are formed on metal layer 25. Protective films 19 and 20 cover the entire gate wiring 42 and the ends of the pad electrodes 41.

[0055] In the semiconductor device 100, a source electrode is formed on the upper surface of the semiconductor substrate 1, and a drain electrode is formed on the back surface of the semiconductor substrate 1. As a result, the main current flows in the vertical direction of the semiconductor substrate 1. In the MOSFET composed of a source layer 5, a well layer 4, a drift layer 3, a gate insulating film 8, and a gate electrode layer 9, the main current is controlled by the gate.

[0056] like Figure 2 As shown, the unit cells are formed in a striped pattern. Multiple gate electrode layers 9 are also formed in a striped pattern. The gate electrode layer 9 is connected to the gate electrode 21 of the gate wiring region 102 adjacent to the end of the active region 101. Figure 4 At the contact hole 30 surrounded by X shown, the gate electrode 21 is connected to the gate wiring 42. Additionally, in Figure 2 , Figure 4 At the contact hole 29 surrounded by X shown, the semiconductor substrate 1 contacts the pad electrode 41. Thus, the source is grounded.

[0057] Next, the manufacturing method of the semiconductor device 100 will be described. Figures 6-21 This is a cross-sectional view illustrating the manufacturing method of the semiconductor device 100 according to Embodiment 1. Figure 6 , Figure 7 These are cross-sectional views A-B and C-D of the active region 101 after the processes of forming the diffusion layer, MOS gate, interlayer film, and wiring have been completed. The processes up to this point can be achieved using conventional semiconductor processes, therefore descriptions are omitted.

[0058] Next, a Ti film 26 is formed on the metal layers 13 and 24 using techniques such as sputtering. Figure 8 , Figure 9 These are cross-sectional views A-B and C-D, showing the Ti film 26 in place. Next, resist patterning was performed using standard photolithography techniques. Figure 10 , Figure 11 These are cross-sectional views A-B and C-D, respectively, showing the state after the resist 27 has been patterned.

[0059] Next, the Ti film 26 is etched using the photoresist 27 as a mask. As a result, a metal layer 25 is formed at the specified location. Figure 12 , Figure 13 These are cross-sectional views A-B and C-D, showing the state with metal layer 25 formed. At this point, the size and position of the resist 27 are adjusted as needed so that metal layer 25 can cover metal layers 23 and 24.

[0060] Next, after removing the resist 27, a nitride film 28 is formed using methods such as deposition. Figure 14 , Figure 15 These are cross-sectional views A-B and C-D, showing the state with the nitride film 28 formed. Then, resist patterning is performed using conventional photolithography techniques. Figure 16 , Figure 17 These are cross-sectional views A-B and C-D, respectively, showing the state in which resist 27 has been formed.

[0061] Next, the resist 27 is used as a mask to etch the nitride film 28, forming a protective film 19 at the specified location. Figure 18 , Figure 19 These are cross-sectional views A-B and C-D, showing the state with the protective film 19 formed. At this time, the size and position of the resist 27 are adjusted so that the portion of the metal layer 23 or metal layer 24 in contact with the metal layer 25 is completely covered by the protective film 19.

[0062] Next, remove the resist 27. Figure 20 , Figure 21 These are cross-sectional views A-B and C-D, showing the state after removing resist 27. Subsequent processes can be achieved using conventional semiconductor processes, therefore, details are omitted.

[0063] Next, the operation of the semiconductor device 100 will be explained. When the positive voltage applied to the gate pad 103 is above the threshold voltage of the MOSFET, the MOSFET is turned on. As a result, the drain voltage decreases, the main current flows between the source and drain, and the semiconductor device 100 becomes in the on state. Conversely, when the negative voltage applied to the gate pad 103 in the on state is below the threshold voltage, the MOSFET is turned off. As a result, the current between the source and drain is cut off, the drain voltage rises, and the semiconductor device 100 becomes in the off state.

[0064] In the off state, the depletion layer in the termination region 104 extends laterally from the active region 101 towards the end of the termination region 104. At this time, the electric field strength is set below a predetermined value through the FLR layer 16 and the channel cutoff layer 17. Therefore, the gate wiring 42 formed in the region closest to the termination region 104 at the end of the active region 101 is more susceptible to the drain voltage than the active region 101.

[0065] Furthermore, under high temperature and humidity conditions, moisture can sometimes infiltrate from the outside while ionizing. In particular, in transfer-molded products, moisture can infiltrate from the chip ends through resin interfaces, etc. Thus, especially at the outer periphery of the chip, the metal layer 23 formed of Al on the gate wiring 42 is more susceptible to corrosion than other parts due to the influence of temperature, humidity, and electric field.

[0066] In contrast, in this embodiment, the metal layer 23 formed of Al is covered by the metal layer 25 of the Ti electrode, which has excellent corrosion resistance. Therefore, it is possible to improve moisture resistance or acid resistance and increase THB (Temperature Humidity Bias) tolerance.

[0067] Furthermore, in the gate wiring 42, the upper surface and both sides of the metal layer 23 are entirely covered by the metal layer 25. That is, the contact portion between the metal layer 23 and the metal layer 25 is not exposed relative to the components disposed on the protective film 19. As a result, the portion of the contact between the two metals such as Al and Ti can be prevented from being exposed to moisture through the protective film 20, sealing resin, etc. Therefore, corrosion of the metal caused by localized cell effect can be suppressed, and moisture resistance or acid resistance can be further improved.

[0068] Furthermore, the gate wiring 42 is covered by a protective film 19. This further inhibits moisture intrusion and improves moisture resistance or acid resistance. In particular, the upper surface and both sides of the gate wiring 42 are entirely covered by the protective film 19, thereby further improving moisture resistance or acid resistance.

[0069] Furthermore, a portion of the active region 101 needs to be bonded to the packaged electrode via methods such as wire bonding or solder bonding. Therefore, a portion of the metal layers 13 and 24 is exposed. Specifically, a pad opening 41a is formed on the pad electrode 41, where the metal layer 24 exposes from the metal layer 25. At the pad opening 41a, the metal layer 24 is not covered by the metal layer 25. Therefore, the contact portion of the metal layers 24 and 25, i.e., the end of the metal layer 25, may be exposed at a position facing the pad opening 41a.

[0070] In contrast, in this embodiment, the contact portion between the metal layer 24 and the metal layer 25 facing the pad opening 41a is covered by a protective film 19. That is, in the pad electrode 41, the contact portion between the metal layer 24 and the metal layer 25 is not exposed relative to the component disposed on the protective film 19. Therefore, galvanic corrosion and localized galvanic effects can be prevented, and moisture resistance or acid resistance can be further improved.

[0071] Furthermore, in this embodiment, a protective film 20, which is a polyimide film, is also provided on top of the protective film 19. This allows for stress relief, particularly in molded sealing products. Additionally, the protective film 20 covers the corners of the gate wiring 42 and the pad electrodes 41. This allows for stress relief in areas where stress is easily applied, such as the steps of the wiring.

[0072] In this embodiment, the metal layer 25 is formed of Ti. The thickness of this Ti film is preferably set to a thickness that will not produce pinholes; considering the impact on etching and wafer warpage, it is preferably around 200-3000 Å. Alternatively, the metal layer 25 may also be formed of a material containing Ti, Au, or Pt, which have excellent moisture resistance. The metal layer 25 only needs to contain a metal with higher moisture resistance or acid resistance than metal layers 23 and 24.

[0073] In this embodiment, metal layers 23 and 24 are formed of Al. However, they are not limited to this; metal layers 23 and 24 may also contain Al or Cu. Metal layers 23 and 24 are not limited to pure aluminum (Al); they may also be AlSi or AlSiCu, or they may be wiring with Cu as the main material.

[0074] The thickness of the nitride film 19 used as the protective film is preferably such that it will not crack under operating temperature conditions. Considering the impact on etching and wafer warpage, it is preferably around 5000~30000 Å. The protective film 19 can also be an oxide film. The protective film 19 can also be a glass coating such as a plasma nitride film or a plasma oxide film.

[0075] In this embodiment, the contact portion between the metal layer 23 and the metal layer 24 in the gate wiring 42 located closest to the terminal region 104 in the gate wiring region 102 is not exposed relative to the component disposed on the protective film 19. However, this is not a limitation; it is sufficient that in any wiring in the wiring region between the active region 101 and the terminal region 104, the contact portion between the metal layer 23 and the metal layer 24 is not exposed relative to the component disposed on the protective film 19.

[0076] This structure, which conceals the contact areas of different metal layers, can be applied to any wiring on the semiconductor substrate 1. As described above, this structure is particularly effective when applied to wiring on the outer periphery of a chip, but regardless of the wiring it is applied to, it can improve moisture resistance and acid resistance.

[0077] For example, a structure in which the contact portions of metal layers 24 and 25 are not exposed can be applied to the pad electrode 41, while the gate wiring 42 does not use the above structure. Similarly, a structure in which the contact portions of metal layers 23 and 25 are not exposed can be applied to the gate wiring 42, while the pad electrode 41 does not use the above structure. Here, "the contact portions of different metal layers are not exposed relative to the components disposed on the protective film" means that the ends of the contact surfaces of different metal layers are not exposed relative to the components disposed on the protective film 19.

[0078] In addition, Figure 5 In this example, the upper surface and both sides of the gate wiring 42 are entirely covered by the protective film 19. However, this is not a limitation; the protective film 19 only needs to cover at least a portion of the gate wiring 42. For example, the protective film 19 can also be configured to cover only a portion of the gate wiring 42 from the upper surface of the metal layer 25 to the sides of the metal layer 23. With this structure, the metal layer 25 and the protective film 19 can also be used to improve moisture resistance or acid resistance. Furthermore, it is preferable that the contact portions of the metal layers 23 and 25 and the contact portions of the metal layers 24 and 25 are not exposed, but a portion may be exposed within permissible limits.

[0079] The semiconductor substrate 1 can also be a silicon substrate, or it can be formed from a wide-bandgap semiconductor. The wide-bandgap semiconductor is silicon carbide, gallium nitride-based materials, or diamond. In addition, the semiconductor device 100 is not limited to MOSFETs, but can also be other devices such as IGBTs.

[0080] The above-described modifications can be appropriately applied to the semiconductor device involved in the following embodiments. Furthermore, since the semiconductor device involved in the following embodiments shares many similarities with Embodiment 1, the differences from Embodiment 1 will be described.

[0081] Implementation Method 2

[0082] Figure 22 This is an enlarged view of region 107 at the end of the active region 101 involved in Embodiment 2. Figure 23 It is by... Figure 22 A cross-sectional view obtained by cutting along the C-D line. In this embodiment, the difference from Embodiment 1 is that the metal layer 25 is only disposed on the upper surface of the metal layer 23 and the upper surface of the metal layer 24. That is, the side surfaces of the metal layer 23 and the metal layer 24 are exposed from the metal layer 25. Other structures are the same as in Embodiment 1.

[0083] In this embodiment, metal layers 23 and 24 are partially covered by metal layer 25 to improve moisture resistance. Furthermore, in the gate wiring 42, a protective film 19 is provided from the upper surface of metal layer 25 to the side surfaces of both sides of metal layer 23. Therefore, even when metal layer 25 is only provided on the upper surface of metal layer 23, the ends of the contact surfaces between metal layer 23 and metal layer 25 can be covered by the protective film 19. Additionally, the ends of the contact surfaces between metal layer 24 and metal layer 25 are also covered by the protective film 19. Therefore, moisture resistance or acid resistance can be improved.

[0084] Similar to Embodiment 1, the protective film 19 may not cover the entire gate wiring 42. The protective film 19 can be provided from the upper surface of the metal layer 25 to the side surfaces of both sides of the metal layer 23. Alternatively, the protective film 19 can be provided from the upper surface of the metal layer 25 to the side surfaces of the metal layer 24. Thus, the ends of the metal layer 25 can be covered by the protective film 19.

[0085] Implementation Method 3

[0086] Figure 24 This is an enlarged view of region 107 at the end of the active region 101 involved in Embodiment 3. Figure 25 It is by... Figure 24 A cross-sectional view obtained by cutting along the C-D line. In this embodiment, the difference from Embodiment 1 is that the metal layer 24 in the pad electrode 41 is also completely covered by the metal layer 25. The other structures are the same as in Embodiment 1.

[0087] In this embodiment, the upper and side surfaces of the metal layers 23 and 24, which serve as Al electrodes, are completely covered by the metal layer 25, which serves as a Ti electrode. Therefore, the contact portion between the metal layer 23 or 24 and the metal layer 25 is not exposed, improving moisture resistance or acid resistance. Furthermore, by covering a portion of the gate wiring 42 and the pad electrode 41 with a protective film 19, moisture resistance or acid resistance can be further improved.

[0088] Implementation Method 4

[0089] Figure 26This is an enlarged view of region 107 at the end of the active region 101 involved in Embodiment 4. Figure 27 It is by... Figure 26 A cross-sectional view obtained by cutting along a C-D line. In this embodiment, the difference from Embodiment 1 is that the contact portion between metal layer 24 and metal layer 25 is exposed from the protective film 19 in the pad electrode 41. The other structures are the same as in Embodiment 1. In this embodiment, the moisture resistance of the pad electrode 41 is reduced compared to Embodiment 1. However, in the gate wiring 42, the contact portion between metal layer 23 and metal layer 25 is not exposed relative to the components disposed on the protective film 19. Therefore, in areas susceptible to temperature, humidity, and electric field influences, moisture resistance or acid resistance can be improved.

[0090] Implementation Method 5

[0091] Figure 28 This is a top view of the semiconductor device 100 according to Embodiment 5. Figure 29 This is an enlarged view of region 107 at the end of the active region 101 according to Embodiment 5. Figure 30 It is by... Figure 29 A cross-sectional view obtained by cutting along the E-F line. In this embodiment, a source pad wiring region 108 is provided between the gate wiring region 102 and the termination region 104. The source pad wiring region 108 is the region in the semiconductor substrate 1 where the source pad wiring 48 is provided.

[0092] In the source pad wiring region 108, a metal layer 32 serving as an Al electrode is formed on top of the barrier metal layer 22. A metal layer 25 formed of Ti is formed on top of the metal layer 32. The barrier metal layer 22, the metal layer 32, and the metal layer 25 disposed on the metal layer 32 constitute the source pad wiring 48. The source pad wiring 48 is connected to the well layer 4 and the contact layer 6 at the contact hole 31. The source pad wiring 48 is connected to the source electrode of the active region 101.

[0093] In this embodiment, the upper surface and both sides of the metal layer 32 in the source pad wiring 48 are entirely covered by the metal layer 25. Therefore, the contact portion between the metal layer 32 and the metal layer 25 is not exposed relative to the component disposed on the protective film 19. Furthermore, the upper surface and both sides of the source pad wiring 48 are entirely covered by the protective film 19. This improves moisture resistance and acid resistance.

[0094] In this embodiment, the source pad wiring 48 is a wiring located at the position closest to the terminal region 104. Therefore, considering the intrusion path of moisture and the electric field distribution of the terminal region 104, the source pad wiring 48 is also protected by the metal layer 25 and the protective film 19, in addition to the gate wiring 42.

[0095] Alternatively, only one of the gate wiring 42 and the source pad wiring 48 may be protected. Furthermore, in this embodiment, an example is shown where the source wiring is provided in the wiring region; however, if the semiconductor device 100 is an IGBT, the emitter wiring may also be provided.

[0096] The technical features described in each embodiment can also be used in combination as appropriate.

[0097] The various methods disclosed herein are summarized below as appendices.

[0098] (Note 1)

[0099] A semiconductor device, characterized in that,

[0100] have:

[0101] Semiconductor substrate;

[0102] Wiring is disposed on the aforementioned semiconductor substrate; and

[0103] A protective film covering at least a portion of the aforementioned wiring.

[0104] The aforementioned wiring comprises: a first metal layer; and a second metal layer disposed on top of the first metal layer, and comprising a metal with higher moisture resistance or acid resistance than the first metal layer.

[0105] In the above wiring, the contact portion between the first metal layer and the second metal layer is not exposed relative to the component disposed on the protective film.

[0106] (Note 2)

[0107] The semiconductor device according to Appendix 1 is characterized in that,

[0108] The aforementioned semiconductor substrate has an active region, a wiring region outside the active region, and a termination region outside the wiring region.

[0109] The aforementioned wiring is installed in the aforementioned wiring area.

[0110] (Note 3)

[0111] A semiconductor device, characterized in that,

[0112] have:

[0113] A semiconductor substrate having an active region, a wiring region outside the active region, and a terminal region outside the wiring region;

[0114] Wiring is installed above the aforementioned wiring area; and

[0115] A protective film covering at least a portion of the aforementioned wiring.

[0116] The aforementioned wiring comprises: a first metal layer; and a second metal layer disposed on top of the first metal layer, and comprising a metal with higher moisture resistance or acid resistance than the first metal layer.

[0117] The protective film is disposed from the upper surface of the second metal layer to the sides of both sides of the first metal layer.

[0118] (Note 4)

[0119] The semiconductor device according to Appendix 3 is characterized in that,

[0120] In the above wiring, the contact portion between the first metal layer and the second metal layer is not exposed relative to the component disposed on the protective film.

[0121] (Note 5)

[0122] The semiconductor device described in any one of Appendices 2 to 4 is characterized in that,

[0123] The aforementioned wiring is located at the position closest to the aforementioned terminal area within the aforementioned wiring area.

[0124] (Note 6)

[0125] The semiconductor device described in any one of Appendices 1 to 5 is characterized in that,

[0126] The upper surface and both sides of the first metal layer are completely covered by the second metal layer.

[0127] (Note 7)

[0128] The semiconductor device described in any one of Appendices 2 to 5 is characterized in that,

[0129] The aforementioned semiconductor device includes a pad electrode, the pad electrode having a third metal layer disposed above the active region, and a fourth metal layer disposed above the third metal layer and comprising a metal with higher moisture resistance or acid resistance than the third metal layer.

[0130] The pad electrode has an opening where the third metal layer is exposed from the fourth metal layer.

[0131] The contact portion between the third metal layer and the fourth metal layer facing the opening of the pad is covered by the protective film.

[0132] (Postscript 8)

[0133] The semiconductor device described in any one of Appendices 1 to 7 is characterized in that,

[0134] The above wiring is gate wiring.

[0135] (Note 9)

[0136] The semiconductor device described in any one of Appendices 1 to 7 is characterized in that,

[0137] The above wiring is either source wiring or emitter wiring.

[0138] (Postscript 10)

[0139] The semiconductor device described in any one of Appendices 1 to 9 is characterized in that,

[0140] The second metal layer mentioned above contains Ti, Au, or Pt.

[0141] (Postscript 11)

[0142] The semiconductor device described in any one of Appendices 1 to 10 is characterized in that,

[0143] The first metal layer mentioned above contains Al or Cu.

[0144] (Postscript 12)

[0145] The semiconductor device described in any one of Appendices 1 to 11 is characterized in that,

[0146] The aforementioned semiconductor device includes a polyimide film disposed on the aforementioned protective film.

[0147] (Postscript 13)

[0148] The semiconductor device according to Appendix 12 is characterized in that,

[0149] The polyimide film covers the corners of the wiring.

[0150] (Postscript 14)

[0151] The semiconductor device described in any one of Appendices 1 to 13 is characterized in that,

[0152] The aforementioned protective film is a nitrided film or an oxide film.

[0153] (Postscript 15)

[0154] The semiconductor device described in any one of Appendices 1 to 14 is characterized in that,

[0155] The aforementioned semiconductor substrate is formed from a wide-bandgap semiconductor.

[0156] (Postscript 16)

[0157] The semiconductor device according to Appendix 15 is characterized in that,

[0158] The aforementioned wide-bandgap semiconductors are silicon carbide, gallium nitride-based materials, or diamond.

[0159] (Postscript 17)

[0160] A semiconductor device, characterized in that,

[0161] have:

[0162] Semiconductor substrate;

[0163] The bonding pad electrodes are disposed on the aforementioned semiconductor substrate; and

[0164] A protective film is applied to the aforementioned pad electrodes.

[0165] The aforementioned pad electrode has: a first metal layer; and a second metal layer disposed on the first metal layer, and comprising a metal with higher moisture resistance or acid resistance than the first metal layer.

[0166] The pad electrode has an opening where the first metal layer exposes from the second metal layer.

[0167] The contact portion between the first metal layer and the second metal layer facing the opening of the pad is covered by the protective film.

Claims

1. A semiconductor device, characterized in that, have: Semiconductor substrate; Wiring is disposed on the semiconductor substrate; and A protective film covering at least a portion of the wiring. The wiring has: a first metal layer; A second metal layer is disposed on top of the first metal layer and comprises a metal with higher moisture resistance or acid resistance than the first metal layer. In the wiring, the contact portion between the first metal layer and the second metal layer is not exposed relative to the component disposed on the protective film.

2. The semiconductor device according to claim 1, characterized in that, The semiconductor substrate has an active region, a wiring region outside the active region, and a termination region outside the wiring region. The wiring is provided in the wiring area.

3. A semiconductor device, characterized in that, have: A semiconductor substrate having an active region, a wiring region outside the active region, and a terminal region outside the wiring region; Wiring is installed above the wiring area; as well as A protective film covering at least a portion of the wiring. The wiring has: a first metal layer; A second metal layer is disposed on top of the first metal layer and comprises a metal with higher moisture resistance or acid resistance than the first metal layer. The protective film is disposed from the upper surface of the second metal layer to the sides of both sides of the first metal layer.

4. The semiconductor device according to claim 3, characterized in that, In the wiring, the contact portion between the first metal layer and the second metal layer is not exposed relative to the component disposed on the protective film.

5. The semiconductor device according to any one of claims 2 to 4, characterized in that, The wiring is the wiring located at the position closest to the terminal area in the wiring area.

6. The semiconductor device according to any one of claims 1 to 4, characterized in that, The upper surface and both sides of the first metal layer are completely covered by the second metal layer.

7. The semiconductor device according to any one of claims 2 to 4, characterized in that, The semiconductor device includes a pad electrode having a third metal layer disposed above the active region and a fourth metal layer disposed above the third metal layer and comprising a metal having higher moisture resistance or acid resistance than the third metal layer. The pad electrode has an opening where the third metal layer exposes from the fourth metal layer. The contact portion between the third metal layer and the fourth metal layer facing the opening of the pad is covered by the protective film.

8. The semiconductor device according to any one of claims 1 to 4, characterized in that, The wiring is a gate wiring.

9. The semiconductor device according to any one of claims 1 to 4, characterized in that, The wiring is either source wiring or emitter wiring.

10. The semiconductor device according to any one of claims 1 to 4, characterized in that, The second metal layer contains Ti, Au, or Pt.

11. The semiconductor device according to any one of claims 1 to 4, characterized in that, The first metal layer contains Al or Cu.

12. The semiconductor device according to any one of claims 1 to 4, characterized in that, The semiconductor device includes a polyimide film disposed on the protective film.

13. The semiconductor device according to claim 12, characterized in that, The polyimide film covers the corners of the wiring.

14. The semiconductor device according to any one of claims 1 to 4, characterized in that, The protective film is a nitrided film or an oxide film.

15. The semiconductor device according to any one of claims 1 to 4, characterized in that, The semiconductor substrate is formed of a wide-bandgap semiconductor.

16. The semiconductor device according to claim 15, characterized in that, The wide-bandgap semiconductor is silicon carbide, gallium nitride-based materials, or diamond.

17. A semiconductor device, characterized in that, have: Semiconductor substrate; Bonding pad electrodes are disposed on the semiconductor substrate; and A protective film is disposed on the pad electrode. The pad electrode has: a first metal layer; A second metal layer is disposed on top of the first metal layer and comprises a metal with higher moisture resistance or acid resistance than the first metal layer. The pad electrode has an opening where the first metal layer exposes from the second metal layer. The contact portion between the first metal layer and the second metal layer facing the opening of the pad is covered by the protective film.

Images