A power conversion device, a semiconductor device applied to the power conversion device, and a device manufacturing method

Abstract

This invention relates to the field of power electronics technology, specifically to a power conversion device, a semiconductor device applied to the power conversion device, and a method for fabricating the device. The power conversion device includes a DC input terminal, an AC output terminal, a power conversion circuit connected between the DC input terminal and the AC output terminal, and a control unit. The power conversion circuit includes at least one semiconductor device. One side of the base region in the semiconductor device cell has a field-plate composite shielding structure and a Schottky diode structure, while the other side has a single-sided conductive channel structure. The field-plate composite shielding structure is used to modulate the electric field distribution in the drift region of the semiconductor device when the device is subjected to high voltage. The control unit is electrically connected to the gate electrode layer of the semiconductor device and is used to output a PWM control signal to control the on / off state of the semiconductor device. This invention can improve the operational reliability of power conversion devices under high-voltage conditions.

Description

Technical Field

[0001] This invention relates to the field of power electronics technology, and in particular to a power conversion device, a semiconductor device used in the power conversion device, and a method for fabricating the device. Background Technology

[0002] In high-voltage, high-power power conversion systems (such as photovoltaic inverters, different power supplies, and rail transit traction converters), silicon carbide (SiC) materials have become important materials for the preparation of power devices in medium- and high-power applications (such as new energy vehicles and photovoltaic inverters) due to their excellent properties such as wide bandgap, high critical breakdown field strength, and high thermal conductivity.

[0003] However, existing planar gate SiC MOSFET device structures still have the following inherent drawbacks when applied to high-voltage, high-frequency conditions: Limited switching performance: Traditional symmetrical channel designs result in a large overlap area between the gate and drain, leading to significant Miller capacitance (Cgd). This large Miller capacitance severely limits the device's switching speed, increases switching losses, and increases the risk of bridge arm shoot-through.

[0004] Reliability risk: Under high voltage blocking conditions, electric field lines tend to concentrate at the end of the gate oxide layer (especially at the corner of the channel), forming electric field spikes, which cause huge electrical stress to the gate oxide layer. Long-term operation will reduce the gate oxide lifetime and threaten the long-term reliability of the device.

[0005] Poor performance of the body diode: The built-in body diode (PN junction) of the device has a large reverse recovery charge (Qrr), resulting in high reverse recovery losses and susceptibility to electromagnetic interference (EMI). To solve this problem, the system often requires an external freewheeling diode, which increases the system cost and complexity.

[0006] To address the aforementioned issues, some technical solutions have attempted to optimize individual performance indicators, but these solutions are mostly limited to the framework of planar processes. They have already approached physical limits in terms of electric field management, parasitic parameter control, and functional integration, becoming a key bottleneck restricting the widespread application of switching devices in high-voltage fields for power conversion equipment. Summary of the Invention

[0007] This application aims to at least solve the technical problems existing in the prior art, and to provide a power conversion device, a semiconductor device applied to the power conversion device, and a method for fabricating the device.

[0008] In a first aspect, the present invention provides a power conversion device, including a DC input terminal, an AC output terminal, a power conversion circuit connected between the DC input terminal and the AC output terminal, and a control unit. The power conversion circuit includes at least one semiconductor device. A field plate composite shielding structure and a Schottky diode structure are formed on one side of the base region of the semiconductor device cell, and a single-sided conductive channel structure is formed on the other side. The source metal layer of the semiconductor device forms an ohmic contact with the single-sided conductive channel structure, and the Schottky diode structure forms a Schottky contact with the source metal layer. The field plate composite shielding structure is used to modulate the electric field distribution in the drift region of the semiconductor device when the device is subjected to high voltage. The control unit is electrically connected to the gate electrode layer of the semiconductor device and is used to output a PWM control signal to control the turn-on and turn-off of the semiconductor device.

[0009] By adopting the above technical solution, the field plate composite shielding structure, the Schottky diode structure, and the single-sided conductive channel structure are integrated into the same cell. On the one hand, the field plate composite shielding structure effectively modulates the electric field in the drift region when the device is subjected to high voltage, suppressing the electric field spike at the gate oxide end and improving the device's withstand voltage and long-term gate oxide reliability. On the other hand, the single-sided conductive channel structure physically eliminates the redundant gate-drain overlap region in traditional symmetrical channels, significantly reducing Miller capacitance, increasing switching speed, and reducing switching losses. At the same time, the integrated Schottky diode structure provides a majority carrier transport path for reverse freewheeling, with almost no reverse recovery charge, fundamentally solving the problems of high reverse recovery loss and electromagnetic interference in body diodes. As a result, the operational reliability and power conversion efficiency of power conversion equipment under high voltage and high frequency conditions are comprehensively improved.

[0010] Secondly, the present invention provides a semiconductor device comprising, from bottom to top, a drain metal layer, a first conductivity type substrate, a first conductivity type buffer layer, a first conductivity type drift region, and a source metal layer. It also includes a field plate composite shielding structure, a single-sided conductive channel structure, and a Schottky diode structure formed on the side of the first conductivity type drift region away from the first conductivity type buffer layer, with the source metal layer forming an ohmic contact with the single-sided conductive channel structure. A groove is formed on the side of the first conductivity type drift region away from the first conductivity type buffer layer, and the groove extends downward to the middle section of the drift region; The field plate composite shielding structure includes a first and a second conductivity type shielding layer, which are formed at the bottom of the trench and on the sidewall of one side of the trench; the trench is filled with polycrystalline silicon to form a field plate electrode, which is electrically connected to the source metal layer. The Schottky diode structure is disposed on the sidewall of the trench away from the first and second conductivity type shielding layers, and the Schottky diode structure forms a Schottky contact with the source metal layer; A single-sided conductive channel structure is disposed on the side of the trench away from the Schottky diode structure. The single-sided conductive channel structure includes a first conductivity type carrier storage layer and a first conductivity type JFET region disposed sequentially on a first conductivity type drift region. One side of the first conductivity type JFET region is in contact with a first and second conductivity type shielding layer. The single-sided conductive channel structure also includes a second conductivity type base region, which is formed on the side of the first conductivity type JFET region away from the first and second conductivity type shielding layers; A gate oxide layer and a gate electrode layer are sequentially formed on the side of the base region of the second conductivity type away from the carrier storage layer of the first conductivity type. The source metal layer and the gate electrode layer are electrically isolated.

[0011] Optionally, a second conductivity type shielding layer is formed between the second conductivity type base region and the first conductivity type carrier storage layer. A first conductivity type source region and a second conductivity type contact region are sequentially formed on the side of the second conductivity type base region away from the first conductivity type JFET region. The second conductivity type base region, the first conductivity type source region, and the second conductivity type contact region are all arranged side by side on the side of the second conductivity type shielding layer away from the first conductivity type carrier storage layer.

[0012] Optionally, the source metal layer is simultaneously electrically connected to the source region of the first conductivity type, the contact region of the second conductivity type, the Schottky diode structure, and the field plate electrode in the trench.

[0013] Optionally, an interlayer dielectric layer is formed between the source metal layer and the gate electrode layer, and the source metal layer and the gate electrode layer are electrically isolated through the interlayer dielectric layer. The source metal layer forms an ohmic contact with the second conductivity type contact region and the first conductivity type source region through contact holes in the interlayer dielectric layer.

[0014] Optionally, the doping concentration of impurity atoms in the first and second conductivity type shielding layer is higher than the doping concentration of impurity atoms in the second conductivity type base region, and the doping concentration of impurity atoms in the second conductivity type shielding layer is higher than the doping concentration of impurity atoms in the second conductivity type base region.

[0015] Optionally, the gate oxide layer is simultaneously in contact with the first conductivity type JFET region and the second conductivity type base region.

[0016] Optionally, the doping concentration of impurity atoms in the first conductivity type substrate is higher than the doping concentration of impurity atoms in the first conductivity type buffer layer, the doping concentration of impurity atoms in the first conductivity type buffer layer is higher than the doping concentration of impurity atoms in the first conductivity type drift layer, and the doping concentration of the first conductivity type carrier storage layer is higher than the doping concentration of impurity atoms in the first conductivity type drift layer.

[0017] Optionally, the first conductivity type is N-type, and the second conductivity type is P-type.

[0018] Optionally, the Schottky diode structure is an N+ type Schottky barrier diode.

[0019] Thirdly, the present invention provides a method for fabricating a semiconductor device, the method comprising: Provide a substrate of the first conductivity type; A first conductivity type buffer layer and a first conductivity type drift region are sequentially formed on top of a first conductivity type substrate; A groove is formed on the side of the first conductivity type drift region away from the first conductivity type buffer layer; By using an ion implantation process, a second type of conductivity impurity is implanted into the bottom of the trench and one sidewall to form a first and second type of conductivity shielding layer; on the other sidewall of the trench, a Schottky diode structure is formed by selective ion implantation. The trench is filled with doped polycrystalline silicon and then etched back to the top of the trench to form a field plate electrode. A patterning layer is formed on the side of the first conductivity type drift region away from the first conductivity type buffer layer, and photoresist is spin-coated. The photolithography machine is controlled to define the active region pattern combination through a mask, and the active region pattern combination is etched to form a single-sided conductive channel structure in the patterning layer. An interlayer dielectric layer is deposited, and contact holes are etched to achieve electrical connection between the source metal layer and the source region of the first conductivity type, the contact region of the second conductivity type, the Schottky diode structure, and the field plate electrode in the trench; Al metal is deposited on the top of the chip using a source mask to form a source metal layer; Al metal is deposited on the bottom of the chip using a drain mask to form a drain metal layer.

[0020] In summary, this application includes the following beneficial technical effects: This invention integrates a field plate composite shielding structure, a Schottky diode structure, and a single-sided conductive channel structure into a single cell. On one hand, the field plate composite shielding structure effectively modulates the electric field in the drift region when the device is subjected to high voltage, suppressing electric field spikes at the gate oxide terminals and improving the device's withstand voltage and long-term gate oxide reliability. On the other hand, the single-sided conductive channel structure physically eliminates the redundant gate-drain overlap region found in traditional symmetrical channels, significantly reducing Miller capacitance, increasing switching speed, and reducing switching losses. Simultaneously, the integrated Schottky diode structure provides a majority carrier transport path for reverse freewheeling, with almost no reverse recovery charge, fundamentally solving the problems of high reverse recovery loss and electromagnetic interference associated with body diodes. Therefore, the operational reliability and power conversion efficiency of power conversion equipment under high voltage and high frequency conditions are comprehensively improved. The composite shielding structure, consisting of a first and second conductivity type shielding layer at the bottom of the trench and one sidewall, and a field plate electrode at the same potential as the source, actively attracts electric field lines and homogenizes the gate oxide electric field through a dual mechanism of PN junction depletion and field plate electrostatic induction in the blocking state, effectively improving the breakdown voltage and long-term gate oxide reliability. A Schottky diode structure forming a Schottky contact with the source is integrated on the other sidewall of the trench, providing a low-dropout reverse freewheeling path for majority carrier transport. The reverse recovery charge is minimal, fundamentally eliminating the efficiency loss and EMI problems caused by the body diode. Furthermore, the first conductivity type carrier storage layer and the JFET region reduce the on-resistance, enabling each functional area to be physically separated and independently optimized in three-dimensional space. This achieves a synergistic improvement in key performance indicators such as switching speed, withstand voltage, reverse recovery, and on-resistance, resulting in a significant improvement in the overall quality factor. Attached Figure Description

[0021] Figure 1 This is a schematic diagram of the structure of a semiconductor device provided in an embodiment of the present invention; Figure 2 This is a schematic diagram of the circuit topology of a power conversion device provided in an embodiment of the present invention.

[0022] Reference numerals: 1. Drain metal layer; 2. First conductivity type substrate; 3. First conductivity type buffer layer; 4. First conductivity type drift region; 5. Source metal layer; 61. Trench; 62. First and second conductivity type shielding layer; 63. Field plate electrode; 71. First conductivity type carrier storage layer; 72. First conductivity type JFET region; 73. Second conductivity type base region; 74. Second and second conductivity type shielding layer; 75. First conductivity type source region; 76. Second conductivity type contact region; 8. Schottky diode structure; 91. Gate oxide layer; 92. Gate electrode layer; 93. Interlayer dielectric layer.

[0023] The realization of the objective, functional features and advantages of the present invention will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. Detailed Implementation

[0024] Embodiments of the present invention are described in detail below. Examples of these embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present invention, and should not be construed as limiting the present invention.

[0025] In the description of this invention, it should be understood that the terms "longitudinal", "lateral", "up", "down", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this invention.

[0026] In the description of this invention, unless otherwise specified and limited, it should be noted that the terms "installation", "connection" and "linking" should be interpreted broadly. For example, they can refer to mechanical or electrical connections, or internal connections between two components. They can be direct connections or indirect connections through an intermediate medium. Those skilled in the art can understand the specific meaning of the above terms according to the specific circumstances.

[0027] Example 1 Figure 1 This is a schematic diagram of the cell structure of a semiconductor device provided in an embodiment of the present invention. A cell is the basic unit of the active region of a SiC MOSFET device. The active region of a SiC MOSFET device is the core functional area on the chip that enables current conduction, and it is composed of a large number of repeating cell units. The front side of the cell is the source region, and the back side is the drain region. A current path is formed by controlling the channel through the gate. A complete SiC MOSFET device is composed of a large number of repeating cells arranged in the active region. These cells achieve high current carrying capacity through interconnection integration. The cell structure typically includes a polysilicon gate, an N+ source, a P-type base region, and a P-shielding region, defined on a silicon carbide epitaxial layer through photolithography and ion implantation processes. For example, in an octagonal cell design, the polysilicon, N+, and P-shielding regions all adopt an octagonal layout, and adjacent cells are interconnected through polysilicon connecting strips to form a regular array. The semiconductor device cell provided in this application includes, from bottom to top, a drain metal layer 1, a first conductivity type substrate 2, a first conductivity type buffer layer 3, a first conductivity type drift region 4, and a source metal layer 5. The semiconductor device further includes a field plate composite shielding structure, a single-sided conductive channel structure, and a Schottky diode structure 8 formed on the side of the first conductivity type drift region 4 away from the first conductivity type buffer layer 3, and the source metal layer 5 forms an ohmic contact with the single-sided conductive channel structure.

[0028] A longitudinal deep trench 61 is provided on the side of the first conductivity type drift region 4 away from the first conductivity type buffer layer 3, and the trench 61 extends downward to the middle section of the first conductivity type drift region 4.

[0029] The field plate composite shielding structure includes a first and second conductivity type shielding layer 62, which is formed at the bottom of a trench 61 and on one sidewall of the trench 61 by selective aluminum ion implantation. The trench 61 is filled with doped polysilicon to form a field plate electrode 63, which is electrically connected to the source metal layer 5. The field plate electrode 63 maintains equipotential connection with the source metal layer through subsequent interconnect processes. The first and second conductivity type shielding layers 62 and the field plate electrode 63 together constitute a deep trench field plate composite shielding structure. In this embodiment, the first and second conductivity type shielding layers 62 are mainly used to form a space charge region under high drain voltage, protecting the gate oxide layer 91 under high voltage.

[0030] The Schottky diode structure 8 is disposed on the sidewall of the trench 61 away from the first and second conductivity type shielding layer 62, and the Schottky diode structure 8 forms a Schottky contact with the source metal layer 5.

[0031] A single-sided conductive channel structure is disposed on the side of trench 61 away from Schottky diode structure 8. The single-sided conductive channel structure includes a first conductivity type carrier storage layer 71 and a first conductivity type JFET region 72 sequentially disposed on the first conductivity type drift region 4. One side of the first conductivity type JFET region 72 is in contact with the first and second conductivity type shielding layers 62. The N-type JFET region, through appropriate N-type doping and position design, provides a low-resistance path for electrons in the on-state, significantly reducing the specific on-resistance. In the blocking state, it works in synergy with the P+ shielding layers and P-type base regions on both sides to deplete, effectively pinching off and shielding the electric field spikes at the gate oxide end, thereby improving the breakdown voltage and gate oxide reliability.

[0032] The single-sided conductive channel structure also includes a second conductivity type base region 73, which is formed on the side of the first conductivity type JFET region 72 away from the first and second conductivity type shielding layers 62.

[0033] A gate oxide layer 91 and a gate electrode layer 92 are sequentially formed on the side of the base region 73 of the second conductivity type away from the carrier storage layer 71 of the first conductivity type to form a unique conductive channel; the source metal layer 5 and the gate electrode layer 92 are electrically isolated.

[0034] The thickness of the first conductivity type drift region 4 is greater than the thickness of the first conductivity type buffer layer 3. During fabrication, a thin first conductivity type buffer layer 3 is first epitaxially grown on the first conductivity type substrate 2, then the first conductivity type drift region 4 is epitaxially grown on the first conductivity type buffer layer 3, and finally the first conductivity type carrier storage layer 71 is grown on the first conductivity type drift region 4. The doping concentration of impurity atoms in the first conductivity type substrate 2 is higher than the doping concentration of impurity atoms in the first conductivity type buffer layer 3, and the doping concentration of impurity atoms in the first conductivity type buffer layer 3 is higher than the doping concentration of impurity atoms in the first conductivity type drift layer. The doping concentration of the first conductivity type carrier storage layer 71 is higher than the doping concentration of impurity atoms in the first conductivity type drift layer.

[0035] The first conductivity type buffer layer 3 can cut off the electric field when the forward blocking voltage is applied, so that the electric field lines drop to zero in the first conductivity type buffer layer 3; the low-doped first conductivity type drift region 4 is used to withstand high voltage; the doping concentration of the first conductivity type carrier storage layer 71 is higher than the doping concentration of the impurity atoms in the first conductivity type drift region 4, and the first conductivity type carrier storage layer 71 is used to increase the carrier concentration to reduce the on-resistance.

[0036] A second conductivity type shielding layer 74 is formed between the second conductivity type base region 73 and the first conductivity type carrier storage layer 71. A first conductivity type source region 75 and a second conductivity type contact region 76 are sequentially formed on the side of the second conductivity type base region 73 away from the first conductivity type JFET region 72. The second conductivity type base region 73, the first conductivity type source region 75, and the second conductivity type contact region 76 are all arranged side-by-side on the side of the second conductivity type shielding layer 74 away from the first conductivity type carrier storage layer 71. The second conductivity type contact region 76 is located at the cell boundary. The gate oxide layer 91 is in contact with both the first conductivity type JFET region 72 and the second conductivity type base region 73.

[0037] The gate oxide layer 91 is located only above the first conductivity type JFET region 72 and the second conductivity type base region 73. A portion of the lower surface of the gate oxide layer 91 contacts the upper surface of the first conductivity type JFET region 72, and a portion of the lower surface of the gate oxide layer 91 contacts a portion of the upper surface of the second conductivity type base region 73. The gate electrode layer 92 is disposed on the side of the gate oxide layer 91 away from the first conductivity type drift region 4. The gate electrode layer 92 is only disposed on one side of the cell to form a single-sided conductive channel structure design, which greatly reduces the overlap area between the gate and the drain, thereby significantly reducing the Miller capacitance. This reduces the gate charge and switching time during the switching process, improves the switching speed, and significantly reduces the switching loss.

[0038] The doping concentration of impurity atoms in the first and second conductivity type shielding layer 62 is higher than that in the second conductivity type base region 73, and the doping concentration of impurity atoms in the second conductivity type shielding layer 74 is higher than that in the second conductivity type base region 73. The concentration of impurity atoms in the second conductivity type contact region 76 is even higher than that in the first and second conductor type shielding layers (and the second conductor type shielding layer). The second conductivity type contact region 76 is mainly used to form an ohmic contact between the source and the semiconductor surface, enabling current to flow from the semiconductor to the source.

[0039] The source metal layer 5 is electrically interconnected with the first conductivity type source region 75, the second conductivity type contact region 76, the Schottky diode structure 8, and the field plate electrode 63 in the trench 61, forming a common potential node. An interlayer dielectric layer 93 is formed between the source metal layer 5 and the gate electrode layer 92. The source metal layer 5 and the polysilicon gate electrode layer 92 are electrically isolated through the interlayer dielectric layer 93. The source metal layer 5 forms an ohmic contact with the second conductivity type contact region 76 and the first conductivity type source region 75 through contact holes in the interlayer dielectric layer 93.

[0040] In this embodiment, the first conductivity type is N-type and the second conductivity type is P-type. The N-type conductive region is generated by doping with donor impurities, such as nitrogen (N) and phosphorus (P). The donor impurities provide free electrons, making the semiconductor mainly conductive by electrons. The P-type conductive region is generated by doping with acceptor impurities, such as boron (B) and aluminum (Al). The acceptor impurities provide holes, making the semiconductor mainly conductive by holes.

[0041] In a preferred embodiment of this example, the Schottky diode structure 8 is an N+ type Schottky barrier diode. The N+ Schottky barrier diode (N+ SBD), integrated on the sidewall of trench 61, is a majority carrier device. Theoretically, its reverse recovery charge and reverse recovery time are almost zero, eliminating the switching losses and EMI problems caused by minority carrier storage in traditional body diodes. Simultaneously, the Schottky junction formed by the heavily doped N+ region and the source metal has a lower barrier height, resulting in a significantly lower forward voltage drop than the body diode. Furthermore, the three-dimensional structure of the deep trench sidewall increases the effective contact area, making the current distribution more uniform and achieving low-loss reverse freewheeling without increasing the chip area. In addition, the wide bandgap characteristics of SiC material combined with optimized N+ doping allow it to maintain a low reverse leakage current even at high temperatures, while the lower turn-on voltage than the body diode ensures that current preferentially flows through the Schottky channel, thereby preventing the body diode from participating in conduction.

[0042] Reference Figure 1When a forward bias voltage higher than the threshold voltage is applied to the gate electrode layer 92, inversion occurs on the surface of the second conductivity type base region 73 (P Well) beneath the gate oxide layer 91, forming an N-type conductive channel on one side. Electrons flow from the source metal layer 5, through the first conductivity type source region 75 (N+ Source), the conductive channel, sequentially into the first conductivity type JFET region 72 (N JFET), the first conductivity type carrier storage layer 71 (N CSL), the first conductivity type drift region 4 (N- Drift), the first conductivity type buffer layer 3 (N+ Buffer), and the first conductivity type substrate 2 (N+ Substrate), and finally flow out from the drain metal layer 1. The current direction (hole flow direction) is opposite to the electron flow direction, that is, the current flows from the drain to the source.

[0043] When the gate voltage is zero or negative and a positive voltage is applied to the drain, the depletion region formed by the first and second conductivity type shielding layer 62, the second and second conductivity type shielding layer 74 (P+ Shield), and the first conductivity type drift region 4 (N- Drift) can effectively absorb electric field lines, significantly reduce the electric field peak at the end of the gate oxide layer 91, and protect the gate oxide.

[0044] When the device operates in the third quadrant, i.e., the source potential is higher than the drain potential, the current preferentially conducts through the integrated Schottky diode structure 8 (N+ SBD). Since it is a majority carrier device, there is almost no reverse recovery charge, which greatly reduces reverse recovery loss and associated switching noise.

[0045] This application is particularly applicable to high-frequency power conversion systems that require ultra-fast switching speeds, extremely high power density, and excellent reliability, such as electric drive systems for new energy vehicles, on-board chargers (OBCs), power supplies for data center servers, and photovoltaic energy storage inverters.

[0046] Example 2 Based on the same inventive concept, one embodiment of the present invention provides a method for fabricating a semiconductor device, comprising: S1. Provide a first conductivity type substrate 2; in this embodiment, the first conductivity type substrate 2 is a SiC N+ type substrate (N+ Substrate).

[0047] S2. A first conductivity type buffer layer 3, a first conductivity type drift region 4, and a first conductivity type carrier storage layer 71 are sequentially formed on the substrate 2 of the first conductivity type. A first conductivity type buffer layer 3 (N+ Buffer) is formed on a first conductivity type substrate 2 by epitaxial growth. A first conductivity type drift layer (N- Drift) is formed on the first conductivity type buffer layer 3 by further epitaxial growth. Then, N-ion implantation is performed on the surface of the N-type drift region through an N CSL mask to form a first conductivity type carrier storage layer 71 (NCSL).

[0048] S3, forming a composite shielding structure for the field plate and a Schottky diode structure 8: A groove 61 is formed on the side of the first conductivity type drift region 4 away from the first conductivity type buffer layer 3; On the surface of the first conductivity type drift region 4 away from the buffer layer, a longitudinal trench 61 is formed by photolithography and etching processes (such as ICP etching). The trench 61 extends downward to the middle depth of the first conductivity type drift region 4.

[0049] By using ion implantation, a second type of conductivity impurity (such as aluminum ions) is implanted into the bottom of trench 61 and one sidewall thereon. After activation by high-temperature annealing, a first and second type of conductivity shielding layer 62 is formed. On the other sidewall of trench 61, a Schottky diode structure 8 is formed by selective ion implantation, and rapid thermal annealing is performed to activate the implanted impurities. The trench 61 is filled with doped polysilicon and then etched back to the top of the trench 61 to form the field plate electrode 63.

[0050] S4. Forming a single-sided conductive channel structure: A patterning layer is formed on the side of the first conductivity type drift region 4 away from the first conductivity type buffer layer 3, and photoresist is spin-coated. The photolithography machine is controlled to define the active region pattern combination through a mask, and the active region pattern combination is etched to form a single-sided conductive channel structure in the patterning layer. Specifically, a first conductivity type JFET region 72 is formed on the other side of the trench 61 away from the first and second conductivity type shielding layer 62 by multiple epitaxial growth combined with selective ion implantation.

[0051] On the side of the first conductivity type JFET region 72 away from the first and second conductivity types, a second conductivity type base region 73 (P Well) is formed.

[0052] On the side of the second conductivity type base region 73 away from the first conductivity type JFET region 72, a first conductivity type source region 75 and a second conductivity type contact region 76 are formed sequentially.

[0053] Above the base region 73 of the second conductivity type, a gate oxide layer 91 is formed by thermal oxidation or deposition, followed by deposition and etching of polysilicon to form a gate electrode layer 92. The gate electrode layer 92 is located only above the P-type base region, thus forming a unique single-sided conductive channel.

[0054] S5, deposit interlayer dielectric layer 93, and etch contact holes to achieve electrical connection between source metal layer 5 and source region 75 of first conductivity type, contact region 76 of second conductivity type, Schottky diode structure 8 and field plate electrode 63 in trench 61.

[0055] S6. Deposit Al metal on the top of the chip using a source mask to form a source metal layer 5.

[0056] Specifically, the source metal layer 5 is deposited through an alloying process; during preparation, the source metal layer 5 forms an ohmic contact with the first conductivity type source region 75, the second conductivity type contact region 76, and the field plate electrode 63; the source metal layer 5 forms a Schottky contact with the Schottky diode structure 8 (N+ SBD region).

[0057] S7. An Al metal layer is deposited on the bottom of the chip using a drain mask to form a drain layer.

[0058] Specifically, drain metal is deposited on the back side of the substrate to form an ohmic contact. A passivation layer (such as silicon nitride) is deposited, and electrode windows are etched to complete device fabrication.

[0059] Example 3 This application also provides a power conversion device, which can be a photovoltaic inverter, a wind power converter, an uninterruptible power supply, an on-board charger, or a rail transit traction converter.

[0060] In this embodiment, the power conversion device includes a DC input terminal, an AC output terminal, a power conversion circuit connected between the DC input terminal and the AC output terminal, and a control unit. The power conversion circuit includes at least one semiconductor device as described in Embodiment 1. A field plate composite shielding structure and a Schottky diode structure 8 are formed on one side of the base region in the semiconductor device cell, and a single-sided conductive channel structure is formed on the other side. The source metal layer 5 of the semiconductor device forms an ohmic contact with the single-sided conductive channel structure, and the Schottky diode structure 8 forms a Schottky contact with the source metal layer 5. The field plate composite shielding structure is used to modulate the electric field distribution in the drift region of the semiconductor device when the device is subjected to high voltage. The specific structure of the semiconductor device has been described in detail above, and for the sake of brevity, it will not be repeated here.

[0061] The control unit is electrically connected to the gate electrode layer of the semiconductor device and outputs a PWM control signal to control the turn-on and turn-off of the semiconductor device. The field plate composite shielding structure, Schottky diode structure, and single-sided conductive channel structure are integrated into the same cell. On the one hand, the field plate composite shielding structure effectively modulates the electric field in the drift region when the device is subjected to high voltage, suppressing electric field spikes at the gate oxide end and improving the device's withstand voltage and long-term gate oxide reliability. On the other hand, the single-sided conductive channel structure physically eliminates the redundant gate-drain overlap region in traditional symmetrical channels, significantly reducing Miller capacitance, increasing switching speed, and reducing switching losses. Simultaneously, the integrated Schottky diode structure provides a majority carrier transport path for reverse freewheeling, with almost no reverse recovery charge, fundamentally solving the problems of high reverse recovery loss and electromagnetic interference in body diodes. Therefore, the operational reliability and power conversion efficiency of the power conversion equipment under high voltage and high frequency conditions are comprehensively improved.

[0062] Specifically, the power conversion circuit can be any one of a half-bridge circuit, a full-bridge circuit, a three-phase full-bridge inverter circuit, a multi-level inverter circuit, or a DC-DC conversion circuit; preferably, it can be a half-bridge power module or inverter.

[0063] To facilitate understanding by those skilled in the art, the location and function of SiC MOSFET devices will be further explained below using a half-bridge inverter circuit as an example.

[0064] Figure 2 This is a schematic diagram of the topology of the half-bridge inverter circuit of the present invention. Figure 2 As shown, the half-bridge inverter circuit includes a DC input terminal (V... DC + and V DC -), AC output terminal (AC Out) and upper bridge arm switch Q1 and lower bridge arm switch Q2 connected in series between the positive and negative terminals of DC input terminal.

[0065] The upper bridge arm switch Q1 and / or the lower bridge arm switch Q2 adopt the semiconductor device structure described in Embodiment 1. Specifically, the half-bridge circuit also includes a gate control unit (Controller), and the PWM signal output by the control unit is connected to the gate electrode layer 92 of the upper bridge arm switch Q1 and the lower bridge arm switch Q2, respectively.

[0066] Reference Figure 2 In this embodiment, the drain of the upper bridge arm switch Q1 is connected to the DC input terminal V. DC +Connection: The source of the upper bridge arm switch Q1 is connected to the drain of the lower bridge arm switch Q2, and the source of the lower bridge arm switch Q2 is connected to the DC input terminal V. DC- Connection: The AC output terminal (AC Out) is connected between the source of the upper bridge arm switch Q1 and the drain of the lower bridge arm switch Q2; the first signal output terminal of the control unit is communicatively connected to the gate of the upper bridge arm switch Q1, and the second signal output terminal of the control unit is communicatively connected to the gate of the lower bridge arm switch Q2; during operation, the control unit controls Q1 and Q2 to conduct alternately through the PWM signal, converting the DC bus voltage into a high-frequency AC square wave voltage output.

[0067] In the description of this specification, the references to terms such as "an embodiment," "some embodiments," "example," "specific example," "a implementation," "a preferred implementation," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the present invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0068] Although embodiments of the invention have been shown and described, those skilled in the art will understand that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of the invention, the scope of which is defined by the claims and their equivalents.

Claims

1. A power conversion device, characterized in that, It includes a DC input terminal, an AC output terminal, a power conversion circuit connected between the DC input terminal and the AC output terminal, and a control unit. The power conversion circuit includes at least one semiconductor device, which includes, from bottom to top, a drain metal layer (1), a first conductivity type substrate (2), a first conductivity type buffer layer (3), a first conductivity type drift region (4), and a source metal layer (5). It also includes a field plate composite shielding structure, a single-sided conductive channel structure and a Schottky diode structure (8) formed on the side of the first conductivity type drift region (4) away from the first conductivity type buffer layer (3), and the source metal layer (5) forms an ohmic contact with the single-sided conductive channel structure; A groove (61) is provided on the side of the first conductivity type drift region (4) away from the first conductivity type buffer layer (3), and the groove (61) extends downward to the middle section of the first conductivity type drift region (4); The field plate composite shielding structure includes a first and second conductivity type shielding layer (62), which is formed at the bottom of the trench (61) and on the sidewall of one side of the trench (61); The trench (61) is filled with polycrystalline silicon to form a field plate electrode (63), which is electrically connected to the source metal layer (5). The Schottky diode structure (8) is disposed on the sidewall of the trench (61) away from the first and second conductivity type shielding layer (62), and the Schottky diode structure (8) forms a Schottky contact with the source metal layer (5); The single-sided conductive channel structure is disposed on the side of the trench (61) away from the Schottky diode structure (8). The single-sided conductive channel structure includes a first conductive type carrier storage layer (71) and a first conductive type JFET region (72) disposed sequentially on the first conductive type drift region (4). One side of the first conductive type JFET region (72) is in contact with the first and second conductive type shielding layers (62). The single-sided conductive channel structure also includes a second conductivity type base region (73), which is formed on the side of the first conductivity type JFET region (72) away from the first and second conductivity type shielding layers (62); A gate oxide layer (91) and a gate electrode layer (92) are sequentially formed on the side of the base region (73) of the second conductivity type away from the carrier storage layer (71) of the first conductivity type. The source metal layer (5) and the gate electrode layer (92) are electrically isolated; The control unit is electrically connected to the gate electrode layer (92) of the semiconductor device and is used to output a PWM control signal to control the turn-on and turn-off of the semiconductor device.

2. A semiconductor device, applied to the power conversion equipment of claim 1, characterized in that, It includes, from bottom to top, a drain metal layer (1), a first conductivity type substrate (2), a first conductivity type buffer layer (3), a first conductivity type drift region (4), and a source metal layer (5). It also includes a field plate composite shielding structure, a single-sided conductive channel structure and a Schottky diode structure (8) formed on the side of the first conductivity type drift region (4) away from the first conductivity type buffer layer (3), and the source metal layer (5) forms an ohmic contact with the single-sided conductive channel structure; A groove (61) is provided on the side of the first conductivity type drift region (4) away from the first conductivity type buffer layer (3), and the groove (61) extends downward to the middle section of the first conductivity type drift region (4); The field plate composite shielding structure includes a first and second conductivity type shielding layer (62), which is formed at the bottom of the trench (61) and on the sidewall of one side of the trench (61); The trench (61) is filled with polycrystalline silicon to form a field plate electrode (63), which is electrically connected to the source metal layer (5). The Schottky diode structure (8) is disposed on the sidewall of the trench (61) away from the first and second conductivity type shielding layer (62), and the Schottky diode structure (8) forms a Schottky contact with the source metal layer (5); The single-sided conductive channel structure is disposed on the side of the trench (61) away from the Schottky diode structure (8). The single-sided conductive channel structure includes a first conductive type carrier storage layer (71) and a first conductive type JFET region (72) disposed sequentially on the first conductive type drift region (4). One side of the first conductive type JFET region (72) is in contact with the first and second conductive type shielding layers (62). The single-sided conductive channel structure also includes a second conductivity type base region (73), which is formed on the side of the first conductivity type JFET region (72) away from the first and second conductivity type shielding layers (62); A gate oxide layer (91) and a gate electrode layer (92) are sequentially formed on the side of the base region (73) of the second conductivity type away from the carrier storage layer (71) of the first conductivity type. The source metal layer (5) and the gate electrode layer (92) are electrically isolated.

3. The semiconductor device as described in claim 2, characterized in that, A second conductivity type shielding layer (74) is formed between the second conductivity type base region (73) and the first conductivity type carrier storage layer (71). A first conductivity type source region (75) and a second conductivity type contact region (76) are formed sequentially on the side of the second conductivity type base region (73) away from the first conductivity type JFET region (72). The second conductivity type base region (73), the first conductivity type source region (75), and the second conductivity type contact region (76) are all arranged side by side on the side of the second conductivity type shielding layer (74) away from the first conductivity type carrier storage layer (71).

4. The semiconductor device as described in claim 3, characterized in that, The source metal layer (5) is simultaneously electrically connected to the first conductivity type source region (75), the second conductivity type contact region (76), the Schottky diode structure (8), and the field plate electrode (63) in the trench (61).

5. The semiconductor device as described in claim 3, characterized in that, An interlayer dielectric layer (93) is formed between the source metal layer (5) and the gate electrode layer (92). The source metal layer (5) and the gate electrode layer (92) are electrically isolated by the interlayer dielectric layer (93). The source metal layer (5) forms an ohmic contact with the second conductivity type contact region (76) and the first conductivity type source region (75) through the contact hole in the interlayer dielectric layer (93).

6. The semiconductor device as claimed in claim 3, characterized in that, The doping concentration of impurity atoms in the first second conductivity type shielding layer (62) is higher than that in the second conductivity type base region (73), and the doping concentration of impurity atoms in the second second conductivity type shielding layer (74) is higher than that in the second conductivity type base region (73).

7. The semiconductor device according to any one of claims 2 to 6, characterized in that, The gate oxide layer (91) is in contact with both the first conductivity type JFET region (72) and the second conductivity type base region (73).

8. The semiconductor device according to any one of claims 2 to 6, characterized in that, The doping concentration of impurity atoms in the first conductivity type substrate (2) is higher than that in the first conductivity type buffer layer (3), and the doping concentration of impurity atoms in the first conductivity type buffer layer (3) is higher than that in the first conductivity type drift layer; the doping concentration of the first conductivity type carrier storage layer (71) is higher than that in the first conductivity type drift layer.

9. The semiconductor device according to any one of claims 2 to 6, characterized in that, The first conductivity type is N-type, the second conductivity type is P-type, and the Schottky diode structure (8) is an N+ type Schottky barrier diode.

10. A method for fabricating a semiconductor device, used to fabricate the semiconductor device according to any one of claims 2 to 9, characterized in that, include: Provide a substrate of the first conductivity type (2); A first conductivity type buffer layer (3) and a first conductivity type drift region (4) are sequentially formed on top of a first conductivity type substrate (2); A groove (61) is provided on the side of the first conductivity type drift region (4) away from the first conductivity type buffer layer (3); By means of ion implantation, a second type of impurity is implanted into the bottom of the trench (61) and one sidewall therein to form a first and second type of shielding layer (62); on the other sidewall of the trench (61), a Schottky diode structure (8) is formed by selective ion implantation. The trench (61) is filled with doped polysilicon and etched back to the top of the trench (61) to form the field plate electrode (63); A patterning layer is formed on the side of the first conductivity type drift region (4) away from the first conductivity type buffer layer (3), and photoresist is spin-coated. The photolithography machine is controlled to define the active region pattern combination through a mask, and the active region pattern combination is etched to form a single-sided conductive channel structure in the patterning layer. Deposit an interlayer dielectric layer (93) and etch contact holes to achieve electrical connection between the source metal layer (5) and the first conductivity type source region (75), the second conductivity type contact region (76), the Schottky diode structure (8), and the field plate electrode (63) in the trench (61); Al metal is deposited on the top of the chip using a source mask to form a source metal layer (5); An Al metal layer is deposited on the bottom of the chip using a drain mask to form a drain metal layer (1).

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