Semiconductor structure and method of manufacturing the same, chip

Abstract

This disclosure provides a semiconductor structure, its fabrication method, and a chip, relating to the field of semiconductor chip technology, to improve capacitor performance. The semiconductor structure includes a substrate, a support structure, and a capacitor structure. The support structure is disposed on the substrate and includes at least one stacked portion. The stacked portion includes a first blocking portion and a first insulating portion. The first insulating portion is disposed on the side of the first blocking portion near the substrate and is recessed relative to the first blocking portion. A first groove is formed between the stacked portion adjacent to the substrate and the substrate. The capacitor structure includes a first electrode, a dielectric layer, and a second electrode. The first electrode, dielectric layer, and second electrode sequentially cover the surface of the support structure and the inner wall of the first groove near the substrate, and the portion of the capacitor structure located within the first groove forms a second groove. This semiconductor structure is used in a chip.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor chip technology, and in particular to a semiconductor structure, its fabrication method, and a chip. Background Technology

[0002] Passive components such as capacitors, resistors, and inductors are required in integrated circuit design. Capacitors typically employ either a metal-insulator-metal (MIM) structure or a metal-oxide-metal (MOM) structure. MIM structures are widely used because they offer higher capacitance density.

[0003] However, the increasing demand for highly integrated integrated circuits has led to limitations in the design size of capacitor structures. Consequently, the capacitance density of capacitors decreases as the design size shrinks, which in turn reduces the performance of the capacitors. Summary of the Invention

[0004] This disclosure provides a semiconductor structure, its fabrication method, and a chip to improve capacitor performance.

[0005] In a first aspect, a semiconductor structure is provided, including a substrate, a support structure, and a capacitor structure. The support structure is disposed on the substrate and includes at least one stacked portion. The stacked portion includes a first blocking portion and a first insulating portion. The first insulating portion is disposed on the side of the first blocking portion near the substrate and is recessed relative to the first blocking portion. A first groove is formed between the stacked portion adjacent to the substrate and the substrate. The capacitor structure includes a first electrode, a dielectric layer, and a second electrode. The first electrode, the dielectric layer, and the second electrode sequentially cover the surface of the support structure and the inner wall of the first groove near the substrate. The portion of the capacitor structure located within the first groove forms a second groove.

[0006] In this configuration, the portion of the capacitor structure located within the first groove has an overlapping orthographic projection onto the substrate. That is, the overlapping portions of the capacitor structure's orthographic projections on the substrate share the same area. This allows for an increase in the facing area of ​​the first and second plates in the capacitor structure without increasing the area occupied by the capacitor structure on the substrate, thereby increasing the capacitance density and improving the performance of the capacitor structure.

[0007] In some embodiments, the support structure includes a plurality of stacked portions; two adjacent first blocking portions and corresponding first insulating portions form a third groove; and the portion of the capacitor structure located within the third groove forms a fourth groove.

[0008] In some embodiments, the depths of the second groove and the fourth groove are 150 nm to 180 nm.

[0009] In some embodiments, the capacitor structure includes a first portion and a second portion connected together, the first portion covering the surface of the support structure, and the second portion at least covering the inner wall of the first groove near the substrate. In a projected image onto the substrate, the second portion extends beyond the first portion; and in the portion of the second portion extending beyond the first portion, the first electrode extends beyond the dielectric layer and the second electrode.

[0010] In some embodiments, in the portion of the second portion that extends beyond the first portion, the orthographic projection of the dielectric layer on the substrate coincides with the orthographic projection of the second electrode on the substrate.

[0011] In some embodiments, the semiconductor structure further includes a second insulating layer, a first contact plug, and a second contact plug. The second insulating layer is disposed on the side of the capacitor structure away from the support structure and fills the second groove and the fourth groove. The first contact plug penetrates the second insulating layer and contacts the first electrode plate. The second contact plug penetrates the second insulating layer and contacts the second electrode plate.

[0012] In some embodiments, the semiconductor structure includes a plurality of the support structures, and in the capacitor structure covering the plurality of support structures, the first electrode plate is integrally formed.

[0013] In some embodiments, the semiconductor structure further includes a second barrier layer disposed between the substrate and the support structure; a second portion of the capacitor structure covers the second barrier layer.

[0014] In a second aspect, a chip is provided, comprising a semiconductor structure as described in the above embodiments.

[0015] The chip provided in the second aspect has the same structure and beneficial technical effects as the semiconductor structure provided in the first aspect, and will not be described in detail here.

[0016] Thirdly, a method for fabricating a semiconductor structure is provided, for fabricating the semiconductor structure as provided in the first aspect. The fabrication method includes:

[0017] Provide substrate.

[0018] A support structure is formed on the substrate, the support structure including at least one stacked portion, the stacked portion including a first blocking portion and a first insulating portion; the first insulating portion is disposed on the side of the first blocking portion close to the substrate, and the first insulating portion is recessed relative to the first blocking portion; a first groove is formed between the stacked portion adjacent to the substrate and the substrate.

[0019] A capacitor structure is formed, the capacitor structure including a first electrode, a dielectric layer and a second electrode, the first electrode, the dielectric layer and the second electrode sequentially covering the surface of the support structure and the inner wall of the first groove near the substrate, and the portion of the capacitor structure located in the first groove forms a second groove.

[0020] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and do not limit this application. Attached Figure Description

[0021] To more clearly illustrate the technical solutions in this disclosure, the accompanying drawings used in some embodiments of this disclosure will be briefly described below. Obviously, the drawings described below are only drawings of some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings. In addition, the drawings described below can be regarded as schematic diagrams and are not intended to limit the actual size of the product, the actual process of the method, etc. involved in the embodiments of this disclosure.

[0022] Figure 1 A block diagram of a chip according to some embodiments;

[0023] Figure 2 This is a structural diagram of a semiconductor structure according to some embodiments;

[0024] Figure 3 This is a structural diagram of yet another semiconductor structure according to some embodiments;

[0025] Figures 4-6 This is a flowchart of a method for fabricating a semiconductor structure according to some embodiments;

[0026] Figures 7-12 This is a structural diagram corresponding to each step in a method for fabricating a semiconductor structure according to some embodiments. Detailed Implementation

[0027] The technical solutions in some embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments provided in this disclosure are within the scope of protection of this disclosure.

[0028] Unless the context otherwise requires, throughout the specification and claims, the term "comprise" and its other forms, such as the third-person singular "comprises" and the present participle "comprising," are interpreted as open-ended and encompassing, meaning "including, but not limited to." In the description of the specification, terms such as "one embodiment," "some embodiments," "exemplary embodiments," "example," "specific example," or "some examples," etc., are intended to indicate that a particular feature, structure, material, or characteristic associated with that embodiment or example is included in at least one embodiment or example of this disclosure. The illustrative representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics mentioned may be included in any suitable manner in any one or more embodiments or examples.

[0029] Hereinafter, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of embodiments of this disclosure, unless otherwise stated, "a plurality of" means two or more.

[0030] In describing some embodiments, the term "connection" and its derivative expressions may be used. The term "connection" should be interpreted broadly; for example, "connection" can be a mechanical connection or an electrical connection; it can be a fixed connection or a detachable connection, or an integral connection; it can be a direct connection or an indirect connection through an intermediate medium; it can be a connection within two components. Those skilled in the art will understand the specific meaning of the above terms herein based on the specific circumstances.

[0031] "A and / or B" includes the following three combinations: A only, B only, and a combination of A and B.

[0032] As used herein, “parallel,” “perpendicular,” and “equal” include the described situation and situations that are similar to the described situation, within an acceptable range of deviation, which is determined by those skilled in the art taking into account the measurement under discussion and the error associated with the measurement of a particular quantity (i.e., the limitations of the measurement system). For example, “parallel” includes absolute parallelism and approximate parallelism, where an acceptable range of deviation for approximate parallelism may be, for example, within 5°; “perpendicular” includes absolute perpendicularity and approximate perpendicularity, where an acceptable range of deviation for approximate perpendicularity may also be, for example, within 5°; “equal” includes absolute equality and approximate equality, where an acceptable range of deviation for approximate equality may be, for example, a difference between the two equals being less than or equal to 5% of either one.

[0033] In this disclosure, terms such as “down,” “below,” “above,” and “up” are used to explain the relationships between components shown in the accompanying drawings. The terms may be relative concepts and described based on the directions shown in the drawings, or based on the sequence of process steps, but are not limited thereto.

[0034] This document describes exemplary embodiments with reference to cross-sectional views and / or plan views, which are idealized exemplary drawings. In the drawings, the thickness of layers and the area of ​​regions are enlarged for clarity. Therefore, variations in shape relative to the drawings are contemplated due to, for example, manufacturing techniques and / or tolerances. Thus, exemplary embodiments should not be construed as being limited to the shapes of the regions shown herein, but rather include shape deviations due to, for example, manufacturing processes. For example, etched areas shown as rectangular would typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to show the actual shapes of the areas of the device, nor are they intended to limit the scope of the exemplary embodiments.

[0035] like Figure 1 As shown, some embodiments of this disclosure provide a chip 1000 that can be applied to and packaged into different types of electronic products. Examples include mobile phones (e.g., cell phones), desktop computers, tablets, laptops, servers, in-vehicle devices, game consoles, printers, positioning devices, wearable devices, smart sensors, power banks, virtual reality (VR) devices, augmented reality (AR) devices, and other electronic devices.

[0036] The chip 1000 may include at least one of a processor 200, a memory 300, and a controller 400. Furthermore, the chip 1000 may also include a cache, etc., but this disclosure does not specifically limit its inclusion in these embodiments.

[0037] It should be noted that processor 200 is used to interpret computer instructions from electronic devices and process data in computer software. This processor 200 may be, for example, a Central Processing Unit (CPU). Memory 300 is used to store the code of computer programs and provide space for exchanging data between running programs. Controller 400 is used to manage the data stored in memory 300 and to communicate with external devices (e.g., a host computer).

[0038] In some embodiments, such as Figure 2 As shown, chip 1000 includes semiconductor structure 100. Semiconductor structure 100 includes substrate 10 and capacitor structure 30. Capacitor structure 30 includes a first electrode 31, a dielectric layer 32 and a second electrode 33, wherein the first electrode 31, dielectric layer 32 and second electrode 33 are arranged in a direction that moves away from substrate 10 in sequence.

[0039] It should be noted that the material of the substrate 10 includes at least one of silicon (Si), germanium (Ge), silicon germanide (SiGe), silicon carbide (SiC), and gallium arsenide (GaAs).

[0040] In related technologies, the increasing demand for highly integrated chips has led to limitations in the design size of capacitor structures. Consequently, the capacitance density of capacitor structures decreases as the design size shrinks, resulting in reduced performance of the capacitor structures.

[0041] Based on this, such as Figure 2 As shown, some embodiments of the semiconductor structure 100 provided in this disclosure further include a support structure 20, which is disposed on a substrate 10. The support structure 20 includes at least one stacked portion 21, which includes a first blocking portion 22 and a first insulating portion 23. The first insulating portion 23 is disposed on the side of the first blocking portion 22 near the substrate 10, and the first insulating portion 23 is recessed relative to the first blocking portion 22. A first groove 24 is formed between the stacked portion 21 adjacent to the substrate 10 and the substrate 10. The capacitor structure 30 includes a first electrode 31, a dielectric layer 32, and a second electrode 33. The first electrode 31, the dielectric layer 32, and the second electrode 33 sequentially cover the surface of the support structure 20 and the inner wall of the first groove 24 near the substrate 10, and the portion of the capacitor structure 30 located in the first groove 24 forms a second groove 34.

[0042] In this configuration, the portion of the capacitor structure 30 located within the first groove 24 has an overlapping orthographic projection on the substrate 10. That is, the overlapping portions of the orthographic projections of the capacitor structure 30 on the substrate 10 jointly occupy the same area on the substrate 10. This allows for an increase in the facing area of ​​the first electrode 31 and the second electrode 33 in the capacitor structure 30 without increasing the area occupied by the capacitor structure 30 on the substrate 10, thereby increasing the capacitance density of the capacitor structure 30 and improving its performance.

[0043] It should be noted that capacitance density refers to the capacitance per unit volume or unit area. Capacitance density is an important indicator for measuring the charge storage capacity of the capacitor structure 30, and it can intuitively reflect the efficiency of the capacitor structure 30 in storing charge within a limited space.

[0044] In some examples, the material of the first blocking portion 22 includes silicon nitride and / or silicon carbonitride. The material of the first insulating portion 23 includes silicon oxide. The material of the dielectric layer 32 includes at least one of hafnium oxide, zirconium oxide, and aluminum oxide. The materials of the first electrode 31 and the second electrode 33 include at least one of titanium nitride, tantalum nitride, and tantalum.

[0045] In some embodiments, such as Figure 2 As shown, the support structure 20 includes multiple stacked portions 21. Two adjacent first blocking portions 22 and corresponding first insulating portions 23 form a third groove 25. The portion of the capacitor structure 30 located within the third groove 25 forms a fourth groove 35. The corresponding first insulating portion 23 refers to the first insulating portion 23 between two adjacent first blocking portions 22.

[0046] In this configuration, the portion of capacitor structure 30 located within the third groove 25 also overlaps in its orthographic projection onto the substrate 10. In other words, this allows for a further increase in the facing area of ​​the first electrode 31 and the second electrode 33 within capacitor structure 30 without increasing the area occupied by capacitor structure 30 on substrate 10, while ensuring that the orthographic projections of the portion of capacitor structure 30 located within the first groove 24 overlap on substrate 10. This further increases the capacitance density of capacitor structure 30 and improves its performance.

[0047] In some examples, such as Figure 2 As shown, the support structure 20 includes three stacked portions 21, two adjacent first blocking portions 22 and corresponding first insulating portions 23 form a third groove 25, and the portion of the capacitor structure 30 located in the third groove 25 forms a fourth groove 35.

[0048] In some examples, the support structure 20 includes four stacked portions 21, two adjacent first blocking portions 22 and corresponding first insulating portions 23 form a third groove 25, and the portion of the capacitor structure 30 located in the third groove 25 forms a fourth groove 35.

[0049] It should be noted that the support structure 20 may also include 5, 6 or more stacked parts 21. This disclosure does not impose specific limitations, as long as the design concept is the same.

[0050] In some embodiments, the depths of the second groove 34 and the fourth groove 35 are 150 nm to 180 nm. For example, the depth of the second groove 34 is any one of 150 nm, 155 nm, 160 nm, 170 nm, 175 nm, or 180 nm. The depth of the fourth groove 35 is any one of 150 nm, 155 nm, 160 nm, 170 nm, 175 nm, or 180 nm.

[0051] In some embodiments, such as Figure 2 As shown, the capacitor structure 30 includes a first portion 30a and a second portion 30b connected to each other. The first portion 30a covers the surface of the support structure 20, and the second portion 30b at least covers the inner wall of the first groove 24 near the substrate 10. In a normal projection onto the substrate, the second portion 30b extends beyond the first portion 30a, and in the portion of the second portion 30b that extends beyond the first portion 30a, the first electrode 31 extends beyond the dielectric layer 32 and the second electrode 33.

[0052] In some embodiments, such as Figure 2 As shown, in the portion of the second part 30b that extends beyond the first part 30a, the orthographic projection of the dielectric layer 32 on the substrate 10 coincides with the orthographic projection of the second electrode 33 on the substrate 10. It should be noted that this structure can be fabricated using a single photoresist exposure and development process, followed by etching of the dielectric layer 32 and the second electrode 33. For details, please refer to the fabrication method described below; further elaboration will not be repeated here.

[0053] In this case, it is possible to perform a photoresist exposure and development process, and then etch the dielectric layer 32 and the second electrode 33 separately, thereby saving an exposure and development process, reducing production costs, and improving production efficiency.

[0054] In other embodiments, in the portion of the second portion 30b that extends beyond the first portion 30a, the orthogonal projection of the dielectric layer 32 onto the substrate 10 extends beyond the orthogonal projection of the second electrode 33 onto the substrate 10.

[0055] In some embodiments, such as Figure 2As shown, the semiconductor structure 100 further includes a second insulating layer 40, a first contact plug 51, and a second contact plug 52. The second insulating layer 40 is disposed on the side of the capacitor structure 30 away from the support structure 20 and fills the second groove 34 and the fourth groove 35. The first contact plug 51 penetrates the second insulating layer 40 and contacts the first electrode plate 31. The second contact plug 52 penetrates the second insulating layer 40 and contacts the second electrode plate 33.

[0056] In some examples, such as Figure 2 As shown, the second insulating layer 40 also contacts the dielectric layer 32 of the second portion 30b and the side of the end of the second electrode plate 33.

[0057] The materials of the first contact plug 51 and the second contact plug 52 include metals, for example, the materials of the first contact plug 51 and the second contact plug 52 include at least one of copper (Cu), tungsten (W) and titanium nitride (TiN).

[0058] In some embodiments, such as Figure 2 As shown, the semiconductor structure 100 further includes a second barrier layer 60, which is disposed between the substrate 10 and the support structure 20. The second portion 30b of the capacitor structure 30 covers the second barrier layer 60. The second barrier layer 60 is used to prevent the first electrode 31 from diffusing into the substrate 10, thereby avoiding leakage.

[0059] The material of the second barrier layer 60 includes silicon nitride (SiN) and / or silicon carbonitride (SiCN).

[0060] In some embodiments, such as Figure 3 As shown, the semiconductor structure 100 includes multiple support structures 20, and in the capacitor structure 30 covering the multiple support structures 20, the first electrode 31 is integrally formed. In this case, a continuous and uniform first electrode film can be formed on the support structures 20 by processes such as chemical vapor deposition or physical vapor deposition. This avoids interface defects caused by splicing, such as gaps and unevenness, thereby improving the stability of the capacitor structure 30. At the same time, it can also avoid splicing interfaces between the first electrodes 31 of adjacent capacitor structures 30, thereby reducing contact resistance and thus reducing the energy loss of the capacitor structure 30.

[0061] In some embodiments, the shape of the orthographic projection of the capacitor structure 30 onto the substrate 10 includes any one of a rectangle, a circle, and an ellipse.

[0062] Some embodiments of this disclosure also provide a method for fabricating a semiconductor structure, such as... Figure 4 As shown, the preparation method includes steps S100 to S300.

[0063] S100: Provides substrate 10.

[0064] In the above steps, the substrate 10 is made of at least one of silicon (Si), germanium (Ge), silicon germanide (SiGe), silicon carbide (SiC), and gallium arsenide (GaAs).

[0065] S200: A support structure 20 is formed on the substrate 10.

[0066] In the above steps, such as Figure 9 As shown, the support structure 20 includes at least one stacked portion 21. The stacked portion 21 includes a first blocking portion 22 and a first insulating portion 23. The first insulating portion 23 is disposed on the side of the first blocking portion 22 close to the substrate 10, and the first insulating portion 23 is recessed relative to the first blocking portion 22. A first groove 24 is formed between the stacked portion 21 adjacent to the substrate 10 and the substrate 10.

[0067] S300: Forms a capacitor structure 30.

[0068] In the above steps, such as Figure 11 As shown, the capacitor structure 30 includes a first electrode 31, a dielectric layer 32, and a second electrode 33. The first electrode 31, the dielectric layer 32, and the second electrode 33 sequentially cover the surface of the support structure 20 and the inner wall of the first groove 24 near the substrate 10, and the portion of the capacitor structure 30 located in the first groove 24 forms a second groove 34.

[0069] In some embodiments, such as Figure 5 As shown, in S200, the preparation method includes S210 to S230.

[0070] S210: At least one stacked layer 211 is formed on the substrate 10.

[0071] In the above steps, such as Figure 7 As shown, a first insulating layer 231 and a first barrier layer 221 are sequentially formed on a substrate 10 through a deposition process, and at least one stacked layer 211 is repeatedly formed. The thickness of the first insulating layer 231 ranges from 500 nm to 800 nm, and the thickness of the first barrier layer 221 ranges from 50 nm to 80 nm. The material of the first insulating layer 231 includes silicon oxide. The material of the first barrier layer 221 includes silicon nitride and / or silicon carbonitride.

[0072] S220: A first mask layer 11 is formed on the stacked layer 211, and an initial stacked portion 212 is formed using the first mask layer 11 as a mask.

[0073] In the above steps, such as Figure 8As shown, the first mask layer 11 is, for example, a photoresist layer with openings, through which the stacked layers exposed within the openings are etched to form an initial stacked portion 212. The initial stacked portion 212 includes an initial first insulating portion 232 and an initial first blocking portion 222.

[0074] S230: Forming a supporting structure 20.

[0075] In the above steps, such as Figure 8 and Figure 9 As shown, in a direction parallel to the plane of the substrate 10, the initial first insulating portion 232 in the initial stacked portion 212 is etched using a wet etching process to a depth ranging from 150 nm to 180 nm, forming a first insulating portion 23 and a first blocking portion 22, such that the first insulating portion 23 is recessed relative to the first blocking portion 22. A first groove 24 is formed between the stacked portion 21 adjacent to the substrate 10 and the substrate 10, and two adjacent first blocking portions 22 and their corresponding first insulating portions 23 form a third groove 25.

[0076] In some embodiments, such as Figure 6 As shown, in S300, the preparation method includes S310 to S320.

[0077] S310: Forms the initial capacitor structure 301.

[0078] In the above steps, such as Figure 10 As shown, the initial capacitor structure 301 includes a first portion 30a and a second initial portion 301b connected to each other. The first portion 30a covers the surface of the support structure 20, and the second initial portion 301b covers at least the inner wall of the first groove 24 near the substrate 10.

[0079] Specifically, S310 may include: sequentially depositing a first electrode film 311, a dielectric layer film 321, and a second electrode film 331 on the inner wall of the support structure 20 and the first groove 24 near the substrate 10. The thicknesses of the first electrode film 311, the dielectric layer film 321, and the second electrode film 331 range from 10 nm to 50 nm. The dielectric layer film 321 is made of at least one of hafnium oxide, zirconium oxide, and aluminum oxide. The materials of the first electrode film 311 and the second electrode film 331 include at least one of titanium nitride, tantalum nitride, and tantalum.

[0080] S320: A second mask layer is formed on the second initial portion, and the second portion 30b is formed using the second mask layer as a mask.

[0081] In the above steps, such as Figure 11As shown, in the orthographic projection onto the substrate 10, the second portion 30b extends beyond the first portion 30a, and in the portion of the second portion 30b that extends beyond the first portion 30a, the first electrode 31 extends beyond the dielectric layer 32 and the second electrode 33.

[0082] S320 may specifically include: the second mask layer may be a photoresist layer with an opening, and the second electrode film and the dielectric layer film exposed in the opening are etched in sequence to form the first electrode 31, the dielectric layer 32 and the second electrode 33, that is, to form the second part 30b.

[0083] In some embodiments, the preparation method further includes S400 after S300.

[0084] S400: Forming a second insulating layer 40, a first contact plug 51, and a second contact plug 52.

[0085] In the above steps, such as Figure 12 As shown, the second insulating layer 40 is disposed on the side of the capacitor structure 30 away from the support structure 20, and fills the second groove 34 and the fourth groove 35. The first contact plug 51 penetrates the second insulating layer 40 and contacts the first electrode plate 31. The second contact plug 52 penetrates the second insulating layer 40 and contacts the second electrode plate 33.

[0086] Specifically, S400 may include: forming a second insulating layer 40 on the surface of the capacitor structure 30 through a deposition process; then etching the second insulating layer 40 to form a first sub-groove and a second sub-groove; forming a first contact plug 51 in the first sub-groove through a deposition process; and forming a second contact plug 52 in the second sub-groove through a deposition process.

[0087] In some embodiments, the preparation method further includes S110 between S100 and S200.

[0088] S110: Form the second barrier layer 60.

[0089] In the above steps, such as Figure 9 and Figure 11 As shown, a second barrier layer 60 is disposed between the substrate 10 and the support structure 20, and the second portion 30b of the capacitor structure 30 covers the second barrier layer 60. The material of the second barrier layer 60 includes silicon nitride (SiN) and / or silicon carbonitride (SiCN).

[0090] S110 may specifically include: forming a second barrier layer 60 on the substrate 10 by a deposition process.

[0091] In the description of this specification, specific features, structures, materials, or characteristics may be combined in any suitable manner in one or more embodiments or examples.

[0092] The above are merely specific embodiments of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A semiconductor structure, characterized by, include: Substrate; A support structure is disposed on the substrate; the support structure includes at least one stacked portion, the stacked portion including a first blocking portion and a first insulating portion; The first insulating portion is disposed on the side of the first blocking portion near the substrate, and the first insulating portion is recessed relative to the first blocking portion; a first groove is formed between the stacked portion adjacent to the substrate and the substrate; A capacitor structure includes a first electrode plate, a dielectric layer, and a second electrode plate. The first electrode plate, the dielectric layer, and the second electrode plate sequentially cover the surface of the support structure and the inner wall of the first groove near the substrate. The portion of the capacitor structure located within the first groove forms a second groove.

2. The semiconductor structure of claim 1, wherein, The support structure includes multiple stacked portions; two adjacent first blocking portions and the corresponding first insulating portions form a third groove; the portion of the capacitor structure located within the third groove forms a fourth groove.

3. The semiconductor structure of claim 2, wherein, The depths of the second and fourth grooves are 150 nm to 180 nm.

4. The semiconductor structure of claim 2, wherein, The capacitor structure includes a first part and a second part connected to each other, the first part covering the surface of the support structure, and the second part at least covering the inner wall of the first groove near the substrate; In a projected image onto the substrate, the second portion extends beyond the first portion; Furthermore, in the portion of the second part that extends beyond the first part, the first electrode extends beyond the dielectric layer and the second electrode.

5. The semiconductor structure of claim 4, wherein, In the portion of the second part that extends beyond the first part, the orthographic projection of the dielectric layer on the substrate coincides with the orthographic projection of the second electrode on the substrate.

6. The semiconductor structure of claim 2, wherein, Also includes: A second insulating layer is disposed on the side of the capacitor structure away from the support structure, and fills the second groove and the fourth groove; The first contact plug penetrates the second insulating layer and is in contact with the first electrode plate; The second contact plug penetrates the second insulating layer and contacts the second electrode plate.

7. The semiconductor structure of claim 1, wherein, The capacitor structure includes multiple support structures, and the first electrode plate is integrally formed in the capacitor structure covering the multiple support structures.

8. The semiconductor structure of claim 1, wherein, Also includes: A second barrier layer is disposed between the substrate and the support structure; The second part of the capacitor structure covers the second barrier layer.

9. A chip, characterized by Includes the semiconductor structure as described in any one of claims 1 to 8.

10. A method of fabricating a semiconductor structure, characterized by, For preparing the semiconductor structure as described in any one of claims 1 to 8, comprising: Provide substrate; A support structure is formed on the substrate, the support structure including at least one stacked portion, the stacked portion including a first blocking portion and a first insulating portion; the first insulating portion is disposed on the side of the first blocking portion close to the substrate, and the first insulating portion is recessed relative to the first blocking portion; a first groove is formed between the stacked portion adjacent to the substrate and the substrate; A capacitor structure is formed, the capacitor structure including a first electrode, a dielectric layer and a second electrode, the first electrode, the dielectric layer and the second electrode sequentially covering the surface of the support structure and the inner wall of the first groove near the substrate, and the portion of the capacitor structure located in the first groove forms a second groove.

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