maintaining a rough uniformity of aging of equivalent processing circuitry in pipeline stages in a processor

Abstract

An apparatus and method for maintaining substantially uniform aging of equivalent processing circuitry in a pipeline stage of a processor are disclosed. The processor includes one or more processing units, each including one or more pipelines. Each pipeline includes a series of pipeline stages, each performing a specific function. In this regard, the processor also includes an aging management circuit (AMC) configured to store performance factors indicative of aging of the equivalent processing circuitry in the pipeline stages. In response to a work input in a given pipeline stage, the AMC is further configured to route the work input to one of the equivalent processing circuitry in the pipeline stage based on the stored performance factors. Thus, the AMC controls the frequency of use of the equivalent processing circuitry in its pipeline stage to substantially maintain uniform aging of the equivalent processing circuitry.

Description

Priority application

[0001] This application claims priority to U.S. Patent Application Serial No. 18 / 533,711, filed December 8, 2023, entitled “Maintening Approximate Uniformity of Aging of Equivalent Processing Circuits in a Pipeline Stage(s) in a Processor,” the entire contents of which are incorporated herein by reference. Background Technology

[0002] I. Technical Field

[0003] This disclosure relates to routing operations within a pipeline stage in a processor-based system (e.g., a graphics processing unit (GPU)-based system, a central processing unit (CPU)-based system), and more specifically to apparatus and methods for uniformly aging redundant circuitry within a pipeline stage.

[0004] II. Background Technology

[0005] A processor comprises one or more microprocessors, also known as cores. Microprocessors, also called processing units (PUs), perform computational tasks in a wide variety of applications. One type of conventional microprocessor or PU is the Central Processing Unit (CPU). Another type of microprocessor or PU is a dedicated processing unit called a Graphics Processing Unit (GPU). GPUs are designed with dedicated hardware to accelerate the rendering of graphics and video data to be displayed. GPUs can be implemented as integrated elements of a general-purpose CPU or as discrete hardware components separate from the CPU. A PU executes software instructions that command the processor to fetch data from locations in memory and use the fetched data to perform one or more processor operations. The results can then be stored in memory. This memory can be, for example, a PU-local cache, a shared local cache between PUs within a PU block, a shared cache between multiple PU blocks, and / or system memory in a processor-based system. Cache memory (which may also be simply referred to as "cache") is a smaller, faster memory that stores copies of data stored at frequently accessed memory addresses in main memory or higher-level cache memory to reduce memory access latency. Therefore, a PU can use cache memory to reduce memory access time.

[0006] A PU includes pipeline stages to perform one or more operations using the extracted data. When processing instructions, at each pipeline stage, there may be equivalent circuitry that performs the function of that specific pipeline stage for instruction processing. Examples of equivalent circuitry at a pipeline stage include multiple decoding circuits at a decoding stage to increase parallel operation and thus increase the throughput of that stage. Summary of the Invention

[0007] The aspects disclosed in the detailed description include maintaining approximately uniform aging of the equivalent processing circuitry in the pipeline stages of the processor. The processor includes one or more processing units (each also referred to as a "core"), which include one or more pipelines. A pipeline includes a series of pipeline stages, each performing a specific function within its specific pipeline stage. For example, a pipeline stage may include a fetch stage, a decode stage, and an execution stage. Some pipeline stages include redundant processing circuitry to provide multiple channels within the pipeline stage that can process multiple instructions or instructions with increased bit widths to increase the overall throughput of the pipeline stage. Many unpredictable factors affect the aging of the equivalent processing circuitry when designing a PU, including factors such as negative bias temperature instability (NBTI), hot carrier injection (HCI), and temperature gradients on the semiconductor chip in which the PU is deployed. In this regard, the processor also includes aging management circuitry (AMC) configured to store performance factors indicating the aging of the equivalent processing circuitry in the pipeline stages. In response to a working input in a given pipeline stage, the AMC is further configured to route the working input to an equivalent processing circuit within the equivalent processing circuitry of the pipeline stage based on a stored performance factor. In this way, the AMC controls the frequency of use of the equivalent processing circuitry in its pipeline stage to substantially maintain uniform aging of the equivalent processing circuitry. Maintaining substantially uniform aging of the equivalent processing circuitry in the pipeline stage can advantageously save power and extend the mean time to failure (MTBF) of the collective equivalent processing circuitry in the respective pipeline stage. This method of maintaining substantially uniform aging can be particularly important in processors with multiple processing units (PUs) deployed in a single semiconductor chip (also known as a multi-core chip), such as in mobile vehicles, where the lifespan is typically longer than that of multi-core chips used in other devices and applications, such as tablets, PCs, and mobile phones.

[0008] In this regard, in one aspect, a processor including a first processing unit is disclosed. The first processing unit includes a first pipeline including a plurality of first pipeline stages, the first pipeline stages including a plurality of first equivalent processing circuits. The first processing unit further includes an aging management circuit (AMC) configured to store a plurality of first performance factors indicating the aging of the plurality of first equivalent processing circuits in the first pipeline stages and corresponding to the plurality of first equivalent processing circuits, and in response to a first working input, the AMC is further configured to route the first working input to one of the plurality of first equivalent processing circuits based on the first performance factors.

[0009] In another aspect, a method for maintaining approximately uniform aging of equivalent processing circuitry in a first processing unit is disclosed. The first processing unit includes a first pipeline comprising a plurality of first pipeline stages, each of the plurality of first pipeline stages including a plurality of first equivalent processing circuitry. The method includes: storing a plurality of first performance factors indicating the aging of the plurality of first equivalent processing circuitry in the first pipeline stages and corresponding to the plurality of first equivalent processing circuitry; and, in response to a first working input, routing a first working input to one of the plurality of first equivalent processing circuitry based on the first performance factors.

[0010] In another aspect, a processor is provided for maintaining approximately uniform aging of equivalent processing circuitry in a first processing unit. The first processing unit includes a first pipeline comprising a plurality of first pipeline stages, each of the plurality of first pipeline stages including a plurality of first equivalent processing circuitry. The processor includes means for storing a plurality of first performance factors indicating the aging of the plurality of first equivalent processing circuitry in the first pipeline stages and corresponding to the plurality of first equivalent processing circuitry; and means for routing a first working input to one of the plurality of first equivalent processing circuitry based on the first performance factors, in response to a first working input. Attached Figure Description

[0011] Figure 1This is a block diagram of an exemplary processor-based system, which includes multiple processing units (PUs) and a memory system, including a cache memory system and a system memory. The cache memory system includes a hierarchical structure of local and shared cache memories, and the processor-based system includes an exemplary aging management circuit (AMC) for routing input work based on the stored performance factors of the equivalent processing circuits in the pipeline stage to maintain approximately uniform aging of the equivalent processing circuits.

[0012] Figure 2 yes Figure 1 More detailed block diagrams of exemplary AMCs and PUs;

[0013] Figure 3A It is stored in Figure 1 and Figure 2 In the exemplary AMC or Figure 2 A table of exemplary performance factors for aging of equivalent processing circuits in the resource utilization priority circuitry of the decoding pipeline stage.

[0014] Figure 3B It is an ordered list of exemplary sequences of equivalent processing circuitry in a decoding pipeline stage, the ordered list being based on indications Figure 1 and Figure 2 The aging of stored performance factors in an exemplary AMC;

[0015] Figure 4 It comes from Figure 2 Part of the block diagram, including Figure 2 A more detailed description of the aging profiling circuitry is provided to facilitate understanding of the aging process. Figure 2 Discussion of exemplary measurements performed on the equivalent processing circuitry in the decoding pipeline stage of the processing unit;

[0016] Figure 5 This is a flowchart illustrating an exemplary process for maintaining the approximate uniformity of aging of equivalent processing circuitry in a pipeline stage of a processor, the processor including... Figure 1 The processor and Figure 2 PU in; and

[0017] Figure 6 This is a block diagram of an exemplary processor-based system that may include multiple processing units (PUs) and a memory system, the memory system including a cache memory system and system memory, the cache memory system including a hierarchical structure of local and shared cache memories, and wherein the processor-based system includes an exemplary analog-to-multiplexer (AMC) for storing performance factors based on equivalent processing circuitry in a pipeline stage, and according to, but not limited to, including, […]. Figure 5Any exemplary process in the process, and according to any exemplary aspect disclosed herein, to route input operations to maintain approximately uniform aging of the equivalent processing circuitry. Detailed Implementation

[0018] Several exemplary aspects of this disclosure will now be described with reference to the accompanying drawings. The word “exemplary” is used herein to mean “serving as an example, instance, or illustration.” Any aspect described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other aspects.

[0019] The aspects disclosed in the detailed description include maintaining approximately uniform aging of the equivalent processing circuitry in the pipeline stages of the processor. The processor includes one or more processing units (each also referred to as a "core"), which include one or more pipelines. Each pipeline includes a series of pipeline stages, each performing a specific function. For example, a pipeline stage may include a fetch stage, a decode stage, and an execution stage. Some pipeline stages include redundant processing circuitry to provide multiple channels within the pipeline stage that can process one or more instructions with increased bit widths to increase the overall throughput of the pipeline stage. Many unpredictable factors affect the aging of the equivalent processing circuitry when designing the PU, including but not limited to negative bias temperature instability (NBTI), hot carrier injection (HCI), and temperature gradients on the semiconductor chip in which the PU is deployed. In this regard, the processor also includes aging management circuitry (AMC) configured to store performance factors indicating the aging of the equivalent processing circuitry in the pipeline stages. In response to a given pipeline stage's operating input, the AMC is further configured to route the operating input to an equivalent processing circuit within the pipeline stage based on a stored performance factor. In this way, the AMC controls the frequency of use of the equivalent processing circuit within its pipeline stage to substantially maintain uniform aging of the equivalent processing circuit. Maintaining substantially uniform aging of the equivalent processing circuit within the pipeline stage can advantageously save power and extend the mean time before failure of the collective equivalent processing circuit within the corresponding pipeline stage. This method of maintaining approximately uniform aging can be particularly important in processors with multiple processing units (PUs) deployed on a single semiconductor chip (also known as a multi-core chip), such as in mobile vehicles, where the lifespan is typically longer than that of multi-core chips used in other devices and applications, such as tablets, PCs, and mobile phones.

[0020] In this respect, Figure 1This is a block diagram of an exemplary processor-based system 100, which includes an exemplary aging management circuit (AMC) for routing input work based on stored performance factors of an equivalent processing circuit in a pipeline stage to maintain approximately uniform aging of the equivalent processing circuit. Before discussing these aspects, other exemplary aspects of the processor-based system 100 are described below first.

[0021] The processor-based system 100 includes multiple (multi)processing units (PUs) (multi-PU) processors 102, or also referred to as a multiprocessor, which includes multiple PUs 104(0)-104(N) and a hierarchical memory system. As part of the hierarchical memory system, for example, PU 104(0) includes a private local cache memory 106, which may be a Level 2 (L2) cache memory. PUs 104(1), PU 104(2), PU 104(N-1), and PU 104(N) are configured to interface with corresponding local shared cache memories 106S(0)-106S(X), which may also be, for example, L2 cache memories. If a data read request from PU 104(0)-104(N) results in a cache miss for the corresponding cache memory 106, 106S(0)-106S(X), the read request may be passed to the next level cache memory, which in this example is the shared system cache memory 108. For example, the shared system cache memory 108 may be a Level 3 (L3) cache memory. Cache memory 106, local shared cache memories 106S(0)-106S(X), and shared system cache memory 108 are part of a hierarchical cache memory system 110. An interconnect bus 112, which may be a uniform bus, is provided, which allows each of the PUs 104(0)-104(N) to access the local shared cache memory 106S(0)-106S(X) (if shared to PUs 104(0)-104(N)), the shared system cache memory 108, and other shared resources coupled to the interconnect bus 112.

[0022] Figure 1 The processor-based system 100 includes an aging management circuit (AMC) 114 configured to store performance factors indicating the aging of equivalent processing circuits in the pipeline stage and corresponding to those equivalent processing circuits. In response to a working input in the pipeline stage, the AMC 114 is further configured to route the working input to one of the equivalent processing circuits in the pipeline stage based on the performance factors, to maintain approximately uniform aging of the equivalent processing circuits in the pipeline stage of the processing unit. Figure 2 The following discussion will cover more details of AMC 114, including the pipeline, pipeline stage, and equivalent processing circuitry within the pipeline stage. AMC 114 can be deployed in a PU shown as AMC 114(0), or it can be distributed between a local AMC 114(0) residing in any or all of the PUs 104(0)-104(N) and a remote AMC 114(1) residing in the multi-PU processor 102. The remote AMC 114(1) may alternatively reside in the interconnect bus 112.

[0023] Continue to refer to Figure 1 In this example, the processor-based system 100 also includes a snoop controller 116, which is also coupled to the interconnect bus 112. The snoop controller 116 is circuitry that monitors or snoops on cache memory bus transactions on the interconnect bus 112 to maintain cache coherency among cache memories 106, 106S(0)-106S(X), 108 in the cache memory system 110. Other shared resources accessible by PUs 104(0)-104(N) via the interconnect bus 112 may include input / output (I / O) devices 118 and system memory 120 (e.g., dynamic random access memory (DRAM)). If a read request issued by PU 104(0)-104(N) results in a cache miss in each of the cache memories 106, 106S(0)-106S(X), 108 accessible to PU 104(0)-104(N), the read request is serviced by system memory 120, and the data associated with the read request is installed in the cache memories 106, 106S(0)-106S(X), 108 associated with the requesting PU 104(0)-104(N).

[0024] Figure 2 Examples include the AMC 114 and processing units (such as, more specifically, Figure 1 A block diagram of PU 104(0) in [the diagram]. It will also be combined with [other components]. Figures 3A to 3B and Figure 4 discuss Figure 2In this example, PU 104(0) includes six pipeline stages, each of which receives a majority of a working input and routes the working input to an equivalent processing circuit in the corresponding pipeline stage. The six pipeline stages include: a fetch stage 200, which includes equivalent processing circuits 202A-202D, each configured to fetch instruction 204 from cache memory system 110 and system memory 120; a decode stage 206, which includes equivalent processing circuits 208A-208D, each configured to decode instruction 204, which is a working input, into a micro-operation (micro-manipulation) signal 210; and a dispatch stage 212, which includes equivalent processing circuits 214A-214G, each configured to route the micro-manipulation signal 210, which is a working input, to a dispatch stage 216. Scheduling stage 216 is one of the six pipeline stages of PU 104(0) and includes equivalent processing circuits 218A-218D and 220A-220D, each configured to schedule the micro-operation signal 210, which is a working input, to execution stage 222. Execution stage 222 is one of the six pipeline stages of PU 104(0) and includes integer execution stage 224 and vector execution stage 226. Equivalent processing circuits 218A-218D are configured to schedule the micro-operation signal 210 for execution at integer execution stage 224. Integer execution stage 224 includes equivalent processing circuits 228A-228D, each configured to perform an integer operation on the micro-operation signal 210. Equivalent processing circuits 220A-220D are configured to schedule the micro-operation signal 210 for execution at vector execution stage 226. Vector execution stage 226 includes equivalent processing circuits 230A-230D, each configured to perform a vector operation on micro-operation signal 210. The result 232 of execution stage 222 is passed to write-back stage 234, the sixth pipeline stage of PU 104(0). Write-back stage 234 includes circuitry for writing the result 232 back to cache memory system 110.

[0025] For simplicity, PU 104(0) is depicted as showing six pipeline stages: fetch stage 200, decode stage 206, dispatch stage 212, schedule stage 216, execution stage 222, and write-back stage 234. However, PU 104(0) may include additional pipeline stages. Again for simplicity, PU 104(0) is depicted as including two pipelines: one pipeline is defined by the path between fetch stage 200, decode stage 206, dispatch stage 212, schedule stage 216, integer execution stage 224, and write-back stage 234; and the other pipeline is defined by another path between fetch stage 200, decode stage 206, dispatch stage 212, schedule stage 216, vector execution stage 226, and write-back stage 234. Note that additional pipelines may be implicit within these paths based on various factors, including the width of the fetched instructions, the number of channels that a particular equivalent circuit can process, and the degree of redundancy between equivalent circuits. For simplicity, PU 104(0) is shown as having a specific number of equivalent processing circuits at each pipeline stage. The number of equivalent processing circuits at each pipeline stage can vary based on various design points. The redundancy between equivalent processing circuits can vary and does not need to be exactly the same with respect to the equivalent processing circuits at the corresponding pipeline stages. For example, equivalent processing circuits 228A-228D are equivalent in the sense that micro-operation signal 210 can be similarly executed by equivalent processing circuits 228A-228D. Equivalent processing circuit 228A can be an arithmetic logic unit capable of performing integer operations on 32-bit or 64-bit micro-operation signals, while equivalent processing circuit 228B can be another arithmetic logic unit capable of performing integer operations only on 64-bit micro-operation signals. If the micro-operation signal is a 64-bit micro-operation signal, then processing circuits 222A and 222B are considered equivalent for a particular 64-bit micro-operation signal.

[0026] Returning to AMC 114, which includes aging profiling circuitry 236 and resource utilization and priority encoder (RUP) circuitry 238A-238E. Generally, RUP circuitry 238A-238E is configured to route work inputs (such as instruction 204 and micro-operation signal 210) to the equivalent processing circuitry at their respective pipeline stages based on priority factors (such as the availability of the corresponding equivalent processing circuitry). Additionally, in response to work inputs, RUP circuitry 238A-238E is configured to route work inputs to one of the equivalent processing circuitry in the pipeline stage where the RUP circuitry resides based on a performance factor indicating aging. The performance factor indicating aging can be based on a measurement of throughput through a specific equivalent processing circuitry. Throughput through a specific equivalent processing circuitry can be measured by the number of transactions within a specific time period or the amount of time taken to complete a fixed number of transactions. For example, the throughput of the equivalent processing circuits 208A-208D in the decoding stage 206 can be measured by the aging profiling circuit 236 sending a fixed number of instructions to each of the equivalent processing circuits 208A-208D and determining the time taken for each of the equivalent processing circuits 208A-208D to process the fixed number of instructions. Alternatively, the throughput of the equivalent processing circuits 208A-208D in the decoding stage 206 can be measured by the aging profiling circuit 236 setting a timer to a fixed time and sending instructions to each of the equivalent processing circuits 208A-208D and determining the number of instructions successfully decoded within the fixed time. The equivalent processing circuits 208A-208D in the decoding stage 206 can be measured individually by the aging profiling circuit 236 each time the PU 104(0) is started or at a predetermined start time. The start time occurs when the multiprocessor 102 is initially powered (also known as a cold start) or when the PU 104(0) is individually reset (also known as a warm start). Figure 4 A more detailed example of the equivalent processing circuitry 208A-208D used to measure the decoding stage 206 is discussed. Measurements of the equivalent processing circuitry at other pipeline stages are similar, except that sample micromanipulation signals, instead of sample commands, are transmitted from the aging profiling circuitry 236 to the other pipeline stages.

[0027] Figure 3A It is stored in Figure 1 or Figure 2 In the exemplary AMC 114 or Figure 2 Table 300 shows exemplary performance factors 301 for aging of equivalent processing circuits 208A-208D in the RUP circuit 238A of the RUP circuit 238A in the decoding stage 206. Table 300 stores performance factors corresponding to the corresponding equivalent processing circuits 208A-208D, where the lowest value indicates the most recent equivalent processing circuit 302 and the highest value indicates the oldest equivalent processing circuit 304.

[0028] Instead of referencing a storage table such as Table 300, an ordered list can be stored, where a performance factor is used to maintain the ordered list. Figure 3B This is an ordered list 306 of exemplary sequences of equivalent processing circuits in a decoding pipeline stage, the order of which is based on indications. Figure 1 and Figure 2 The aging measurement performance factor in the exemplary AMC 114. The first position 308 illustrates the equivalent processing circuit 208C as the newest circuit, while the last position 310 illustrates the equivalent processing circuit 208B as the oldest circuit.

[0029] In response to instruction 204, the RUP circuit 238A in the decoding stage 206 selects the latest available equivalent circuit from a performance factor table (e.g., table 300) or an ordered list (e.g., ordered list 306) to route the instruction for decoding. If equivalent processing circuit 208C is available, the RUP circuit 238A selects equivalent processing circuit 208C to decode the instruction. Table 300 or alternative ordered list 306 may be stored in the RUP circuit 238A or in the aging profiling circuit 236 and accessed by the RUP circuit 238A in response to instruction 204.

[0030] RUP circuits 238B-238E operate in a similar manner, wherein each RUP circuit 238B-238E will include a corresponding table, ordered list, or combination of both, similar to Table 300 or ordered list 306, and in response to a working input (such as micro-operation signal 210), selects the latest equivalent processing circuit in the pipeline stage to process micro-operation signal 210.

[0031] Figure 4 It comes from Figure 2 A portion of block diagram 200, including Figure 2 A more detailed description of the aging profiling circuit 236 in the diagram is provided to facilitate understanding of the aging process. Figure 2This section discusses exemplary measurements performed on the equivalent processing circuitry 208A in the decoding pipeline stage 206 of PU 104(0). The aging profiling circuitry 236 includes a control unit 402, an aging measurement unit 404, and an Enhanced Built-in Self-Test (EBIST) unit 406. The control unit 402 controls the selection and isolation of the appropriate equivalent processing circuitry that requires measurement for performance factors indicative of aging. The EBIST unit 406 includes conventional built-in self-test techniques for determining the operability of the equivalent processing circuitry by passing a test mode as input to the appropriate equivalent processing circuitry and testing whether the return result from the appropriate equivalent processing circuitry matches the expected result of the test mode. The EBIST unit 406 is also coupled to the aging measurement unit 404 to measure and determine the performance factors indicative of aging. In this regard, the control unit 402 determines the specific pipeline stage to be tested and retrieves the test mode for the equivalent processing circuitry in the specific pipeline stage from the cache memory system 110 or system memory 120. The control unit 402 triggers the aging measurement unit 404 to start a timer. The aging measurement unit 404 triggers the EBIST unit 406 to transmit test modes to the respective equivalent processing circuits of a specific pipeline level. A timer measures the time taken for each equivalent processing circuit to process the test mode. When a test mode is completed by the corresponding equivalent processing circuit, the EBIST unit 406 or the profiled equivalent processing circuit signals the timer in the aging measurement unit 404. The control unit 402 determines the aging performance factor indicative of each equivalent processing circuit based on the time taken for each equivalent processing circuit to complete the test mode. The control unit 402 stores the aging information as a performance factor in the aging profiling circuit 236 or the resource utilization priority circuit of the tested pipeline level for use by the measured equivalent processing circuit, or as a list of measured equivalent processing circuits based on aging order. The control unit 402 may store the aging information in the system memory 120 to avoid measurement each time the multiprocessor 102 is started.

[0032] In this example, control unit 402 selects equivalent processing circuit 208A (also known as decoder circuit). Since equivalent processing circuit 208A decodes instructions (also known as instruction queues) from equivalent processing circuit 202A, control unit 402 also isolates equivalent processing circuit 202A. EBIST unit 406 provides instruction vectors (also known as instruction queues) to equivalent processing circuit 202A. The vectors contain sequentially ordered instructions used to test critical and most frequently used paths in equivalent processing circuit 208A. The mix of instructions in the vectors includes arithmetic, logical, and conditional instructions. The vectors can be hundreds of instructions long. Burn-in measurement unit 404 starts a timer to track the time spent by equivalent processing circuit 208A decoding the vectors and triggers equivalent processing circuit 208A to begin decoding the first instruction (also known as instruction queue) in the vectors from equivalent processing circuit 202A. When burn-in profiling equivalent processing circuit 208A, it is configured to operate in autotime mode. In auto-time mode, the equivalent processing circuit 208A manages the speed at which it decodes instructions from the vector, allowing it to read the next instruction after completing the current one. After the equivalent processing circuit 208A completes decoding an instruction, a decoding completion signal is asserted for the equivalent processing circuit 208A to decode the next instruction (aka instruction queue) from the equivalent processing circuit 202A. The equivalent processing circuit 208A continues decoding instructions from the vector until the last instruction in the vector is decoded. At this point, the equivalent processing circuit 208A triggers the aging measurement unit 404 to stop its timer and end the aging profiling of the equivalent processing circuit 208A. The aging measurement unit 404 stores the number of timer cycles spent by the equivalent processing circuit 208A decoding the instruction vector. In this example, the aging performance factor of the equivalent processing circuit 208A can be the number of timer cycles used to decode the instruction vector, or it can be an algorithmic function based on the number of timer cycles used to decode the instruction vector. The same aging profiling method is used to profile the equivalent processing circuits 208B-208D. The aging measurement unit 404 also stores the aging performance factors of the equivalent processing circuits 208B-208D. The aging analysis factors may also be stored in the RUP circuit 238A, or alternatively.

[0033] Figure 5 This is a flowchart illustrating an exemplary process 500 for maintaining approximately uniform aging of equivalent processing circuitry in a pipeline stage of a processor, the processor including... Figure 1 The processor and Figure 2 The processing unit within it. In this respect, Figure 5A first exemplary step in process 500 may include storing an indication of aging of a plurality of first equivalent processing circuits 208A-208D in a first pipeline stage 206 and a plurality of first performance factors 300 corresponding to the plurality of first equivalent processing circuits (block 502). A next step in process 500 may include: in response to a first working input 204 (block 504), routing the first working input 204 to one of the plurality of first equivalent processing circuits 208A-208D based on a first performance factor among the plurality of first performance factors 300 (block 506).

[0034] Electronic devices that can be provided in or integrated into any processor-based device, including exemplary processor-based systems (such as...) Figure 1 The processor-based system 100 includes multiple CPUs and a memory system, the memory system including a cache memory system and system memory, the cache memory system including a hierarchical structure of local and shared cache memories, and wherein the processor-based system includes an exemplary AMC (such as...). Figures 1 to 2 AMC 114 in the pipeline stage is used to store performance factors based on the equivalent processing circuitry in the pipeline stage, and according to, but not limited to, any exemplary process (such as...). Figure 5 The process (500) and, according to any aspect disclosed herein, routes input operations to maintain approximately uniform aging of the equivalent processing circuitry. Examples include, but are not limited to, set-top boxes, entertainment units, navigation devices, communication devices, fixed location data units, mobile location data units, Global Positioning System (GPS) devices, mobile phones, cellular phones, smartphones, Session Initiation Protocol (SIP) phones, tablet computers, tablet phones, servers, computers, portable computers, mobile computing devices, laptop computers, wearable computing devices (e.g., smartwatches, health or fitness trackers, glasses, etc.), desktop computers, personal digital assistants (PDAs), monitors, computer monitors, televisions, tuners, radios, satellite radios, music players, digital music players, portable music players, digital video players, video players, digital video disc (DVD) players, portable digital video players, automobiles, vehicle components, avionics systems, and multirotor aircraft.

[0035] In this respect, Figure 6An example of a processor-based system 600 is illustrated. This processor-based system may include multiple CPUs and a memory system, including a cache memory system and system memory. The cache memory system includes a hierarchical structure of local and shared cache memories, and the processor-based system 600 includes an exemplary AMC 602 (such as...). Figures 1 to 2 The AMC 114 in the pipeline stage is used to store performance factors based on the equivalent processing circuitry in the pipeline stage, and according to, but not limited to, the AMC 114. Figure 5 The exemplary process 500 in the document, and according to any exemplary aspect disclosed herein, routes input work to maintain a generally uniform aging of the equivalent processing circuitry. In this example, the processor-based system 600 may be formed as an integrated circuit (IC) 604, as a system-on-a-chip (SoC) 606 in one or more processing units, such as a central processing unit (CPU) 608. The processor-based system 600 includes a CPU 608, which includes one or more PUs, which may also be referred to as CPU cores or processor cores. The CPU 608 may have a cache memory 612 coupled to the CPU 608 for fast access to temporarily stored data. The CPU 608 is coupled to a system bus 614 and may be coupled to master and slave devices included in the processor-based system 600. As is well known, the CPU 608 communicates with these other devices by exchanging address, control, and data information via the system bus 614. For example, the CPU 608 may communicate a bus transaction request to a memory controller 616, which is an example of a slave device. Figure 6 Not illustrated, but multiple system buses 614 may be provided, each of which constitutes a different architecture.

[0036] Other master and slave devices can be connected to system bus 614. For example... Figure 6As illustrated, by way of example, these devices may include a memory system 620, one or more input devices 622, one or more output devices 624, one or more network interface devices 626, and one or more display controllers 628, the memory system including a memory controller 616 and a memory array 618. Each of the memory system 620, one or more input devices 622, one or more output devices 624, one or more network interface devices 626, and one or more display controllers 628 may be provided in the same or different processor-based system 600. Input devices 622 may include any type of input device, including but not limited to input keys, switches, voice processors, etc. Output devices 624 may include any type of output device, including but not limited to audio, video, other visual indicators, etc. Network interface devices 626 may be any device configured to allow the exchange of data to and from network 630. Network 630 may be any type of network, including but not limited to wired or wireless networks, private or public networks, local area networks (LANs), wireless local area networks (WLANs), wide area networks (WANs), Bluetooth. ™ Networks and the Internet. The network interface device 626 can be configured to support any type of communication protocol desired.

[0037] CPU 608 can also be configured to access display controller 628 via system bus 614 to control information transmitted to one or more displays 632. Display controller 628 transmits information to be displayed to displays 632 via one or more video processors 634, which process the information into a format suitable for use by displays 632. As an example, display controller 628 and video processors 634 can be included as ICs in the same or different processor-based systems 600. Displays 632 can include any type of display, including but not limited to cathode ray tube (CRT), liquid crystal display (LCD), plasma display, light-emitting diode (LED) display, etc.

[0038] Those skilled in the art will further understand that the various exemplary logic blocks, modules, circuits, and algorithms described in connection with the aspects disclosed herein can be implemented as electronic hardware, instructions stored in memory, or in another computer-readable medium, wherein any such instructions are executed by a processor or other processing device or a combination of both. As an example, the devices and components described herein can be employed in any circuit, hardware component, integrated circuit (IC), or IC chip. The memory disclosed herein can be of any type and size and can be configured to store any type of information desired. To clearly illustrate this interchangeability, the functionality of the various exemplary components, blocks, modules, circuits, and steps has been generally described above. How such functionality is implemented depends on the specific application, design choices, and / or design constraints imposed on the overall system. Those skilled in the art may implement the described functionality in different ways for each specific application, but such specific implementation decisions should not be construed as departing from the scope of this disclosure.

[0039] The various exemplary logic blocks, modules, and circuits described in conjunction with the aspects disclosed herein may be implemented or executed using a processor, digital signal processor (DSP), application-specific integrated circuit (ASIC), field-programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic unit, discrete hardware component, or any combination thereof, designed to perform the functions described herein. The processor may be a microprocessor, but in alternative embodiments, the processor may be any conventional processor, controller, microcontroller, or state machine. The processor may also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors cooperating with a DSP core, or any other such configuration).

[0040] The aspects disclosed herein may be embodied in hardware and instructions stored in the hardware, and may reside in, for example, random access memory (RAM), flash memory, read-only memory (ROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), registers, hard disks, removable disks, CD-ROMs, or any other form of computer-readable medium known in the art. An exemplary storage medium is coupled to a processor, enabling the processor to read information from and write information to the storage medium. Alternatively, the storage medium may be integral with the processor. The processor and storage medium may reside in an ASIC. The ASIC may reside in a remote station. Alternatively, the processor and storage medium may reside as discrete components in a remote station, base station, or server.

[0041] It should also be noted that the operational steps described in any of the exemplary aspects of this document are described for the purpose of providing examples and discussion. The described operations may be performed in many different orders other than the order illustrated. Furthermore, the operations described in a single operational step may actually be performed in multiple different steps. In addition, one or more operational steps discussed in the exemplary aspects may be combined. It should be understood that, as will be apparent to those skilled in the art, many different modifications may be made to the operational steps illustrated in the flowcharts. Those skilled in the art will also understand that any of a variety of different techniques and arts can be used to represent information and signals. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be mentioned throughout the above description may be represented by voltage, current, electromagnetic waves, magnetic fields or magnetic particles, light fields or optical particles, or any combination thereof.

[0042] The prior description of this disclosure is provided to enable any person skilled in the art to make or use this disclosure. Various modifications to this disclosure will be apparent to those skilled in the art, and the general principles defined herein can be applied to other variations. Therefore, this disclosure is not intended to be limited to the examples and designs described herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

[0043] Specific implementation examples are described in the following numbered clauses:

[0044] 1. A processor, the processor comprising:

[0045] A first processing unit, the first processing unit comprising:

[0046] A first pipeline, comprising a plurality of first pipeline stages, wherein each first pipeline stage comprises a plurality of first equivalent processing circuits; and

[0047] An aging management circuit (AMC) is configured to:

[0048] The storage indicates the aging of the plurality of first equivalent processing circuits in the first pipeline stage and a plurality of first performance factors corresponding to the plurality of first equivalent processing circuits; and

[0049] In response to a first working input, the first working input is routed to one of the plurality of first equivalent processing circuits based on a first performance factor among the plurality of first performance factors.

[0050] 2. The processor according to Clause 1, wherein the AMC is further configured to measure the plurality of first equivalent processing circuits to obtain the plurality of first performance factors.

[0051] 3. The processor according to clause 1 or 2, wherein:

[0052] The first pipeline stage is the decoding stage, and

[0053] The plurality of first equivalent processing circuits are plurality of decoding circuits.

[0054] 4. The processor according to any one of clauses 1 to 3, wherein the plurality of first performance factors includes the throughput of the plurality of first equivalent processing circuits.

[0055] 5. The processor according to any one of clauses 1 to 4, wherein the processor further comprises:

[0056] The second pipeline stage in the plurality of first pipeline stages, the second pipeline stage including a plurality of second equivalent processing circuits.

[0057] The AMC is further configured as follows:

[0058] Storing multiple second performance factors corresponding to the multiple second equivalent processing circuits; and

[0059] In response to the second working input of the second pipeline stage, the second working input is routed to one of the plurality of second equivalent processing circuits based on the second performance factor among the plurality of second performance factors.

[0060] 6. The processor according to any one of clauses 1 to 5, wherein:

[0061] The plurality of first pipeline stages includes one or more pipeline stages, and the one or more pipeline stages include equivalent processing circuitry; and

[0062] The AMC also includes multiple resource utilization and priority encoder circuits corresponding to the one or more pipeline stages.

[0063] 7. The processor according to any one of clauses 1 to 6, wherein the AMC further comprises an aging and profiling circuit, the aging and profiling circuit being configured to:

[0064] Measuring the plurality of first equivalent processing circuits; and

[0065] Determine the plurality of first performance factors that indicate the aging.

[0066] 8. The processor according to any one of clauses 1 to 6, wherein the AMC further comprises an aging profiling circuit configured to: upon startup of the first processing unit or at a predetermined time after resetting the first processing unit:

[0067] Measuring the plurality of first equivalent processing circuits; and

[0068] Determine the plurality of first performance factors that indicate the aging.

[0069] 9. The processor according to any one of clauses 1 to 8, wherein the processor further comprises:

[0070] The second processing unit includes:

[0071] The second pipeline includes multiple second pipeline stages, and each of the multiple second pipeline stages includes multiple second equivalent processing circuits.

[0072] The AMC is further configured as follows:

[0073] Storing a plurality of second performance factors corresponding to the plurality of second equivalent processing circuits in the second pipeline stage; and

[0074] In response to the second working input, the second working input is routed to one of the plurality of second equivalent processing circuits based on the second performance factor among the plurality of second performance factors.

[0075] 10. A method for maintaining substantially uniform aging of equivalent processing circuitry in a first processing unit, the first processing unit comprising a first pipeline, the first pipeline comprising a plurality of first pipeline stages, the first pipeline stages comprising a plurality of first equivalent processing circuitry, the method comprising:

[0076] The storage indicates the aging of the plurality of first equivalent processing circuits in the first pipeline stage and a plurality of first performance factors corresponding to the plurality of first equivalent processing circuits; and

[0077] In response to a first working input, the first working input is routed to one of the plurality of first equivalent processing circuits based on a first performance factor among the plurality of first performance factors.

[0078] 11. The method according to Clause 10, the method further comprising measuring the plurality of first equivalent processing circuits to obtain the plurality of first performance factors.

[0079] 12. The method according to clause 10 or 11, wherein:

[0080] The first pipeline stage is the decoding stage, and

[0081] The plurality of first equivalent processing circuits are plurality of decoding circuits.

[0082] 13. The method according to any one of clauses 10 to 12, wherein the plurality of first performance factors includes the throughput of the plurality of first equivalent processing circuits.

[0083] 14. The method according to any one of claims 10 to 13, wherein the first processing unit further comprises a second pipeline stage of the plurality of first pipeline stages, the second pipeline stage comprising a plurality of second equivalent processing circuits, the method further comprising:

[0084] Storing multiple second performance factors corresponding to the multiple second equivalent processing circuits; and

[0085] In response to the second working input of the second pipeline stage, the second working input is routed to one of the plurality of second equivalent processing circuits based on the second performance factor among the plurality of second performance factors.

[0086] 15. The method according to any one of clauses 10 to 14, wherein the method further comprises:

[0087] Measuring the plurality of first equivalent processing circuits; and

[0088] Determine the plurality of first performance factors that indicate the aging.

[0089] 16. The method according to any one of clauses 10 to 14, further comprising: at startup of the first processing unit or at a predetermined time for resetting the first processing unit:

[0090] Measuring the plurality of first equivalent processing circuits; and

[0091] Determine the plurality of first performance factors that indicate the aging.

[0092] 17. The method according to any one of clauses 10 to 15, wherein the method further comprises:

[0093] The storage includes multiple second performance factors corresponding to multiple second equivalent processing circuits in multiple second pipeline stages within the second pipeline of the second processing unit; and

[0094] In response to the second working input, the second working input is routed to one of the plurality of second equivalent processing circuits based on the second performance factor among the plurality of second performance factors.

[0095] 18. A processor for maintaining substantially uniform aging of equivalent processing circuitry in a first processing unit, the first processing unit comprising a first pipeline, the first pipeline comprising a plurality of first pipeline stages, the first pipeline stages comprising a plurality of first equivalent processing circuitry, the processor comprising:

[0096] Components for storing indications of the aging of the plurality of first equivalent processing circuits in the first pipeline stage and a plurality of first performance factors corresponding to the plurality of first equivalent processing circuits; and

[0097] A component that, in response to a first working input, routes the first working input to one of the plurality of first equivalent processing circuits based on a first performance factor among the plurality of first performance factors.

[0098] 19. The processor according to Clause 18, the processor further comprising components for measuring the plurality of first equivalent processing circuits to obtain the plurality of first performance factors.

[0099] 20. The processor according to Clause 18, further comprising:

[0100] Components for measuring the plurality of first equivalent processing circuits; and

[0101] Components used to determine the plurality of first performance factors indicating the aging.

Claims

1. A processor, the processor comprising: A first processing unit, the first processing unit comprising: A first pipeline, comprising a plurality of first pipeline stages, wherein each first pipeline stage comprises a plurality of first equivalent processing circuits; and An aging management circuit (AMC) is configured to: The storage indicates the aging of the plurality of first equivalent processing circuits in the first pipeline stage and a plurality of first performance factors corresponding to the plurality of first equivalent processing circuits; and In response to a first working input, the first working input is routed to one of the plurality of first equivalent processing circuits based on a first performance factor among the plurality of first performance factors.

2. The processor of claim 1, wherein the AMC is further configured to measure the plurality of first equivalent processing circuits to obtain the plurality of first performance factors.

3. The processor according to claim 1, wherein: The first pipeline stage is the decoding stage, and The plurality of first equivalent processing circuits are plurality of decoding circuits.

4. The processor of claim 1, wherein the plurality of first performance factors include the throughput of the plurality of first equivalent processing circuits.

5. The processor according to claim 1, further comprising: The second pipeline stage in the plurality of first pipeline stages, the second pipeline stage including a plurality of second equivalent processing circuits. The AMC is further configured as follows: Storing multiple second performance factors corresponding to the multiple second equivalent processing circuits; and In response to the second working input of the second pipeline stage, the second working input is routed to one of the plurality of second equivalent processing circuits based on the second performance factor among the plurality of second performance factors.

6. The processor according to claim 1, wherein: The plurality of first pipeline stages includes one or more pipeline stages, and the one or more pipeline stages include equivalent processing circuitry; and The AMC also includes multiple resource utilization and priority encoder circuits corresponding to the one or more pipeline stages.

7. The processor of claim 6, wherein the AMC further comprises a aging and profiling circuit, the aging and profiling circuit being configured to: Measuring the plurality of first equivalent processing circuits; and Determine the plurality of first performance factors that indicate the aging.

8. The processor of claim 6, wherein the AMC further comprises an aging profiling circuit configured to activate upon startup of the first processing unit or at a predetermined time after resetting the first processing unit: Measuring the plurality of first equivalent processing circuits; and Determine the plurality of first performance factors that indicate the aging.

9. The processor according to claim 1, further comprising: The second processing unit includes: The second pipeline includes multiple second pipeline stages, and each of the multiple second pipeline stages includes multiple second equivalent processing circuits. The AMC is further configured as follows: Storing a plurality of second performance factors corresponding to the plurality of second equivalent processing circuits in the second pipeline stage; and In response to the second working input, the second working input is routed to one of the plurality of second equivalent processing circuits based on the second performance factor among the plurality of second performance factors.

10. A method for maintaining substantially uniform aging of equivalent processing circuitry in a first processing unit, the first processing unit comprising a first pipeline, the first pipeline comprising a plurality of first pipeline stages, the first pipeline stages comprising a plurality of first equivalent processing circuitry, the method comprising: The storage indicates the aging of the plurality of first equivalent processing circuits in the first pipeline stage and a plurality of first performance factors corresponding to the plurality of first equivalent processing circuits; as well as In response to a first working input, the first working input is routed to one of the plurality of first equivalent processing circuits based on a first performance factor among the plurality of first performance factors.

11. The method of claim 10, further comprising measuring the plurality of first equivalent processing circuits to obtain the plurality of first performance factors.

12. The method according to claim 10, wherein: The first pipeline stage is the decoding stage, and The plurality of first equivalent processing circuits are plurality of decoding circuits.

13. The method of claim 10, wherein the plurality of first performance factors includes the throughput of the plurality of first equivalent processing circuits.

14. The method of claim 10, wherein the first processing unit further comprises a second pipeline stage among the plurality of first pipeline stages, the second pipeline stage comprising a plurality of second equivalent processing circuits, the method further comprising: Store multiple second performance factors corresponding to the multiple second equivalent processing circuits; as well as In response to the second working input of the second pipeline stage, the second working input is routed to one of the plurality of second equivalent processing circuits based on the second performance factor among the plurality of second performance factors.

15. The method according to claim 10, further comprising: Measure the plurality of first equivalent processing circuits; as well as Determine the plurality of first performance factors that indicate the aging.

16. The method of claim 10, further comprising: upon startup of the first processing unit or at a predetermined time for resetting the first processing unit: Measuring the plurality of first equivalent processing circuits; and Determine the plurality of first performance factors that indicate the aging.

17. The method according to claim 10, further comprising: The storage corresponds to multiple second performance factors of multiple second equivalent processing circuits in multiple second pipeline stages in the second pipeline of the second processing unit. as well as In response to the second working input, the second working input is routed to one of the plurality of second equivalent processing circuits based on the second performance factor among the plurality of second performance factors.

18. A processor for maintaining substantially uniform aging of equivalent processing circuitry in a first processing unit, the first processing unit comprising a first pipeline, the first pipeline comprising a plurality of first pipeline stages, the first pipeline stages comprising a plurality of first equivalent processing circuitry, the processor comprising: Components for storing an indication of the aging of the plurality of first equivalent processing circuits in the first pipeline stage and a plurality of first performance factors corresponding to the plurality of first equivalent processing circuits; and A component that, in response to a first working input, routes the first working input to one of the plurality of first equivalent processing circuits based on a first performance factor among the plurality of first performance factors.

19. The processor of claim 18, further comprising a component for measuring the plurality of first equivalent processing circuits to obtain the plurality of first performance factors.

20. The processor of claim 18, further comprising: Components used for measuring the plurality of first equivalent processing circuits; and Components used to determine the plurality of first performance factors indicating the aging.

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